1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <stdio.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 12 #include <rte_alarm.h> 13 #include <rte_branch_prediction.h> 14 #include <rte_debug.h> 15 #include <rte_devargs.h> 16 #include <rte_dev.h> 17 #include <rte_kvargs.h> 18 #include <rte_malloc.h> 19 #include <rte_mbuf_pool_ops.h> 20 #include <rte_prefetch.h> 21 #include <rte_bus_vdev.h> 22 23 #include "octeontx_ethdev.h" 24 #include "octeontx_rxtx.h" 25 #include "octeontx_logs.h" 26 27 struct evdev_priv_data { 28 OFFLOAD_FLAGS; /*Sequence should not be changed */ 29 } __rte_cache_aligned; 30 31 struct octeontx_vdev_init_params { 32 uint8_t nr_port; 33 }; 34 35 uint16_t 36 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX]; 37 38 enum octeontx_link_speed { 39 OCTEONTX_LINK_SPEED_SGMII, 40 OCTEONTX_LINK_SPEED_XAUI, 41 OCTEONTX_LINK_SPEED_RXAUI, 42 OCTEONTX_LINK_SPEED_10G_R, 43 OCTEONTX_LINK_SPEED_40G_R, 44 OCTEONTX_LINK_SPEED_RESERVE1, 45 OCTEONTX_LINK_SPEED_QSGMII, 46 OCTEONTX_LINK_SPEED_RESERVE2 47 }; 48 49 int otx_net_logtype_mbox; 50 int otx_net_logtype_init; 51 int otx_net_logtype_driver; 52 53 RTE_INIT(otx_net_init_log) 54 { 55 otx_net_logtype_mbox = rte_log_register("pmd.net.octeontx.mbox"); 56 if (otx_net_logtype_mbox >= 0) 57 rte_log_set_level(otx_net_logtype_mbox, RTE_LOG_NOTICE); 58 59 otx_net_logtype_init = rte_log_register("pmd.net.octeontx.init"); 60 if (otx_net_logtype_init >= 0) 61 rte_log_set_level(otx_net_logtype_init, RTE_LOG_NOTICE); 62 63 otx_net_logtype_driver = rte_log_register("pmd.net.octeontx.driver"); 64 if (otx_net_logtype_driver >= 0) 65 rte_log_set_level(otx_net_logtype_driver, RTE_LOG_NOTICE); 66 } 67 68 /* Parse integer from integer argument */ 69 static int 70 parse_integer_arg(const char *key __rte_unused, 71 const char *value, void *extra_args) 72 { 73 int *i = (int *)extra_args; 74 75 *i = atoi(value); 76 if (*i < 0) { 77 octeontx_log_err("argument has to be positive."); 78 return -1; 79 } 80 81 return 0; 82 } 83 84 static int 85 octeontx_parse_vdev_init_params(struct octeontx_vdev_init_params *params, 86 struct rte_vdev_device *dev) 87 { 88 struct rte_kvargs *kvlist = NULL; 89 int ret = 0; 90 91 static const char * const octeontx_vdev_valid_params[] = { 92 OCTEONTX_VDEV_NR_PORT_ARG, 93 NULL 94 }; 95 96 const char *input_args = rte_vdev_device_args(dev); 97 if (params == NULL) 98 return -EINVAL; 99 100 101 if (input_args) { 102 kvlist = rte_kvargs_parse(input_args, 103 octeontx_vdev_valid_params); 104 if (kvlist == NULL) 105 return -1; 106 107 ret = rte_kvargs_process(kvlist, 108 OCTEONTX_VDEV_NR_PORT_ARG, 109 &parse_integer_arg, 110 ¶ms->nr_port); 111 if (ret < 0) 112 goto free_kvlist; 113 } 114 115 free_kvlist: 116 rte_kvargs_free(kvlist); 117 return ret; 118 } 119 120 static int 121 octeontx_port_open(struct octeontx_nic *nic) 122 { 123 octeontx_mbox_bgx_port_conf_t bgx_port_conf; 124 int res; 125 126 res = 0; 127 memset(&bgx_port_conf, 0x0, sizeof(bgx_port_conf)); 128 PMD_INIT_FUNC_TRACE(); 129 130 res = octeontx_bgx_port_open(nic->port_id, &bgx_port_conf); 131 if (res < 0) { 132 octeontx_log_err("failed to open port %d", res); 133 return res; 134 } 135 136 nic->node = bgx_port_conf.node; 137 nic->port_ena = bgx_port_conf.enable; 138 nic->base_ichan = bgx_port_conf.base_chan; 139 nic->base_ochan = bgx_port_conf.base_chan; 140 nic->num_ichans = bgx_port_conf.num_chans; 141 nic->num_ochans = bgx_port_conf.num_chans; 142 nic->bgx_mtu = bgx_port_conf.mtu; 143 nic->bpen = bgx_port_conf.bpen; 144 nic->fcs_strip = bgx_port_conf.fcs_strip; 145 nic->bcast_mode = bgx_port_conf.bcast_mode; 146 nic->mcast_mode = bgx_port_conf.mcast_mode; 147 nic->speed = bgx_port_conf.mode; 148 149 memcpy(&nic->mac_addr[0], &bgx_port_conf.macaddr[0], 150 RTE_ETHER_ADDR_LEN); 151 152 octeontx_log_dbg("port opened %d", nic->port_id); 153 return res; 154 } 155 156 static void 157 octeontx_port_close(struct octeontx_nic *nic) 158 { 159 PMD_INIT_FUNC_TRACE(); 160 161 octeontx_bgx_port_close(nic->port_id); 162 octeontx_log_dbg("port closed %d", nic->port_id); 163 } 164 165 static int 166 octeontx_port_start(struct octeontx_nic *nic) 167 { 168 PMD_INIT_FUNC_TRACE(); 169 170 return octeontx_bgx_port_start(nic->port_id); 171 } 172 173 static int 174 octeontx_port_stop(struct octeontx_nic *nic) 175 { 176 PMD_INIT_FUNC_TRACE(); 177 178 return octeontx_bgx_port_stop(nic->port_id); 179 } 180 181 static int 182 octeontx_port_promisc_set(struct octeontx_nic *nic, int en) 183 { 184 struct rte_eth_dev *dev; 185 int res; 186 187 res = 0; 188 PMD_INIT_FUNC_TRACE(); 189 dev = nic->dev; 190 191 res = octeontx_bgx_port_promisc_set(nic->port_id, en); 192 if (res < 0) { 193 octeontx_log_err("failed to set promiscuous mode %d", 194 nic->port_id); 195 return res; 196 } 197 198 /* Set proper flag for the mode */ 199 dev->data->promiscuous = (en != 0) ? 1 : 0; 200 201 octeontx_log_dbg("port %d : promiscuous mode %s", 202 nic->port_id, en ? "set" : "unset"); 203 204 return 0; 205 } 206 207 static int 208 octeontx_port_stats(struct octeontx_nic *nic, struct rte_eth_stats *stats) 209 { 210 octeontx_mbox_bgx_port_stats_t bgx_stats; 211 int res; 212 213 PMD_INIT_FUNC_TRACE(); 214 215 res = octeontx_bgx_port_stats(nic->port_id, &bgx_stats); 216 if (res < 0) { 217 octeontx_log_err("failed to get port stats %d", nic->port_id); 218 return res; 219 } 220 221 stats->ipackets = bgx_stats.rx_packets; 222 stats->ibytes = bgx_stats.rx_bytes; 223 stats->imissed = bgx_stats.rx_dropped; 224 stats->ierrors = bgx_stats.rx_errors; 225 stats->opackets = bgx_stats.tx_packets; 226 stats->obytes = bgx_stats.tx_bytes; 227 stats->oerrors = bgx_stats.tx_errors; 228 229 octeontx_log_dbg("port%d stats inpkts=%" PRIx64 " outpkts=%" PRIx64 "", 230 nic->port_id, stats->ipackets, stats->opackets); 231 232 return 0; 233 } 234 235 static int 236 octeontx_port_stats_clr(struct octeontx_nic *nic) 237 { 238 PMD_INIT_FUNC_TRACE(); 239 240 return octeontx_bgx_port_stats_clr(nic->port_id); 241 } 242 243 static inline void 244 devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf, 245 struct rte_event_dev_info *info) 246 { 247 memset(dev_conf, 0, sizeof(struct rte_event_dev_config)); 248 dev_conf->dequeue_timeout_ns = info->min_dequeue_timeout_ns; 249 250 dev_conf->nb_event_ports = info->max_event_ports; 251 dev_conf->nb_event_queues = info->max_event_queues; 252 253 dev_conf->nb_event_queue_flows = info->max_event_queue_flows; 254 dev_conf->nb_event_port_dequeue_depth = 255 info->max_event_port_dequeue_depth; 256 dev_conf->nb_event_port_enqueue_depth = 257 info->max_event_port_enqueue_depth; 258 dev_conf->nb_event_port_enqueue_depth = 259 info->max_event_port_enqueue_depth; 260 dev_conf->nb_events_limit = 261 info->max_num_events; 262 } 263 264 static uint16_t 265 octeontx_tx_offload_flags(struct rte_eth_dev *eth_dev) 266 { 267 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 268 uint16_t flags = 0; 269 270 if (!(nic->tx_offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) 271 flags |= OCCTX_TX_OFFLOAD_MBUF_NOFF_F; 272 273 if (nic->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 274 flags |= OCCTX_TX_MULTI_SEG_F; 275 276 return flags; 277 } 278 279 static uint16_t 280 octeontx_rx_offload_flags(struct rte_eth_dev *eth_dev) 281 { 282 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 283 struct rte_eth_dev_data *data = eth_dev->data; 284 struct rte_eth_conf *conf = &data->dev_conf; 285 struct rte_eth_rxmode *rxmode = &conf->rxmode; 286 uint16_t flags = 0; 287 288 if (rxmode->mq_mode == ETH_MQ_RX_RSS) 289 flags |= OCCTX_RX_OFFLOAD_RSS_F; 290 291 if (nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 292 flags |= OCCTX_RX_MULTI_SEG_F; 293 eth_dev->data->scattered_rx = 1; 294 /* If scatter mode is enabled, TX should also be in multi 295 * seg mode, else memory leak will occur 296 */ 297 nic->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS; 298 } 299 300 return flags; 301 } 302 303 static int 304 octeontx_dev_configure(struct rte_eth_dev *dev) 305 { 306 struct rte_eth_dev_data *data = dev->data; 307 struct rte_eth_conf *conf = &data->dev_conf; 308 struct rte_eth_rxmode *rxmode = &conf->rxmode; 309 struct rte_eth_txmode *txmode = &conf->txmode; 310 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 311 int ret; 312 313 PMD_INIT_FUNC_TRACE(); 314 RTE_SET_USED(conf); 315 316 if (!rte_eal_has_hugepages()) { 317 octeontx_log_err("huge page is not configured"); 318 return -EINVAL; 319 } 320 321 if (txmode->mq_mode) { 322 octeontx_log_err("tx mq_mode DCB or VMDq not supported"); 323 return -EINVAL; 324 } 325 326 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 327 rxmode->mq_mode != ETH_MQ_RX_RSS) { 328 octeontx_log_err("unsupported rx qmode %d", rxmode->mq_mode); 329 return -EINVAL; 330 } 331 332 if (!(txmode->offloads & DEV_TX_OFFLOAD_MT_LOCKFREE)) { 333 PMD_INIT_LOG(NOTICE, "cant disable lockfree tx"); 334 txmode->offloads |= DEV_TX_OFFLOAD_MT_LOCKFREE; 335 } 336 337 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 338 octeontx_log_err("setting link speed/duplex not supported"); 339 return -EINVAL; 340 } 341 342 if (conf->dcb_capability_en) { 343 octeontx_log_err("DCB enable not supported"); 344 return -EINVAL; 345 } 346 347 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 348 octeontx_log_err("flow director not supported"); 349 return -EINVAL; 350 } 351 352 nic->num_tx_queues = dev->data->nb_tx_queues; 353 354 ret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ, 355 nic->num_tx_queues, 356 nic->base_ochan); 357 if (ret) { 358 octeontx_log_err("failed to open channel %d no-of-txq %d", 359 nic->base_ochan, nic->num_tx_queues); 360 return -EFAULT; 361 } 362 363 ret = octeontx_dev_vlan_offload_init(dev); 364 if (ret) { 365 octeontx_log_err("failed to initialize vlan offload"); 366 return -EFAULT; 367 } 368 369 nic->pki.classifier_enable = false; 370 nic->pki.hash_enable = true; 371 nic->pki.initialized = false; 372 373 nic->rx_offloads |= rxmode->offloads; 374 nic->tx_offloads |= txmode->offloads; 375 nic->rx_offload_flags |= octeontx_rx_offload_flags(dev); 376 nic->tx_offload_flags |= octeontx_tx_offload_flags(dev); 377 378 return 0; 379 } 380 381 static void 382 octeontx_dev_close(struct rte_eth_dev *dev) 383 { 384 struct octeontx_txq *txq = NULL; 385 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 386 unsigned int i; 387 int ret; 388 389 PMD_INIT_FUNC_TRACE(); 390 391 rte_event_dev_close(nic->evdev); 392 393 octeontx_dev_vlan_offload_fini(dev); 394 395 ret = octeontx_pko_channel_close(nic->base_ochan); 396 if (ret < 0) { 397 octeontx_log_err("failed to close channel %d VF%d %d %d", 398 nic->base_ochan, nic->port_id, nic->num_tx_queues, 399 ret); 400 } 401 /* Free txq resources for this port */ 402 for (i = 0; i < nic->num_tx_queues; i++) { 403 txq = dev->data->tx_queues[i]; 404 if (!txq) 405 continue; 406 407 rte_free(txq); 408 } 409 410 /* Free MAC address table */ 411 rte_free(dev->data->mac_addrs); 412 dev->data->mac_addrs = NULL; 413 414 dev->tx_pkt_burst = NULL; 415 dev->rx_pkt_burst = NULL; 416 } 417 418 static int 419 octeontx_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 420 { 421 uint32_t buffsz, frame_size = mtu + OCCTX_L2_OVERHEAD; 422 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 423 struct rte_eth_dev_data *data = eth_dev->data; 424 int rc = 0; 425 426 /* Check if MTU is within the allowed range */ 427 if (frame_size < OCCTX_MIN_FRS || frame_size > OCCTX_MAX_FRS) 428 return -EINVAL; 429 430 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 431 432 /* Refuse MTU that requires the support of scattered packets 433 * when this feature has not been enabled before. 434 */ 435 if (data->dev_started && frame_size > buffsz && 436 !(nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER)) { 437 octeontx_log_err("Scatter mode is disabled"); 438 return -EINVAL; 439 } 440 441 /* Check <seg size> * <max_seg> >= max_frame */ 442 if ((nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) && 443 (frame_size > buffsz * OCCTX_RX_NB_SEG_MAX)) 444 return -EINVAL; 445 446 rc = octeontx_pko_send_mtu(nic->port_id, frame_size); 447 if (rc) 448 return rc; 449 450 rc = octeontx_bgx_port_mtu_set(nic->port_id, frame_size); 451 if (rc) 452 return rc; 453 454 if (frame_size > RTE_ETHER_MAX_LEN) 455 nic->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 456 else 457 nic->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 458 459 /* Update max_rx_pkt_len */ 460 data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 461 octeontx_log_info("Received pkt beyond maxlen %d will be dropped", 462 frame_size); 463 464 return rc; 465 } 466 467 static int 468 octeontx_recheck_rx_offloads(struct octeontx_rxq *rxq) 469 { 470 struct rte_eth_dev *eth_dev = rxq->eth_dev; 471 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 472 struct rte_eth_dev_data *data = eth_dev->data; 473 struct rte_pktmbuf_pool_private *mbp_priv; 474 struct evdev_priv_data *evdev_priv; 475 struct rte_eventdev *dev; 476 uint32_t buffsz; 477 478 /* Get rx buffer size */ 479 mbp_priv = rte_mempool_get_priv(rxq->pool); 480 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 481 482 /* Setup scatter mode if needed by jumbo */ 483 if (data->dev_conf.rxmode.max_rx_pkt_len > buffsz) { 484 nic->rx_offloads |= DEV_RX_OFFLOAD_SCATTER; 485 nic->rx_offload_flags |= octeontx_rx_offload_flags(eth_dev); 486 nic->tx_offload_flags |= octeontx_tx_offload_flags(eth_dev); 487 } 488 489 /* Sharing offload flags via eventdev priv region */ 490 dev = &rte_eventdevs[rxq->evdev]; 491 evdev_priv = dev->data->dev_private; 492 evdev_priv->rx_offload_flags = nic->rx_offload_flags; 493 evdev_priv->tx_offload_flags = nic->tx_offload_flags; 494 495 /* Setup MTU based on max_rx_pkt_len */ 496 nic->mtu = data->dev_conf.rxmode.max_rx_pkt_len - OCCTX_L2_OVERHEAD; 497 498 return 0; 499 } 500 501 static int 502 octeontx_dev_start(struct rte_eth_dev *dev) 503 { 504 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 505 struct octeontx_rxq *rxq; 506 int ret = 0, i; 507 508 PMD_INIT_FUNC_TRACE(); 509 /* Rechecking if any new offload set to update 510 * rx/tx burst function pointer accordingly. 511 */ 512 for (i = 0; i < dev->data->nb_rx_queues; i++) { 513 rxq = dev->data->rx_queues[i]; 514 octeontx_recheck_rx_offloads(rxq); 515 } 516 517 /* Setting up the mtu based on max_rx_pkt_len */ 518 ret = octeontx_dev_mtu_set(dev, nic->mtu); 519 if (ret) { 520 octeontx_log_err("Failed to set default MTU size %d", ret); 521 goto error; 522 } 523 524 /* 525 * Tx start 526 */ 527 octeontx_set_tx_function(dev); 528 ret = octeontx_pko_channel_start(nic->base_ochan); 529 if (ret < 0) { 530 octeontx_log_err("fail to conf VF%d no. txq %d chan %d ret %d", 531 nic->port_id, nic->num_tx_queues, nic->base_ochan, 532 ret); 533 goto error; 534 } 535 536 /* 537 * Rx start 538 */ 539 dev->rx_pkt_burst = octeontx_recv_pkts; 540 ret = octeontx_pki_port_start(nic->port_id); 541 if (ret < 0) { 542 octeontx_log_err("fail to start Rx on port %d", nic->port_id); 543 goto channel_stop_error; 544 } 545 546 /* 547 * Start port 548 */ 549 ret = octeontx_port_start(nic); 550 if (ret < 0) { 551 octeontx_log_err("failed start port %d", ret); 552 goto pki_port_stop_error; 553 } 554 555 PMD_TX_LOG(DEBUG, "pko: start channel %d no.of txq %d port %d", 556 nic->base_ochan, nic->num_tx_queues, nic->port_id); 557 558 ret = rte_event_dev_start(nic->evdev); 559 if (ret < 0) { 560 octeontx_log_err("failed to start evdev: ret (%d)", ret); 561 goto pki_port_stop_error; 562 } 563 564 /* Success */ 565 return ret; 566 567 pki_port_stop_error: 568 octeontx_pki_port_stop(nic->port_id); 569 channel_stop_error: 570 octeontx_pko_channel_stop(nic->base_ochan); 571 error: 572 return ret; 573 } 574 575 static void 576 octeontx_dev_stop(struct rte_eth_dev *dev) 577 { 578 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 579 int ret; 580 581 PMD_INIT_FUNC_TRACE(); 582 583 rte_event_dev_stop(nic->evdev); 584 585 ret = octeontx_port_stop(nic); 586 if (ret < 0) { 587 octeontx_log_err("failed to req stop port %d res=%d", 588 nic->port_id, ret); 589 return; 590 } 591 592 ret = octeontx_pki_port_stop(nic->port_id); 593 if (ret < 0) { 594 octeontx_log_err("failed to stop pki port %d res=%d", 595 nic->port_id, ret); 596 return; 597 } 598 599 ret = octeontx_pko_channel_stop(nic->base_ochan); 600 if (ret < 0) { 601 octeontx_log_err("failed to stop channel %d VF%d %d %d", 602 nic->base_ochan, nic->port_id, nic->num_tx_queues, 603 ret); 604 return; 605 } 606 } 607 608 static int 609 octeontx_dev_promisc_enable(struct rte_eth_dev *dev) 610 { 611 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 612 613 PMD_INIT_FUNC_TRACE(); 614 return octeontx_port_promisc_set(nic, 1); 615 } 616 617 static int 618 octeontx_dev_promisc_disable(struct rte_eth_dev *dev) 619 { 620 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 621 622 PMD_INIT_FUNC_TRACE(); 623 return octeontx_port_promisc_set(nic, 0); 624 } 625 626 static int 627 octeontx_port_link_status(struct octeontx_nic *nic) 628 { 629 int res; 630 631 PMD_INIT_FUNC_TRACE(); 632 res = octeontx_bgx_port_link_status(nic->port_id); 633 if (res < 0) { 634 octeontx_log_err("failed to get port %d link status", 635 nic->port_id); 636 return res; 637 } 638 639 nic->link_up = (uint8_t)res; 640 octeontx_log_dbg("port %d link status %d", nic->port_id, nic->link_up); 641 642 return res; 643 } 644 645 /* 646 * Return 0 means link status changed, -1 means not changed 647 */ 648 static int 649 octeontx_dev_link_update(struct rte_eth_dev *dev, 650 int wait_to_complete __rte_unused) 651 { 652 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 653 struct rte_eth_link link; 654 int res; 655 656 PMD_INIT_FUNC_TRACE(); 657 658 res = octeontx_port_link_status(nic); 659 if (res < 0) { 660 octeontx_log_err("failed to request link status %d", res); 661 return res; 662 } 663 664 link.link_status = nic->link_up; 665 666 switch (nic->speed) { 667 case OCTEONTX_LINK_SPEED_SGMII: 668 link.link_speed = ETH_SPEED_NUM_1G; 669 break; 670 671 case OCTEONTX_LINK_SPEED_XAUI: 672 link.link_speed = ETH_SPEED_NUM_10G; 673 break; 674 675 case OCTEONTX_LINK_SPEED_RXAUI: 676 case OCTEONTX_LINK_SPEED_10G_R: 677 link.link_speed = ETH_SPEED_NUM_10G; 678 break; 679 case OCTEONTX_LINK_SPEED_QSGMII: 680 link.link_speed = ETH_SPEED_NUM_5G; 681 break; 682 case OCTEONTX_LINK_SPEED_40G_R: 683 link.link_speed = ETH_SPEED_NUM_40G; 684 break; 685 686 case OCTEONTX_LINK_SPEED_RESERVE1: 687 case OCTEONTX_LINK_SPEED_RESERVE2: 688 default: 689 link.link_speed = ETH_SPEED_NUM_NONE; 690 octeontx_log_err("incorrect link speed %d", nic->speed); 691 break; 692 } 693 694 link.link_duplex = ETH_LINK_FULL_DUPLEX; 695 link.link_autoneg = ETH_LINK_AUTONEG; 696 697 return rte_eth_linkstatus_set(dev, &link); 698 } 699 700 static int 701 octeontx_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 702 { 703 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 704 705 PMD_INIT_FUNC_TRACE(); 706 return octeontx_port_stats(nic, stats); 707 } 708 709 static int 710 octeontx_dev_stats_reset(struct rte_eth_dev *dev) 711 { 712 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 713 714 PMD_INIT_FUNC_TRACE(); 715 return octeontx_port_stats_clr(nic); 716 } 717 718 static void 719 octeontx_dev_mac_addr_del(struct rte_eth_dev *dev, uint32_t index) 720 { 721 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 722 int ret; 723 724 ret = octeontx_bgx_port_mac_del(nic->port_id, index); 725 if (ret != 0) 726 octeontx_log_err("failed to del MAC address filter on port %d", 727 nic->port_id); 728 } 729 730 static int 731 octeontx_dev_mac_addr_add(struct rte_eth_dev *dev, 732 struct rte_ether_addr *mac_addr, 733 uint32_t index, 734 __rte_unused uint32_t vmdq) 735 { 736 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 737 int ret; 738 739 ret = octeontx_bgx_port_mac_add(nic->port_id, mac_addr->addr_bytes, 740 index); 741 if (ret < 0) { 742 octeontx_log_err("failed to add MAC address filter on port %d", 743 nic->port_id); 744 return ret; 745 } 746 747 return 0; 748 } 749 750 static int 751 octeontx_dev_default_mac_addr_set(struct rte_eth_dev *dev, 752 struct rte_ether_addr *addr) 753 { 754 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 755 int ret; 756 757 ret = octeontx_bgx_port_mac_set(nic->port_id, addr->addr_bytes); 758 if (ret == 0) { 759 /* Update same mac address to BGX CAM table */ 760 ret = octeontx_bgx_port_mac_add(nic->port_id, addr->addr_bytes, 761 0); 762 } 763 if (ret < 0) { 764 octeontx_log_err("failed to set MAC address on port %d", 765 nic->port_id); 766 } 767 768 return ret; 769 } 770 771 static int 772 octeontx_dev_info(struct rte_eth_dev *dev, 773 struct rte_eth_dev_info *dev_info) 774 { 775 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 776 777 /* Autonegotiation may be disabled */ 778 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 779 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 780 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | 781 ETH_LINK_SPEED_40G; 782 783 /* Min/Max MTU supported */ 784 dev_info->min_rx_bufsize = OCCTX_MIN_FRS; 785 dev_info->max_rx_pktlen = OCCTX_MAX_FRS; 786 dev_info->max_mtu = dev_info->max_rx_pktlen - OCCTX_L2_OVERHEAD; 787 dev_info->min_mtu = dev_info->min_rx_bufsize - OCCTX_L2_OVERHEAD; 788 789 dev_info->max_mac_addrs = 790 octeontx_bgx_port_mac_entries_get(nic->port_id); 791 dev_info->max_rx_pktlen = PKI_MAX_PKTLEN; 792 dev_info->max_rx_queues = 1; 793 dev_info->max_tx_queues = PKO_MAX_NUM_DQ; 794 dev_info->min_rx_bufsize = 0; 795 796 dev_info->default_rxconf = (struct rte_eth_rxconf) { 797 .rx_free_thresh = 0, 798 .rx_drop_en = 0, 799 .offloads = OCTEONTX_RX_OFFLOADS, 800 }; 801 802 dev_info->default_txconf = (struct rte_eth_txconf) { 803 .tx_free_thresh = 0, 804 .offloads = OCTEONTX_TX_OFFLOADS, 805 }; 806 807 dev_info->rx_offload_capa = OCTEONTX_RX_OFFLOADS; 808 dev_info->tx_offload_capa = OCTEONTX_TX_OFFLOADS; 809 dev_info->rx_queue_offload_capa = OCTEONTX_RX_OFFLOADS; 810 dev_info->tx_queue_offload_capa = OCTEONTX_TX_OFFLOADS; 811 812 return 0; 813 } 814 815 static void 816 octeontx_dq_info_getter(octeontx_dq_t *dq, void *out) 817 { 818 ((octeontx_dq_t *)out)->lmtline_va = dq->lmtline_va; 819 ((octeontx_dq_t *)out)->ioreg_va = dq->ioreg_va; 820 ((octeontx_dq_t *)out)->fc_status_va = dq->fc_status_va; 821 } 822 823 static int 824 octeontx_vf_start_tx_queue(struct rte_eth_dev *dev, struct octeontx_nic *nic, 825 uint16_t qidx) 826 { 827 struct octeontx_txq *txq; 828 int res; 829 830 PMD_INIT_FUNC_TRACE(); 831 832 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) 833 return 0; 834 835 txq = dev->data->tx_queues[qidx]; 836 837 res = octeontx_pko_channel_query_dqs(nic->base_ochan, 838 &txq->dq, 839 sizeof(octeontx_dq_t), 840 txq->queue_id, 841 octeontx_dq_info_getter); 842 if (res < 0) { 843 res = -EFAULT; 844 goto close_port; 845 } 846 847 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 848 return res; 849 850 close_port: 851 (void)octeontx_port_stop(nic); 852 octeontx_pko_channel_stop(nic->base_ochan); 853 octeontx_pko_channel_close(nic->base_ochan); 854 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 855 return res; 856 } 857 858 static int 859 octeontx_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 860 { 861 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 862 863 PMD_INIT_FUNC_TRACE(); 864 qidx = qidx % PKO_VF_NUM_DQ; 865 return octeontx_vf_start_tx_queue(dev, nic, qidx); 866 } 867 868 static inline int 869 octeontx_vf_stop_tx_queue(struct rte_eth_dev *dev, struct octeontx_nic *nic, 870 uint16_t qidx) 871 { 872 int ret = 0; 873 874 RTE_SET_USED(nic); 875 PMD_INIT_FUNC_TRACE(); 876 877 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) 878 return 0; 879 880 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 881 return ret; 882 } 883 884 static int 885 octeontx_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 886 { 887 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 888 889 PMD_INIT_FUNC_TRACE(); 890 qidx = qidx % PKO_VF_NUM_DQ; 891 892 return octeontx_vf_stop_tx_queue(dev, nic, qidx); 893 } 894 895 static void 896 octeontx_dev_tx_queue_release(void *tx_queue) 897 { 898 struct octeontx_txq *txq = tx_queue; 899 int res; 900 901 PMD_INIT_FUNC_TRACE(); 902 903 if (txq) { 904 res = octeontx_dev_tx_queue_stop(txq->eth_dev, txq->queue_id); 905 if (res < 0) 906 octeontx_log_err("failed stop tx_queue(%d)\n", 907 txq->queue_id); 908 909 rte_free(txq); 910 } 911 } 912 913 static int 914 octeontx_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 915 uint16_t nb_desc, unsigned int socket_id, 916 const struct rte_eth_txconf *tx_conf __rte_unused) 917 { 918 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 919 struct octeontx_txq *txq = NULL; 920 uint16_t dq_num; 921 int res = 0; 922 923 RTE_SET_USED(nb_desc); 924 RTE_SET_USED(socket_id); 925 926 dq_num = (nic->pko_vfid * PKO_VF_NUM_DQ) + qidx; 927 928 /* Socket id check */ 929 if (socket_id != (unsigned int)SOCKET_ID_ANY && 930 socket_id != (unsigned int)nic->node) 931 PMD_TX_LOG(INFO, "socket_id expected %d, configured %d", 932 socket_id, nic->node); 933 934 /* Free memory prior to re-allocation if needed. */ 935 if (dev->data->tx_queues[qidx] != NULL) { 936 PMD_TX_LOG(DEBUG, "freeing memory prior to re-allocation %d", 937 qidx); 938 octeontx_dev_tx_queue_release(dev->data->tx_queues[qidx]); 939 dev->data->tx_queues[qidx] = NULL; 940 } 941 942 /* Allocating tx queue data structure */ 943 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct octeontx_txq), 944 RTE_CACHE_LINE_SIZE, nic->node); 945 if (txq == NULL) { 946 octeontx_log_err("failed to allocate txq=%d", qidx); 947 res = -ENOMEM; 948 goto err; 949 } 950 951 txq->eth_dev = dev; 952 txq->queue_id = dq_num; 953 dev->data->tx_queues[qidx] = txq; 954 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 955 956 res = octeontx_pko_channel_query_dqs(nic->base_ochan, 957 &txq->dq, 958 sizeof(octeontx_dq_t), 959 txq->queue_id, 960 octeontx_dq_info_getter); 961 if (res < 0) { 962 res = -EFAULT; 963 goto err; 964 } 965 966 PMD_TX_LOG(DEBUG, "[%d]:[%d] txq=%p nb_desc=%d lmtline=%p ioreg_va=%p fc_status_va=%p", 967 qidx, txq->queue_id, txq, nb_desc, txq->dq.lmtline_va, 968 txq->dq.ioreg_va, 969 txq->dq.fc_status_va); 970 971 return res; 972 973 err: 974 if (txq) 975 rte_free(txq); 976 977 return res; 978 } 979 980 static int 981 octeontx_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 982 uint16_t nb_desc, unsigned int socket_id, 983 const struct rte_eth_rxconf *rx_conf, 984 struct rte_mempool *mb_pool) 985 { 986 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 987 struct rte_mempool_ops *mp_ops = NULL; 988 struct octeontx_rxq *rxq = NULL; 989 pki_pktbuf_cfg_t pktbuf_conf; 990 pki_hash_cfg_t pki_hash; 991 pki_qos_cfg_t pki_qos; 992 uintptr_t pool; 993 int ret, port; 994 uint16_t gaura; 995 unsigned int ev_queues = (nic->ev_queues * nic->port_id) + qidx; 996 unsigned int ev_ports = (nic->ev_ports * nic->port_id) + qidx; 997 998 RTE_SET_USED(nb_desc); 999 1000 memset(&pktbuf_conf, 0, sizeof(pktbuf_conf)); 1001 memset(&pki_hash, 0, sizeof(pki_hash)); 1002 memset(&pki_qos, 0, sizeof(pki_qos)); 1003 1004 mp_ops = rte_mempool_get_ops(mb_pool->ops_index); 1005 if (strcmp(mp_ops->name, "octeontx_fpavf")) { 1006 octeontx_log_err("failed to find octeontx_fpavf mempool"); 1007 return -ENOTSUP; 1008 } 1009 1010 /* Handle forbidden configurations */ 1011 if (nic->pki.classifier_enable) { 1012 octeontx_log_err("cannot setup queue %d. " 1013 "Classifier option unsupported", qidx); 1014 return -EINVAL; 1015 } 1016 1017 port = nic->port_id; 1018 1019 /* Rx deferred start is not supported */ 1020 if (rx_conf->rx_deferred_start) { 1021 octeontx_log_err("rx deferred start not supported"); 1022 return -EINVAL; 1023 } 1024 1025 /* Verify queue index */ 1026 if (qidx >= dev->data->nb_rx_queues) { 1027 octeontx_log_err("QID %d not supporteded (0 - %d available)\n", 1028 qidx, (dev->data->nb_rx_queues - 1)); 1029 return -ENOTSUP; 1030 } 1031 1032 /* Socket id check */ 1033 if (socket_id != (unsigned int)SOCKET_ID_ANY && 1034 socket_id != (unsigned int)nic->node) 1035 PMD_RX_LOG(INFO, "socket_id expected %d, configured %d", 1036 socket_id, nic->node); 1037 1038 /* Allocating rx queue data structure */ 1039 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct octeontx_rxq), 1040 RTE_CACHE_LINE_SIZE, nic->node); 1041 if (rxq == NULL) { 1042 octeontx_log_err("failed to allocate rxq=%d", qidx); 1043 return -ENOMEM; 1044 } 1045 1046 if (!nic->pki.initialized) { 1047 pktbuf_conf.port_type = 0; 1048 pki_hash.port_type = 0; 1049 pki_qos.port_type = 0; 1050 1051 pktbuf_conf.mmask.f_wqe_skip = 1; 1052 pktbuf_conf.mmask.f_first_skip = 1; 1053 pktbuf_conf.mmask.f_later_skip = 1; 1054 pktbuf_conf.mmask.f_mbuff_size = 1; 1055 pktbuf_conf.mmask.f_cache_mode = 1; 1056 1057 pktbuf_conf.wqe_skip = OCTTX_PACKET_WQE_SKIP; 1058 pktbuf_conf.first_skip = OCTTX_PACKET_FIRST_SKIP(mb_pool); 1059 pktbuf_conf.later_skip = OCTTX_PACKET_LATER_SKIP; 1060 pktbuf_conf.mbuff_size = (mb_pool->elt_size - 1061 RTE_PKTMBUF_HEADROOM - 1062 rte_pktmbuf_priv_size(mb_pool) - 1063 sizeof(struct rte_mbuf)); 1064 1065 pktbuf_conf.cache_mode = PKI_OPC_MODE_STF2_STT; 1066 1067 ret = octeontx_pki_port_pktbuf_config(port, &pktbuf_conf); 1068 if (ret != 0) { 1069 octeontx_log_err("fail to configure pktbuf for port %d", 1070 port); 1071 rte_free(rxq); 1072 return ret; 1073 } 1074 PMD_RX_LOG(DEBUG, "Port %d Rx pktbuf configured:\n" 1075 "\tmbuf_size:\t0x%0x\n" 1076 "\twqe_skip:\t0x%0x\n" 1077 "\tfirst_skip:\t0x%0x\n" 1078 "\tlater_skip:\t0x%0x\n" 1079 "\tcache_mode:\t%s\n", 1080 port, 1081 pktbuf_conf.mbuff_size, 1082 pktbuf_conf.wqe_skip, 1083 pktbuf_conf.first_skip, 1084 pktbuf_conf.later_skip, 1085 (pktbuf_conf.cache_mode == 1086 PKI_OPC_MODE_STT) ? 1087 "STT" : 1088 (pktbuf_conf.cache_mode == 1089 PKI_OPC_MODE_STF) ? 1090 "STF" : 1091 (pktbuf_conf.cache_mode == 1092 PKI_OPC_MODE_STF1_STT) ? 1093 "STF1_STT" : "STF2_STT"); 1094 1095 if (nic->pki.hash_enable) { 1096 pki_hash.tag_dlc = 1; 1097 pki_hash.tag_slc = 1; 1098 pki_hash.tag_dlf = 1; 1099 pki_hash.tag_slf = 1; 1100 pki_hash.tag_prt = 1; 1101 octeontx_pki_port_hash_config(port, &pki_hash); 1102 } 1103 1104 pool = (uintptr_t)mb_pool->pool_id; 1105 1106 /* Get the gaura Id */ 1107 gaura = octeontx_fpa_bufpool_gaura(pool); 1108 1109 pki_qos.qpg_qos = PKI_QPG_QOS_NONE; 1110 pki_qos.num_entry = 1; 1111 pki_qos.drop_policy = 0; 1112 pki_qos.tag_type = 0L; 1113 pki_qos.qos_entry[0].port_add = 0; 1114 pki_qos.qos_entry[0].gaura = gaura; 1115 pki_qos.qos_entry[0].ggrp_ok = ev_queues; 1116 pki_qos.qos_entry[0].ggrp_bad = ev_queues; 1117 pki_qos.qos_entry[0].grptag_bad = 0; 1118 pki_qos.qos_entry[0].grptag_ok = 0; 1119 1120 ret = octeontx_pki_port_create_qos(port, &pki_qos); 1121 if (ret < 0) { 1122 octeontx_log_err("failed to create QOS port=%d, q=%d", 1123 port, qidx); 1124 rte_free(rxq); 1125 return ret; 1126 } 1127 nic->pki.initialized = true; 1128 } 1129 1130 rxq->port_id = nic->port_id; 1131 rxq->eth_dev = dev; 1132 rxq->queue_id = qidx; 1133 rxq->evdev = nic->evdev; 1134 rxq->ev_queues = ev_queues; 1135 rxq->ev_ports = ev_ports; 1136 rxq->pool = mb_pool; 1137 1138 octeontx_recheck_rx_offloads(rxq); 1139 dev->data->rx_queues[qidx] = rxq; 1140 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1141 return 0; 1142 } 1143 1144 static void 1145 octeontx_dev_rx_queue_release(void *rxq) 1146 { 1147 rte_free(rxq); 1148 } 1149 1150 static const uint32_t * 1151 octeontx_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1152 { 1153 static const uint32_t ptypes[] = { 1154 RTE_PTYPE_L3_IPV4, 1155 RTE_PTYPE_L3_IPV4_EXT, 1156 RTE_PTYPE_L3_IPV6, 1157 RTE_PTYPE_L3_IPV6_EXT, 1158 RTE_PTYPE_L4_TCP, 1159 RTE_PTYPE_L4_UDP, 1160 RTE_PTYPE_L4_FRAG, 1161 RTE_PTYPE_UNKNOWN 1162 }; 1163 1164 if (dev->rx_pkt_burst == octeontx_recv_pkts) 1165 return ptypes; 1166 1167 return NULL; 1168 } 1169 1170 static int 1171 octeontx_pool_ops(struct rte_eth_dev *dev, const char *pool) 1172 { 1173 RTE_SET_USED(dev); 1174 1175 if (!strcmp(pool, "octeontx_fpavf")) 1176 return 0; 1177 1178 return -ENOTSUP; 1179 } 1180 1181 /* Initialize and register driver with DPDK Application */ 1182 static const struct eth_dev_ops octeontx_dev_ops = { 1183 .dev_configure = octeontx_dev_configure, 1184 .dev_infos_get = octeontx_dev_info, 1185 .dev_close = octeontx_dev_close, 1186 .dev_start = octeontx_dev_start, 1187 .dev_stop = octeontx_dev_stop, 1188 .promiscuous_enable = octeontx_dev_promisc_enable, 1189 .promiscuous_disable = octeontx_dev_promisc_disable, 1190 .link_update = octeontx_dev_link_update, 1191 .stats_get = octeontx_dev_stats_get, 1192 .stats_reset = octeontx_dev_stats_reset, 1193 .mac_addr_remove = octeontx_dev_mac_addr_del, 1194 .mac_addr_add = octeontx_dev_mac_addr_add, 1195 .mac_addr_set = octeontx_dev_default_mac_addr_set, 1196 .vlan_offload_set = octeontx_dev_vlan_offload_set, 1197 .vlan_filter_set = octeontx_dev_vlan_filter_set, 1198 .tx_queue_start = octeontx_dev_tx_queue_start, 1199 .tx_queue_stop = octeontx_dev_tx_queue_stop, 1200 .tx_queue_setup = octeontx_dev_tx_queue_setup, 1201 .tx_queue_release = octeontx_dev_tx_queue_release, 1202 .rx_queue_setup = octeontx_dev_rx_queue_setup, 1203 .rx_queue_release = octeontx_dev_rx_queue_release, 1204 .dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get, 1205 .mtu_set = octeontx_dev_mtu_set, 1206 .pool_ops_supported = octeontx_pool_ops, 1207 }; 1208 1209 /* Create Ethdev interface per BGX LMAC ports */ 1210 static int 1211 octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev, 1212 int socket_id) 1213 { 1214 int res; 1215 size_t pko_vfid; 1216 char octtx_name[OCTEONTX_MAX_NAME_LEN]; 1217 struct octeontx_nic *nic = NULL; 1218 struct rte_eth_dev *eth_dev = NULL; 1219 struct rte_eth_dev_data *data; 1220 const char *name = rte_vdev_device_name(dev); 1221 int max_entries; 1222 1223 PMD_INIT_FUNC_TRACE(); 1224 1225 sprintf(octtx_name, "%s_%d", name, port); 1226 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1227 eth_dev = rte_eth_dev_attach_secondary(octtx_name); 1228 if (eth_dev == NULL) 1229 return -ENODEV; 1230 1231 eth_dev->dev_ops = &octeontx_dev_ops; 1232 eth_dev->device = &dev->device; 1233 octeontx_set_tx_function(eth_dev); 1234 eth_dev->rx_pkt_burst = octeontx_recv_pkts; 1235 rte_eth_dev_probing_finish(eth_dev); 1236 return 0; 1237 } 1238 1239 /* Reserve an ethdev entry */ 1240 eth_dev = rte_eth_dev_allocate(octtx_name); 1241 if (eth_dev == NULL) { 1242 octeontx_log_err("failed to allocate rte_eth_dev"); 1243 res = -ENOMEM; 1244 goto err; 1245 } 1246 data = eth_dev->data; 1247 1248 nic = rte_zmalloc_socket(octtx_name, sizeof(*nic), 0, socket_id); 1249 if (nic == NULL) { 1250 octeontx_log_err("failed to allocate nic structure"); 1251 res = -ENOMEM; 1252 goto err; 1253 } 1254 data->dev_private = nic; 1255 pko_vfid = octeontx_pko_get_vfid(); 1256 1257 if (pko_vfid == SIZE_MAX) { 1258 octeontx_log_err("failed to get pko vfid"); 1259 res = -ENODEV; 1260 goto err; 1261 } 1262 1263 nic->pko_vfid = pko_vfid; 1264 nic->port_id = port; 1265 nic->evdev = evdev; 1266 1267 res = octeontx_port_open(nic); 1268 if (res < 0) 1269 goto err; 1270 1271 /* Rx side port configuration */ 1272 res = octeontx_pki_port_open(port); 1273 if (res != 0) { 1274 octeontx_log_err("failed to open PKI port %d", port); 1275 res = -ENODEV; 1276 goto err; 1277 } 1278 1279 eth_dev->device = &dev->device; 1280 eth_dev->intr_handle = NULL; 1281 eth_dev->data->kdrv = RTE_KDRV_NONE; 1282 eth_dev->data->numa_node = dev->device.numa_node; 1283 1284 data->port_id = eth_dev->data->port_id; 1285 1286 nic->ev_queues = 1; 1287 nic->ev_ports = 1; 1288 1289 data->dev_link.link_status = ETH_LINK_DOWN; 1290 data->dev_started = 0; 1291 data->promiscuous = 0; 1292 data->all_multicast = 0; 1293 data->scattered_rx = 0; 1294 1295 /* Get maximum number of supported MAC entries */ 1296 max_entries = octeontx_bgx_port_mac_entries_get(nic->port_id); 1297 if (max_entries < 0) { 1298 octeontx_log_err("Failed to get max entries for mac addr"); 1299 res = -ENOTSUP; 1300 goto err; 1301 } 1302 1303 data->mac_addrs = rte_zmalloc_socket(octtx_name, max_entries * 1304 RTE_ETHER_ADDR_LEN, 0, 1305 socket_id); 1306 if (data->mac_addrs == NULL) { 1307 octeontx_log_err("failed to allocate memory for mac_addrs"); 1308 res = -ENOMEM; 1309 goto err; 1310 } 1311 1312 eth_dev->dev_ops = &octeontx_dev_ops; 1313 1314 /* Finally save ethdev pointer to the NIC structure */ 1315 nic->dev = eth_dev; 1316 1317 if (nic->port_id != data->port_id) { 1318 octeontx_log_err("eth_dev->port_id (%d) is diff to orig (%d)", 1319 data->port_id, nic->port_id); 1320 res = -EINVAL; 1321 goto free_mac_addrs; 1322 } 1323 1324 /* Update port_id mac to eth_dev */ 1325 memcpy(data->mac_addrs, nic->mac_addr, RTE_ETHER_ADDR_LEN); 1326 1327 /* Update same mac address to BGX CAM table at index 0 */ 1328 octeontx_bgx_port_mac_add(nic->port_id, nic->mac_addr, 0); 1329 1330 PMD_INIT_LOG(DEBUG, "ethdev info: "); 1331 PMD_INIT_LOG(DEBUG, "port %d, port_ena %d ochan %d num_ochan %d tx_q %d", 1332 nic->port_id, nic->port_ena, 1333 nic->base_ochan, nic->num_ochans, 1334 nic->num_tx_queues); 1335 PMD_INIT_LOG(DEBUG, "speed %d mtu %d", nic->speed, nic->bgx_mtu); 1336 1337 rte_octeontx_pchan_map[(nic->base_ochan >> 8) & 0x7] 1338 [(nic->base_ochan >> 4) & 0xF] = data->port_id; 1339 1340 rte_eth_dev_probing_finish(eth_dev); 1341 return data->port_id; 1342 1343 free_mac_addrs: 1344 rte_free(data->mac_addrs); 1345 err: 1346 if (nic) 1347 octeontx_port_close(nic); 1348 1349 rte_eth_dev_release_port(eth_dev); 1350 1351 return res; 1352 } 1353 1354 /* Un initialize octeontx device */ 1355 static int 1356 octeontx_remove(struct rte_vdev_device *dev) 1357 { 1358 char octtx_name[OCTEONTX_MAX_NAME_LEN]; 1359 struct rte_eth_dev *eth_dev = NULL; 1360 struct octeontx_nic *nic = NULL; 1361 int i; 1362 1363 if (dev == NULL) 1364 return -EINVAL; 1365 1366 for (i = 0; i < OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT; i++) { 1367 sprintf(octtx_name, "eth_octeontx_%d", i); 1368 1369 /* reserve an ethdev entry */ 1370 eth_dev = rte_eth_dev_allocated(octtx_name); 1371 if (eth_dev == NULL) 1372 return -ENODEV; 1373 1374 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1375 rte_eth_dev_release_port(eth_dev); 1376 continue; 1377 } 1378 1379 nic = octeontx_pmd_priv(eth_dev); 1380 rte_event_dev_stop(nic->evdev); 1381 PMD_INIT_LOG(INFO, "Closing octeontx device %s", octtx_name); 1382 1383 rte_eth_dev_release_port(eth_dev); 1384 rte_event_dev_close(nic->evdev); 1385 } 1386 1387 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1388 return 0; 1389 1390 /* Free FC resource */ 1391 octeontx_pko_fc_free(); 1392 1393 return 0; 1394 } 1395 1396 /* Initialize octeontx device */ 1397 static int 1398 octeontx_probe(struct rte_vdev_device *dev) 1399 { 1400 const char *dev_name; 1401 static int probe_once; 1402 uint8_t socket_id, qlist; 1403 int tx_vfcnt, port_id, evdev, qnum, pnum, res, i; 1404 struct rte_event_dev_config dev_conf; 1405 const char *eventdev_name = "event_octeontx"; 1406 struct rte_event_dev_info info; 1407 struct rte_eth_dev *eth_dev; 1408 1409 struct octeontx_vdev_init_params init_params = { 1410 OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 1411 }; 1412 1413 dev_name = rte_vdev_device_name(dev); 1414 1415 if (rte_eal_process_type() == RTE_PROC_SECONDARY && 1416 strlen(rte_vdev_device_args(dev)) == 0) { 1417 eth_dev = rte_eth_dev_attach_secondary(dev_name); 1418 if (!eth_dev) { 1419 PMD_INIT_LOG(ERR, "Failed to probe %s", dev_name); 1420 return -1; 1421 } 1422 /* TODO: request info from primary to set up Rx and Tx */ 1423 eth_dev->dev_ops = &octeontx_dev_ops; 1424 eth_dev->device = &dev->device; 1425 rte_eth_dev_probing_finish(eth_dev); 1426 return 0; 1427 } 1428 1429 res = octeontx_parse_vdev_init_params(&init_params, dev); 1430 if (res < 0) 1431 return -EINVAL; 1432 1433 if (init_params.nr_port > OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT) { 1434 octeontx_log_err("nr_port (%d) > max (%d)", init_params.nr_port, 1435 OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT); 1436 return -ENOTSUP; 1437 } 1438 1439 PMD_INIT_LOG(DEBUG, "initializing %s pmd", dev_name); 1440 1441 socket_id = rte_socket_id(); 1442 1443 tx_vfcnt = octeontx_pko_vf_count(); 1444 1445 if (tx_vfcnt < init_params.nr_port) { 1446 octeontx_log_err("not enough PKO (%d) for port number (%d)", 1447 tx_vfcnt, init_params.nr_port); 1448 return -EINVAL; 1449 } 1450 evdev = rte_event_dev_get_dev_id(eventdev_name); 1451 if (evdev < 0) { 1452 octeontx_log_err("eventdev %s not found", eventdev_name); 1453 return -ENODEV; 1454 } 1455 1456 res = rte_event_dev_info_get(evdev, &info); 1457 if (res < 0) { 1458 octeontx_log_err("failed to eventdev info %d", res); 1459 return -EINVAL; 1460 } 1461 1462 PMD_INIT_LOG(DEBUG, "max_queue %d max_port %d", 1463 info.max_event_queues, info.max_event_ports); 1464 1465 if (octeontx_pko_init_fc(tx_vfcnt)) 1466 return -ENOMEM; 1467 1468 devconf_set_default_sane_values(&dev_conf, &info); 1469 res = rte_event_dev_configure(evdev, &dev_conf); 1470 if (res < 0) 1471 goto parse_error; 1472 1473 rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, 1474 (uint32_t *)&pnum); 1475 rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, 1476 (uint32_t *)&qnum); 1477 if (pnum < qnum) { 1478 octeontx_log_err("too few event ports (%d) for event_q(%d)", 1479 pnum, qnum); 1480 res = -EINVAL; 1481 goto parse_error; 1482 } 1483 1484 /* Enable all queues available */ 1485 for (i = 0; i < qnum; i++) { 1486 res = rte_event_queue_setup(evdev, i, NULL); 1487 if (res < 0) { 1488 octeontx_log_err("failed to setup event_q(%d): res %d", 1489 i, res); 1490 goto parse_error; 1491 } 1492 } 1493 1494 /* Enable all ports available */ 1495 for (i = 0; i < pnum; i++) { 1496 res = rte_event_port_setup(evdev, i, NULL); 1497 if (res < 0) { 1498 res = -ENODEV; 1499 octeontx_log_err("failed to setup ev port(%d) res=%d", 1500 i, res); 1501 goto parse_error; 1502 } 1503 } 1504 1505 /* 1506 * Do 1:1 links for ports & queues. All queues would be mapped to 1507 * one port. If there are more ports than queues, then some ports 1508 * won't be linked to any queue. 1509 */ 1510 for (i = 0; i < qnum; i++) { 1511 /* Link one queue to one event port */ 1512 qlist = i; 1513 res = rte_event_port_link(evdev, i, &qlist, NULL, 1); 1514 if (res < 0) { 1515 res = -ENODEV; 1516 octeontx_log_err("failed to link port (%d): res=%d", 1517 i, res); 1518 goto parse_error; 1519 } 1520 } 1521 1522 /* Create ethdev interface */ 1523 for (i = 0; i < init_params.nr_port; i++) { 1524 port_id = octeontx_create(dev, i, evdev, socket_id); 1525 if (port_id < 0) { 1526 octeontx_log_err("failed to create device %s", 1527 dev_name); 1528 res = -ENODEV; 1529 goto parse_error; 1530 } 1531 1532 PMD_INIT_LOG(INFO, "created ethdev %s for port %d", dev_name, 1533 port_id); 1534 } 1535 1536 if (probe_once) { 1537 octeontx_log_err("interface %s not supported", dev_name); 1538 octeontx_remove(dev); 1539 res = -ENOTSUP; 1540 goto parse_error; 1541 } 1542 rte_mbuf_set_platform_mempool_ops("octeontx_fpavf"); 1543 probe_once = 1; 1544 1545 return 0; 1546 1547 parse_error: 1548 octeontx_pko_fc_free(); 1549 return res; 1550 } 1551 1552 static struct rte_vdev_driver octeontx_pmd_drv = { 1553 .probe = octeontx_probe, 1554 .remove = octeontx_remove, 1555 }; 1556 1557 RTE_PMD_REGISTER_VDEV(OCTEONTX_PMD, octeontx_pmd_drv); 1558 RTE_PMD_REGISTER_ALIAS(OCTEONTX_PMD, eth_octeontx); 1559 RTE_PMD_REGISTER_PARAM_STRING(OCTEONTX_PMD, "nr_port=<int> "); 1560