1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <stdio.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 12 #include <rte_alarm.h> 13 #include <rte_branch_prediction.h> 14 #include <rte_bus_vdev.h> 15 #include <rte_cycles.h> 16 #include <rte_debug.h> 17 #include <rte_devargs.h> 18 #include <rte_dev.h> 19 #include <rte_kvargs.h> 20 #include <rte_malloc.h> 21 #include <rte_mbuf_pool_ops.h> 22 #include <rte_prefetch.h> 23 24 #include "octeontx_ethdev.h" 25 #include "octeontx_rxtx.h" 26 #include "octeontx_logs.h" 27 28 struct evdev_priv_data { 29 OFFLOAD_FLAGS; /*Sequence should not be changed */ 30 } __rte_cache_aligned; 31 32 struct octeontx_vdev_init_params { 33 uint8_t nr_port; 34 }; 35 36 uint16_t 37 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX]; 38 39 enum octeontx_link_speed { 40 OCTEONTX_LINK_SPEED_SGMII, 41 OCTEONTX_LINK_SPEED_XAUI, 42 OCTEONTX_LINK_SPEED_RXAUI, 43 OCTEONTX_LINK_SPEED_10G_R, 44 OCTEONTX_LINK_SPEED_40G_R, 45 OCTEONTX_LINK_SPEED_RESERVE1, 46 OCTEONTX_LINK_SPEED_QSGMII, 47 OCTEONTX_LINK_SPEED_RESERVE2 48 }; 49 50 int otx_net_logtype_mbox; 51 int otx_net_logtype_init; 52 int otx_net_logtype_driver; 53 54 RTE_INIT(otx_net_init_log) 55 { 56 otx_net_logtype_mbox = rte_log_register("pmd.net.octeontx.mbox"); 57 if (otx_net_logtype_mbox >= 0) 58 rte_log_set_level(otx_net_logtype_mbox, RTE_LOG_NOTICE); 59 60 otx_net_logtype_init = rte_log_register("pmd.net.octeontx.init"); 61 if (otx_net_logtype_init >= 0) 62 rte_log_set_level(otx_net_logtype_init, RTE_LOG_NOTICE); 63 64 otx_net_logtype_driver = rte_log_register("pmd.net.octeontx.driver"); 65 if (otx_net_logtype_driver >= 0) 66 rte_log_set_level(otx_net_logtype_driver, RTE_LOG_NOTICE); 67 } 68 69 /* Parse integer from integer argument */ 70 static int 71 parse_integer_arg(const char *key __rte_unused, 72 const char *value, void *extra_args) 73 { 74 int *i = (int *)extra_args; 75 76 *i = atoi(value); 77 if (*i < 0) { 78 octeontx_log_err("argument has to be positive."); 79 return -1; 80 } 81 82 return 0; 83 } 84 85 static int 86 octeontx_parse_vdev_init_params(struct octeontx_vdev_init_params *params, 87 struct rte_vdev_device *dev) 88 { 89 struct rte_kvargs *kvlist = NULL; 90 int ret = 0; 91 92 static const char * const octeontx_vdev_valid_params[] = { 93 OCTEONTX_VDEV_NR_PORT_ARG, 94 NULL 95 }; 96 97 const char *input_args = rte_vdev_device_args(dev); 98 if (params == NULL) 99 return -EINVAL; 100 101 102 if (input_args) { 103 kvlist = rte_kvargs_parse(input_args, 104 octeontx_vdev_valid_params); 105 if (kvlist == NULL) 106 return -1; 107 108 ret = rte_kvargs_process(kvlist, 109 OCTEONTX_VDEV_NR_PORT_ARG, 110 &parse_integer_arg, 111 ¶ms->nr_port); 112 if (ret < 0) 113 goto free_kvlist; 114 } 115 116 free_kvlist: 117 rte_kvargs_free(kvlist); 118 return ret; 119 } 120 121 static int 122 octeontx_port_open(struct octeontx_nic *nic) 123 { 124 octeontx_mbox_bgx_port_conf_t bgx_port_conf; 125 octeontx_mbox_bgx_port_fifo_cfg_t fifo_cfg; 126 int res; 127 128 res = 0; 129 memset(&bgx_port_conf, 0x0, sizeof(bgx_port_conf)); 130 PMD_INIT_FUNC_TRACE(); 131 132 res = octeontx_bgx_port_open(nic->port_id, &bgx_port_conf); 133 if (res < 0) { 134 octeontx_log_err("failed to open port %d", res); 135 return res; 136 } 137 138 nic->node = bgx_port_conf.node; 139 nic->port_ena = bgx_port_conf.enable; 140 nic->base_ichan = bgx_port_conf.base_chan; 141 nic->base_ochan = bgx_port_conf.base_chan; 142 nic->num_ichans = bgx_port_conf.num_chans; 143 nic->num_ochans = bgx_port_conf.num_chans; 144 nic->bgx_mtu = bgx_port_conf.mtu; 145 nic->bpen = bgx_port_conf.bpen; 146 nic->fcs_strip = bgx_port_conf.fcs_strip; 147 nic->bcast_mode = bgx_port_conf.bcast_mode; 148 nic->mcast_mode = bgx_port_conf.mcast_mode; 149 nic->speed = bgx_port_conf.mode; 150 151 memset(&fifo_cfg, 0x0, sizeof(fifo_cfg)); 152 153 res = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg); 154 if (res < 0) { 155 octeontx_log_err("failed to get port %d fifo cfg", res); 156 return res; 157 } 158 159 nic->fc.rx_fifosz = fifo_cfg.rx_fifosz; 160 161 memcpy(&nic->mac_addr[0], &bgx_port_conf.macaddr[0], 162 RTE_ETHER_ADDR_LEN); 163 164 octeontx_log_dbg("port opened %d", nic->port_id); 165 return res; 166 } 167 168 static void 169 octeontx_link_status_print(struct rte_eth_dev *eth_dev, 170 struct rte_eth_link *link) 171 { 172 if (link && link->link_status) 173 octeontx_log_info("Port %u: Link Up - speed %u Mbps - %s", 174 (eth_dev->data->port_id), 175 link->link_speed, 176 link->link_duplex == ETH_LINK_FULL_DUPLEX ? 177 "full-duplex" : "half-duplex"); 178 else 179 octeontx_log_info("Port %d: Link Down", 180 (int)(eth_dev->data->port_id)); 181 } 182 183 static void 184 octeontx_link_status_update(struct octeontx_nic *nic, 185 struct rte_eth_link *link) 186 { 187 memset(link, 0, sizeof(*link)); 188 189 link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 190 191 switch (nic->speed) { 192 case OCTEONTX_LINK_SPEED_SGMII: 193 link->link_speed = ETH_SPEED_NUM_1G; 194 break; 195 196 case OCTEONTX_LINK_SPEED_XAUI: 197 link->link_speed = ETH_SPEED_NUM_10G; 198 break; 199 200 case OCTEONTX_LINK_SPEED_RXAUI: 201 case OCTEONTX_LINK_SPEED_10G_R: 202 link->link_speed = ETH_SPEED_NUM_10G; 203 break; 204 case OCTEONTX_LINK_SPEED_QSGMII: 205 link->link_speed = ETH_SPEED_NUM_5G; 206 break; 207 case OCTEONTX_LINK_SPEED_40G_R: 208 link->link_speed = ETH_SPEED_NUM_40G; 209 break; 210 211 case OCTEONTX_LINK_SPEED_RESERVE1: 212 case OCTEONTX_LINK_SPEED_RESERVE2: 213 default: 214 link->link_speed = ETH_SPEED_NUM_NONE; 215 octeontx_log_err("incorrect link speed %d", nic->speed); 216 break; 217 } 218 219 link->link_duplex = ETH_LINK_FULL_DUPLEX; 220 link->link_autoneg = ETH_LINK_AUTONEG; 221 } 222 223 static void 224 octeontx_link_status_poll(void *arg) 225 { 226 struct octeontx_nic *nic = arg; 227 struct rte_eth_link link; 228 struct rte_eth_dev *dev; 229 int res; 230 231 PMD_INIT_FUNC_TRACE(); 232 233 dev = nic->dev; 234 235 res = octeontx_bgx_port_link_status(nic->port_id); 236 if (res < 0) { 237 octeontx_log_err("Failed to get port %d link status", 238 nic->port_id); 239 } else { 240 if (nic->link_up != (uint8_t)res) { 241 nic->link_up = (uint8_t)res; 242 octeontx_link_status_update(nic, &link); 243 octeontx_link_status_print(dev, &link); 244 rte_eth_linkstatus_set(dev, &link); 245 _rte_eth_dev_callback_process(dev, 246 RTE_ETH_EVENT_INTR_LSC, 247 NULL); 248 } 249 } 250 251 res = rte_eal_alarm_set(OCCTX_INTR_POLL_INTERVAL_MS * 1000, 252 octeontx_link_status_poll, nic); 253 if (res < 0) 254 octeontx_log_err("Failed to restart alarm for port %d, err: %d", 255 nic->port_id, res); 256 } 257 258 static void 259 octeontx_port_close(struct octeontx_nic *nic) 260 { 261 PMD_INIT_FUNC_TRACE(); 262 263 rte_eal_alarm_cancel(octeontx_link_status_poll, nic); 264 octeontx_bgx_port_close(nic->port_id); 265 octeontx_log_dbg("port closed %d", nic->port_id); 266 } 267 268 static int 269 octeontx_port_start(struct octeontx_nic *nic) 270 { 271 PMD_INIT_FUNC_TRACE(); 272 273 return octeontx_bgx_port_start(nic->port_id); 274 } 275 276 static int 277 octeontx_port_stop(struct octeontx_nic *nic) 278 { 279 PMD_INIT_FUNC_TRACE(); 280 281 return octeontx_bgx_port_stop(nic->port_id); 282 } 283 284 static int 285 octeontx_port_promisc_set(struct octeontx_nic *nic, int en) 286 { 287 struct rte_eth_dev *dev; 288 int res; 289 290 res = 0; 291 PMD_INIT_FUNC_TRACE(); 292 dev = nic->dev; 293 294 res = octeontx_bgx_port_promisc_set(nic->port_id, en); 295 if (res < 0) { 296 octeontx_log_err("failed to set promiscuous mode %d", 297 nic->port_id); 298 return res; 299 } 300 301 /* Set proper flag for the mode */ 302 dev->data->promiscuous = (en != 0) ? 1 : 0; 303 304 octeontx_log_dbg("port %d : promiscuous mode %s", 305 nic->port_id, en ? "set" : "unset"); 306 307 return 0; 308 } 309 310 static int 311 octeontx_port_stats(struct octeontx_nic *nic, struct rte_eth_stats *stats) 312 { 313 octeontx_mbox_bgx_port_stats_t bgx_stats; 314 int res; 315 316 PMD_INIT_FUNC_TRACE(); 317 318 res = octeontx_bgx_port_stats(nic->port_id, &bgx_stats); 319 if (res < 0) { 320 octeontx_log_err("failed to get port stats %d", nic->port_id); 321 return res; 322 } 323 324 stats->ipackets = bgx_stats.rx_packets; 325 stats->ibytes = bgx_stats.rx_bytes; 326 stats->imissed = bgx_stats.rx_dropped; 327 stats->ierrors = bgx_stats.rx_errors; 328 stats->opackets = bgx_stats.tx_packets; 329 stats->obytes = bgx_stats.tx_bytes; 330 stats->oerrors = bgx_stats.tx_errors; 331 332 octeontx_log_dbg("port%d stats inpkts=%" PRIx64 " outpkts=%" PRIx64 "", 333 nic->port_id, stats->ipackets, stats->opackets); 334 335 return 0; 336 } 337 338 static int 339 octeontx_port_stats_clr(struct octeontx_nic *nic) 340 { 341 PMD_INIT_FUNC_TRACE(); 342 343 return octeontx_bgx_port_stats_clr(nic->port_id); 344 } 345 346 static inline void 347 devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf, 348 struct rte_event_dev_info *info) 349 { 350 memset(dev_conf, 0, sizeof(struct rte_event_dev_config)); 351 dev_conf->dequeue_timeout_ns = info->min_dequeue_timeout_ns; 352 353 dev_conf->nb_event_ports = info->max_event_ports; 354 dev_conf->nb_event_queues = info->max_event_queues; 355 356 dev_conf->nb_event_queue_flows = info->max_event_queue_flows; 357 dev_conf->nb_event_port_dequeue_depth = 358 info->max_event_port_dequeue_depth; 359 dev_conf->nb_event_port_enqueue_depth = 360 info->max_event_port_enqueue_depth; 361 dev_conf->nb_event_port_enqueue_depth = 362 info->max_event_port_enqueue_depth; 363 dev_conf->nb_events_limit = 364 info->max_num_events; 365 } 366 367 static uint16_t 368 octeontx_tx_offload_flags(struct rte_eth_dev *eth_dev) 369 { 370 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 371 uint16_t flags = 0; 372 373 if (nic->tx_offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || 374 nic->tx_offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) 375 flags |= OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F; 376 377 if (nic->tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM || 378 nic->tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM || 379 nic->tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM || 380 nic->tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) 381 flags |= OCCTX_TX_OFFLOAD_L3_L4_CSUM_F; 382 383 if (!(nic->tx_offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) 384 flags |= OCCTX_TX_OFFLOAD_MBUF_NOFF_F; 385 386 if (nic->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 387 flags |= OCCTX_TX_MULTI_SEG_F; 388 389 return flags; 390 } 391 392 static uint16_t 393 octeontx_rx_offload_flags(struct rte_eth_dev *eth_dev) 394 { 395 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 396 uint16_t flags = 0; 397 398 if (nic->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM | 399 DEV_RX_OFFLOAD_UDP_CKSUM)) 400 flags |= OCCTX_RX_OFFLOAD_CSUM_F; 401 402 if (nic->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM | 403 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) 404 flags |= OCCTX_RX_OFFLOAD_CSUM_F; 405 406 if (nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 407 flags |= OCCTX_RX_MULTI_SEG_F; 408 eth_dev->data->scattered_rx = 1; 409 /* If scatter mode is enabled, TX should also be in multi 410 * seg mode, else memory leak will occur 411 */ 412 nic->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS; 413 } 414 415 return flags; 416 } 417 418 static int 419 octeontx_dev_configure(struct rte_eth_dev *dev) 420 { 421 struct rte_eth_dev_data *data = dev->data; 422 struct rte_eth_conf *conf = &data->dev_conf; 423 struct rte_eth_rxmode *rxmode = &conf->rxmode; 424 struct rte_eth_txmode *txmode = &conf->txmode; 425 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 426 int ret; 427 428 PMD_INIT_FUNC_TRACE(); 429 RTE_SET_USED(conf); 430 431 if (!rte_eal_has_hugepages()) { 432 octeontx_log_err("huge page is not configured"); 433 return -EINVAL; 434 } 435 436 if (txmode->mq_mode) { 437 octeontx_log_err("tx mq_mode DCB or VMDq not supported"); 438 return -EINVAL; 439 } 440 441 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 442 rxmode->mq_mode != ETH_MQ_RX_RSS) { 443 octeontx_log_err("unsupported rx qmode %d", rxmode->mq_mode); 444 return -EINVAL; 445 } 446 447 if (!(txmode->offloads & DEV_TX_OFFLOAD_MT_LOCKFREE)) { 448 PMD_INIT_LOG(NOTICE, "cant disable lockfree tx"); 449 txmode->offloads |= DEV_TX_OFFLOAD_MT_LOCKFREE; 450 } 451 452 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 453 octeontx_log_err("setting link speed/duplex not supported"); 454 return -EINVAL; 455 } 456 457 if (conf->dcb_capability_en) { 458 octeontx_log_err("DCB enable not supported"); 459 return -EINVAL; 460 } 461 462 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 463 octeontx_log_err("flow director not supported"); 464 return -EINVAL; 465 } 466 467 nic->num_tx_queues = dev->data->nb_tx_queues; 468 469 ret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ, 470 nic->num_tx_queues, 471 nic->base_ochan); 472 if (ret) { 473 octeontx_log_err("failed to open channel %d no-of-txq %d", 474 nic->base_ochan, nic->num_tx_queues); 475 return -EFAULT; 476 } 477 478 ret = octeontx_dev_vlan_offload_init(dev); 479 if (ret) { 480 octeontx_log_err("failed to initialize vlan offload"); 481 return -EFAULT; 482 } 483 484 nic->pki.classifier_enable = false; 485 nic->pki.hash_enable = true; 486 nic->pki.initialized = false; 487 488 nic->rx_offloads |= rxmode->offloads; 489 nic->tx_offloads |= txmode->offloads; 490 nic->rx_offload_flags |= octeontx_rx_offload_flags(dev); 491 nic->tx_offload_flags |= octeontx_tx_offload_flags(dev); 492 493 return 0; 494 } 495 496 static void 497 octeontx_dev_close(struct rte_eth_dev *dev) 498 { 499 struct octeontx_txq *txq = NULL; 500 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 501 unsigned int i; 502 int ret; 503 504 PMD_INIT_FUNC_TRACE(); 505 506 rte_event_dev_close(nic->evdev); 507 508 octeontx_dev_flow_ctrl_fini(dev); 509 510 octeontx_dev_vlan_offload_fini(dev); 511 512 ret = octeontx_pko_channel_close(nic->base_ochan); 513 if (ret < 0) { 514 octeontx_log_err("failed to close channel %d VF%d %d %d", 515 nic->base_ochan, nic->port_id, nic->num_tx_queues, 516 ret); 517 } 518 /* Free txq resources for this port */ 519 for (i = 0; i < nic->num_tx_queues; i++) { 520 txq = dev->data->tx_queues[i]; 521 if (!txq) 522 continue; 523 524 rte_free(txq); 525 } 526 527 /* Free MAC address table */ 528 rte_free(dev->data->mac_addrs); 529 dev->data->mac_addrs = NULL; 530 531 octeontx_port_close(nic); 532 533 dev->tx_pkt_burst = NULL; 534 dev->rx_pkt_burst = NULL; 535 } 536 537 static int 538 octeontx_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 539 { 540 uint32_t buffsz, frame_size = mtu + OCCTX_L2_OVERHEAD; 541 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 542 struct rte_eth_dev_data *data = eth_dev->data; 543 int rc = 0; 544 545 /* Check if MTU is within the allowed range */ 546 if (frame_size < OCCTX_MIN_FRS || frame_size > OCCTX_MAX_FRS) 547 return -EINVAL; 548 549 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 550 551 /* Refuse MTU that requires the support of scattered packets 552 * when this feature has not been enabled before. 553 */ 554 if (data->dev_started && frame_size > buffsz && 555 !(nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER)) { 556 octeontx_log_err("Scatter mode is disabled"); 557 return -EINVAL; 558 } 559 560 /* Check <seg size> * <max_seg> >= max_frame */ 561 if ((nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) && 562 (frame_size > buffsz * OCCTX_RX_NB_SEG_MAX)) 563 return -EINVAL; 564 565 rc = octeontx_pko_send_mtu(nic->port_id, frame_size); 566 if (rc) 567 return rc; 568 569 rc = octeontx_bgx_port_mtu_set(nic->port_id, frame_size); 570 if (rc) 571 return rc; 572 573 if (frame_size > RTE_ETHER_MAX_LEN) 574 nic->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 575 else 576 nic->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 577 578 /* Update max_rx_pkt_len */ 579 data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 580 octeontx_log_info("Received pkt beyond maxlen %d will be dropped", 581 frame_size); 582 583 return rc; 584 } 585 586 static int 587 octeontx_recheck_rx_offloads(struct octeontx_rxq *rxq) 588 { 589 struct rte_eth_dev *eth_dev = rxq->eth_dev; 590 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 591 struct rte_eth_dev_data *data = eth_dev->data; 592 struct rte_pktmbuf_pool_private *mbp_priv; 593 struct evdev_priv_data *evdev_priv; 594 struct rte_eventdev *dev; 595 uint32_t buffsz; 596 597 /* Get rx buffer size */ 598 mbp_priv = rte_mempool_get_priv(rxq->pool); 599 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 600 601 /* Setup scatter mode if needed by jumbo */ 602 if (data->dev_conf.rxmode.max_rx_pkt_len > buffsz) { 603 nic->rx_offloads |= DEV_RX_OFFLOAD_SCATTER; 604 nic->rx_offload_flags |= octeontx_rx_offload_flags(eth_dev); 605 nic->tx_offload_flags |= octeontx_tx_offload_flags(eth_dev); 606 } 607 608 /* Sharing offload flags via eventdev priv region */ 609 dev = &rte_eventdevs[rxq->evdev]; 610 evdev_priv = dev->data->dev_private; 611 evdev_priv->rx_offload_flags = nic->rx_offload_flags; 612 evdev_priv->tx_offload_flags = nic->tx_offload_flags; 613 614 /* Setup MTU based on max_rx_pkt_len */ 615 nic->mtu = data->dev_conf.rxmode.max_rx_pkt_len - OCCTX_L2_OVERHEAD; 616 617 return 0; 618 } 619 620 static int 621 octeontx_dev_start(struct rte_eth_dev *dev) 622 { 623 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 624 struct octeontx_rxq *rxq; 625 int ret, i; 626 627 PMD_INIT_FUNC_TRACE(); 628 /* Rechecking if any new offload set to update 629 * rx/tx burst function pointer accordingly. 630 */ 631 for (i = 0; i < dev->data->nb_rx_queues; i++) { 632 rxq = dev->data->rx_queues[i]; 633 octeontx_recheck_rx_offloads(rxq); 634 } 635 636 /* Setting up the mtu based on max_rx_pkt_len */ 637 ret = octeontx_dev_mtu_set(dev, nic->mtu); 638 if (ret) { 639 octeontx_log_err("Failed to set default MTU size %d", ret); 640 goto error; 641 } 642 643 /* 644 * Tx start 645 */ 646 octeontx_set_tx_function(dev); 647 ret = octeontx_pko_channel_start(nic->base_ochan); 648 if (ret < 0) { 649 octeontx_log_err("fail to conf VF%d no. txq %d chan %d ret %d", 650 nic->port_id, nic->num_tx_queues, nic->base_ochan, 651 ret); 652 goto error; 653 } 654 655 /* 656 * Rx start 657 */ 658 dev->rx_pkt_burst = octeontx_recv_pkts; 659 ret = octeontx_pki_port_start(nic->port_id); 660 if (ret < 0) { 661 octeontx_log_err("fail to start Rx on port %d", nic->port_id); 662 goto channel_stop_error; 663 } 664 665 /* 666 * Start port 667 */ 668 ret = octeontx_port_start(nic); 669 if (ret < 0) { 670 octeontx_log_err("failed start port %d", ret); 671 goto pki_port_stop_error; 672 } 673 674 PMD_TX_LOG(DEBUG, "pko: start channel %d no.of txq %d port %d", 675 nic->base_ochan, nic->num_tx_queues, nic->port_id); 676 677 ret = rte_event_dev_start(nic->evdev); 678 if (ret < 0) { 679 octeontx_log_err("failed to start evdev: ret (%d)", ret); 680 goto pki_port_stop_error; 681 } 682 683 /* Success */ 684 return ret; 685 686 pki_port_stop_error: 687 octeontx_pki_port_stop(nic->port_id); 688 channel_stop_error: 689 octeontx_pko_channel_stop(nic->base_ochan); 690 error: 691 return ret; 692 } 693 694 static void 695 octeontx_dev_stop(struct rte_eth_dev *dev) 696 { 697 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 698 int ret; 699 700 PMD_INIT_FUNC_TRACE(); 701 702 rte_event_dev_stop(nic->evdev); 703 704 ret = octeontx_port_stop(nic); 705 if (ret < 0) { 706 octeontx_log_err("failed to req stop port %d res=%d", 707 nic->port_id, ret); 708 return; 709 } 710 711 ret = octeontx_pki_port_stop(nic->port_id); 712 if (ret < 0) { 713 octeontx_log_err("failed to stop pki port %d res=%d", 714 nic->port_id, ret); 715 return; 716 } 717 718 ret = octeontx_pko_channel_stop(nic->base_ochan); 719 if (ret < 0) { 720 octeontx_log_err("failed to stop channel %d VF%d %d %d", 721 nic->base_ochan, nic->port_id, nic->num_tx_queues, 722 ret); 723 return; 724 } 725 } 726 727 static int 728 octeontx_dev_promisc_enable(struct rte_eth_dev *dev) 729 { 730 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 731 732 PMD_INIT_FUNC_TRACE(); 733 return octeontx_port_promisc_set(nic, 1); 734 } 735 736 static int 737 octeontx_dev_promisc_disable(struct rte_eth_dev *dev) 738 { 739 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 740 741 PMD_INIT_FUNC_TRACE(); 742 return octeontx_port_promisc_set(nic, 0); 743 } 744 745 static int 746 octeontx_port_link_status(struct octeontx_nic *nic) 747 { 748 int res; 749 750 PMD_INIT_FUNC_TRACE(); 751 res = octeontx_bgx_port_link_status(nic->port_id); 752 if (res < 0) { 753 octeontx_log_err("failed to get port %d link status", 754 nic->port_id); 755 return res; 756 } 757 758 if (nic->link_up != (uint8_t)res || nic->print_flag == -1) { 759 nic->link_up = (uint8_t)res; 760 nic->print_flag = 1; 761 } 762 octeontx_log_dbg("port %d link status %d", nic->port_id, nic->link_up); 763 764 return res; 765 } 766 767 /* 768 * Return 0 means link status changed, -1 means not changed 769 */ 770 static int 771 octeontx_dev_link_update(struct rte_eth_dev *dev, 772 int wait_to_complete __rte_unused) 773 { 774 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 775 struct rte_eth_link link; 776 int res; 777 778 PMD_INIT_FUNC_TRACE(); 779 780 res = octeontx_port_link_status(nic); 781 if (res < 0) { 782 octeontx_log_err("failed to request link status %d", res); 783 return res; 784 } 785 786 octeontx_link_status_update(nic, &link); 787 if (nic->print_flag) { 788 octeontx_link_status_print(nic->dev, &link); 789 nic->print_flag = 0; 790 } 791 792 return rte_eth_linkstatus_set(dev, &link); 793 } 794 795 static int 796 octeontx_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 797 { 798 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 799 800 PMD_INIT_FUNC_TRACE(); 801 return octeontx_port_stats(nic, stats); 802 } 803 804 static int 805 octeontx_dev_stats_reset(struct rte_eth_dev *dev) 806 { 807 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 808 809 PMD_INIT_FUNC_TRACE(); 810 return octeontx_port_stats_clr(nic); 811 } 812 813 static void 814 octeontx_dev_mac_addr_del(struct rte_eth_dev *dev, uint32_t index) 815 { 816 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 817 int ret; 818 819 ret = octeontx_bgx_port_mac_del(nic->port_id, index); 820 if (ret != 0) 821 octeontx_log_err("failed to del MAC address filter on port %d", 822 nic->port_id); 823 } 824 825 static int 826 octeontx_dev_mac_addr_add(struct rte_eth_dev *dev, 827 struct rte_ether_addr *mac_addr, 828 uint32_t index, 829 __rte_unused uint32_t vmdq) 830 { 831 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 832 int ret; 833 834 ret = octeontx_bgx_port_mac_add(nic->port_id, mac_addr->addr_bytes, 835 index); 836 if (ret < 0) { 837 octeontx_log_err("failed to add MAC address filter on port %d", 838 nic->port_id); 839 return ret; 840 } 841 842 return 0; 843 } 844 845 static int 846 octeontx_dev_default_mac_addr_set(struct rte_eth_dev *dev, 847 struct rte_ether_addr *addr) 848 { 849 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 850 int ret; 851 852 ret = octeontx_bgx_port_mac_set(nic->port_id, addr->addr_bytes); 853 if (ret == 0) { 854 /* Update same mac address to BGX CAM table */ 855 ret = octeontx_bgx_port_mac_add(nic->port_id, addr->addr_bytes, 856 0); 857 } 858 if (ret < 0) { 859 octeontx_log_err("failed to set MAC address on port %d", 860 nic->port_id); 861 } 862 863 return ret; 864 } 865 866 static int 867 octeontx_dev_info(struct rte_eth_dev *dev, 868 struct rte_eth_dev_info *dev_info) 869 { 870 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 871 872 /* Autonegotiation may be disabled */ 873 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 874 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 875 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | 876 ETH_LINK_SPEED_40G; 877 878 /* Min/Max MTU supported */ 879 dev_info->min_rx_bufsize = OCCTX_MIN_FRS; 880 dev_info->max_rx_pktlen = OCCTX_MAX_FRS; 881 dev_info->max_mtu = dev_info->max_rx_pktlen - OCCTX_L2_OVERHEAD; 882 dev_info->min_mtu = dev_info->min_rx_bufsize - OCCTX_L2_OVERHEAD; 883 884 dev_info->max_mac_addrs = 885 octeontx_bgx_port_mac_entries_get(nic->port_id); 886 dev_info->max_rx_pktlen = PKI_MAX_PKTLEN; 887 dev_info->max_rx_queues = 1; 888 dev_info->max_tx_queues = PKO_MAX_NUM_DQ; 889 dev_info->min_rx_bufsize = 0; 890 891 dev_info->default_rxconf = (struct rte_eth_rxconf) { 892 .rx_free_thresh = 0, 893 .rx_drop_en = 0, 894 .offloads = OCTEONTX_RX_OFFLOADS, 895 }; 896 897 dev_info->default_txconf = (struct rte_eth_txconf) { 898 .tx_free_thresh = 0, 899 .offloads = OCTEONTX_TX_OFFLOADS, 900 }; 901 902 dev_info->rx_offload_capa = OCTEONTX_RX_OFFLOADS; 903 dev_info->tx_offload_capa = OCTEONTX_TX_OFFLOADS; 904 dev_info->rx_queue_offload_capa = OCTEONTX_RX_OFFLOADS; 905 dev_info->tx_queue_offload_capa = OCTEONTX_TX_OFFLOADS; 906 907 return 0; 908 } 909 910 static void 911 octeontx_dq_info_getter(octeontx_dq_t *dq, void *out) 912 { 913 ((octeontx_dq_t *)out)->lmtline_va = dq->lmtline_va; 914 ((octeontx_dq_t *)out)->ioreg_va = dq->ioreg_va; 915 ((octeontx_dq_t *)out)->fc_status_va = dq->fc_status_va; 916 } 917 918 static int 919 octeontx_vf_start_tx_queue(struct rte_eth_dev *dev, struct octeontx_nic *nic, 920 uint16_t qidx) 921 { 922 struct octeontx_txq *txq; 923 int res; 924 925 PMD_INIT_FUNC_TRACE(); 926 927 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) 928 return 0; 929 930 txq = dev->data->tx_queues[qidx]; 931 932 res = octeontx_pko_channel_query_dqs(nic->base_ochan, 933 &txq->dq, 934 sizeof(octeontx_dq_t), 935 txq->queue_id, 936 octeontx_dq_info_getter); 937 if (res < 0) { 938 res = -EFAULT; 939 goto close_port; 940 } 941 942 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 943 return res; 944 945 close_port: 946 (void)octeontx_port_stop(nic); 947 octeontx_pko_channel_stop(nic->base_ochan); 948 octeontx_pko_channel_close(nic->base_ochan); 949 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 950 return res; 951 } 952 953 int 954 octeontx_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 955 { 956 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 957 958 PMD_INIT_FUNC_TRACE(); 959 qidx = qidx % PKO_VF_NUM_DQ; 960 return octeontx_vf_start_tx_queue(dev, nic, qidx); 961 } 962 963 static inline int 964 octeontx_vf_stop_tx_queue(struct rte_eth_dev *dev, struct octeontx_nic *nic, 965 uint16_t qidx) 966 { 967 int ret = 0; 968 969 RTE_SET_USED(nic); 970 PMD_INIT_FUNC_TRACE(); 971 972 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) 973 return 0; 974 975 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 976 return ret; 977 } 978 979 int 980 octeontx_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 981 { 982 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 983 984 PMD_INIT_FUNC_TRACE(); 985 qidx = qidx % PKO_VF_NUM_DQ; 986 987 return octeontx_vf_stop_tx_queue(dev, nic, qidx); 988 } 989 990 static void 991 octeontx_dev_tx_queue_release(void *tx_queue) 992 { 993 struct octeontx_txq *txq = tx_queue; 994 int res; 995 996 PMD_INIT_FUNC_TRACE(); 997 998 if (txq) { 999 res = octeontx_dev_tx_queue_stop(txq->eth_dev, txq->queue_id); 1000 if (res < 0) 1001 octeontx_log_err("failed stop tx_queue(%d)\n", 1002 txq->queue_id); 1003 1004 rte_free(txq); 1005 } 1006 } 1007 1008 static int 1009 octeontx_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1010 uint16_t nb_desc, unsigned int socket_id, 1011 const struct rte_eth_txconf *tx_conf __rte_unused) 1012 { 1013 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1014 struct octeontx_txq *txq = NULL; 1015 uint16_t dq_num; 1016 int res = 0; 1017 1018 RTE_SET_USED(nb_desc); 1019 RTE_SET_USED(socket_id); 1020 1021 dq_num = (nic->pko_vfid * PKO_VF_NUM_DQ) + qidx; 1022 1023 /* Socket id check */ 1024 if (socket_id != (unsigned int)SOCKET_ID_ANY && 1025 socket_id != (unsigned int)nic->node) 1026 PMD_TX_LOG(INFO, "socket_id expected %d, configured %d", 1027 socket_id, nic->node); 1028 1029 /* Free memory prior to re-allocation if needed. */ 1030 if (dev->data->tx_queues[qidx] != NULL) { 1031 PMD_TX_LOG(DEBUG, "freeing memory prior to re-allocation %d", 1032 qidx); 1033 octeontx_dev_tx_queue_release(dev->data->tx_queues[qidx]); 1034 dev->data->tx_queues[qidx] = NULL; 1035 } 1036 1037 /* Allocating tx queue data structure */ 1038 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct octeontx_txq), 1039 RTE_CACHE_LINE_SIZE, nic->node); 1040 if (txq == NULL) { 1041 octeontx_log_err("failed to allocate txq=%d", qidx); 1042 res = -ENOMEM; 1043 goto err; 1044 } 1045 1046 txq->eth_dev = dev; 1047 txq->queue_id = dq_num; 1048 dev->data->tx_queues[qidx] = txq; 1049 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1050 1051 res = octeontx_pko_channel_query_dqs(nic->base_ochan, 1052 &txq->dq, 1053 sizeof(octeontx_dq_t), 1054 txq->queue_id, 1055 octeontx_dq_info_getter); 1056 if (res < 0) { 1057 res = -EFAULT; 1058 goto err; 1059 } 1060 1061 PMD_TX_LOG(DEBUG, "[%d]:[%d] txq=%p nb_desc=%d lmtline=%p ioreg_va=%p fc_status_va=%p", 1062 qidx, txq->queue_id, txq, nb_desc, txq->dq.lmtline_va, 1063 txq->dq.ioreg_va, 1064 txq->dq.fc_status_va); 1065 1066 return res; 1067 1068 err: 1069 if (txq) 1070 rte_free(txq); 1071 1072 return res; 1073 } 1074 1075 static int 1076 octeontx_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1077 uint16_t nb_desc, unsigned int socket_id, 1078 const struct rte_eth_rxconf *rx_conf, 1079 struct rte_mempool *mb_pool) 1080 { 1081 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1082 struct rte_mempool_ops *mp_ops = NULL; 1083 struct octeontx_rxq *rxq = NULL; 1084 pki_pktbuf_cfg_t pktbuf_conf; 1085 pki_hash_cfg_t pki_hash; 1086 pki_qos_cfg_t pki_qos; 1087 uintptr_t pool; 1088 int ret, port; 1089 uint16_t gaura; 1090 unsigned int ev_queues = (nic->ev_queues * nic->port_id) + qidx; 1091 unsigned int ev_ports = (nic->ev_ports * nic->port_id) + qidx; 1092 1093 RTE_SET_USED(nb_desc); 1094 1095 memset(&pktbuf_conf, 0, sizeof(pktbuf_conf)); 1096 memset(&pki_hash, 0, sizeof(pki_hash)); 1097 memset(&pki_qos, 0, sizeof(pki_qos)); 1098 1099 mp_ops = rte_mempool_get_ops(mb_pool->ops_index); 1100 if (strcmp(mp_ops->name, "octeontx_fpavf")) { 1101 octeontx_log_err("failed to find octeontx_fpavf mempool"); 1102 return -ENOTSUP; 1103 } 1104 1105 /* Handle forbidden configurations */ 1106 if (nic->pki.classifier_enable) { 1107 octeontx_log_err("cannot setup queue %d. " 1108 "Classifier option unsupported", qidx); 1109 return -EINVAL; 1110 } 1111 1112 port = nic->port_id; 1113 1114 /* Rx deferred start is not supported */ 1115 if (rx_conf->rx_deferred_start) { 1116 octeontx_log_err("rx deferred start not supported"); 1117 return -EINVAL; 1118 } 1119 1120 /* Verify queue index */ 1121 if (qidx >= dev->data->nb_rx_queues) { 1122 octeontx_log_err("QID %d not supporteded (0 - %d available)\n", 1123 qidx, (dev->data->nb_rx_queues - 1)); 1124 return -ENOTSUP; 1125 } 1126 1127 /* Socket id check */ 1128 if (socket_id != (unsigned int)SOCKET_ID_ANY && 1129 socket_id != (unsigned int)nic->node) 1130 PMD_RX_LOG(INFO, "socket_id expected %d, configured %d", 1131 socket_id, nic->node); 1132 1133 /* Allocating rx queue data structure */ 1134 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct octeontx_rxq), 1135 RTE_CACHE_LINE_SIZE, nic->node); 1136 if (rxq == NULL) { 1137 octeontx_log_err("failed to allocate rxq=%d", qidx); 1138 return -ENOMEM; 1139 } 1140 1141 if (!nic->pki.initialized) { 1142 pktbuf_conf.port_type = 0; 1143 pki_hash.port_type = 0; 1144 pki_qos.port_type = 0; 1145 1146 pktbuf_conf.mmask.f_wqe_skip = 1; 1147 pktbuf_conf.mmask.f_first_skip = 1; 1148 pktbuf_conf.mmask.f_later_skip = 1; 1149 pktbuf_conf.mmask.f_mbuff_size = 1; 1150 pktbuf_conf.mmask.f_cache_mode = 1; 1151 1152 pktbuf_conf.wqe_skip = OCTTX_PACKET_WQE_SKIP; 1153 pktbuf_conf.first_skip = OCTTX_PACKET_FIRST_SKIP(mb_pool); 1154 pktbuf_conf.later_skip = OCTTX_PACKET_LATER_SKIP; 1155 pktbuf_conf.mbuff_size = (mb_pool->elt_size - 1156 RTE_PKTMBUF_HEADROOM - 1157 rte_pktmbuf_priv_size(mb_pool) - 1158 sizeof(struct rte_mbuf)); 1159 1160 pktbuf_conf.cache_mode = PKI_OPC_MODE_STF2_STT; 1161 1162 ret = octeontx_pki_port_pktbuf_config(port, &pktbuf_conf); 1163 if (ret != 0) { 1164 octeontx_log_err("fail to configure pktbuf for port %d", 1165 port); 1166 rte_free(rxq); 1167 return ret; 1168 } 1169 PMD_RX_LOG(DEBUG, "Port %d Rx pktbuf configured:\n" 1170 "\tmbuf_size:\t0x%0x\n" 1171 "\twqe_skip:\t0x%0x\n" 1172 "\tfirst_skip:\t0x%0x\n" 1173 "\tlater_skip:\t0x%0x\n" 1174 "\tcache_mode:\t%s\n", 1175 port, 1176 pktbuf_conf.mbuff_size, 1177 pktbuf_conf.wqe_skip, 1178 pktbuf_conf.first_skip, 1179 pktbuf_conf.later_skip, 1180 (pktbuf_conf.cache_mode == 1181 PKI_OPC_MODE_STT) ? 1182 "STT" : 1183 (pktbuf_conf.cache_mode == 1184 PKI_OPC_MODE_STF) ? 1185 "STF" : 1186 (pktbuf_conf.cache_mode == 1187 PKI_OPC_MODE_STF1_STT) ? 1188 "STF1_STT" : "STF2_STT"); 1189 1190 if (nic->pki.hash_enable) { 1191 pki_hash.tag_dlc = 1; 1192 pki_hash.tag_slc = 1; 1193 pki_hash.tag_dlf = 1; 1194 pki_hash.tag_slf = 1; 1195 pki_hash.tag_prt = 1; 1196 octeontx_pki_port_hash_config(port, &pki_hash); 1197 } 1198 1199 pool = (uintptr_t)mb_pool->pool_id; 1200 1201 /* Get the gaura Id */ 1202 gaura = octeontx_fpa_bufpool_gaura(pool); 1203 1204 pki_qos.qpg_qos = PKI_QPG_QOS_NONE; 1205 pki_qos.num_entry = 1; 1206 pki_qos.drop_policy = 0; 1207 pki_qos.tag_type = 0L; 1208 pki_qos.qos_entry[0].port_add = 0; 1209 pki_qos.qos_entry[0].gaura = gaura; 1210 pki_qos.qos_entry[0].ggrp_ok = ev_queues; 1211 pki_qos.qos_entry[0].ggrp_bad = ev_queues; 1212 pki_qos.qos_entry[0].grptag_bad = 0; 1213 pki_qos.qos_entry[0].grptag_ok = 0; 1214 1215 ret = octeontx_pki_port_create_qos(port, &pki_qos); 1216 if (ret < 0) { 1217 octeontx_log_err("failed to create QOS port=%d, q=%d", 1218 port, qidx); 1219 rte_free(rxq); 1220 return ret; 1221 } 1222 nic->pki.initialized = true; 1223 } 1224 1225 rxq->port_id = nic->port_id; 1226 rxq->eth_dev = dev; 1227 rxq->queue_id = qidx; 1228 rxq->evdev = nic->evdev; 1229 rxq->ev_queues = ev_queues; 1230 rxq->ev_ports = ev_ports; 1231 rxq->pool = mb_pool; 1232 1233 octeontx_recheck_rx_offloads(rxq); 1234 dev->data->rx_queues[qidx] = rxq; 1235 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1236 1237 return 0; 1238 } 1239 1240 static void 1241 octeontx_dev_rx_queue_release(void *rxq) 1242 { 1243 rte_free(rxq); 1244 } 1245 1246 static const uint32_t * 1247 octeontx_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1248 { 1249 static const uint32_t ptypes[] = { 1250 RTE_PTYPE_L3_IPV4, 1251 RTE_PTYPE_L3_IPV4_EXT, 1252 RTE_PTYPE_L3_IPV6, 1253 RTE_PTYPE_L3_IPV6_EXT, 1254 RTE_PTYPE_L4_TCP, 1255 RTE_PTYPE_L4_UDP, 1256 RTE_PTYPE_L4_FRAG, 1257 RTE_PTYPE_UNKNOWN 1258 }; 1259 1260 if (dev->rx_pkt_burst == octeontx_recv_pkts) 1261 return ptypes; 1262 1263 return NULL; 1264 } 1265 1266 static int 1267 octeontx_pool_ops(struct rte_eth_dev *dev, const char *pool) 1268 { 1269 RTE_SET_USED(dev); 1270 1271 if (!strcmp(pool, "octeontx_fpavf")) 1272 return 0; 1273 1274 return -ENOTSUP; 1275 } 1276 1277 /* Initialize and register driver with DPDK Application */ 1278 static const struct eth_dev_ops octeontx_dev_ops = { 1279 .dev_configure = octeontx_dev_configure, 1280 .dev_infos_get = octeontx_dev_info, 1281 .dev_close = octeontx_dev_close, 1282 .dev_start = octeontx_dev_start, 1283 .dev_stop = octeontx_dev_stop, 1284 .promiscuous_enable = octeontx_dev_promisc_enable, 1285 .promiscuous_disable = octeontx_dev_promisc_disable, 1286 .link_update = octeontx_dev_link_update, 1287 .stats_get = octeontx_dev_stats_get, 1288 .stats_reset = octeontx_dev_stats_reset, 1289 .mac_addr_remove = octeontx_dev_mac_addr_del, 1290 .mac_addr_add = octeontx_dev_mac_addr_add, 1291 .mac_addr_set = octeontx_dev_default_mac_addr_set, 1292 .vlan_offload_set = octeontx_dev_vlan_offload_set, 1293 .vlan_filter_set = octeontx_dev_vlan_filter_set, 1294 .tx_queue_start = octeontx_dev_tx_queue_start, 1295 .tx_queue_stop = octeontx_dev_tx_queue_stop, 1296 .tx_queue_setup = octeontx_dev_tx_queue_setup, 1297 .tx_queue_release = octeontx_dev_tx_queue_release, 1298 .rx_queue_setup = octeontx_dev_rx_queue_setup, 1299 .rx_queue_release = octeontx_dev_rx_queue_release, 1300 .dev_set_link_up = octeontx_dev_set_link_up, 1301 .dev_set_link_down = octeontx_dev_set_link_down, 1302 .dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get, 1303 .mtu_set = octeontx_dev_mtu_set, 1304 .pool_ops_supported = octeontx_pool_ops, 1305 .flow_ctrl_get = octeontx_dev_flow_ctrl_get, 1306 .flow_ctrl_set = octeontx_dev_flow_ctrl_set, 1307 }; 1308 1309 /* Create Ethdev interface per BGX LMAC ports */ 1310 static int 1311 octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev, 1312 int socket_id) 1313 { 1314 int res; 1315 size_t pko_vfid; 1316 char octtx_name[OCTEONTX_MAX_NAME_LEN]; 1317 struct octeontx_nic *nic = NULL; 1318 struct rte_eth_dev *eth_dev = NULL; 1319 struct rte_eth_dev_data *data; 1320 const char *name = rte_vdev_device_name(dev); 1321 int max_entries; 1322 1323 PMD_INIT_FUNC_TRACE(); 1324 1325 sprintf(octtx_name, "%s_%d", name, port); 1326 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1327 eth_dev = rte_eth_dev_attach_secondary(octtx_name); 1328 if (eth_dev == NULL) 1329 return -ENODEV; 1330 1331 eth_dev->dev_ops = &octeontx_dev_ops; 1332 eth_dev->device = &dev->device; 1333 octeontx_set_tx_function(eth_dev); 1334 eth_dev->rx_pkt_burst = octeontx_recv_pkts; 1335 rte_eth_dev_probing_finish(eth_dev); 1336 return 0; 1337 } 1338 1339 /* Reserve an ethdev entry */ 1340 eth_dev = rte_eth_dev_allocate(octtx_name); 1341 if (eth_dev == NULL) { 1342 octeontx_log_err("failed to allocate rte_eth_dev"); 1343 res = -ENOMEM; 1344 goto err; 1345 } 1346 data = eth_dev->data; 1347 1348 nic = rte_zmalloc_socket(octtx_name, sizeof(*nic), 0, socket_id); 1349 if (nic == NULL) { 1350 octeontx_log_err("failed to allocate nic structure"); 1351 res = -ENOMEM; 1352 goto err; 1353 } 1354 data->dev_private = nic; 1355 pko_vfid = octeontx_pko_get_vfid(); 1356 1357 if (pko_vfid == SIZE_MAX) { 1358 octeontx_log_err("failed to get pko vfid"); 1359 res = -ENODEV; 1360 goto err; 1361 } 1362 1363 nic->pko_vfid = pko_vfid; 1364 nic->port_id = port; 1365 nic->evdev = evdev; 1366 1367 res = octeontx_port_open(nic); 1368 if (res < 0) 1369 goto err; 1370 1371 /* Rx side port configuration */ 1372 res = octeontx_pki_port_open(port); 1373 if (res != 0) { 1374 octeontx_log_err("failed to open PKI port %d", port); 1375 res = -ENODEV; 1376 goto err; 1377 } 1378 1379 eth_dev->device = &dev->device; 1380 eth_dev->intr_handle = NULL; 1381 eth_dev->data->kdrv = RTE_KDRV_NONE; 1382 eth_dev->data->numa_node = dev->device.numa_node; 1383 1384 data->port_id = eth_dev->data->port_id; 1385 1386 nic->ev_queues = 1; 1387 nic->ev_ports = 1; 1388 nic->print_flag = -1; 1389 1390 data->dev_link.link_status = ETH_LINK_DOWN; 1391 data->dev_started = 0; 1392 data->promiscuous = 0; 1393 data->all_multicast = 0; 1394 data->scattered_rx = 0; 1395 1396 /* Get maximum number of supported MAC entries */ 1397 max_entries = octeontx_bgx_port_mac_entries_get(nic->port_id); 1398 if (max_entries < 0) { 1399 octeontx_log_err("Failed to get max entries for mac addr"); 1400 res = -ENOTSUP; 1401 goto err; 1402 } 1403 1404 data->mac_addrs = rte_zmalloc_socket(octtx_name, max_entries * 1405 RTE_ETHER_ADDR_LEN, 0, 1406 socket_id); 1407 if (data->mac_addrs == NULL) { 1408 octeontx_log_err("failed to allocate memory for mac_addrs"); 1409 res = -ENOMEM; 1410 goto err; 1411 } 1412 1413 eth_dev->dev_ops = &octeontx_dev_ops; 1414 1415 /* Finally save ethdev pointer to the NIC structure */ 1416 nic->dev = eth_dev; 1417 1418 if (nic->port_id != data->port_id) { 1419 octeontx_log_err("eth_dev->port_id (%d) is diff to orig (%d)", 1420 data->port_id, nic->port_id); 1421 res = -EINVAL; 1422 goto free_mac_addrs; 1423 } 1424 1425 res = rte_eal_alarm_set(OCCTX_INTR_POLL_INTERVAL_MS * 1000, 1426 octeontx_link_status_poll, nic); 1427 if (res) { 1428 octeontx_log_err("Failed to start link polling alarm"); 1429 goto err; 1430 } 1431 1432 /* Update port_id mac to eth_dev */ 1433 memcpy(data->mac_addrs, nic->mac_addr, RTE_ETHER_ADDR_LEN); 1434 1435 /* Update same mac address to BGX CAM table at index 0 */ 1436 octeontx_bgx_port_mac_add(nic->port_id, nic->mac_addr, 0); 1437 1438 res = octeontx_dev_flow_ctrl_init(eth_dev); 1439 if (res < 0) 1440 goto err; 1441 1442 PMD_INIT_LOG(DEBUG, "ethdev info: "); 1443 PMD_INIT_LOG(DEBUG, "port %d, port_ena %d ochan %d num_ochan %d tx_q %d", 1444 nic->port_id, nic->port_ena, 1445 nic->base_ochan, nic->num_ochans, 1446 nic->num_tx_queues); 1447 PMD_INIT_LOG(DEBUG, "speed %d mtu %d", nic->speed, nic->bgx_mtu); 1448 1449 rte_octeontx_pchan_map[(nic->base_ochan >> 8) & 0x7] 1450 [(nic->base_ochan >> 4) & 0xF] = data->port_id; 1451 1452 rte_eth_dev_probing_finish(eth_dev); 1453 return data->port_id; 1454 1455 free_mac_addrs: 1456 rte_free(data->mac_addrs); 1457 data->mac_addrs = NULL; 1458 err: 1459 if (nic) 1460 octeontx_port_close(nic); 1461 1462 rte_eth_dev_release_port(eth_dev); 1463 1464 return res; 1465 } 1466 1467 /* Un initialize octeontx device */ 1468 static int 1469 octeontx_remove(struct rte_vdev_device *dev) 1470 { 1471 char octtx_name[OCTEONTX_MAX_NAME_LEN]; 1472 struct rte_eth_dev *eth_dev = NULL; 1473 struct octeontx_nic *nic = NULL; 1474 int i; 1475 1476 if (dev == NULL) 1477 return -EINVAL; 1478 1479 for (i = 0; i < OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT; i++) { 1480 sprintf(octtx_name, "eth_octeontx_%d", i); 1481 1482 /* reserve an ethdev entry */ 1483 eth_dev = rte_eth_dev_allocated(octtx_name); 1484 if (eth_dev == NULL) 1485 return -ENODEV; 1486 1487 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1488 rte_eth_dev_release_port(eth_dev); 1489 continue; 1490 } 1491 1492 nic = octeontx_pmd_priv(eth_dev); 1493 rte_event_dev_stop(nic->evdev); 1494 PMD_INIT_LOG(INFO, "Closing octeontx device %s", octtx_name); 1495 1496 rte_eth_dev_release_port(eth_dev); 1497 rte_event_dev_close(nic->evdev); 1498 } 1499 1500 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1501 return 0; 1502 1503 /* Free FC resource */ 1504 octeontx_pko_fc_free(); 1505 1506 return 0; 1507 } 1508 1509 /* Initialize octeontx device */ 1510 static int 1511 octeontx_probe(struct rte_vdev_device *dev) 1512 { 1513 const char *dev_name; 1514 static int probe_once; 1515 uint8_t socket_id, qlist; 1516 int tx_vfcnt, port_id, evdev, qnum, pnum, res, i; 1517 struct rte_event_dev_config dev_conf; 1518 const char *eventdev_name = "event_octeontx"; 1519 struct rte_event_dev_info info; 1520 struct rte_eth_dev *eth_dev; 1521 1522 struct octeontx_vdev_init_params init_params = { 1523 OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 1524 }; 1525 1526 dev_name = rte_vdev_device_name(dev); 1527 1528 if (rte_eal_process_type() == RTE_PROC_SECONDARY && 1529 strlen(rte_vdev_device_args(dev)) == 0) { 1530 eth_dev = rte_eth_dev_attach_secondary(dev_name); 1531 if (!eth_dev) { 1532 PMD_INIT_LOG(ERR, "Failed to probe %s", dev_name); 1533 return -1; 1534 } 1535 /* TODO: request info from primary to set up Rx and Tx */ 1536 eth_dev->dev_ops = &octeontx_dev_ops; 1537 eth_dev->device = &dev->device; 1538 rte_eth_dev_probing_finish(eth_dev); 1539 return 0; 1540 } 1541 1542 res = octeontx_parse_vdev_init_params(&init_params, dev); 1543 if (res < 0) 1544 return -EINVAL; 1545 1546 if (init_params.nr_port > OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT) { 1547 octeontx_log_err("nr_port (%d) > max (%d)", init_params.nr_port, 1548 OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT); 1549 return -ENOTSUP; 1550 } 1551 1552 PMD_INIT_LOG(DEBUG, "initializing %s pmd", dev_name); 1553 1554 socket_id = rte_socket_id(); 1555 1556 tx_vfcnt = octeontx_pko_vf_count(); 1557 1558 if (tx_vfcnt < init_params.nr_port) { 1559 octeontx_log_err("not enough PKO (%d) for port number (%d)", 1560 tx_vfcnt, init_params.nr_port); 1561 return -EINVAL; 1562 } 1563 evdev = rte_event_dev_get_dev_id(eventdev_name); 1564 if (evdev < 0) { 1565 octeontx_log_err("eventdev %s not found", eventdev_name); 1566 return -ENODEV; 1567 } 1568 1569 res = rte_event_dev_info_get(evdev, &info); 1570 if (res < 0) { 1571 octeontx_log_err("failed to eventdev info %d", res); 1572 return -EINVAL; 1573 } 1574 1575 PMD_INIT_LOG(DEBUG, "max_queue %d max_port %d", 1576 info.max_event_queues, info.max_event_ports); 1577 1578 if (octeontx_pko_init_fc(tx_vfcnt)) 1579 return -ENOMEM; 1580 1581 devconf_set_default_sane_values(&dev_conf, &info); 1582 res = rte_event_dev_configure(evdev, &dev_conf); 1583 if (res < 0) 1584 goto parse_error; 1585 1586 rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, 1587 (uint32_t *)&pnum); 1588 rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, 1589 (uint32_t *)&qnum); 1590 if (pnum < qnum) { 1591 octeontx_log_err("too few event ports (%d) for event_q(%d)", 1592 pnum, qnum); 1593 res = -EINVAL; 1594 goto parse_error; 1595 } 1596 1597 /* Enable all queues available */ 1598 for (i = 0; i < qnum; i++) { 1599 res = rte_event_queue_setup(evdev, i, NULL); 1600 if (res < 0) { 1601 octeontx_log_err("failed to setup event_q(%d): res %d", 1602 i, res); 1603 goto parse_error; 1604 } 1605 } 1606 1607 /* Enable all ports available */ 1608 for (i = 0; i < pnum; i++) { 1609 res = rte_event_port_setup(evdev, i, NULL); 1610 if (res < 0) { 1611 res = -ENODEV; 1612 octeontx_log_err("failed to setup ev port(%d) res=%d", 1613 i, res); 1614 goto parse_error; 1615 } 1616 } 1617 1618 /* 1619 * Do 1:1 links for ports & queues. All queues would be mapped to 1620 * one port. If there are more ports than queues, then some ports 1621 * won't be linked to any queue. 1622 */ 1623 for (i = 0; i < qnum; i++) { 1624 /* Link one queue to one event port */ 1625 qlist = i; 1626 res = rte_event_port_link(evdev, i, &qlist, NULL, 1); 1627 if (res < 0) { 1628 res = -ENODEV; 1629 octeontx_log_err("failed to link port (%d): res=%d", 1630 i, res); 1631 goto parse_error; 1632 } 1633 } 1634 1635 /* Create ethdev interface */ 1636 for (i = 0; i < init_params.nr_port; i++) { 1637 port_id = octeontx_create(dev, i, evdev, socket_id); 1638 if (port_id < 0) { 1639 octeontx_log_err("failed to create device %s", 1640 dev_name); 1641 res = -ENODEV; 1642 goto parse_error; 1643 } 1644 1645 PMD_INIT_LOG(INFO, "created ethdev %s for port %d", dev_name, 1646 port_id); 1647 } 1648 1649 if (probe_once) { 1650 octeontx_log_err("interface %s not supported", dev_name); 1651 octeontx_remove(dev); 1652 res = -ENOTSUP; 1653 goto parse_error; 1654 } 1655 rte_mbuf_set_platform_mempool_ops("octeontx_fpavf"); 1656 probe_once = 1; 1657 1658 return 0; 1659 1660 parse_error: 1661 octeontx_pko_fc_free(); 1662 return res; 1663 } 1664 1665 static struct rte_vdev_driver octeontx_pmd_drv = { 1666 .probe = octeontx_probe, 1667 .remove = octeontx_remove, 1668 }; 1669 1670 RTE_PMD_REGISTER_VDEV(OCTEONTX_PMD, octeontx_pmd_drv); 1671 RTE_PMD_REGISTER_ALIAS(OCTEONTX_PMD, eth_octeontx); 1672 RTE_PMD_REGISTER_PARAM_STRING(OCTEONTX_PMD, "nr_port=<int> "); 1673