1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #include <inttypes.h> 6 #include <ethdev_pci.h> 7 8 #include "otx_ep_common.h" 9 #include "otx_ep_vf.h" 10 #include "otx2_ep_vf.h" 11 #include "cnxk_ep_vf.h" 12 #include "otx_ep_rxtx.h" 13 #include "otx_ep_mbox.h" 14 15 #define OTX_EP_DEV(_eth_dev) \ 16 ((struct otx_ep_device *)(_eth_dev)->data->dev_private) 17 18 #define OTX_ISM_ENABLE "ism_enable" 19 20 static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = { 21 .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS, 22 .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS, 23 .nb_align = OTX_EP_RXD_ALIGN, 24 }; 25 26 static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = { 27 .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS, 28 .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS, 29 .nb_align = OTX_EP_TXD_ALIGN, 30 }; 31 32 static int 33 parse_flag(const char *key, const char *value, void *extra_args) 34 { 35 RTE_SET_USED(key); 36 37 *(uint8_t *)extra_args = atoi(value); 38 39 return 0; 40 } 41 42 static int 43 otx_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx_ep_device *otx_epvf) 44 { 45 struct rte_kvargs *kvlist; 46 uint8_t ism_enable = 0; 47 48 if (devargs == NULL) 49 goto null_devargs; 50 51 kvlist = rte_kvargs_parse(devargs->args, NULL); 52 if (kvlist == NULL) 53 goto exit; 54 55 rte_kvargs_process(kvlist, OTX_ISM_ENABLE, &parse_flag, &ism_enable); 56 rte_kvargs_free(kvlist); 57 58 null_devargs: 59 otx_epvf->ism_ena = !!ism_enable; 60 61 return 0; 62 63 exit: 64 return -EINVAL; 65 } 66 67 static void 68 otx_ep_set_tx_func(struct rte_eth_dev *eth_dev) 69 { 70 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 71 72 if (otx_epvf->chip_gen == OTX_EP_CN10XX || otx_epvf->chip_gen == OTX_EP_CN9XX) { 73 eth_dev->tx_pkt_burst = &cnxk_ep_xmit_pkts; 74 if (otx_epvf->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 75 eth_dev->tx_pkt_burst = &cnxk_ep_xmit_pkts_mseg; 76 } else { 77 eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts; 78 } 79 80 if (eth_dev->data->dev_started) 81 rte_eth_fp_ops[eth_dev->data->port_id].tx_pkt_burst = 82 eth_dev->tx_pkt_burst; 83 } 84 85 static void 86 otx_ep_set_rx_func(struct rte_eth_dev *eth_dev) 87 { 88 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 89 90 if (otx_epvf->chip_gen == OTX_EP_CN10XX) { 91 eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts; 92 #ifdef RTE_ARCH_X86 93 eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts_sse; 94 #ifdef CC_AVX2_SUPPORT 95 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 96 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) 97 eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts_avx; 98 #endif 99 #elif defined(RTE_ARCH_ARM64) 100 eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts_neon; 101 #endif 102 if (otx_epvf->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 103 eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts_mseg; 104 } else if (otx_epvf->chip_gen == OTX_EP_CN9XX) { 105 eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts; 106 #ifdef RTE_ARCH_X86 107 eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts_sse; 108 #ifdef CC_AVX2_SUPPORT 109 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 110 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) 111 eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts_avx; 112 #endif 113 #elif defined(RTE_ARCH_ARM64) 114 eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts_neon; 115 #endif 116 if (otx_epvf->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 117 eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts_mseg; 118 } else { 119 eth_dev->rx_pkt_burst = &otx_ep_recv_pkts; 120 } 121 122 if (eth_dev->data->dev_started) 123 rte_eth_fp_ops[eth_dev->data->port_id].rx_pkt_burst = 124 eth_dev->rx_pkt_burst; 125 } 126 127 static int 128 otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, 129 struct rte_eth_dev_info *devinfo) 130 { 131 struct otx_ep_device *otx_epvf; 132 int max_rx_pktlen; 133 134 otx_epvf = OTX_EP_DEV(eth_dev); 135 136 max_rx_pktlen = otx_ep_mbox_get_max_pkt_len(eth_dev); 137 if (!max_rx_pktlen) { 138 otx_ep_err("Failed to get Max Rx packet length"); 139 return -EINVAL; 140 } 141 142 devinfo->speed_capa = RTE_ETH_LINK_SPEED_10G; 143 devinfo->max_rx_queues = otx_epvf->max_rx_queues; 144 devinfo->max_tx_queues = otx_epvf->max_tx_queues; 145 146 devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE; 147 devinfo->max_rx_pktlen = max_rx_pktlen; 148 devinfo->max_mtu = devinfo->max_rx_pktlen - OTX_EP_ETH_OVERHEAD; 149 devinfo->min_mtu = RTE_ETHER_MIN_LEN; 150 devinfo->rx_offload_capa = RTE_ETH_RX_OFFLOAD_SCATTER; 151 devinfo->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 152 153 devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS; 154 155 devinfo->rx_desc_lim = otx_ep_rx_desc_lim; 156 devinfo->tx_desc_lim = otx_ep_tx_desc_lim; 157 158 devinfo->default_rxportconf.ring_size = OTX_EP_MIN_OQ_DESCRIPTORS; 159 devinfo->default_txportconf.ring_size = OTX_EP_MIN_IQ_DESCRIPTORS; 160 161 return 0; 162 } 163 164 static int 165 otx_ep_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 166 { 167 RTE_SET_USED(wait_to_complete); 168 169 if (!eth_dev->data->dev_started) 170 return 0; 171 struct rte_eth_link link; 172 int ret = 0; 173 174 memset(&link, 0, sizeof(link)); 175 ret = otx_ep_mbox_get_link_info(eth_dev, &link); 176 if (ret) 177 return -EINVAL; 178 otx_ep_dbg("link status resp link %d duplex %d autoneg %d link_speed %d\n", 179 link.link_status, link.link_duplex, link.link_autoneg, link.link_speed); 180 return rte_eth_linkstatus_set(eth_dev, &link); 181 } 182 183 static int 184 otx_ep_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 185 { 186 struct rte_eth_dev_info devinfo; 187 int32_t ret = 0; 188 189 if (otx_ep_dev_info_get(eth_dev, &devinfo)) { 190 otx_ep_err("Cannot set MTU to %u: failed to get device info", mtu); 191 return -EPERM; 192 } 193 194 /* Check if MTU is within the allowed range */ 195 if (mtu < devinfo.min_mtu) { 196 otx_ep_err("Invalid MTU %u: lower than minimum MTU %u", mtu, devinfo.min_mtu); 197 return -EINVAL; 198 } 199 200 if (mtu > devinfo.max_mtu) { 201 otx_ep_err("Invalid MTU %u; higher than maximum MTU %u", mtu, devinfo.max_mtu); 202 return -EINVAL; 203 } 204 205 ret = otx_ep_mbox_set_mtu(eth_dev, mtu); 206 if (ret) 207 return -EINVAL; 208 209 otx_ep_dbg("MTU is set to %u", mtu); 210 211 return 0; 212 } 213 214 static int 215 otx_ep_dev_set_default_mac_addr(struct rte_eth_dev *eth_dev, 216 struct rte_ether_addr *mac_addr) 217 { 218 int ret; 219 220 ret = otx_ep_mbox_set_mac_addr(eth_dev, mac_addr); 221 if (ret) 222 return -EINVAL; 223 otx_ep_dbg("Default MAC address " RTE_ETHER_ADDR_PRT_FMT "\n", 224 RTE_ETHER_ADDR_BYTES(mac_addr)); 225 rte_ether_addr_copy(mac_addr, eth_dev->data->mac_addrs); 226 return 0; 227 } 228 229 static int 230 otx_ep_dev_start(struct rte_eth_dev *eth_dev) 231 { 232 struct otx_ep_device *otx_epvf; 233 unsigned int q; 234 int ret; 235 236 otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev); 237 /* Enable IQ/OQ for this device */ 238 ret = otx_epvf->fn_list.enable_io_queues(otx_epvf); 239 if (ret) { 240 otx_ep_err("IOQ enable failed\n"); 241 return ret; 242 } 243 244 for (q = 0; q < otx_epvf->nb_rx_queues; q++) { 245 rte_write32(otx_epvf->droq[q]->nb_desc, 246 otx_epvf->droq[q]->pkts_credit_reg); 247 248 rte_wmb(); 249 otx_ep_info("OQ[%d] dbells [%d]\n", q, 250 rte_read32(otx_epvf->droq[q]->pkts_credit_reg)); 251 } 252 253 otx_ep_dev_link_update(eth_dev, 0); 254 255 otx_ep_set_tx_func(eth_dev); 256 otx_ep_set_rx_func(eth_dev); 257 258 otx_ep_info("dev started\n"); 259 260 for (q = 0; q < eth_dev->data->nb_rx_queues; q++) 261 eth_dev->data->rx_queue_state[q] = RTE_ETH_QUEUE_STATE_STARTED; 262 for (q = 0; q < eth_dev->data->nb_tx_queues; q++) 263 eth_dev->data->tx_queue_state[q] = RTE_ETH_QUEUE_STATE_STARTED; 264 265 return 0; 266 } 267 268 /* Stop device and disable input/output functions */ 269 static int 270 otx_ep_dev_stop(struct rte_eth_dev *eth_dev) 271 { 272 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 273 uint16_t i; 274 275 otx_epvf->fn_list.disable_io_queues(otx_epvf); 276 277 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) 278 eth_dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 279 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 280 eth_dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 281 282 return 0; 283 } 284 285 /* 286 * We only need 2 uint32_t locations per IOQ, but separate these so 287 * each IOQ has the variables on its own cache line. 288 */ 289 #define OTX_EP_ISM_BUFFER_SIZE (OTX_EP_MAX_IOQS_PER_VF * RTE_CACHE_LINE_SIZE) 290 static int 291 otx_ep_ism_setup(struct otx_ep_device *otx_epvf) 292 { 293 otx_epvf->ism_buffer_mz = 294 rte_eth_dma_zone_reserve(otx_epvf->eth_dev, "ism", 295 0, OTX_EP_ISM_BUFFER_SIZE, 296 OTX_EP_PCI_RING_ALIGN, 0); 297 298 /* Same DMA buffer is shared by OQ and IQ, clear it at start */ 299 memset(otx_epvf->ism_buffer_mz->addr, 0, OTX_EP_ISM_BUFFER_SIZE); 300 if (otx_epvf->ism_buffer_mz == NULL) { 301 otx_ep_err("Failed to allocate ISM buffer\n"); 302 return(-1); 303 } 304 otx_ep_dbg("ISM: virt: 0x%p, dma: 0x%" PRIX64, 305 (void *)otx_epvf->ism_buffer_mz->addr, 306 otx_epvf->ism_buffer_mz->iova); 307 308 return 0; 309 } 310 311 static int 312 otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) 313 { 314 struct rte_pci_device *pdev = otx_epvf->pdev; 315 uint32_t dev_id = pdev->id.device_id; 316 int ret = 0; 317 318 switch (dev_id) { 319 case PCI_DEVID_OCTEONTX_EP_VF: 320 otx_epvf->chip_id = dev_id; 321 ret = otx_ep_vf_setup_device(otx_epvf); 322 otx_epvf->fn_list.disable_io_queues(otx_epvf); 323 break; 324 case PCI_DEVID_CN9K_EP_NET_VF: 325 case PCI_DEVID_CN98XX_EP_NET_VF: 326 case PCI_DEVID_CNF95N_EP_NET_VF: 327 case PCI_DEVID_CNF95O_EP_NET_VF: 328 otx_epvf->chip_id = dev_id; 329 ret = otx2_ep_vf_setup_device(otx_epvf); 330 otx_epvf->fn_list.disable_io_queues(otx_epvf); 331 if (otx_ep_ism_setup(otx_epvf)) 332 ret = -EINVAL; 333 break; 334 case PCI_DEVID_CN10KA_EP_NET_VF: 335 case PCI_DEVID_CN10KB_EP_NET_VF: 336 case PCI_DEVID_CNF10KA_EP_NET_VF: 337 case PCI_DEVID_CNF10KB_EP_NET_VF: 338 otx_epvf->chip_id = dev_id; 339 ret = cnxk_ep_vf_setup_device(otx_epvf); 340 otx_epvf->fn_list.disable_io_queues(otx_epvf); 341 if (otx_ep_ism_setup(otx_epvf)) 342 ret = -EINVAL; 343 break; 344 default: 345 otx_ep_err("Unsupported device\n"); 346 ret = -EINVAL; 347 } 348 349 if (!ret) 350 otx_ep_info("OTX_EP dev_id[%d]\n", dev_id); 351 352 return ret; 353 } 354 355 /* OTX_EP VF device initialization */ 356 static int 357 otx_epdev_init(struct otx_ep_device *otx_epvf) 358 { 359 uint32_t ethdev_queues; 360 int ret = 0; 361 362 ret = otx_ep_chip_specific_setup(otx_epvf); 363 if (ret) { 364 otx_ep_err("Chip specific setup failed\n"); 365 goto setup_fail; 366 } 367 368 otx_epvf->fn_list.setup_device_regs(otx_epvf); 369 370 otx_epvf->eth_dev->tx_pkt_burst = &cnxk_ep_xmit_pkts; 371 otx_epvf->eth_dev->rx_pkt_burst = &otx_ep_recv_pkts; 372 if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF) { 373 otx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts; 374 otx_epvf->chip_gen = OTX_EP_CN8XX; 375 } else if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF || 376 otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF || 377 otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF || 378 otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF) { 379 otx_epvf->eth_dev->rx_pkt_burst = &cn9k_ep_recv_pkts; 380 otx_epvf->chip_gen = OTX_EP_CN9XX; 381 } else if (otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF || 382 otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF || 383 otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF || 384 otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) { 385 otx_epvf->eth_dev->rx_pkt_burst = &cnxk_ep_recv_pkts; 386 otx_epvf->chip_gen = OTX_EP_CN10XX; 387 } else { 388 otx_ep_err("Invalid chip_id\n"); 389 ret = -EINVAL; 390 goto setup_fail; 391 } 392 ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf); 393 otx_epvf->max_rx_queues = ethdev_queues; 394 otx_epvf->max_tx_queues = ethdev_queues; 395 396 otx_ep_info("OTX_EP Device is Ready\n"); 397 398 setup_fail: 399 return ret; 400 } 401 402 static int 403 otx_ep_dev_configure(struct rte_eth_dev *eth_dev) 404 { 405 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 406 struct rte_eth_dev_data *data = eth_dev->data; 407 struct rte_eth_rxmode *rxmode; 408 struct rte_eth_txmode *txmode; 409 struct rte_eth_conf *conf; 410 411 conf = &data->dev_conf; 412 rxmode = &conf->rxmode; 413 txmode = &conf->txmode; 414 if (eth_dev->data->nb_rx_queues > otx_epvf->max_rx_queues || 415 eth_dev->data->nb_tx_queues > otx_epvf->max_tx_queues) { 416 otx_ep_err("invalid num queues\n"); 417 return -EINVAL; 418 } 419 otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n", 420 eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues); 421 422 otx_epvf->rx_offloads = rxmode->offloads; 423 otx_epvf->tx_offloads = txmode->offloads; 424 425 return 0; 426 } 427 428 /** 429 * Setup our receive queue/ringbuffer. This is the 430 * queue the Octeon uses to send us packets and 431 * responses. We are given a memory pool for our 432 * packet buffers that are used to populate the receive 433 * queue. 434 * 435 * @param eth_dev 436 * Pointer to the structure rte_eth_dev 437 * @param q_no 438 * Queue number 439 * @param num_rx_descs 440 * Number of entries in the queue 441 * @param socket_id 442 * Where to allocate memory 443 * @param rx_conf 444 * Pointer to the struction rte_eth_rxconf 445 * @param mp 446 * Pointer to the packet pool 447 * 448 * @return 449 * - On success, return 0 450 * - On failure, return -1 451 */ 452 static int 453 otx_ep_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, 454 uint16_t num_rx_descs, unsigned int socket_id, 455 const struct rte_eth_rxconf *rx_conf __rte_unused, 456 struct rte_mempool *mp) 457 { 458 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 459 struct rte_pktmbuf_pool_private *mbp_priv; 460 uint16_t buf_size; 461 462 if (q_no >= otx_epvf->max_rx_queues) { 463 otx_ep_err("Invalid rx queue number %u\n", q_no); 464 return -EINVAL; 465 } 466 467 if (num_rx_descs & (num_rx_descs - 1)) { 468 otx_ep_err("Invalid rx desc number should be pow 2 %u\n", 469 num_rx_descs); 470 return -EINVAL; 471 } 472 if (num_rx_descs < (SDP_GBL_WMARK * 8)) { 473 otx_ep_err("Invalid rx desc number(%u) should at least be greater than 8xwmark %u\n", 474 num_rx_descs, (SDP_GBL_WMARK * 8)); 475 return -EINVAL; 476 } 477 478 otx_ep_dbg("setting up rx queue %u\n", q_no); 479 480 mbp_priv = rte_mempool_get_priv(mp); 481 buf_size = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 482 483 if (otx_ep_setup_oqs(otx_epvf, q_no, num_rx_descs, buf_size, mp, 484 socket_id)) { 485 otx_ep_err("droq allocation failed\n"); 486 return -1; 487 } 488 489 eth_dev->data->rx_queues[q_no] = otx_epvf->droq[q_no]; 490 491 return 0; 492 } 493 494 /** 495 * Release the receive queue/ringbuffer. Called by 496 * the upper layers. 497 * 498 * @param dev 499 * Pointer to Ethernet device structure. 500 * @param q_no 501 * Receive queue index. 502 * 503 * @return 504 * - nothing 505 */ 506 static void 507 otx_ep_rx_queue_release(struct rte_eth_dev *dev, uint16_t q_no) 508 { 509 struct otx_ep_droq *rq = dev->data->rx_queues[q_no]; 510 struct otx_ep_device *otx_epvf = rq->otx_ep_dev; 511 int q_id = rq->q_no; 512 513 if (otx_ep_delete_oqs(otx_epvf, q_id)) 514 otx_ep_err("Failed to delete OQ:%d\n", q_id); 515 } 516 517 /** 518 * Allocate and initialize SW ring. Initialize associated HW registers. 519 * 520 * @param eth_dev 521 * Pointer to structure rte_eth_dev 522 * 523 * @param q_no 524 * Queue number 525 * 526 * @param num_tx_descs 527 * Number of ringbuffer descriptors 528 * 529 * @param socket_id 530 * NUMA socket id, used for memory allocations 531 * 532 * @param tx_conf 533 * Pointer to the structure rte_eth_txconf 534 * 535 * @return 536 * - On success, return 0 537 * - On failure, return -errno value 538 */ 539 static int 540 otx_ep_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, 541 uint16_t num_tx_descs, unsigned int socket_id, 542 const struct rte_eth_txconf *tx_conf __rte_unused) 543 { 544 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 545 int retval; 546 547 if (q_no >= otx_epvf->max_tx_queues) { 548 otx_ep_err("Invalid tx queue number %u\n", q_no); 549 return -EINVAL; 550 } 551 if (num_tx_descs & (num_tx_descs - 1)) { 552 otx_ep_err("Invalid tx desc number should be pow 2 %u\n", 553 num_tx_descs); 554 return -EINVAL; 555 } 556 if (num_tx_descs < (SDP_GBL_WMARK * 8)) { 557 otx_ep_err("Invalid tx desc number(%u) should at least be greater than 8*wmark(%u)\n", 558 num_tx_descs, (SDP_GBL_WMARK * 8)); 559 return -EINVAL; 560 } 561 562 retval = otx_ep_setup_iqs(otx_epvf, q_no, num_tx_descs, socket_id); 563 564 if (retval) { 565 otx_ep_err("IQ(TxQ) creation failed.\n"); 566 return retval; 567 } 568 569 eth_dev->data->tx_queues[q_no] = otx_epvf->instr_queue[q_no]; 570 otx_ep_dbg("tx queue[%d] setup\n", q_no); 571 return 0; 572 } 573 574 /** 575 * Release the transmit queue/ringbuffer. Called by 576 * the upper layers. 577 * 578 * @param dev 579 * Pointer to Ethernet device structure. 580 * @param q_no 581 * Transmit queue index. 582 * 583 * @return 584 * - nothing 585 */ 586 static void 587 otx_ep_tx_queue_release(struct rte_eth_dev *dev, uint16_t q_no) 588 { 589 struct otx_ep_instr_queue *tq = dev->data->tx_queues[q_no]; 590 591 otx_ep_delete_iqs(tq->otx_ep_dev, tq->q_no); 592 } 593 594 static int 595 otx_ep_dev_stats_reset(struct rte_eth_dev *dev) 596 { 597 struct otx_ep_device *otx_epvf = OTX_EP_DEV(dev); 598 uint32_t i; 599 600 for (i = 0; i < otx_epvf->nb_tx_queues; i++) 601 memset(&otx_epvf->instr_queue[i]->stats, 0, 602 sizeof(struct otx_ep_iq_stats)); 603 604 for (i = 0; i < otx_epvf->nb_rx_queues; i++) 605 memset(&otx_epvf->droq[i]->stats, 0, 606 sizeof(struct otx_ep_droq_stats)); 607 608 return 0; 609 } 610 611 static int 612 otx_ep_dev_stats_get(struct rte_eth_dev *eth_dev, 613 struct rte_eth_stats *stats) 614 { 615 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 616 struct otx_ep_iq_stats *ostats; 617 struct otx_ep_droq_stats *istats; 618 uint32_t i; 619 620 memset(stats, 0, sizeof(struct rte_eth_stats)); 621 622 for (i = 0; i < otx_epvf->nb_tx_queues; i++) { 623 ostats = &otx_epvf->instr_queue[i]->stats; 624 stats->q_opackets[i] = ostats->tx_pkts; 625 stats->q_obytes[i] = ostats->tx_bytes; 626 stats->opackets += ostats->tx_pkts; 627 stats->obytes += ostats->tx_bytes; 628 stats->oerrors += ostats->instr_dropped; 629 } 630 for (i = 0; i < otx_epvf->nb_rx_queues; i++) { 631 istats = &otx_epvf->droq[i]->stats; 632 stats->q_ipackets[i] = istats->pkts_received; 633 stats->q_ibytes[i] = istats->bytes_received; 634 stats->q_errors[i] = istats->rx_err; 635 stats->ipackets += istats->pkts_received; 636 stats->ibytes += istats->bytes_received; 637 stats->imissed += istats->rx_alloc_failure; 638 stats->ierrors += istats->rx_err; 639 stats->rx_nombuf += istats->rx_alloc_failure; 640 } 641 return 0; 642 } 643 644 static int 645 otx_ep_dev_close(struct rte_eth_dev *eth_dev) 646 { 647 struct otx_ep_device *otx_epvf; 648 uint32_t num_queues, q_no; 649 650 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 651 eth_dev->dev_ops = NULL; 652 eth_dev->rx_pkt_burst = NULL; 653 eth_dev->tx_pkt_burst = NULL; 654 return 0; 655 } 656 657 otx_epvf = OTX_EP_DEV(eth_dev); 658 otx_ep_mbox_send_dev_exit(eth_dev); 659 otx_epvf->fn_list.disable_io_queues(otx_epvf); 660 num_queues = otx_epvf->nb_rx_queues; 661 for (q_no = 0; q_no < num_queues; q_no++) { 662 if (otx_ep_delete_oqs(otx_epvf, q_no)) { 663 otx_ep_err("Failed to delete OQ:%d\n", q_no); 664 return -EINVAL; 665 } 666 } 667 otx_ep_dbg("Num OQs:%d freed\n", otx_epvf->nb_rx_queues); 668 669 num_queues = otx_epvf->nb_tx_queues; 670 for (q_no = 0; q_no < num_queues; q_no++) { 671 if (otx_ep_delete_iqs(otx_epvf, q_no)) { 672 otx_ep_err("Failed to delete IQ:%d\n", q_no); 673 return -EINVAL; 674 } 675 } 676 otx_ep_dbg("Num IQs:%d freed\n", otx_epvf->nb_tx_queues); 677 678 if (rte_eth_dma_zone_free(eth_dev, "ism", 0)) { 679 otx_ep_err("Failed to delete ISM buffer\n"); 680 return -EINVAL; 681 } 682 683 return 0; 684 } 685 686 static int 687 otx_ep_dev_get_mac_addr(struct rte_eth_dev *eth_dev, 688 struct rte_ether_addr *mac_addr) 689 { 690 int ret; 691 692 ret = otx_ep_mbox_get_mac_addr(eth_dev, mac_addr); 693 if (ret) 694 return -EINVAL; 695 otx_ep_dbg("Get MAC address " RTE_ETHER_ADDR_PRT_FMT "\n", 696 RTE_ETHER_ADDR_BYTES(mac_addr)); 697 return 0; 698 } 699 700 /* Define our ethernet definitions */ 701 static const struct eth_dev_ops otx_ep_eth_dev_ops = { 702 .dev_configure = otx_ep_dev_configure, 703 .dev_start = otx_ep_dev_start, 704 .dev_stop = otx_ep_dev_stop, 705 .rx_queue_setup = otx_ep_rx_queue_setup, 706 .rx_queue_release = otx_ep_rx_queue_release, 707 .tx_queue_setup = otx_ep_tx_queue_setup, 708 .tx_queue_release = otx_ep_tx_queue_release, 709 .dev_infos_get = otx_ep_dev_info_get, 710 .stats_get = otx_ep_dev_stats_get, 711 .stats_reset = otx_ep_dev_stats_reset, 712 .link_update = otx_ep_dev_link_update, 713 .dev_close = otx_ep_dev_close, 714 .mtu_set = otx_ep_dev_mtu_set, 715 .mac_addr_set = otx_ep_dev_set_default_mac_addr, 716 }; 717 718 static int 719 otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) 720 { 721 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 722 eth_dev->dev_ops = NULL; 723 eth_dev->rx_pkt_burst = NULL; 724 eth_dev->tx_pkt_burst = NULL; 725 return 0; 726 } 727 728 eth_dev->dev_ops = NULL; 729 eth_dev->rx_pkt_burst = NULL; 730 eth_dev->tx_pkt_burst = NULL; 731 732 return 0; 733 } 734 735 static int otx_ep_eth_dev_query_set_vf_mac(struct rte_eth_dev *eth_dev, 736 struct rte_ether_addr *mac_addr) 737 { 738 int ret_val; 739 740 memset(mac_addr, 0, sizeof(struct rte_ether_addr)); 741 ret_val = otx_ep_dev_get_mac_addr(eth_dev, mac_addr); 742 if (!ret_val) { 743 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 744 otx_ep_dbg("PF doesn't have valid VF MAC addr" RTE_ETHER_ADDR_PRT_FMT "\n", 745 RTE_ETHER_ADDR_BYTES(mac_addr)); 746 rte_eth_random_addr(mac_addr->addr_bytes); 747 otx_ep_dbg("Setting Random MAC address" RTE_ETHER_ADDR_PRT_FMT "\n", 748 RTE_ETHER_ADDR_BYTES(mac_addr)); 749 ret_val = otx_ep_dev_set_default_mac_addr(eth_dev, mac_addr); 750 if (ret_val) { 751 otx_ep_err("Setting MAC address " RTE_ETHER_ADDR_PRT_FMT "fails\n", 752 RTE_ETHER_ADDR_BYTES(mac_addr)); 753 return ret_val; 754 } 755 } 756 otx_ep_dbg("Received valid MAC addr from PF" RTE_ETHER_ADDR_PRT_FMT "\n", 757 RTE_ETHER_ADDR_BYTES(mac_addr)); 758 } else { 759 otx_ep_err("Getting MAC address from PF via Mbox fails with ret_val: %d\n", 760 ret_val); 761 return ret_val; 762 } 763 return 0; 764 } 765 766 static int 767 otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) 768 { 769 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 770 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); 771 struct rte_ether_addr vf_mac_addr; 772 773 /* Single process support */ 774 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 775 eth_dev->dev_ops = &otx_ep_eth_dev_ops; 776 otx_ep_set_tx_func(eth_dev); 777 otx_ep_set_rx_func(eth_dev); 778 return 0; 779 } 780 781 /* Parse devargs string */ 782 if (otx_ethdev_parse_devargs(eth_dev->device->devargs, otx_epvf)) { 783 otx_ep_err("Failed to parse devargs\n"); 784 return -EINVAL; 785 } 786 787 rte_eth_copy_pci_info(eth_dev, pdev); 788 otx_epvf->eth_dev = eth_dev; 789 otx_epvf->port_id = eth_dev->data->port_id; 790 eth_dev->dev_ops = &otx_ep_eth_dev_ops; 791 rte_spinlock_init(&otx_epvf->mbox_lock); 792 793 /* 794 * Initialize negotiated Mbox version to base version of VF Mbox 795 * This will address working legacy PF with latest VF. 796 */ 797 otx_epvf->mbox_neg_ver = OTX_EP_MBOX_VERSION_V1; 798 eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); 799 if (eth_dev->data->mac_addrs == NULL) { 800 otx_ep_err("MAC addresses memory allocation failed\n"); 801 eth_dev->dev_ops = NULL; 802 return -ENOMEM; 803 } 804 rte_eth_random_addr(vf_mac_addr.addr_bytes); 805 rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs); 806 otx_epvf->hw_addr = pdev->mem_resource[0].addr; 807 otx_epvf->pdev = pdev; 808 809 if (otx_epdev_init(otx_epvf)) 810 return -ENOMEM; 811 if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF || 812 otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF || 813 otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF || 814 otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF || 815 otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF || 816 otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF || 817 otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF || 818 otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) { 819 otx_epvf->pkind = SDP_OTX2_PKIND_FS0; 820 otx_ep_info("using pkind %d\n", otx_epvf->pkind); 821 } else if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF) { 822 otx_epvf->pkind = SDP_PKIND; 823 otx_ep_info("Using pkind %d.\n", otx_epvf->pkind); 824 } else { 825 otx_ep_err("Invalid chip id\n"); 826 return -EINVAL; 827 } 828 829 if (otx_ep_mbox_version_check(eth_dev)) 830 return -EINVAL; 831 832 if (otx_ep_eth_dev_query_set_vf_mac(eth_dev, 833 (struct rte_ether_addr *)&vf_mac_addr)) { 834 otx_ep_err("set mac addr failed\n"); 835 return -ENODEV; 836 } 837 rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs); 838 839 return 0; 840 } 841 842 static int 843 otx_ep_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 844 struct rte_pci_device *pci_dev) 845 { 846 return rte_eth_dev_pci_generic_probe(pci_dev, 847 sizeof(struct otx_ep_device), 848 otx_ep_eth_dev_init); 849 } 850 851 static int 852 otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 853 { 854 return rte_eth_dev_pci_generic_remove(pci_dev, 855 otx_ep_eth_dev_uninit); 856 } 857 858 /* Set of PCI devices this driver supports */ 859 static const struct rte_pci_id pci_id_otx_ep_map[] = { 860 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) }, 861 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_EP_NET_VF) }, 862 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) }, 863 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95N_EP_NET_VF) }, 864 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95O_EP_NET_VF) }, 865 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KA_EP_NET_VF) }, 866 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_EP_NET_VF) }, 867 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF10KA_EP_NET_VF) }, 868 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF10KB_EP_NET_VF) }, 869 { .vendor_id = 0, /* sentinel */ } 870 }; 871 872 static struct rte_pci_driver rte_otx_ep_pmd = { 873 .id_table = pci_id_otx_ep_map, 874 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 875 .probe = otx_ep_eth_dev_pci_probe, 876 .remove = otx_ep_eth_dev_pci_remove, 877 }; 878 879 RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd); 880 RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map); 881 RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci"); 882 RTE_LOG_REGISTER_DEFAULT(otx_net_ep_logtype, NOTICE); 883 RTE_PMD_REGISTER_PARAM_STRING(net_otx_ep, 884 OTX_ISM_ENABLE "=<0|1>"); 885