1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #include "ntlog.h" 7 8 #include "nthw_drv.h" 9 #include "nthw_register.h" 10 11 #include "nthw_pcie3.h" 12 13 #define NTHW_TG_REF_FREQ (250000000ULL) 14 15 nthw_pcie3_t *nthw_pcie3_new(void) 16 { 17 nthw_pcie3_t *p = malloc(sizeof(nthw_pcie3_t)); 18 19 if (p) 20 memset(p, 0, sizeof(nthw_pcie3_t)); 21 22 return p; 23 } 24 25 void nthw_pcie3_delete(nthw_pcie3_t *p) 26 { 27 if (p) { 28 memset(p, 0, sizeof(nthw_pcie3_t)); 29 free(p); 30 } 31 } 32 33 int nthw_pcie3_init(nthw_pcie3_t *p, nthw_fpga_t *p_fpga, int n_instance) 34 { 35 nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_PCIE3, n_instance); 36 37 if (p == NULL) 38 return mod == NULL ? -1 : 0; 39 40 if (mod == NULL) { 41 NT_LOG(ERR, NTHW, "%s: PCIE3 %d: no such instance", 42 p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); 43 return -1; 44 } 45 46 p->mp_fpga = p_fpga; 47 p->mn_instance = n_instance; 48 p->mp_mod_pcie3 = mod; 49 50 /* PCIe3 */ 51 p->mp_reg_stat_ctrl = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_CTRL); 52 p->mp_fld_stat_ctrl_ena = 53 nthw_register_get_field(p->mp_reg_stat_ctrl, PCIE3_STAT_CTRL_STAT_ENA); 54 p->mp_fld_stat_ctrl_req = 55 nthw_register_get_field(p->mp_reg_stat_ctrl, PCIE3_STAT_CTRL_STAT_REQ); 56 57 p->mp_reg_stat_rx = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_RX); 58 p->mp_fld_stat_rx_counter = 59 nthw_register_get_field(p->mp_reg_stat_rx, PCIE3_STAT_RX_COUNTER); 60 61 p->mp_reg_stat_tx = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_TX); 62 p->mp_fld_stat_tx_counter = 63 nthw_register_get_field(p->mp_reg_stat_tx, PCIE3_STAT_TX_COUNTER); 64 65 p->mp_reg_stat_ref_clk = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_REFCLK); 66 p->mp_fld_stat_ref_clk_ref_clk = 67 nthw_register_get_field(p->mp_reg_stat_ref_clk, PCIE3_STAT_REFCLK_REFCLK250); 68 69 p->mp_reg_stat_rq_rdy = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_RQ_RDY); 70 p->mp_fld_stat_rq_rdy_counter = 71 nthw_register_get_field(p->mp_reg_stat_rq_rdy, PCIE3_STAT_RQ_RDY_COUNTER); 72 73 p->mp_reg_stat_rq_vld = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_RQ_VLD); 74 p->mp_fld_stat_rq_vld_counter = 75 nthw_register_get_field(p->mp_reg_stat_rq_vld, PCIE3_STAT_RQ_VLD_COUNTER); 76 77 p->mp_reg_status0 = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STATUS0); 78 p->mp_fld_status0_tags_in_use = 79 nthw_register_get_field(p->mp_reg_status0, PCIE3_STATUS0_TAGS_IN_USE); 80 81 p->mp_reg_rp_to_ep_err = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_RP_TO_EP_ERR); 82 p->mp_fld_rp_to_ep_err_cor = 83 nthw_register_get_field(p->mp_reg_rp_to_ep_err, PCIE3_RP_TO_EP_ERR_ERR_COR); 84 p->mp_fld_rp_to_ep_err_non_fatal = 85 nthw_register_get_field(p->mp_reg_rp_to_ep_err, PCIE3_RP_TO_EP_ERR_ERR_NONFATAL); 86 p->mp_fld_rp_to_ep_err_fatal = 87 nthw_register_get_field(p->mp_reg_rp_to_ep_err, PCIE3_RP_TO_EP_ERR_ERR_FATAL); 88 89 p->mp_reg_ep_to_rp_err = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_EP_TO_RP_ERR); 90 p->mp_fld_ep_to_rp_err_cor = 91 nthw_register_get_field(p->mp_reg_ep_to_rp_err, PCIE3_EP_TO_RP_ERR_ERR_COR); 92 p->mp_fld_ep_to_rp_err_non_fatal = 93 nthw_register_get_field(p->mp_reg_ep_to_rp_err, PCIE3_EP_TO_RP_ERR_ERR_NONFATAL); 94 p->mp_fld_ep_to_rp_err_fatal = 95 nthw_register_get_field(p->mp_reg_ep_to_rp_err, PCIE3_EP_TO_RP_ERR_ERR_FATAL); 96 97 p->mp_reg_sample_time = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_SAMPLE_TIME); 98 p->mp_fld_sample_time = 99 nthw_register_get_field(p->mp_reg_sample_time, PCIE3_SAMPLE_TIME_SAMPLE_TIME); 100 101 p->mp_reg_pci_end_point = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_PCI_ENDPOINT); 102 p->mp_fld_pci_end_point_if_id = 103 nthw_register_get_field(p->mp_reg_pci_end_point, PCIE3_PCI_ENDPOINT_IF_ID); 104 p->mp_fld_pci_end_point_send_msg = 105 nthw_register_get_field(p->mp_reg_pci_end_point, PCIE3_PCI_ENDPOINT_SEND_MSG); 106 p->mp_fld_pci_end_point_get_msg = 107 nthw_register_get_field(p->mp_reg_pci_end_point, PCIE3_PCI_ENDPOINT_GET_MSG); 108 p->mp_fld_pci_end_point_dmaep0_allow_mask = 109 nthw_register_get_field(p->mp_reg_pci_end_point, 110 PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK); 111 p->mp_fld_pci_end_point_dmaep1_allow_mask = 112 nthw_register_get_field(p->mp_reg_pci_end_point, 113 PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK); 114 115 if (p->mp_reg_pci_end_point) 116 nthw_register_update(p->mp_reg_pci_end_point); 117 118 p->mp_reg_pci_test0 = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_PCI_TEST0); 119 p->mp_fld_pci_test0 = nthw_register_get_field(p->mp_reg_pci_test0, PCIE3_PCI_TEST0_DATA); 120 121 if (p->mp_reg_pci_test0) 122 nthw_register_update(p->mp_reg_pci_test0); 123 124 p->mp_reg_pci_test1 = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_PCI_TEST1); 125 p->mp_fld_pci_test1 = nthw_register_get_field(p->mp_reg_pci_test1, PCIE3_PCI_TEST1_DATA); 126 127 if (p->mp_reg_pci_test1) 128 nthw_register_update(p->mp_reg_pci_test1); 129 130 p->mp_reg_pci_e3_mark_adr_lsb = 131 nthw_module_get_register(p->mp_mod_pcie3, PCIE3_MARKADR_LSB); 132 p->mp_fld_pci_e3_mark_adr_lsb_adr = 133 nthw_register_get_field(p->mp_reg_pci_e3_mark_adr_lsb, PCIE3_MARKADR_LSB_ADR); 134 135 if (p->mp_reg_pci_e3_mark_adr_lsb) 136 nthw_register_update(p->mp_reg_pci_e3_mark_adr_lsb); 137 138 p->mp_reg_pci_e3_mark_adr_msb = 139 nthw_module_get_register(p->mp_mod_pcie3, PCIE3_MARKADR_MSB); 140 p->mp_fld_pci_e3_mark_adr_msb_adr = 141 nthw_register_get_field(p->mp_reg_pci_e3_mark_adr_msb, PCIE3_MARKADR_MSB_ADR); 142 143 if (p->mp_reg_pci_e3_mark_adr_msb) 144 nthw_register_update(p->mp_reg_pci_e3_mark_adr_msb); 145 146 /* Initial setup - disable markerscheme and bifurcation */ 147 if (p->mp_fld_pci_end_point_dmaep0_allow_mask) 148 nthw_field_clr_flush(p->mp_fld_pci_end_point_dmaep0_allow_mask); 149 150 if (p->mp_fld_pci_end_point_dmaep1_allow_mask) 151 nthw_field_clr_flush(p->mp_fld_pci_end_point_dmaep1_allow_mask); 152 153 if (p->mp_fld_pci_e3_mark_adr_lsb_adr) 154 nthw_field_set_val_flush32(p->mp_fld_pci_e3_mark_adr_lsb_adr, 0UL); 155 156 if (p->mp_fld_pci_e3_mark_adr_msb_adr) 157 nthw_field_set_val_flush32(p->mp_fld_pci_e3_mark_adr_msb_adr, 0UL); 158 159 if (p->mp_fld_pci_end_point_dmaep0_allow_mask) 160 nthw_field_set_flush(p->mp_fld_pci_end_point_dmaep0_allow_mask); 161 162 if (p->mp_fld_pci_end_point_dmaep1_allow_mask) 163 nthw_field_clr_flush(p->mp_fld_pci_end_point_dmaep1_allow_mask); 164 165 return 0; 166 }; 167 168 int nthw_pcie3_trigger_sample_time(nthw_pcie3_t *p) 169 { 170 nthw_field_set_val_flush32(p->mp_fld_sample_time, 0xfee1dead); 171 172 return 0; 173 } 174 175 int nthw_pcie3_stat_req_enable(nthw_pcie3_t *p) 176 { 177 nthw_field_set_all(p->mp_fld_stat_ctrl_ena); 178 nthw_field_set_all(p->mp_fld_stat_ctrl_req); 179 nthw_field_flush_register(p->mp_fld_stat_ctrl_req); 180 return 0; 181 } 182 183 int nthw_pcie3_stat_req_disable(nthw_pcie3_t *p) 184 { 185 nthw_field_clr_all(p->mp_fld_stat_ctrl_ena); 186 nthw_field_set_all(p->mp_fld_stat_ctrl_req); 187 nthw_field_flush_register(p->mp_fld_stat_ctrl_req); 188 return 0; 189 } 190 191 int nthw_pcie3_get_stat(nthw_pcie3_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt, 192 uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq, 193 uint32_t *p_tag_use_cnt, uint32_t *p_rq_rdy_cnt, uint32_t *p_rq_vld_cnt) 194 { 195 *p_rx_cnt = nthw_field_get_updated(p->mp_fld_stat_rx_counter); 196 *p_tx_cnt = nthw_field_get_updated(p->mp_fld_stat_tx_counter); 197 198 *p_ref_clk_cnt = nthw_field_get_updated(p->mp_fld_stat_ref_clk_ref_clk); 199 200 *p_tg_unit_size = NTHW_TG_CNT_SIZE; 201 *p_tg_ref_freq = NTHW_TG_REF_FREQ; 202 203 *p_tag_use_cnt = nthw_field_get_updated(p->mp_fld_status0_tags_in_use); 204 205 *p_rq_rdy_cnt = nthw_field_get_updated(p->mp_fld_stat_rq_rdy_counter); 206 *p_rq_vld_cnt = nthw_field_get_updated(p->mp_fld_stat_rq_vld_counter); 207 208 return 0; 209 } 210 211 int nthw_pcie3_get_stat_rate(nthw_pcie3_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate, 212 uint64_t *p_ref_clk_cnt, uint64_t *p_tag_use_cnt, 213 uint64_t *p_pci_nt_bus_util, uint64_t *p_pci_xil_bus_util) 214 { 215 uint32_t rx_cnt, tx_cnt, ref_clk_cnt; 216 uint32_t tg_unit_size, tg_ref_freq; 217 uint32_t tag_use_cnt, rq_rdy_cnt, rq_vld_cnt; 218 219 nthw_pcie3_get_stat(p, &rx_cnt, &tx_cnt, &ref_clk_cnt, &tg_unit_size, &tg_ref_freq, 220 &tag_use_cnt, &rq_rdy_cnt, &rq_vld_cnt); 221 222 if (ref_clk_cnt) { 223 uint64_t nt_bus_util, xil_bus_util; 224 uint64_t rx_rate, tx_rate; 225 226 rx_rate = ((uint64_t)rx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt; 227 *p_pci_rx_rate = rx_rate; 228 229 tx_rate = ((uint64_t)tx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt; 230 *p_pci_tx_rate = tx_rate; 231 232 *p_ref_clk_cnt = ref_clk_cnt; 233 234 *p_tag_use_cnt = tag_use_cnt; 235 236 nt_bus_util = ((uint64_t)rq_vld_cnt * 1000000ULL) / (uint64_t)ref_clk_cnt; 237 *p_pci_nt_bus_util = nt_bus_util; 238 xil_bus_util = ((uint64_t)rq_rdy_cnt * 1000000ULL) / (uint64_t)ref_clk_cnt; 239 *p_pci_xil_bus_util = xil_bus_util; 240 241 } else { 242 *p_ref_clk_cnt = 0; 243 *p_pci_nt_bus_util = 0; 244 *p_pci_xil_bus_util = 0; 245 } 246 247 return 0; 248 } 249 250 int nthw_pcie3_end_point_counters_sample_post(nthw_pcie3_t *p, 251 struct nthw_hif_end_point_counters *epc) 252 { 253 NT_LOG_DBGX(DBG, NTHW); 254 assert(epc); 255 nthw_pcie3_get_stat_rate(p, &epc->cur_tx, &epc->cur_rx, &epc->n_ref_clk_cnt, 256 &epc->n_tags_in_use, &epc->cur_pci_nt_util, 257 &epc->cur_pci_xil_util); 258 return 0; 259 } 260