1*27c15342SSerhii Iliushyk /* 2*27c15342SSerhii Iliushyk * SPDX-License-Identifier: BSD-3-Clause 3*27c15342SSerhii Iliushyk * Copyright(c) 2023 Napatech A/S 4*27c15342SSerhii Iliushyk */ 5*27c15342SSerhii Iliushyk 6*27c15342SSerhii Iliushyk #ifndef _QSFP_REGISTERS_H 7*27c15342SSerhii Iliushyk #define _QSFP_REGISTERS_H 8*27c15342SSerhii Iliushyk 9*27c15342SSerhii Iliushyk /* 10*27c15342SSerhii Iliushyk * QSFP Registers 11*27c15342SSerhii Iliushyk */ 12*27c15342SSerhii Iliushyk #define QSFP_INT_STATUS_RX_LOS_ADDR 3 13*27c15342SSerhii Iliushyk #define QSFP_TEMP_LIN_ADDR 22 14*27c15342SSerhii Iliushyk #define QSFP_VOLT_LIN_ADDR 26 15*27c15342SSerhii Iliushyk #define QSFP_RX_PWR_LIN_ADDR 34 /* uint16_t [0..3] */ 16*27c15342SSerhii Iliushyk #define QSFP_TX_BIAS_LIN_ADDR 42/* uint16_t [0..3] */ 17*27c15342SSerhii Iliushyk #define QSFP_TX_PWR_LIN_ADDR 50 /* uint16_t [0..3] */ 18*27c15342SSerhii Iliushyk 19*27c15342SSerhii Iliushyk #define QSFP_CONTROL_STATUS_LIN_ADDR 86 20*27c15342SSerhii Iliushyk #define QSFP_SOFT_TX_ALL_DISABLE_BITS 0x0F 21*27c15342SSerhii Iliushyk 22*27c15342SSerhii Iliushyk #define QSFP_POWER_CLASS_BITS_1_4 0xC0 23*27c15342SSerhii Iliushyk #define QSFP_POWER_CLASS_BITS_5_7 0x03 24*27c15342SSerhii Iliushyk 25*27c15342SSerhii Iliushyk #define QSFP_SUP_LEN_INFO_LIN_ADDR 142 /* 5bytes */ 26*27c15342SSerhii Iliushyk #define QSFP_TRANSMITTER_TYPE_LIN_ADDR 147 /* 1byte */ 27*27c15342SSerhii Iliushyk #define QSFP_VENDOR_NAME_LIN_ADDR 148 /* 16bytes */ 28*27c15342SSerhii Iliushyk #define QSFP_VENDOR_PN_LIN_ADDR 168 /* 16bytes */ 29*27c15342SSerhii Iliushyk #define QSFP_VENDOR_SN_LIN_ADDR 196 /* 16bytes */ 30*27c15342SSerhii Iliushyk #define QSFP_VENDOR_DATE_LIN_ADDR 212 /* 8bytes */ 31*27c15342SSerhii Iliushyk #define QSFP_VENDOR_REV_LIN_ADDR 184 /* 2bytes */ 32*27c15342SSerhii Iliushyk 33*27c15342SSerhii Iliushyk #define QSFP_SPEC_COMPLIANCE_CODES_ADDR 131 /* 8 bytes */ 34*27c15342SSerhii Iliushyk #define QSFP_EXT_SPEC_COMPLIANCE_CODES_ADDR 192 /* 1 byte */ 35*27c15342SSerhii Iliushyk 36*27c15342SSerhii Iliushyk #define QSFP_OPTION3_LIN_ADDR 195 37*27c15342SSerhii Iliushyk #define QSFP_OPTION3_TX_DISABLE_BIT (1 << 4) 38*27c15342SSerhii Iliushyk 39*27c15342SSerhii Iliushyk #define QSFP_DMI_OPTION_LIN_ADDR 220 40*27c15342SSerhii Iliushyk #define QSFP_DMI_AVG_PWR_BIT (1 << 3) 41*27c15342SSerhii Iliushyk 42*27c15342SSerhii Iliushyk 43*27c15342SSerhii Iliushyk #endif /* _QSFP_REGISTERS_H */ 44