13a8d7a49SSerhii Iliushyk /* 23a8d7a49SSerhii Iliushyk * SPDX-License-Identifier: BSD-3-Clause 33a8d7a49SSerhii Iliushyk * Copyright(c) 2023 Napatech A/S 43a8d7a49SSerhii Iliushyk */ 53a8d7a49SSerhii Iliushyk 63a8d7a49SSerhii Iliushyk #ifndef __NTNIC_NTHW_FPGA_RST_NT200A0X_H__ 73a8d7a49SSerhii Iliushyk #define __NTNIC_NTHW_FPGA_RST_NT200A0X_H__ 83a8d7a49SSerhii Iliushyk 93a8d7a49SSerhii Iliushyk #include "nthw_drv.h" 103a8d7a49SSerhii Iliushyk #include "nthw_fpga_model.h" 113a8d7a49SSerhii Iliushyk 123a8d7a49SSerhii Iliushyk struct nthw_fpga_rst_nt200a0x { 133a8d7a49SSerhii Iliushyk int mn_fpga_product_id; 143a8d7a49SSerhii Iliushyk int mn_fpga_version; 153a8d7a49SSerhii Iliushyk int mn_fpga_revision; 163a8d7a49SSerhii Iliushyk 173a8d7a49SSerhii Iliushyk int mn_hw_id; 183a8d7a49SSerhii Iliushyk 193a8d7a49SSerhii Iliushyk int mn_si_labs_clock_synth_model; 20*c8662c87SSerhii Iliushyk uint8_t mn_si_labs_clock_synth_i2c_addr; 213a8d7a49SSerhii Iliushyk 223a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_sys; 233a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_sys_mmcm; 243a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_core_mmcm; 253a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_rpp; 263a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_ddr4; 273a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_sdc; 283a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_phy; 293a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_serdes_rx; 303a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_serdes_tx; 313a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_serdes_rx_datapath; 323a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_pcs_rx; 333a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_mac_rx; 343a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_mac_tx; 353a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_ptp; 363a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_ts; 373a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_ptp_mmcm; 383a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_ts_mmcm; 393a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_periph; 403a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_tsm_ref_mmcm; 413a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_rst_tmc; 423a8d7a49SSerhii Iliushyk 433a8d7a49SSerhii Iliushyk /* CTRL register field pointers */ 443a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_ctrl_ts_clk_sel_override; 453a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_ctrl_ts_clk_sel; 463a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_ctrl_ts_clk_sel_ref; 473a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_ctrl_ptp_mmcm_clk_sel; 483a8d7a49SSerhii Iliushyk 493a8d7a49SSerhii Iliushyk /* STAT register field pointers */ 503a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_ddr4_mmcm_locked; 513a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_sys_mmcm_locked; 523a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_core_mmcm_locked; 533a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_ddr4_pll_locked; 543a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_ptp_mmcm_locked; 553a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_ts_mmcm_locked; 563a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_stat_tsm_ref_mmcm_locked; 573a8d7a49SSerhii Iliushyk 583a8d7a49SSerhii Iliushyk /* STICKY register field pointers */ 593a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_ptp_mmcm_unlocked; 603a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_ts_mmcm_unlocked; 613a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_ddr4_mmcm_unlocked; 623a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_ddr4_pll_unlocked; 633a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_core_mmcm_unlocked; 643a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_pci_sys_mmcm_unlocked; 653a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_sticky_tsm_ref_mmcm_unlocked; 663a8d7a49SSerhii Iliushyk 673a8d7a49SSerhii Iliushyk /* POWER register field pointers */ 683a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_power_pu_phy; 693a8d7a49SSerhii Iliushyk nthw_field_t *mp_fld_power_pu_nseb; 703a8d7a49SSerhii Iliushyk 713a8d7a49SSerhii Iliushyk void (*reset_serdes_rx)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, uint32_t rst); 723a8d7a49SSerhii Iliushyk void (*pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, uint32_t rst); 733a8d7a49SSerhii Iliushyk void (*get_serdes_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, 743a8d7a49SSerhii Iliushyk uint32_t *p_set); 753a8d7a49SSerhii Iliushyk void (*get_pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, 763a8d7a49SSerhii Iliushyk uint32_t *p_set); 773a8d7a49SSerhii Iliushyk bool (*is_rst_serdes_rx_datapath_implemented)(struct nthw_fpga_rst_nt200a0x *p); 783a8d7a49SSerhii Iliushyk }; 793a8d7a49SSerhii Iliushyk 803a8d7a49SSerhii Iliushyk typedef struct nthw_fpga_rst_nt200a0x nthw_fpga_rst_nt200a0x_t; 813a8d7a49SSerhii Iliushyk 823a8d7a49SSerhii Iliushyk #endif /* __NTHW_FPGA_RST_NT200A0X_H__ */ 83