1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2014, 2015 Netronome Systems, Inc. 3 * All rights reserved. 4 */ 5 6 /* 7 * vim:shiftwidth=8:noexpandtab 8 * 9 * Netronome network device driver: Control BAR layout 10 */ 11 #ifndef _NFP_NET_CTRL_H_ 12 #define _NFP_NET_CTRL_H_ 13 14 /* 15 * Configuration BAR size. 16 * 17 * The configuration BAR is 8K in size, but on the NFP6000, due to 18 * THB-350, 32k needs to be reserved. 19 */ 20 #ifdef __NFP_IS_6000 21 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 22 #else 23 #define NFP_NET_CFG_BAR_SZ (8 * 1024) 24 #endif 25 26 /* Offset in Freelist buffer where packet starts on RX */ 27 #define NFP_NET_RX_OFFSET 32 28 29 /* working with metadata api (NFD version > 3.0) */ 30 #define NFP_NET_META_FIELD_SIZE 4 31 #define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1) 32 33 /* Prepend field types */ 34 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 35 36 /* Hash type pre-pended when a RSS hash was computed */ 37 #define NFP_NET_RSS_NONE 0 38 #define NFP_NET_RSS_IPV4 1 39 #define NFP_NET_RSS_IPV6 2 40 #define NFP_NET_RSS_IPV6_EX 3 41 #define NFP_NET_RSS_IPV4_TCP 4 42 #define NFP_NET_RSS_IPV6_TCP 5 43 #define NFP_NET_RSS_IPV6_EX_TCP 6 44 #define NFP_NET_RSS_IPV4_UDP 7 45 #define NFP_NET_RSS_IPV6_UDP 8 46 #define NFP_NET_RSS_IPV6_EX_UDP 9 47 48 /* 49 * @NFP_NET_TXR_MAX: Maximum number of TX rings 50 * @NFP_NET_TXR_MASK: Mask for TX rings 51 * @NFP_NET_RXR_MAX: Maximum number of RX rings 52 * @NFP_NET_RXR_MASK: Mask for RX rings 53 */ 54 #define NFP_NET_TXR_MAX 64 55 #define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1) 56 #define NFP_NET_RXR_MAX 64 57 #define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1) 58 59 /* 60 * Read/Write config words (0x0000 - 0x002c) 61 * @NFP_NET_CFG_CTRL: Global control 62 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 63 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 64 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 65 * @NFP_NET_CFG_MTU: Set MTU size 66 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 67 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 68 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 69 * @NFP_NET_CFG_MACADDR: MAC address 70 * 71 * TODO: 72 * - define Error details in UPDATE 73 */ 74 #define NFP_NET_CFG_CTRL 0x0000 75 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 76 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 77 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 78 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 79 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 80 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 81 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 82 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 83 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 84 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 85 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 86 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 87 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 88 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 89 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 90 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 91 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 92 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 93 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 94 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */ 95 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */ 96 #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ 97 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 98 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 99 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31)/* live MAC addr change */ 100 #define NFP_NET_CFG_UPDATE 0x0004 101 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 102 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 103 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 104 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 105 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 106 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 107 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 108 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 109 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 110 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 111 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 112 #define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */ 113 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 114 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 115 #define NFP_NET_CFG_MTU 0x0018 116 #define NFP_NET_CFG_FLBUFSZ 0x001c 117 #define NFP_NET_CFG_EXN 0x001f 118 #define NFP_NET_CFG_LSC 0x0020 119 #define NFP_NET_CFG_MACADDR 0x0024 120 121 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2) 122 123 /* 124 * Read-only words (0x0030 - 0x0050): 125 * @NFP_NET_CFG_VERSION: Firmware version number 126 * @NFP_NET_CFG_STS: Status 127 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 128 * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings 129 * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings 130 * @NFP_NET_MAX_MTU: Maximum support MTU 131 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 132 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 133 * 134 * TODO: 135 * - define more STS bits 136 */ 137 #define NFP_NET_CFG_VERSION 0x0030 138 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 139 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 140 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 141 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 142 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 143 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 144 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 145 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 146 #define NFP_NET_CFG_STS 0x0034 147 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 148 /* Link rate */ 149 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 150 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 151 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 152 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 153 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 154 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 155 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 156 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 157 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 158 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 159 #define NFP_NET_CFG_CAP 0x0038 160 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 161 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 162 #define NFP_NET_CFG_MAX_MTU 0x0044 163 /* Next two words are being used by VFs for solving THB350 issue */ 164 #define NFP_NET_CFG_START_TXQ 0x0048 165 #define NFP_NET_CFG_START_RXQ 0x004c 166 167 /* 168 * NFP-3200 workaround (0x0050 - 0x0058) 169 * @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix) 170 */ 171 #define NFP_NET_CFG_SPARE_ADDR 0x0050 172 /** 173 * NFP6000/NFP4000 - Prepend configuration 174 */ 175 #define NFP_NET_CFG_RX_OFFSET 0x0050 176 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 177 178 /** 179 * Reuse spare address to contain the offset from the start of 180 * the host buffer where the first byte of the received frame 181 * will land. Any metadata will come prior to that offset. If the 182 * value in this field is 0, it means that that the metadata will 183 * always land starting at the first byte of the host buffer and 184 * packet data will immediately follow the metadata. As always, 185 * the RX descriptor indicates the presence or absence of metadata 186 * along with the length thereof. 187 */ 188 #define NFP_NET_CFG_RX_OFFSET_ADDR 0x0050 189 190 #define NFP_NET_CFG_VXLAN_PORT 0x0060 191 #define NFP_NET_CFG_VXLAN_SZ 0x0008 192 193 /* Offload definitions */ 194 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t)) 195 196 /** 197 * 64B reserved for future use (0x0080 - 0x00c0) 198 */ 199 #define NFP_NET_CFG_RESERVED 0x0080 200 #define NFP_NET_CFG_RESERVED_SZ 0x0040 201 202 /* 203 * RSS configuration (0x0100 - 0x01ac): 204 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 205 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 206 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 207 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 208 */ 209 #define NFP_NET_CFG_RSS_BASE 0x0100 210 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 211 #define NFP_NET_CFG_RSS_MASK (0x7f) 212 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 213 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 214 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 215 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 216 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 217 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 218 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 219 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 220 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 221 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 222 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 223 NFP_NET_CFG_RSS_KEY_SZ) 224 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 225 226 /* 227 * TX ring configuration (0x200 - 0x800) 228 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 229 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 230 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 231 * @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 232 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 233 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 234 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 235 */ 236 #define NFP_NET_CFG_TXR_BASE 0x0200 237 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 238 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 239 ((_x) * 0x8)) 240 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 241 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 242 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 243 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 244 ((_x) * 0x4)) 245 246 /* 247 * RX ring configuration (0x0800 - 0x0c00) 248 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 249 * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries) 250 * @NFP_NET_CFG_RXR_SZ: Per TX ring ring size (1B entries) 251 * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries) 252 * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries) 253 * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 254 */ 255 #define NFP_NET_CFG_RXR_BASE 0x0800 256 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 257 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 258 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 259 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 260 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 261 ((_x) * 0x4)) 262 263 /* 264 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 265 * These registers are only used when MSI-X auto-masking is not 266 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 267 * by MSI-X entry and are 1B in size. If an entry is zero, the 268 * corresponding entry is enabled. If the FW generates an interrupt, 269 * it writes a cause into the corresponding field. This also masks 270 * the MSI-X entry and the host driver must clear the register to 271 * re-enable the interrupt. 272 */ 273 #define NFP_NET_CFG_ICR_BASE 0x0c00 274 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 275 #define NFP_NET_CFG_ICR_UNMASKED 0x0 276 #define NFP_NET_CFG_ICR_RXTX 0x1 277 #define NFP_NET_CFG_ICR_LSC 0x2 278 279 /* 280 * General device stats (0x0d00 - 0x0d90) 281 * all counters are 64bit. 282 */ 283 #define NFP_NET_CFG_STATS_BASE 0x0d00 284 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 285 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 286 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 287 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 288 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 289 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 290 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 291 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 292 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 293 294 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 295 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 296 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 297 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 298 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 299 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 300 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 301 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 302 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 303 304 /* 305 * Per ring stats (0x1000 - 0x1800) 306 * options, 64bit per entry 307 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 308 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 309 */ 310 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 311 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 312 ((_x) * 0x10)) 313 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 314 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 315 ((_x) * 0x10)) 316 317 /* PF multiport offset */ 318 #define NFP_PF_CSR_SLICE_SIZE (32 * 1024) 319 320 #endif /* _NFP_NET_CTRL_H_ */ 321 /* 322 * Local variables: 323 * c-file-style: "Linux" 324 * indent-tabs-mode: t 325 * End: 326 */ 327