1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Marvell International Ltd. 3 * Copyright(c) 2017-2021 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_string_fns.h> 8 #include <ethdev_driver.h> 9 #include <rte_kvargs.h> 10 #include <rte_log.h> 11 #include <rte_malloc.h> 12 #include <rte_bus_vdev.h> 13 14 #include <fcntl.h> 15 #include <linux/ethtool.h> 16 #include <linux/sockios.h> 17 #include <net/if.h> 18 #include <net/if_arp.h> 19 #include <sys/ioctl.h> 20 #include <sys/socket.h> 21 #include <sys/stat.h> 22 #include <sys/types.h> 23 24 #include <rte_mvep_common.h> 25 #include "mrvl_ethdev.h" 26 #include "mrvl_qos.h" 27 #include "mrvl_flow.h" 28 #include "mrvl_mtr.h" 29 #include "mrvl_tm.h" 30 31 /* bitmask with reserved hifs */ 32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 33 /* bitmask with reserved bpools */ 34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 35 /* bitmask with reserved kernel RSS tables */ 36 #define MRVL_MUSDK_RSS_RESERVED 0x0F 37 /* maximum number of available hifs */ 38 #define MRVL_MUSDK_HIFS_MAX 9 39 40 /* prefetch shift */ 41 #define MRVL_MUSDK_PREFETCH_SHIFT 2 42 43 /* TCAM has 25 entries reserved for uc/mc filter entries */ 44 #define MRVL_MAC_ADDRS_MAX 25 45 #define MRVL_MATCH_LEN 16 46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 47 /* Maximum allowable packet size */ 48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 49 50 #define MRVL_IFACE_NAME_ARG "iface" 51 #define MRVL_CFG_ARG "cfg" 52 53 #define MRVL_BURST_SIZE 64 54 55 #define MRVL_ARP_LENGTH 28 56 57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000 59 60 /** Port Rx offload capabilities */ 61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ 62 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 63 DEV_RX_OFFLOAD_CHECKSUM) 64 65 /** Port Tx offloads capabilities */ 66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 67 DEV_TX_OFFLOAD_UDP_CKSUM | \ 68 DEV_TX_OFFLOAD_TCP_CKSUM | \ 69 DEV_TX_OFFLOAD_MULTI_SEGS) 70 71 static const char * const valid_args[] = { 72 MRVL_IFACE_NAME_ARG, 73 MRVL_CFG_ARG, 74 NULL 75 }; 76 77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 78 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 79 static int used_bpools[PP2_NUM_PKT_PROC] = { 80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 81 }; 82 83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 86 87 struct mrvl_ifnames { 88 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 89 int idx; 90 }; 91 92 /* 93 * To use buffer harvesting based on loopback port shadow queue structure 94 * was introduced for buffers information bookkeeping. 95 * 96 * Before sending the packet, related buffer information (pp2_buff_inf) is 97 * stored in shadow queue. After packet is transmitted no longer used 98 * packet buffer is released back to it's original hardware pool, 99 * on condition it originated from interface. 100 * In case it was generated by application itself i.e: mbuf->port field is 101 * 0xff then its released to software mempool. 102 */ 103 struct mrvl_shadow_txq { 104 int head; /* write index - used when sending buffers */ 105 int tail; /* read index - used when releasing buffers */ 106 u16 size; /* queue occupied size */ 107 u16 num_to_release; /* number of descriptors sent, that can be 108 * released 109 */ 110 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 111 }; 112 113 struct mrvl_rxq { 114 struct mrvl_priv *priv; 115 struct rte_mempool *mp; 116 int queue_id; 117 int port_id; 118 int cksum_enabled; 119 uint64_t bytes_recv; 120 uint64_t drop_mac; 121 }; 122 123 struct mrvl_txq { 124 struct mrvl_priv *priv; 125 int queue_id; 126 int port_id; 127 uint64_t bytes_sent; 128 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 129 int tx_deferred_start; 130 }; 131 132 static int mrvl_lcore_first; 133 static int mrvl_lcore_last; 134 static int mrvl_dev_num; 135 136 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 137 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 138 struct pp2_hif *hif, unsigned int core_id, 139 struct mrvl_shadow_txq *sq, int qid, int force); 140 141 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 142 uint16_t nb_pkts); 143 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 144 uint16_t nb_pkts); 145 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); 146 static void mrvl_deinit_pp2(void); 147 static void mrvl_deinit_hifs(void); 148 149 static int 150 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 151 uint32_t index, uint32_t vmdq __rte_unused); 152 static int 153 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 154 static int 155 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 156 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev); 157 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev); 158 159 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 160 #name, offsetof(struct pp2_ppio_statistics, name), \ 161 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 162 } 163 164 /* Table with xstats data */ 165 static struct { 166 const char *name; 167 unsigned int offset; 168 unsigned int size; 169 } mrvl_xstats_tbl[] = { 170 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 171 MRVL_XSTATS_TBL_ENTRY(rx_packets), 172 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 173 MRVL_XSTATS_TBL_ENTRY(rx_errors), 174 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 175 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 176 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 177 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 178 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 179 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 180 MRVL_XSTATS_TBL_ENTRY(tx_packets), 181 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 182 MRVL_XSTATS_TBL_ENTRY(tx_errors) 183 }; 184 185 static inline void 186 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) 187 { 188 sq->ent[sq->head].buff.cookie = (uint64_t)buf; 189 sq->ent[sq->head].buff.addr = buf ? 190 rte_mbuf_data_iova_default(buf) : 0; 191 192 sq->ent[sq->head].bpool = 193 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS || 194 buf->refcnt > 1)) ? NULL : 195 mrvl_port_to_bpool_lookup[buf->port]; 196 197 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 198 sq->size++; 199 } 200 201 static inline void 202 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf) 203 { 204 pp2_ppio_outq_desc_reset(desc); 205 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf)); 206 pp2_ppio_outq_desc_set_pkt_offset(desc, 0); 207 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf)); 208 } 209 210 static inline int 211 mrvl_get_bpool_size(int pp2_id, int pool_id) 212 { 213 int i; 214 int size = 0; 215 216 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 217 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 218 219 return size; 220 } 221 222 static inline int 223 mrvl_reserve_bit(int *bitmap, int max) 224 { 225 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 226 227 if (n >= max) 228 return -1; 229 230 *bitmap |= 1 << n; 231 232 return n; 233 } 234 235 static int 236 mrvl_init_hif(int core_id) 237 { 238 struct pp2_hif_params params; 239 char match[MRVL_MATCH_LEN]; 240 int ret; 241 242 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 243 if (ret < 0) { 244 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 245 return ret; 246 } 247 248 snprintf(match, sizeof(match), "hif-%d", ret); 249 memset(¶ms, 0, sizeof(params)); 250 params.match = match; 251 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 252 ret = pp2_hif_init(¶ms, &hifs[core_id]); 253 if (ret) { 254 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 255 return ret; 256 } 257 258 return 0; 259 } 260 261 static inline struct pp2_hif* 262 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 263 { 264 int ret; 265 266 if (likely(hifs[core_id] != NULL)) 267 return hifs[core_id]; 268 269 rte_spinlock_lock(&priv->lock); 270 271 ret = mrvl_init_hif(core_id); 272 if (ret < 0) { 273 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 274 goto out; 275 } 276 277 if (core_id < mrvl_lcore_first) 278 mrvl_lcore_first = core_id; 279 280 if (core_id > mrvl_lcore_last) 281 mrvl_lcore_last = core_id; 282 out: 283 rte_spinlock_unlock(&priv->lock); 284 285 return hifs[core_id]; 286 } 287 288 /** 289 * Set tx burst function according to offload flag 290 * 291 * @param dev 292 * Pointer to Ethernet device structure. 293 */ 294 static void 295 mrvl_set_tx_function(struct rte_eth_dev *dev) 296 { 297 struct mrvl_priv *priv = dev->data->dev_private; 298 299 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 300 if (priv->multiseg) { 301 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n"); 302 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst; 303 } else { 304 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n"); 305 dev->tx_pkt_burst = mrvl_tx_pkt_burst; 306 } 307 } 308 309 /** 310 * Configure rss based on dpdk rss configuration. 311 * 312 * @param priv 313 * Pointer to private structure. 314 * @param rss_conf 315 * Pointer to RSS configuration. 316 * 317 * @return 318 * 0 on success, negative error value otherwise. 319 */ 320 static int 321 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 322 { 323 if (rss_conf->rss_key) 324 MRVL_LOG(WARNING, "Changing hash key is not supported"); 325 326 if (rss_conf->rss_hf == 0) { 327 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 328 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { 329 priv->ppio_params.inqs_params.hash_type = 330 PP2_PPIO_HASH_T_2_TUPLE; 331 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 332 priv->ppio_params.inqs_params.hash_type = 333 PP2_PPIO_HASH_T_5_TUPLE; 334 priv->rss_hf_tcp = 1; 335 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 336 priv->ppio_params.inqs_params.hash_type = 337 PP2_PPIO_HASH_T_5_TUPLE; 338 priv->rss_hf_tcp = 0; 339 } else { 340 return -EINVAL; 341 } 342 343 return 0; 344 } 345 346 /** 347 * Ethernet device configuration. 348 * 349 * Prepare the driver for a given number of TX and RX queues and 350 * configure RSS. 351 * 352 * @param dev 353 * Pointer to Ethernet device structure. 354 * 355 * @return 356 * 0 on success, negative error value otherwise. 357 */ 358 static int 359 mrvl_dev_configure(struct rte_eth_dev *dev) 360 { 361 struct mrvl_priv *priv = dev->data->dev_private; 362 int ret; 363 364 if (priv->ppio) { 365 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 366 return -EINVAL; 367 } 368 369 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && 370 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 371 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 372 dev->data->dev_conf.rxmode.mq_mode); 373 return -EINVAL; 374 } 375 376 if (dev->data->dev_conf.rxmode.split_hdr_size) { 377 MRVL_LOG(INFO, "Split headers not supported"); 378 return -EINVAL; 379 } 380 381 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 382 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 383 MRVL_PP2_ETH_HDRS_LEN; 384 385 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 386 priv->multiseg = 1; 387 388 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 389 dev->data->nb_rx_queues); 390 if (ret < 0) 391 return ret; 392 393 ret = mrvl_configure_txqs(priv, dev->data->port_id, 394 dev->data->nb_tx_queues); 395 if (ret < 0) 396 return ret; 397 398 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 399 priv->ppio_params.maintain_stats = 1; 400 priv->nb_rx_queues = dev->data->nb_rx_queues; 401 402 ret = mrvl_tm_init(dev); 403 if (ret < 0) 404 return ret; 405 406 if (dev->data->nb_rx_queues == 1 && 407 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 408 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 409 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 410 411 return 0; 412 } 413 414 return mrvl_configure_rss(priv, 415 &dev->data->dev_conf.rx_adv_conf.rss_conf); 416 } 417 418 /** 419 * DPDK callback to change the MTU. 420 * 421 * Setting the MTU affects hardware MRU (packets larger than the MRU 422 * will be dropped). 423 * 424 * @param dev 425 * Pointer to Ethernet device structure. 426 * @param mtu 427 * New MTU. 428 * 429 * @return 430 * 0 on success, negative error value otherwise. 431 */ 432 static int 433 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 434 { 435 struct mrvl_priv *priv = dev->data->dev_private; 436 uint16_t mru; 437 uint16_t mbuf_data_size = 0; /* SW buffer size */ 438 int ret; 439 440 mru = MRVL_PP2_MTU_TO_MRU(mtu); 441 /* 442 * min_rx_buf_size is equal to mbuf data size 443 * if pmd didn't set it differently 444 */ 445 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 446 /* Prevent PMD from: 447 * - setting mru greater than the mbuf size resulting in 448 * hw and sw buffer size mismatch 449 * - setting mtu that requires the support of scattered packets 450 * when this feature has not been enabled/supported so far 451 * (TODO check scattered_rx flag here once scattered RX is supported). 452 */ 453 if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) { 454 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS; 455 mtu = MRVL_PP2_MRU_TO_MTU(mru); 456 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted " 457 "by current mbuf size: %u. Set MTU to %u, MRU to %u", 458 mbuf_data_size, mtu, mru); 459 } 460 461 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) { 462 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru); 463 return -EINVAL; 464 } 465 466 dev->data->mtu = mtu; 467 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE; 468 469 if (!priv->ppio) 470 return 0; 471 472 ret = pp2_ppio_set_mru(priv->ppio, mru); 473 if (ret) { 474 MRVL_LOG(ERR, "Failed to change MRU"); 475 return ret; 476 } 477 478 ret = pp2_ppio_set_mtu(priv->ppio, mtu); 479 if (ret) { 480 MRVL_LOG(ERR, "Failed to change MTU"); 481 return ret; 482 } 483 484 return 0; 485 } 486 487 /** 488 * DPDK callback to bring the link up. 489 * 490 * @param dev 491 * Pointer to Ethernet device structure. 492 * 493 * @return 494 * 0 on success, negative error value otherwise. 495 */ 496 static int 497 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 498 { 499 struct mrvl_priv *priv = dev->data->dev_private; 500 int ret; 501 502 if (!priv->ppio) { 503 dev->data->dev_link.link_status = ETH_LINK_UP; 504 return 0; 505 } 506 507 ret = pp2_ppio_enable(priv->ppio); 508 if (ret) 509 return ret; 510 511 /* 512 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 513 * as pp2_ppio_enable() changes port->t_mode from default 0 to 514 * PP2_TRAFFIC_INGRESS_EGRESS. 515 * 516 * Set mtu to default DPDK value here. 517 */ 518 ret = mrvl_mtu_set(dev, dev->data->mtu); 519 if (ret) { 520 pp2_ppio_disable(priv->ppio); 521 return ret; 522 } 523 524 dev->data->dev_link.link_status = ETH_LINK_UP; 525 return 0; 526 } 527 528 /** 529 * DPDK callback to bring the link down. 530 * 531 * @param dev 532 * Pointer to Ethernet device structure. 533 * 534 * @return 535 * 0 on success, negative error value otherwise. 536 */ 537 static int 538 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 539 { 540 struct mrvl_priv *priv = dev->data->dev_private; 541 int ret; 542 543 if (!priv->ppio) { 544 dev->data->dev_link.link_status = ETH_LINK_DOWN; 545 return 0; 546 } 547 ret = pp2_ppio_disable(priv->ppio); 548 if (ret) 549 return ret; 550 551 dev->data->dev_link.link_status = ETH_LINK_DOWN; 552 return 0; 553 } 554 555 /** 556 * DPDK callback to start tx queue. 557 * 558 * @param dev 559 * Pointer to Ethernet device structure. 560 * @param queue_id 561 * Transmit queue index. 562 * 563 * @return 564 * 0 on success, negative error value otherwise. 565 */ 566 static int 567 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 568 { 569 struct mrvl_priv *priv = dev->data->dev_private; 570 int ret; 571 572 if (!priv) 573 return -EPERM; 574 575 /* passing 1 enables given tx queue */ 576 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 577 if (ret) { 578 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 579 return ret; 580 } 581 582 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 583 584 return 0; 585 } 586 587 /** 588 * DPDK callback to stop tx queue. 589 * 590 * @param dev 591 * Pointer to Ethernet device structure. 592 * @param queue_id 593 * Transmit queue index. 594 * 595 * @return 596 * 0 on success, negative error value otherwise. 597 */ 598 static int 599 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 600 { 601 struct mrvl_priv *priv = dev->data->dev_private; 602 int ret; 603 604 if (!priv->ppio) 605 return -EPERM; 606 607 /* passing 0 disables given tx queue */ 608 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 609 if (ret) { 610 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 611 return ret; 612 } 613 614 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 615 616 return 0; 617 } 618 619 /** 620 * DPDK callback to start the device. 621 * 622 * @param dev 623 * Pointer to Ethernet device structure. 624 * 625 * @return 626 * 0 on success, negative errno value on failure. 627 */ 628 static int 629 mrvl_dev_start(struct rte_eth_dev *dev) 630 { 631 struct mrvl_priv *priv = dev->data->dev_private; 632 char match[MRVL_MATCH_LEN]; 633 int ret = 0, i, def_init_size; 634 uint32_t j; 635 struct rte_vlan_filter_conf *vfc; 636 struct rte_ether_addr *mac_addr; 637 638 if (priv->ppio) 639 return mrvl_dev_set_link_up(dev); 640 641 snprintf(match, sizeof(match), "ppio-%d:%d", 642 priv->pp_id, priv->ppio_id); 643 priv->ppio_params.match = match; 644 645 /* 646 * Calculate the minimum bpool size for refill feature as follows: 647 * 2 default burst sizes multiply by number of rx queues. 648 * If the bpool size will be below this value, new buffers will 649 * be added to the pool. 650 */ 651 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 652 653 /* In case initial bpool size configured in queues setup is 654 * smaller than minimum size add more buffers 655 */ 656 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 657 if (priv->bpool_init_size < def_init_size) { 658 int buffs_to_add = def_init_size - priv->bpool_init_size; 659 660 priv->bpool_init_size += buffs_to_add; 661 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 662 if (ret) 663 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 664 } 665 666 /* 667 * Calculate the maximum bpool size for refill feature as follows: 668 * maximum number of descriptors in rx queue multiply by number 669 * of rx queues plus minimum bpool size. 670 * In case the bpool size will exceed this value, superfluous buffers 671 * will be removed 672 */ 673 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 674 priv->bpool_min_size; 675 676 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 677 if (ret) { 678 MRVL_LOG(ERR, "Failed to init ppio"); 679 return ret; 680 } 681 682 /* 683 * In case there are some some stale uc/mc mac addresses flush them 684 * here. It cannot be done during mrvl_dev_close() as port information 685 * is already gone at that point (due to pp2_ppio_deinit() in 686 * mrvl_dev_stop()). 687 */ 688 if (!priv->uc_mc_flushed) { 689 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 690 if (ret) { 691 MRVL_LOG(ERR, 692 "Failed to flush uc/mc filter list"); 693 goto out; 694 } 695 priv->uc_mc_flushed = 1; 696 } 697 698 ret = mrvl_mtu_set(dev, dev->data->mtu); 699 if (ret) 700 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); 701 702 if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0])) 703 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]); 704 705 for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) { 706 mac_addr = &dev->data->mac_addrs[i]; 707 708 /* skip zero address */ 709 if (rte_is_zero_ether_addr(mac_addr)) 710 continue; 711 712 mrvl_mac_addr_add(dev, mac_addr, i, 0); 713 } 714 715 if (dev->data->all_multicast == 1) 716 mrvl_allmulticast_enable(dev); 717 718 vfc = &dev->data->vlan_filter_conf; 719 for (j = 0; j < RTE_DIM(vfc->ids); j++) { 720 uint64_t vlan; 721 uint64_t vbit; 722 uint64_t ids = vfc->ids[j]; 723 724 if (ids == 0) 725 continue; 726 727 while (ids) { 728 vlan = 64 * j; 729 /* count trailing zeroes */ 730 vbit = ~ids & (ids - 1); 731 /* clear least significant bit set */ 732 ids ^= (ids ^ (ids - 1)) ^ vbit; 733 for (; vbit; vlan++) 734 vbit >>= 1; 735 ret = mrvl_vlan_filter_set(dev, vlan, 1); 736 if (ret) { 737 MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); 738 goto out; 739 } 740 } 741 } 742 743 /* For default QoS config, don't start classifier. */ 744 if (mrvl_qos_cfg && 745 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) { 746 ret = mrvl_start_qos_mapping(priv); 747 if (ret) { 748 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 749 goto out; 750 } 751 } 752 753 ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode); 754 if (ret) { 755 MRVL_LOG(ERR, "Failed to set loopback"); 756 goto out; 757 } 758 759 if (dev->data->promiscuous == 1) 760 mrvl_promiscuous_enable(dev); 761 762 if (dev->data->dev_link.link_status == ETH_LINK_UP) { 763 ret = mrvl_dev_set_link_up(dev); 764 if (ret) { 765 MRVL_LOG(ERR, "Failed to set link up"); 766 dev->data->dev_link.link_status = ETH_LINK_DOWN; 767 goto out; 768 } 769 } 770 771 /* start tx queues */ 772 for (i = 0; i < dev->data->nb_tx_queues; i++) { 773 struct mrvl_txq *txq = dev->data->tx_queues[i]; 774 775 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 776 777 if (!txq->tx_deferred_start) 778 continue; 779 780 /* 781 * All txqs are started by default. Stop them 782 * so that tx_deferred_start works as expected. 783 */ 784 ret = mrvl_tx_queue_stop(dev, i); 785 if (ret) 786 goto out; 787 } 788 789 mrvl_flow_init(dev); 790 mrvl_mtr_init(dev); 791 mrvl_set_tx_function(dev); 792 793 return 0; 794 out: 795 MRVL_LOG(ERR, "Failed to start device"); 796 pp2_ppio_deinit(priv->ppio); 797 return ret; 798 } 799 800 /** 801 * Flush receive queues. 802 * 803 * @param dev 804 * Pointer to Ethernet device structure. 805 */ 806 static void 807 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 808 { 809 int i; 810 811 MRVL_LOG(INFO, "Flushing rx queues"); 812 for (i = 0; i < dev->data->nb_rx_queues; i++) { 813 int ret, num; 814 815 do { 816 struct mrvl_rxq *q = dev->data->rx_queues[i]; 817 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 818 819 num = MRVL_PP2_RXD_MAX; 820 ret = pp2_ppio_recv(q->priv->ppio, 821 q->priv->rxq_map[q->queue_id].tc, 822 q->priv->rxq_map[q->queue_id].inq, 823 descs, (uint16_t *)&num); 824 } while (ret == 0 && num); 825 } 826 } 827 828 /** 829 * Flush transmit shadow queues. 830 * 831 * @param dev 832 * Pointer to Ethernet device structure. 833 */ 834 static void 835 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 836 { 837 int i, j; 838 struct mrvl_txq *txq; 839 840 MRVL_LOG(INFO, "Flushing tx shadow queues"); 841 for (i = 0; i < dev->data->nb_tx_queues; i++) { 842 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 843 844 for (j = 0; j < RTE_MAX_LCORE; j++) { 845 struct mrvl_shadow_txq *sq; 846 847 if (!hifs[j]) 848 continue; 849 850 sq = &txq->shadow_txqs[j]; 851 mrvl_free_sent_buffers(txq->priv->ppio, 852 hifs[j], j, sq, txq->queue_id, 1); 853 while (sq->tail != sq->head) { 854 uint64_t addr = cookie_addr_high | 855 sq->ent[sq->tail].buff.cookie; 856 rte_pktmbuf_free( 857 (struct rte_mbuf *)addr); 858 sq->tail = (sq->tail + 1) & 859 MRVL_PP2_TX_SHADOWQ_MASK; 860 } 861 memset(sq, 0, sizeof(*sq)); 862 } 863 } 864 } 865 866 /** 867 * Flush hardware bpool (buffer-pool). 868 * 869 * @param dev 870 * Pointer to Ethernet device structure. 871 */ 872 static void 873 mrvl_flush_bpool(struct rte_eth_dev *dev) 874 { 875 struct mrvl_priv *priv = dev->data->dev_private; 876 struct pp2_hif *hif; 877 uint32_t num; 878 int ret; 879 unsigned int core_id = rte_lcore_id(); 880 881 if (core_id == LCORE_ID_ANY) 882 core_id = rte_get_main_lcore(); 883 884 hif = mrvl_get_hif(priv, core_id); 885 886 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 887 if (ret) { 888 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 889 return; 890 } 891 892 while (num--) { 893 struct pp2_buff_inf inf; 894 uint64_t addr; 895 896 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 897 if (ret) 898 break; 899 900 addr = cookie_addr_high | inf.cookie; 901 rte_pktmbuf_free((struct rte_mbuf *)addr); 902 } 903 } 904 905 /** 906 * DPDK callback to stop the device. 907 * 908 * @param dev 909 * Pointer to Ethernet device structure. 910 */ 911 static int 912 mrvl_dev_stop(struct rte_eth_dev *dev) 913 { 914 return mrvl_dev_set_link_down(dev); 915 } 916 917 /** 918 * DPDK callback to close the device. 919 * 920 * @param dev 921 * Pointer to Ethernet device structure. 922 */ 923 static int 924 mrvl_dev_close(struct rte_eth_dev *dev) 925 { 926 struct mrvl_priv *priv = dev->data->dev_private; 927 size_t i; 928 929 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 930 return 0; 931 932 mrvl_flush_rx_queues(dev); 933 mrvl_flush_tx_shadow_queues(dev); 934 mrvl_flow_deinit(dev); 935 mrvl_mtr_deinit(dev); 936 937 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 938 struct pp2_ppio_tc_params *tc_params = 939 &priv->ppio_params.inqs_params.tcs_params[i]; 940 941 if (tc_params->inqs_params) { 942 rte_free(tc_params->inqs_params); 943 tc_params->inqs_params = NULL; 944 } 945 } 946 947 if (priv->cls_tbl) { 948 pp2_cls_tbl_deinit(priv->cls_tbl); 949 priv->cls_tbl = NULL; 950 } 951 952 if (priv->qos_tbl) { 953 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 954 priv->qos_tbl = NULL; 955 } 956 957 mrvl_flush_bpool(dev); 958 mrvl_tm_deinit(dev); 959 960 if (priv->ppio) { 961 pp2_ppio_deinit(priv->ppio); 962 priv->ppio = NULL; 963 } 964 965 /* policer must be released after ppio deinitialization */ 966 if (priv->default_policer) { 967 pp2_cls_plcr_deinit(priv->default_policer); 968 priv->default_policer = NULL; 969 } 970 971 972 if (priv->bpool) { 973 pp2_bpool_deinit(priv->bpool); 974 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 975 priv->bpool = NULL; 976 } 977 978 mrvl_dev_num--; 979 980 if (mrvl_dev_num == 0) { 981 MRVL_LOG(INFO, "Perform MUSDK deinit"); 982 mrvl_deinit_hifs(); 983 mrvl_deinit_pp2(); 984 rte_mvep_deinit(MVEP_MOD_T_PP2); 985 } 986 987 return 0; 988 } 989 990 /** 991 * DPDK callback to retrieve physical link information. 992 * 993 * @param dev 994 * Pointer to Ethernet device structure. 995 * @param wait_to_complete 996 * Wait for request completion (ignored). 997 * 998 * @return 999 * 0 on success, negative error value otherwise. 1000 */ 1001 static int 1002 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 1003 { 1004 /* 1005 * TODO 1006 * once MUSDK provides necessary API use it here 1007 */ 1008 struct mrvl_priv *priv = dev->data->dev_private; 1009 struct ethtool_cmd edata; 1010 struct ifreq req; 1011 int ret, fd, link_up; 1012 1013 if (!priv->ppio) 1014 return -EPERM; 1015 1016 edata.cmd = ETHTOOL_GSET; 1017 1018 strcpy(req.ifr_name, dev->data->name); 1019 req.ifr_data = (void *)&edata; 1020 1021 fd = socket(AF_INET, SOCK_DGRAM, 0); 1022 if (fd == -1) 1023 return -EFAULT; 1024 1025 ret = ioctl(fd, SIOCETHTOOL, &req); 1026 if (ret == -1) { 1027 close(fd); 1028 return -EFAULT; 1029 } 1030 1031 close(fd); 1032 1033 switch (ethtool_cmd_speed(&edata)) { 1034 case SPEED_10: 1035 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M; 1036 break; 1037 case SPEED_100: 1038 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M; 1039 break; 1040 case SPEED_1000: 1041 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; 1042 break; 1043 case SPEED_10000: 1044 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; 1045 break; 1046 default: 1047 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; 1048 } 1049 1050 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : 1051 ETH_LINK_HALF_DUPLEX; 1052 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : 1053 ETH_LINK_FIXED; 1054 pp2_ppio_get_link_state(priv->ppio, &link_up); 1055 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 1056 1057 return 0; 1058 } 1059 1060 /** 1061 * DPDK callback to enable promiscuous mode. 1062 * 1063 * @param dev 1064 * Pointer to Ethernet device structure. 1065 * 1066 * @return 1067 * 0 on success, negative error value otherwise. 1068 */ 1069 static int 1070 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 1071 { 1072 struct mrvl_priv *priv = dev->data->dev_private; 1073 int ret; 1074 1075 if (priv->isolated) 1076 return -ENOTSUP; 1077 1078 if (!priv->ppio) 1079 return 0; 1080 1081 ret = pp2_ppio_set_promisc(priv->ppio, 1); 1082 if (ret) { 1083 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 1084 return -EAGAIN; 1085 } 1086 1087 return 0; 1088 } 1089 1090 /** 1091 * DPDK callback to enable allmulti mode. 1092 * 1093 * @param dev 1094 * Pointer to Ethernet device structure. 1095 * 1096 * @return 1097 * 0 on success, negative error value otherwise. 1098 */ 1099 static int 1100 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 1101 { 1102 struct mrvl_priv *priv = dev->data->dev_private; 1103 int ret; 1104 1105 if (priv->isolated) 1106 return -ENOTSUP; 1107 1108 if (!priv->ppio) 1109 return 0; 1110 1111 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 1112 if (ret) { 1113 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 1114 return -EAGAIN; 1115 } 1116 1117 return 0; 1118 } 1119 1120 /** 1121 * DPDK callback to disable promiscuous mode. 1122 * 1123 * @param dev 1124 * Pointer to Ethernet device structure. 1125 * 1126 * @return 1127 * 0 on success, negative error value otherwise. 1128 */ 1129 static int 1130 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 1131 { 1132 struct mrvl_priv *priv = dev->data->dev_private; 1133 int ret; 1134 1135 if (priv->isolated) 1136 return -ENOTSUP; 1137 1138 if (!priv->ppio) 1139 return 0; 1140 1141 ret = pp2_ppio_set_promisc(priv->ppio, 0); 1142 if (ret) { 1143 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 1144 return -EAGAIN; 1145 } 1146 1147 return 0; 1148 } 1149 1150 /** 1151 * DPDK callback to disable allmulticast mode. 1152 * 1153 * @param dev 1154 * Pointer to Ethernet device structure. 1155 * 1156 * @return 1157 * 0 on success, negative error value otherwise. 1158 */ 1159 static int 1160 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 1161 { 1162 struct mrvl_priv *priv = dev->data->dev_private; 1163 int ret; 1164 1165 if (priv->isolated) 1166 return -ENOTSUP; 1167 1168 if (!priv->ppio) 1169 return 0; 1170 1171 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 1172 if (ret) { 1173 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 1174 return -EAGAIN; 1175 } 1176 1177 return 0; 1178 } 1179 1180 /** 1181 * DPDK callback to remove a MAC address. 1182 * 1183 * @param dev 1184 * Pointer to Ethernet device structure. 1185 * @param index 1186 * MAC address index. 1187 */ 1188 static void 1189 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 1190 { 1191 struct mrvl_priv *priv = dev->data->dev_private; 1192 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1193 int ret; 1194 1195 if (priv->isolated) 1196 return; 1197 1198 if (!priv->ppio) 1199 return; 1200 1201 ret = pp2_ppio_remove_mac_addr(priv->ppio, 1202 dev->data->mac_addrs[index].addr_bytes); 1203 if (ret) { 1204 rte_ether_format_addr(buf, sizeof(buf), 1205 &dev->data->mac_addrs[index]); 1206 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 1207 } 1208 } 1209 1210 /** 1211 * DPDK callback to add a MAC address. 1212 * 1213 * @param dev 1214 * Pointer to Ethernet device structure. 1215 * @param mac_addr 1216 * MAC address to register. 1217 * @param index 1218 * MAC address index. 1219 * @param vmdq 1220 * VMDq pool index to associate address with (unused). 1221 * 1222 * @return 1223 * 0 on success, negative error value otherwise. 1224 */ 1225 static int 1226 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1227 uint32_t index, uint32_t vmdq __rte_unused) 1228 { 1229 struct mrvl_priv *priv = dev->data->dev_private; 1230 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1231 int ret; 1232 1233 if (priv->isolated) 1234 return -ENOTSUP; 1235 1236 if (!priv->ppio) 1237 return 0; 1238 1239 if (index == 0) 1240 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1241 return -1; 1242 1243 /* 1244 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1245 * parameter uc_filter_max. Maximum number of mc addresses is then 1246 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1247 * 21 respectively. 1248 * 1249 * If more than uc_filter_max uc addresses were added to filter list 1250 * then NIC will switch to promiscuous mode automatically. 1251 * 1252 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1253 * were added to filter list then NIC will switch to all-multicast mode 1254 * automatically. 1255 */ 1256 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1257 if (ret) { 1258 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1259 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1260 return -1; 1261 } 1262 1263 return 0; 1264 } 1265 1266 /** 1267 * DPDK callback to set the primary MAC address. 1268 * 1269 * @param dev 1270 * Pointer to Ethernet device structure. 1271 * @param mac_addr 1272 * MAC address to register. 1273 * 1274 * @return 1275 * 0 on success, negative error value otherwise. 1276 */ 1277 static int 1278 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1279 { 1280 struct mrvl_priv *priv = dev->data->dev_private; 1281 int ret; 1282 1283 if (priv->isolated) 1284 return -ENOTSUP; 1285 1286 if (!priv->ppio) 1287 return 0; 1288 1289 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1290 if (ret) { 1291 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1292 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1293 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1294 } 1295 1296 return ret; 1297 } 1298 1299 /** 1300 * DPDK callback to get device statistics. 1301 * 1302 * @param dev 1303 * Pointer to Ethernet device structure. 1304 * @param stats 1305 * Stats structure output buffer. 1306 * 1307 * @return 1308 * 0 on success, negative error value otherwise. 1309 */ 1310 static int 1311 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1312 { 1313 struct mrvl_priv *priv = dev->data->dev_private; 1314 struct pp2_ppio_statistics ppio_stats; 1315 uint64_t drop_mac = 0; 1316 unsigned int i, idx, ret; 1317 1318 if (!priv->ppio) 1319 return -EPERM; 1320 1321 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1322 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1323 struct pp2_ppio_inq_statistics rx_stats; 1324 1325 if (!rxq) 1326 continue; 1327 1328 idx = rxq->queue_id; 1329 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1330 MRVL_LOG(ERR, 1331 "rx queue %d stats out of range (0 - %d)", 1332 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1333 continue; 1334 } 1335 1336 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1337 priv->rxq_map[idx].tc, 1338 priv->rxq_map[idx].inq, 1339 &rx_stats, 0); 1340 if (unlikely(ret)) { 1341 MRVL_LOG(ERR, 1342 "Failed to update rx queue %d stats", idx); 1343 break; 1344 } 1345 1346 stats->q_ibytes[idx] = rxq->bytes_recv; 1347 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1348 stats->q_errors[idx] = rx_stats.drop_early + 1349 rx_stats.drop_fullq + 1350 rx_stats.drop_bm + 1351 rxq->drop_mac; 1352 stats->ibytes += rxq->bytes_recv; 1353 drop_mac += rxq->drop_mac; 1354 } 1355 1356 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1357 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1358 struct pp2_ppio_outq_statistics tx_stats; 1359 1360 if (!txq) 1361 continue; 1362 1363 idx = txq->queue_id; 1364 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1365 MRVL_LOG(ERR, 1366 "tx queue %d stats out of range (0 - %d)", 1367 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1368 } 1369 1370 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1371 &tx_stats, 0); 1372 if (unlikely(ret)) { 1373 MRVL_LOG(ERR, 1374 "Failed to update tx queue %d stats", idx); 1375 break; 1376 } 1377 1378 stats->q_opackets[idx] = tx_stats.deq_desc; 1379 stats->q_obytes[idx] = txq->bytes_sent; 1380 stats->obytes += txq->bytes_sent; 1381 } 1382 1383 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1384 if (unlikely(ret)) { 1385 MRVL_LOG(ERR, "Failed to update port statistics"); 1386 return ret; 1387 } 1388 1389 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1390 stats->opackets += ppio_stats.tx_packets; 1391 stats->imissed += ppio_stats.rx_fullq_dropped + 1392 ppio_stats.rx_bm_dropped + 1393 ppio_stats.rx_early_dropped + 1394 ppio_stats.rx_fifo_dropped + 1395 ppio_stats.rx_cls_dropped; 1396 stats->ierrors = drop_mac; 1397 1398 return 0; 1399 } 1400 1401 /** 1402 * DPDK callback to clear device statistics. 1403 * 1404 * @param dev 1405 * Pointer to Ethernet device structure. 1406 * 1407 * @return 1408 * 0 on success, negative error value otherwise. 1409 */ 1410 static int 1411 mrvl_stats_reset(struct rte_eth_dev *dev) 1412 { 1413 struct mrvl_priv *priv = dev->data->dev_private; 1414 int i; 1415 1416 if (!priv->ppio) 1417 return 0; 1418 1419 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1420 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1421 1422 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1423 priv->rxq_map[i].inq, NULL, 1); 1424 rxq->bytes_recv = 0; 1425 rxq->drop_mac = 0; 1426 } 1427 1428 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1429 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1430 1431 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1432 txq->bytes_sent = 0; 1433 } 1434 1435 return pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1436 } 1437 1438 /** 1439 * DPDK callback to get extended statistics. 1440 * 1441 * @param dev 1442 * Pointer to Ethernet device structure. 1443 * @param stats 1444 * Pointer to xstats table. 1445 * @param n 1446 * Number of entries in xstats table. 1447 * @return 1448 * Negative value on error, number of read xstats otherwise. 1449 */ 1450 static int 1451 mrvl_xstats_get(struct rte_eth_dev *dev, 1452 struct rte_eth_xstat *stats, unsigned int n) 1453 { 1454 struct mrvl_priv *priv = dev->data->dev_private; 1455 struct pp2_ppio_statistics ppio_stats; 1456 unsigned int i; 1457 1458 if (!stats) 1459 return 0; 1460 1461 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1462 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) { 1463 uint64_t val; 1464 1465 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1466 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1467 mrvl_xstats_tbl[i].offset); 1468 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1469 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1470 mrvl_xstats_tbl[i].offset); 1471 else 1472 return -EINVAL; 1473 1474 stats[i].id = i; 1475 stats[i].value = val; 1476 } 1477 1478 return n; 1479 } 1480 1481 /** 1482 * DPDK callback to reset extended statistics. 1483 * 1484 * @param dev 1485 * Pointer to Ethernet device structure. 1486 * 1487 * @return 1488 * 0 on success, negative error value otherwise. 1489 */ 1490 static int 1491 mrvl_xstats_reset(struct rte_eth_dev *dev) 1492 { 1493 return mrvl_stats_reset(dev); 1494 } 1495 1496 /** 1497 * DPDK callback to get extended statistics names. 1498 * 1499 * @param dev (unused) 1500 * Pointer to Ethernet device structure. 1501 * @param xstats_names 1502 * Pointer to xstats names table. 1503 * @param size 1504 * Size of the xstats names table. 1505 * @return 1506 * Number of read names. 1507 */ 1508 static int 1509 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1510 struct rte_eth_xstat_name *xstats_names, 1511 unsigned int size) 1512 { 1513 unsigned int i; 1514 1515 if (!xstats_names) 1516 return RTE_DIM(mrvl_xstats_tbl); 1517 1518 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1519 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name, 1520 RTE_ETH_XSTATS_NAME_SIZE); 1521 1522 return size; 1523 } 1524 1525 /** 1526 * DPDK callback to get information about the device. 1527 * 1528 * @param dev 1529 * Pointer to Ethernet device structure (unused). 1530 * @param info 1531 * Info structure output buffer. 1532 */ 1533 static int 1534 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 1535 struct rte_eth_dev_info *info) 1536 { 1537 info->speed_capa = ETH_LINK_SPEED_10M | 1538 ETH_LINK_SPEED_100M | 1539 ETH_LINK_SPEED_1G | 1540 ETH_LINK_SPEED_10G; 1541 1542 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1543 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1544 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1545 1546 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1547 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1548 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1549 1550 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1551 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1552 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1553 1554 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1555 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1556 1557 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1558 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1559 1560 info->flow_type_rss_offloads = ETH_RSS_IPV4 | 1561 ETH_RSS_NONFRAG_IPV4_TCP | 1562 ETH_RSS_NONFRAG_IPV4_UDP; 1563 1564 /* By default packets are dropped if no descriptors are available */ 1565 info->default_rxconf.rx_drop_en = 1; 1566 1567 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1568 1569 return 0; 1570 } 1571 1572 /** 1573 * Return supported packet types. 1574 * 1575 * @param dev 1576 * Pointer to Ethernet device structure (unused). 1577 * 1578 * @return 1579 * Const pointer to the table with supported packet types. 1580 */ 1581 static const uint32_t * 1582 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1583 { 1584 static const uint32_t ptypes[] = { 1585 RTE_PTYPE_L2_ETHER, 1586 RTE_PTYPE_L2_ETHER_VLAN, 1587 RTE_PTYPE_L2_ETHER_QINQ, 1588 RTE_PTYPE_L3_IPV4, 1589 RTE_PTYPE_L3_IPV4_EXT, 1590 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1591 RTE_PTYPE_L3_IPV6, 1592 RTE_PTYPE_L3_IPV6_EXT, 1593 RTE_PTYPE_L2_ETHER_ARP, 1594 RTE_PTYPE_L4_TCP, 1595 RTE_PTYPE_L4_UDP 1596 }; 1597 1598 return ptypes; 1599 } 1600 1601 /** 1602 * DPDK callback to get information about specific receive queue. 1603 * 1604 * @param dev 1605 * Pointer to Ethernet device structure. 1606 * @param rx_queue_id 1607 * Receive queue index. 1608 * @param qinfo 1609 * Receive queue information structure. 1610 */ 1611 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1612 struct rte_eth_rxq_info *qinfo) 1613 { 1614 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1615 struct mrvl_priv *priv = dev->data->dev_private; 1616 int inq = priv->rxq_map[rx_queue_id].inq; 1617 int tc = priv->rxq_map[rx_queue_id].tc; 1618 struct pp2_ppio_tc_params *tc_params = 1619 &priv->ppio_params.inqs_params.tcs_params[tc]; 1620 1621 qinfo->mp = q->mp; 1622 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1623 } 1624 1625 /** 1626 * DPDK callback to get information about specific transmit queue. 1627 * 1628 * @param dev 1629 * Pointer to Ethernet device structure. 1630 * @param tx_queue_id 1631 * Transmit queue index. 1632 * @param qinfo 1633 * Transmit queue information structure. 1634 */ 1635 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1636 struct rte_eth_txq_info *qinfo) 1637 { 1638 struct mrvl_priv *priv = dev->data->dev_private; 1639 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1640 1641 qinfo->nb_desc = 1642 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1643 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1644 } 1645 1646 /** 1647 * DPDK callback to Configure a VLAN filter. 1648 * 1649 * @param dev 1650 * Pointer to Ethernet device structure. 1651 * @param vlan_id 1652 * VLAN ID to filter. 1653 * @param on 1654 * Toggle filter. 1655 * 1656 * @return 1657 * 0 on success, negative error value otherwise. 1658 */ 1659 static int 1660 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1661 { 1662 struct mrvl_priv *priv = dev->data->dev_private; 1663 1664 if (priv->isolated) 1665 return -ENOTSUP; 1666 1667 if (!priv->ppio) 1668 return 0; 1669 1670 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1671 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1672 } 1673 1674 /** 1675 * Release buffers to hardware bpool (buffer-pool) 1676 * 1677 * @param rxq 1678 * Receive queue pointer. 1679 * @param num 1680 * Number of buffers to release to bpool. 1681 * 1682 * @return 1683 * 0 on success, negative error value otherwise. 1684 */ 1685 static int 1686 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1687 { 1688 struct buff_release_entry entries[num]; 1689 struct rte_mbuf *mbufs[num]; 1690 int i, ret; 1691 unsigned int core_id; 1692 struct pp2_hif *hif; 1693 struct pp2_bpool *bpool; 1694 1695 core_id = rte_lcore_id(); 1696 if (core_id == LCORE_ID_ANY) 1697 core_id = rte_get_main_lcore(); 1698 1699 hif = mrvl_get_hif(rxq->priv, core_id); 1700 if (!hif) 1701 return -1; 1702 1703 bpool = rxq->priv->bpool; 1704 1705 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1706 if (ret) 1707 return ret; 1708 1709 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1710 cookie_addr_high = 1711 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1712 1713 for (i = 0; i < num; i++) { 1714 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1715 != cookie_addr_high) { 1716 MRVL_LOG(ERR, 1717 "mbuf virtual addr high is out of range " 1718 "0x%x instead of 0x%x\n", 1719 (uint32_t)((uint64_t)mbufs[i] >> 32), 1720 (uint32_t)(cookie_addr_high >> 32)); 1721 goto out; 1722 } 1723 1724 entries[i].buff.addr = 1725 rte_mbuf_data_iova_default(mbufs[i]); 1726 entries[i].buff.cookie = (uintptr_t)mbufs[i]; 1727 entries[i].bpool = bpool; 1728 } 1729 1730 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1731 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1732 1733 if (i != num) 1734 goto out; 1735 1736 return 0; 1737 out: 1738 for (; i < num; i++) 1739 rte_pktmbuf_free(mbufs[i]); 1740 1741 return -1; 1742 } 1743 1744 /** 1745 * DPDK callback to configure the receive queue. 1746 * 1747 * @param dev 1748 * Pointer to Ethernet device structure. 1749 * @param idx 1750 * RX queue index. 1751 * @param desc 1752 * Number of descriptors to configure in queue. 1753 * @param socket 1754 * NUMA socket on which memory must be allocated. 1755 * @param conf 1756 * Thresholds parameters. 1757 * @param mp 1758 * Memory pool for buffer allocations. 1759 * 1760 * @return 1761 * 0 on success, negative error value otherwise. 1762 */ 1763 static int 1764 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1765 unsigned int socket, 1766 const struct rte_eth_rxconf *conf, 1767 struct rte_mempool *mp) 1768 { 1769 struct mrvl_priv *priv = dev->data->dev_private; 1770 struct mrvl_rxq *rxq; 1771 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp); 1772 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1773 int ret, tc, inq; 1774 uint64_t offloads; 1775 1776 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1777 1778 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1779 /* 1780 * Unknown TC mapping, mapping will not have a correct queue. 1781 */ 1782 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1783 idx, priv->ppio_id); 1784 return -EFAULT; 1785 } 1786 1787 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - 1788 MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN; 1789 if (frame_size < max_rx_pkt_len) { 1790 MRVL_LOG(WARNING, 1791 "Mbuf size must be increased to %u bytes to hold up " 1792 "to %u bytes of data.", 1793 buf_size + max_rx_pkt_len - frame_size, 1794 max_rx_pkt_len); 1795 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1796 MRVL_LOG(INFO, "Setting max rx pkt len to %u", 1797 dev->data->dev_conf.rxmode.max_rx_pkt_len); 1798 } 1799 1800 if (dev->data->rx_queues[idx]) { 1801 rte_free(dev->data->rx_queues[idx]); 1802 dev->data->rx_queues[idx] = NULL; 1803 } 1804 1805 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 1806 if (!rxq) 1807 return -ENOMEM; 1808 1809 rxq->priv = priv; 1810 rxq->mp = mp; 1811 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; 1812 rxq->queue_id = idx; 1813 rxq->port_id = dev->data->port_id; 1814 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 1815 1816 tc = priv->rxq_map[rxq->queue_id].tc, 1817 inq = priv->rxq_map[rxq->queue_id].inq; 1818 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 1819 desc; 1820 1821 ret = mrvl_fill_bpool(rxq, desc); 1822 if (ret) { 1823 rte_free(rxq); 1824 return ret; 1825 } 1826 1827 priv->bpool_init_size += desc; 1828 1829 dev->data->rx_queues[idx] = rxq; 1830 1831 return 0; 1832 } 1833 1834 /** 1835 * DPDK callback to release the receive queue. 1836 * 1837 * @param rxq 1838 * Generic receive queue pointer. 1839 */ 1840 static void 1841 mrvl_rx_queue_release(void *rxq) 1842 { 1843 struct mrvl_rxq *q = rxq; 1844 struct pp2_ppio_tc_params *tc_params; 1845 int i, num, tc, inq; 1846 struct pp2_hif *hif; 1847 unsigned int core_id = rte_lcore_id(); 1848 1849 if (core_id == LCORE_ID_ANY) 1850 core_id = rte_get_main_lcore(); 1851 1852 if (!q) 1853 return; 1854 1855 hif = mrvl_get_hif(q->priv, core_id); 1856 1857 if (!hif) 1858 return; 1859 1860 tc = q->priv->rxq_map[q->queue_id].tc; 1861 inq = q->priv->rxq_map[q->queue_id].inq; 1862 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 1863 num = tc_params->inqs_params[inq].size; 1864 for (i = 0; i < num; i++) { 1865 struct pp2_buff_inf inf; 1866 uint64_t addr; 1867 1868 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 1869 addr = cookie_addr_high | inf.cookie; 1870 rte_pktmbuf_free((struct rte_mbuf *)addr); 1871 } 1872 1873 rte_free(q); 1874 } 1875 1876 /** 1877 * DPDK callback to configure the transmit queue. 1878 * 1879 * @param dev 1880 * Pointer to Ethernet device structure. 1881 * @param idx 1882 * Transmit queue index. 1883 * @param desc 1884 * Number of descriptors to configure in the queue. 1885 * @param socket 1886 * NUMA socket on which memory must be allocated. 1887 * @param conf 1888 * Tx queue configuration parameters. 1889 * 1890 * @return 1891 * 0 on success, negative error value otherwise. 1892 */ 1893 static int 1894 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1895 unsigned int socket, 1896 const struct rte_eth_txconf *conf) 1897 { 1898 struct mrvl_priv *priv = dev->data->dev_private; 1899 struct mrvl_txq *txq; 1900 1901 if (dev->data->tx_queues[idx]) { 1902 rte_free(dev->data->tx_queues[idx]); 1903 dev->data->tx_queues[idx] = NULL; 1904 } 1905 1906 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 1907 if (!txq) 1908 return -ENOMEM; 1909 1910 txq->priv = priv; 1911 txq->queue_id = idx; 1912 txq->port_id = dev->data->port_id; 1913 txq->tx_deferred_start = conf->tx_deferred_start; 1914 dev->data->tx_queues[idx] = txq; 1915 1916 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 1917 1918 return 0; 1919 } 1920 1921 /** 1922 * DPDK callback to release the transmit queue. 1923 * 1924 * @param txq 1925 * Generic transmit queue pointer. 1926 */ 1927 static void 1928 mrvl_tx_queue_release(void *txq) 1929 { 1930 struct mrvl_txq *q = txq; 1931 1932 if (!q) 1933 return; 1934 1935 rte_free(q); 1936 } 1937 1938 /** 1939 * DPDK callback to get flow control configuration. 1940 * 1941 * @param dev 1942 * Pointer to Ethernet device structure. 1943 * @param fc_conf 1944 * Pointer to the flow control configuration. 1945 * 1946 * @return 1947 * 0 on success, negative error value otherwise. 1948 */ 1949 static int 1950 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1951 { 1952 struct mrvl_priv *priv = dev->data->dev_private; 1953 int ret, en; 1954 1955 if (!priv) 1956 return -EPERM; 1957 1958 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 1959 if (ret) { 1960 MRVL_LOG(ERR, "Failed to read rx pause state"); 1961 return ret; 1962 } 1963 1964 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; 1965 1966 return 0; 1967 } 1968 1969 /** 1970 * DPDK callback to set flow control configuration. 1971 * 1972 * @param dev 1973 * Pointer to Ethernet device structure. 1974 * @param fc_conf 1975 * Pointer to the flow control configuration. 1976 * 1977 * @return 1978 * 0 on success, negative error value otherwise. 1979 */ 1980 static int 1981 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1982 { 1983 struct mrvl_priv *priv = dev->data->dev_private; 1984 1985 if (!priv) 1986 return -EPERM; 1987 1988 if (fc_conf->high_water || 1989 fc_conf->low_water || 1990 fc_conf->pause_time || 1991 fc_conf->mac_ctrl_frame_fwd || 1992 fc_conf->autoneg) { 1993 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 1994 1995 return -EINVAL; 1996 } 1997 1998 if (fc_conf->mode == RTE_FC_NONE || 1999 fc_conf->mode == RTE_FC_RX_PAUSE) { 2000 int ret, en; 2001 2002 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; 2003 ret = pp2_ppio_set_rx_pause(priv->ppio, en); 2004 if (ret) 2005 MRVL_LOG(ERR, 2006 "Failed to change flowctrl on RX side"); 2007 2008 return ret; 2009 } 2010 2011 return 0; 2012 } 2013 2014 /** 2015 * Update RSS hash configuration 2016 * 2017 * @param dev 2018 * Pointer to Ethernet device structure. 2019 * @param rss_conf 2020 * Pointer to RSS configuration. 2021 * 2022 * @return 2023 * 0 on success, negative error value otherwise. 2024 */ 2025 static int 2026 mrvl_rss_hash_update(struct rte_eth_dev *dev, 2027 struct rte_eth_rss_conf *rss_conf) 2028 { 2029 struct mrvl_priv *priv = dev->data->dev_private; 2030 2031 if (priv->isolated) 2032 return -ENOTSUP; 2033 2034 return mrvl_configure_rss(priv, rss_conf); 2035 } 2036 2037 /** 2038 * DPDK callback to get RSS hash configuration. 2039 * 2040 * @param dev 2041 * Pointer to Ethernet device structure. 2042 * @rss_conf 2043 * Pointer to RSS configuration. 2044 * 2045 * @return 2046 * Always 0. 2047 */ 2048 static int 2049 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 2050 struct rte_eth_rss_conf *rss_conf) 2051 { 2052 struct mrvl_priv *priv = dev->data->dev_private; 2053 enum pp2_ppio_hash_type hash_type = 2054 priv->ppio_params.inqs_params.hash_type; 2055 2056 rss_conf->rss_key = NULL; 2057 2058 if (hash_type == PP2_PPIO_HASH_T_NONE) 2059 rss_conf->rss_hf = 0; 2060 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 2061 rss_conf->rss_hf = ETH_RSS_IPV4; 2062 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 2063 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; 2064 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 2065 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; 2066 2067 return 0; 2068 } 2069 2070 /** 2071 * DPDK callback to get rte_flow callbacks. 2072 * 2073 * @param dev 2074 * Pointer to the device structure. 2075 * @param filer_type 2076 * Flow filter type. 2077 * @param filter_op 2078 * Flow filter operation. 2079 * @param arg 2080 * Pointer to pass the flow ops. 2081 * 2082 * @return 2083 * 0 on success, negative error value otherwise. 2084 */ 2085 static int 2086 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 2087 enum rte_filter_type filter_type, 2088 enum rte_filter_op filter_op, void *arg) 2089 { 2090 switch (filter_type) { 2091 case RTE_ETH_FILTER_GENERIC: 2092 if (filter_op != RTE_ETH_FILTER_GET) 2093 return -EINVAL; 2094 *(const void **)arg = &mrvl_flow_ops; 2095 return 0; 2096 default: 2097 MRVL_LOG(WARNING, "Filter type (%d) not supported", 2098 filter_type); 2099 return -EINVAL; 2100 } 2101 } 2102 2103 /** 2104 * DPDK callback to get rte_mtr callbacks. 2105 * 2106 * @param dev 2107 * Pointer to the device structure. 2108 * @param ops 2109 * Pointer to pass the mtr ops. 2110 * 2111 * @return 2112 * Always 0. 2113 */ 2114 static int 2115 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2116 { 2117 *(const void **)ops = &mrvl_mtr_ops; 2118 2119 return 0; 2120 } 2121 2122 /** 2123 * DPDK callback to get rte_tm callbacks. 2124 * 2125 * @param dev 2126 * Pointer to the device structure. 2127 * @param ops 2128 * Pointer to pass the tm ops. 2129 * 2130 * @return 2131 * Always 0. 2132 */ 2133 static int 2134 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2135 { 2136 *(const void **)ops = &mrvl_tm_ops; 2137 2138 return 0; 2139 } 2140 2141 static const struct eth_dev_ops mrvl_ops = { 2142 .dev_configure = mrvl_dev_configure, 2143 .dev_start = mrvl_dev_start, 2144 .dev_stop = mrvl_dev_stop, 2145 .dev_set_link_up = mrvl_dev_set_link_up, 2146 .dev_set_link_down = mrvl_dev_set_link_down, 2147 .dev_close = mrvl_dev_close, 2148 .link_update = mrvl_link_update, 2149 .promiscuous_enable = mrvl_promiscuous_enable, 2150 .allmulticast_enable = mrvl_allmulticast_enable, 2151 .promiscuous_disable = mrvl_promiscuous_disable, 2152 .allmulticast_disable = mrvl_allmulticast_disable, 2153 .mac_addr_remove = mrvl_mac_addr_remove, 2154 .mac_addr_add = mrvl_mac_addr_add, 2155 .mac_addr_set = mrvl_mac_addr_set, 2156 .mtu_set = mrvl_mtu_set, 2157 .stats_get = mrvl_stats_get, 2158 .stats_reset = mrvl_stats_reset, 2159 .xstats_get = mrvl_xstats_get, 2160 .xstats_reset = mrvl_xstats_reset, 2161 .xstats_get_names = mrvl_xstats_get_names, 2162 .dev_infos_get = mrvl_dev_infos_get, 2163 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 2164 .rxq_info_get = mrvl_rxq_info_get, 2165 .txq_info_get = mrvl_txq_info_get, 2166 .vlan_filter_set = mrvl_vlan_filter_set, 2167 .tx_queue_start = mrvl_tx_queue_start, 2168 .tx_queue_stop = mrvl_tx_queue_stop, 2169 .rx_queue_setup = mrvl_rx_queue_setup, 2170 .rx_queue_release = mrvl_rx_queue_release, 2171 .tx_queue_setup = mrvl_tx_queue_setup, 2172 .tx_queue_release = mrvl_tx_queue_release, 2173 .flow_ctrl_get = mrvl_flow_ctrl_get, 2174 .flow_ctrl_set = mrvl_flow_ctrl_set, 2175 .rss_hash_update = mrvl_rss_hash_update, 2176 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 2177 .filter_ctrl = mrvl_eth_filter_ctrl, 2178 .mtr_ops_get = mrvl_mtr_ops_get, 2179 .tm_ops_get = mrvl_tm_ops_get, 2180 }; 2181 2182 /** 2183 * Return packet type information and l3/l4 offsets. 2184 * 2185 * @param desc 2186 * Pointer to the received packet descriptor. 2187 * @param l3_offset 2188 * l3 packet offset. 2189 * @param l4_offset 2190 * l4 packet offset. 2191 * 2192 * @return 2193 * Packet type information. 2194 */ 2195 static inline uint64_t 2196 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 2197 uint8_t *l3_offset, uint8_t *l4_offset) 2198 { 2199 enum pp2_inq_l3_type l3_type; 2200 enum pp2_inq_l4_type l4_type; 2201 enum pp2_inq_vlan_tag vlan_tag; 2202 uint64_t packet_type; 2203 2204 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 2205 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 2206 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 2207 2208 packet_type = RTE_PTYPE_L2_ETHER; 2209 2210 switch (vlan_tag) { 2211 case PP2_INQ_VLAN_TAG_SINGLE: 2212 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 2213 break; 2214 case PP2_INQ_VLAN_TAG_DOUBLE: 2215 case PP2_INQ_VLAN_TAG_TRIPLE: 2216 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 2217 break; 2218 default: 2219 break; 2220 } 2221 2222 switch (l3_type) { 2223 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 2224 packet_type |= RTE_PTYPE_L3_IPV4; 2225 break; 2226 case PP2_INQ_L3_TYPE_IPV4_OK: 2227 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 2228 break; 2229 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 2230 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 2231 break; 2232 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 2233 packet_type |= RTE_PTYPE_L3_IPV6; 2234 break; 2235 case PP2_INQ_L3_TYPE_IPV6_EXT: 2236 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 2237 break; 2238 case PP2_INQ_L3_TYPE_ARP: 2239 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 2240 /* 2241 * In case of ARP l4_offset is set to wrong value. 2242 * Set it to proper one so that later on mbuf->l3_len can be 2243 * calculated subtracting l4_offset and l3_offset. 2244 */ 2245 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 2246 break; 2247 default: 2248 break; 2249 } 2250 2251 switch (l4_type) { 2252 case PP2_INQ_L4_TYPE_TCP: 2253 packet_type |= RTE_PTYPE_L4_TCP; 2254 break; 2255 case PP2_INQ_L4_TYPE_UDP: 2256 packet_type |= RTE_PTYPE_L4_UDP; 2257 break; 2258 default: 2259 break; 2260 } 2261 2262 return packet_type; 2263 } 2264 2265 /** 2266 * Get offload information from the received packet descriptor. 2267 * 2268 * @param desc 2269 * Pointer to the received packet descriptor. 2270 * 2271 * @return 2272 * Mbuf offload flags. 2273 */ 2274 static inline uint64_t 2275 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) 2276 { 2277 uint64_t flags; 2278 enum pp2_inq_desc_status status; 2279 2280 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2281 if (unlikely(status != PP2_DESC_ERR_OK)) 2282 flags = PKT_RX_IP_CKSUM_BAD; 2283 else 2284 flags = PKT_RX_IP_CKSUM_GOOD; 2285 2286 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2287 if (unlikely(status != PP2_DESC_ERR_OK)) 2288 flags |= PKT_RX_L4_CKSUM_BAD; 2289 else 2290 flags |= PKT_RX_L4_CKSUM_GOOD; 2291 2292 return flags; 2293 } 2294 2295 /** 2296 * DPDK callback for receive. 2297 * 2298 * @param rxq 2299 * Generic pointer to the receive queue. 2300 * @param rx_pkts 2301 * Array to store received packets. 2302 * @param nb_pkts 2303 * Maximum number of packets in array. 2304 * 2305 * @return 2306 * Number of packets successfully received. 2307 */ 2308 static uint16_t 2309 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2310 { 2311 struct mrvl_rxq *q = rxq; 2312 struct pp2_ppio_desc descs[nb_pkts]; 2313 struct pp2_bpool *bpool; 2314 int i, ret, rx_done = 0; 2315 int num; 2316 struct pp2_hif *hif; 2317 unsigned int core_id = rte_lcore_id(); 2318 2319 hif = mrvl_get_hif(q->priv, core_id); 2320 2321 if (unlikely(!q->priv->ppio || !hif)) 2322 return 0; 2323 2324 bpool = q->priv->bpool; 2325 2326 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2327 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2328 if (unlikely(ret < 0)) 2329 return 0; 2330 2331 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2332 2333 for (i = 0; i < nb_pkts; i++) { 2334 struct rte_mbuf *mbuf; 2335 uint8_t l3_offset, l4_offset; 2336 enum pp2_inq_desc_status status; 2337 uint64_t addr; 2338 2339 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2340 struct pp2_ppio_desc *pref_desc; 2341 u64 pref_addr; 2342 2343 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2344 pref_addr = cookie_addr_high | 2345 pp2_ppio_inq_desc_get_cookie(pref_desc); 2346 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2347 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2348 } 2349 2350 addr = cookie_addr_high | 2351 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2352 mbuf = (struct rte_mbuf *)addr; 2353 rte_pktmbuf_reset(mbuf); 2354 2355 /* drop packet in case of mac, overrun or resource error */ 2356 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2357 if (unlikely(status != PP2_DESC_ERR_OK)) { 2358 struct pp2_buff_inf binf = { 2359 .addr = rte_mbuf_data_iova_default(mbuf), 2360 .cookie = (uint64_t)mbuf, 2361 }; 2362 2363 pp2_bpool_put_buff(hif, bpool, &binf); 2364 mrvl_port_bpool_size 2365 [bpool->pp2_id][bpool->id][core_id]++; 2366 q->drop_mac++; 2367 continue; 2368 } 2369 2370 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2371 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2372 mbuf->data_len = mbuf->pkt_len; 2373 mbuf->port = q->port_id; 2374 mbuf->packet_type = 2375 mrvl_desc_to_packet_type_and_offset(&descs[i], 2376 &l3_offset, 2377 &l4_offset); 2378 mbuf->l2_len = l3_offset; 2379 mbuf->l3_len = l4_offset - l3_offset; 2380 2381 if (likely(q->cksum_enabled)) 2382 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); 2383 2384 rx_pkts[rx_done++] = mbuf; 2385 q->bytes_recv += mbuf->pkt_len; 2386 } 2387 2388 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2389 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2390 2391 if (unlikely(num <= q->priv->bpool_min_size || 2392 (!rx_done && num < q->priv->bpool_init_size))) { 2393 mrvl_fill_bpool(q, MRVL_BURST_SIZE); 2394 } else if (unlikely(num > q->priv->bpool_max_size)) { 2395 int i; 2396 int pkt_to_remove = num - q->priv->bpool_init_size; 2397 struct rte_mbuf *mbuf; 2398 struct pp2_buff_inf buff; 2399 2400 for (i = 0; i < pkt_to_remove; i++) { 2401 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2402 if (ret) 2403 break; 2404 mbuf = (struct rte_mbuf *) 2405 (cookie_addr_high | buff.cookie); 2406 rte_pktmbuf_free(mbuf); 2407 } 2408 mrvl_port_bpool_size 2409 [bpool->pp2_id][bpool->id][core_id] -= i; 2410 } 2411 rte_spinlock_unlock(&q->priv->lock); 2412 } 2413 2414 return rx_done; 2415 } 2416 2417 /** 2418 * Prepare offload information. 2419 * 2420 * @param ol_flags 2421 * Offload flags. 2422 * @param packet_type 2423 * Packet type bitfield. 2424 * @param l3_type 2425 * Pointer to the pp2_ouq_l3_type structure. 2426 * @param l4_type 2427 * Pointer to the pp2_outq_l4_type structure. 2428 * @param gen_l3_cksum 2429 * Will be set to 1 in case l3 checksum is computed. 2430 * @param l4_cksum 2431 * Will be set to 1 in case l4 checksum is computed. 2432 * 2433 * @return 2434 * 0 on success, negative error value otherwise. 2435 */ 2436 static inline int 2437 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, 2438 enum pp2_outq_l3_type *l3_type, 2439 enum pp2_outq_l4_type *l4_type, 2440 int *gen_l3_cksum, 2441 int *gen_l4_cksum) 2442 { 2443 /* 2444 * Based on ol_flags prepare information 2445 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2446 * for offloading. 2447 */ 2448 if (ol_flags & PKT_TX_IPV4) { 2449 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2450 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; 2451 } else if (ol_flags & PKT_TX_IPV6) { 2452 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2453 /* no checksum for ipv6 header */ 2454 *gen_l3_cksum = 0; 2455 } else { 2456 /* if something different then stop processing */ 2457 return -1; 2458 } 2459 2460 ol_flags &= PKT_TX_L4_MASK; 2461 if ((packet_type & RTE_PTYPE_L4_TCP) && 2462 ol_flags == PKT_TX_TCP_CKSUM) { 2463 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2464 *gen_l4_cksum = 1; 2465 } else if ((packet_type & RTE_PTYPE_L4_UDP) && 2466 ol_flags == PKT_TX_UDP_CKSUM) { 2467 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2468 *gen_l4_cksum = 1; 2469 } else { 2470 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2471 /* no checksum for other type */ 2472 *gen_l4_cksum = 0; 2473 } 2474 2475 return 0; 2476 } 2477 2478 /** 2479 * Release already sent buffers to bpool (buffer-pool). 2480 * 2481 * @param ppio 2482 * Pointer to the port structure. 2483 * @param hif 2484 * Pointer to the MUSDK hardware interface. 2485 * @param sq 2486 * Pointer to the shadow queue. 2487 * @param qid 2488 * Queue id number. 2489 * @param force 2490 * Force releasing packets. 2491 */ 2492 static inline void 2493 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2494 unsigned int core_id, struct mrvl_shadow_txq *sq, 2495 int qid, int force) 2496 { 2497 struct buff_release_entry *entry; 2498 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2499 int i; 2500 2501 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2502 2503 sq->num_to_release += nb_done; 2504 2505 if (likely(!force && 2506 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2507 return; 2508 2509 nb_done = sq->num_to_release; 2510 sq->num_to_release = 0; 2511 2512 for (i = 0; i < nb_done; i++) { 2513 entry = &sq->ent[sq->tail + num]; 2514 if (unlikely(!entry->buff.addr)) { 2515 MRVL_LOG(ERR, 2516 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2517 sq->tail, (u64)entry->buff.cookie, 2518 (u64)entry->buff.addr); 2519 skip_bufs = 1; 2520 goto skip; 2521 } 2522 2523 if (unlikely(!entry->bpool)) { 2524 struct rte_mbuf *mbuf; 2525 2526 mbuf = (struct rte_mbuf *)entry->buff.cookie; 2527 rte_pktmbuf_free(mbuf); 2528 skip_bufs = 1; 2529 goto skip; 2530 } 2531 2532 mrvl_port_bpool_size 2533 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2534 num++; 2535 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2536 goto skip; 2537 continue; 2538 skip: 2539 if (likely(num)) 2540 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2541 num += skip_bufs; 2542 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2543 sq->size -= num; 2544 num = 0; 2545 skip_bufs = 0; 2546 } 2547 2548 if (likely(num)) { 2549 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2550 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2551 sq->size -= num; 2552 } 2553 } 2554 2555 /** 2556 * DPDK callback for transmit. 2557 * 2558 * @param txq 2559 * Generic pointer transmit queue. 2560 * @param tx_pkts 2561 * Packets to transmit. 2562 * @param nb_pkts 2563 * Number of packets in array. 2564 * 2565 * @return 2566 * Number of packets successfully transmitted. 2567 */ 2568 static uint16_t 2569 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2570 { 2571 struct mrvl_txq *q = txq; 2572 struct mrvl_shadow_txq *sq; 2573 struct pp2_hif *hif; 2574 struct pp2_ppio_desc descs[nb_pkts]; 2575 unsigned int core_id = rte_lcore_id(); 2576 int i, ret, bytes_sent = 0; 2577 uint16_t num, sq_free_size; 2578 uint64_t addr; 2579 2580 hif = mrvl_get_hif(q->priv, core_id); 2581 sq = &q->shadow_txqs[core_id]; 2582 2583 if (unlikely(!q->priv->ppio || !hif)) 2584 return 0; 2585 2586 if (sq->size) 2587 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2588 sq, q->queue_id, 0); 2589 2590 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2591 if (unlikely(nb_pkts > sq_free_size)) 2592 nb_pkts = sq_free_size; 2593 2594 for (i = 0; i < nb_pkts; i++) { 2595 struct rte_mbuf *mbuf = tx_pkts[i]; 2596 int gen_l3_cksum, gen_l4_cksum; 2597 enum pp2_outq_l3_type l3_type; 2598 enum pp2_outq_l4_type l4_type; 2599 2600 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2601 struct rte_mbuf *pref_pkt_hdr; 2602 2603 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2604 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2605 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2606 } 2607 2608 mrvl_fill_shadowq(sq, mbuf); 2609 mrvl_fill_desc(&descs[i], mbuf); 2610 2611 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2612 /* 2613 * in case unsupported ol_flags were passed 2614 * do not update descriptor offload information 2615 */ 2616 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2617 &l3_type, &l4_type, &gen_l3_cksum, 2618 &gen_l4_cksum); 2619 if (unlikely(ret)) 2620 continue; 2621 2622 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2623 mbuf->l2_len, 2624 mbuf->l2_len + mbuf->l3_len, 2625 gen_l3_cksum, gen_l4_cksum); 2626 } 2627 2628 num = nb_pkts; 2629 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2630 /* number of packets that were not sent */ 2631 if (unlikely(num > nb_pkts)) { 2632 for (i = nb_pkts; i < num; i++) { 2633 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2634 MRVL_PP2_TX_SHADOWQ_MASK; 2635 addr = sq->ent[sq->head].buff.cookie; 2636 bytes_sent -= 2637 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2638 } 2639 sq->size -= num - nb_pkts; 2640 } 2641 2642 q->bytes_sent += bytes_sent; 2643 2644 return nb_pkts; 2645 } 2646 2647 /** DPDK callback for S/G transmit. 2648 * 2649 * @param txq 2650 * Generic pointer transmit queue. 2651 * @param tx_pkts 2652 * Packets to transmit. 2653 * @param nb_pkts 2654 * Number of packets in array. 2655 * 2656 * @return 2657 * Number of packets successfully transmitted. 2658 */ 2659 static uint16_t 2660 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 2661 uint16_t nb_pkts) 2662 { 2663 struct mrvl_txq *q = txq; 2664 struct mrvl_shadow_txq *sq; 2665 struct pp2_hif *hif; 2666 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS]; 2667 struct pp2_ppio_sg_pkts pkts; 2668 uint8_t frags[nb_pkts]; 2669 unsigned int core_id = rte_lcore_id(); 2670 int i, j, ret, bytes_sent = 0; 2671 int tail, tail_first; 2672 uint16_t num, sq_free_size; 2673 uint16_t nb_segs, total_descs = 0; 2674 uint64_t addr; 2675 2676 hif = mrvl_get_hif(q->priv, core_id); 2677 sq = &q->shadow_txqs[core_id]; 2678 pkts.frags = frags; 2679 pkts.num = 0; 2680 2681 if (unlikely(!q->priv->ppio || !hif)) 2682 return 0; 2683 2684 if (sq->size) 2685 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2686 sq, q->queue_id, 0); 2687 2688 /* Save shadow queue free size */ 2689 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2690 2691 tail = 0; 2692 for (i = 0; i < nb_pkts; i++) { 2693 struct rte_mbuf *mbuf = tx_pkts[i]; 2694 struct rte_mbuf *seg = NULL; 2695 int gen_l3_cksum, gen_l4_cksum; 2696 enum pp2_outq_l3_type l3_type; 2697 enum pp2_outq_l4_type l4_type; 2698 2699 nb_segs = mbuf->nb_segs; 2700 tail_first = tail; 2701 total_descs += nb_segs; 2702 2703 /* 2704 * Check if total_descs does not exceed 2705 * shadow queue free size 2706 */ 2707 if (unlikely(total_descs > sq_free_size)) { 2708 total_descs -= nb_segs; 2709 break; 2710 } 2711 2712 /* Check if nb_segs does not exceed the max nb of desc per 2713 * fragmented packet 2714 */ 2715 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) { 2716 total_descs -= nb_segs; 2717 RTE_LOG(ERR, PMD, 2718 "Too many segments. Packet won't be sent.\n"); 2719 break; 2720 } 2721 2722 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2723 struct rte_mbuf *pref_pkt_hdr; 2724 2725 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2726 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2727 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2728 } 2729 2730 pkts.frags[pkts.num] = nb_segs; 2731 pkts.num++; 2732 2733 seg = mbuf; 2734 for (j = 0; j < nb_segs - 1; j++) { 2735 /* For the subsequent segments, set shadow queue 2736 * buffer to NULL 2737 */ 2738 mrvl_fill_shadowq(sq, NULL); 2739 mrvl_fill_desc(&descs[tail], seg); 2740 2741 tail++; 2742 seg = seg->next; 2743 } 2744 /* Put first mbuf info in last shadow queue entry */ 2745 mrvl_fill_shadowq(sq, mbuf); 2746 /* Update descriptor with last segment */ 2747 mrvl_fill_desc(&descs[tail++], seg); 2748 2749 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2750 /* In case unsupported ol_flags were passed 2751 * do not update descriptor offload information 2752 */ 2753 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2754 &l3_type, &l4_type, &gen_l3_cksum, 2755 &gen_l4_cksum); 2756 if (unlikely(ret)) 2757 continue; 2758 2759 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, 2760 l4_type, mbuf->l2_len, 2761 mbuf->l2_len + mbuf->l3_len, 2762 gen_l3_cksum, gen_l4_cksum); 2763 } 2764 2765 num = total_descs; 2766 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs, 2767 &total_descs, &pkts); 2768 /* number of packets that were not sent */ 2769 if (unlikely(num > total_descs)) { 2770 for (i = total_descs; i < num; i++) { 2771 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2772 MRVL_PP2_TX_SHADOWQ_MASK; 2773 2774 addr = sq->ent[sq->head].buff.cookie; 2775 if (addr) 2776 bytes_sent -= 2777 rte_pktmbuf_pkt_len((struct rte_mbuf *) 2778 (cookie_addr_high | addr)); 2779 } 2780 sq->size -= num - total_descs; 2781 nb_pkts = pkts.num; 2782 } 2783 2784 q->bytes_sent += bytes_sent; 2785 2786 return nb_pkts; 2787 } 2788 2789 /** 2790 * Initialize packet processor. 2791 * 2792 * @return 2793 * 0 on success, negative error value otherwise. 2794 */ 2795 static int 2796 mrvl_init_pp2(void) 2797 { 2798 struct pp2_init_params init_params; 2799 2800 memset(&init_params, 0, sizeof(init_params)); 2801 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 2802 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 2803 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 2804 2805 return pp2_init(&init_params); 2806 } 2807 2808 /** 2809 * Deinitialize packet processor. 2810 * 2811 * @return 2812 * 0 on success, negative error value otherwise. 2813 */ 2814 static void 2815 mrvl_deinit_pp2(void) 2816 { 2817 pp2_deinit(); 2818 } 2819 2820 /** 2821 * Create private device structure. 2822 * 2823 * @param dev_name 2824 * Pointer to the port name passed in the initialization parameters. 2825 * 2826 * @return 2827 * Pointer to the newly allocated private device structure. 2828 */ 2829 static struct mrvl_priv * 2830 mrvl_priv_create(const char *dev_name) 2831 { 2832 struct pp2_bpool_params bpool_params; 2833 char match[MRVL_MATCH_LEN]; 2834 struct mrvl_priv *priv; 2835 int ret, bpool_bit; 2836 2837 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 2838 if (!priv) 2839 return NULL; 2840 2841 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 2842 &priv->pp_id, &priv->ppio_id); 2843 if (ret) 2844 goto out_free_priv; 2845 2846 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 2847 PP2_BPOOL_NUM_POOLS); 2848 if (bpool_bit < 0) 2849 goto out_free_priv; 2850 priv->bpool_bit = bpool_bit; 2851 2852 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 2853 priv->bpool_bit); 2854 memset(&bpool_params, 0, sizeof(bpool_params)); 2855 bpool_params.match = match; 2856 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 2857 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 2858 if (ret) 2859 goto out_clear_bpool_bit; 2860 2861 priv->ppio_params.type = PP2_PPIO_T_NIC; 2862 rte_spinlock_init(&priv->lock); 2863 2864 return priv; 2865 out_clear_bpool_bit: 2866 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2867 out_free_priv: 2868 rte_free(priv); 2869 return NULL; 2870 } 2871 2872 /** 2873 * Create device representing Ethernet port. 2874 * 2875 * @param name 2876 * Pointer to the port's name. 2877 * 2878 * @return 2879 * 0 on success, negative error value otherwise. 2880 */ 2881 static int 2882 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 2883 { 2884 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 2885 struct rte_eth_dev *eth_dev; 2886 struct mrvl_priv *priv; 2887 struct ifreq req; 2888 2889 eth_dev = rte_eth_dev_allocate(name); 2890 if (!eth_dev) 2891 return -ENOMEM; 2892 2893 priv = mrvl_priv_create(name); 2894 if (!priv) { 2895 ret = -ENOMEM; 2896 goto out_free; 2897 } 2898 eth_dev->data->dev_private = priv; 2899 2900 eth_dev->data->mac_addrs = 2901 rte_zmalloc("mac_addrs", 2902 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 2903 if (!eth_dev->data->mac_addrs) { 2904 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 2905 ret = -ENOMEM; 2906 goto out_free; 2907 } 2908 2909 memset(&req, 0, sizeof(req)); 2910 strcpy(req.ifr_name, name); 2911 ret = ioctl(fd, SIOCGIFHWADDR, &req); 2912 if (ret) 2913 goto out_free; 2914 2915 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 2916 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN); 2917 2918 eth_dev->device = &vdev->device; 2919 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 2920 mrvl_set_tx_function(eth_dev); 2921 eth_dev->dev_ops = &mrvl_ops; 2922 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2923 2924 eth_dev->data->dev_link.link_status = ETH_LINK_UP; 2925 2926 rte_eth_dev_probing_finish(eth_dev); 2927 return 0; 2928 out_free: 2929 rte_eth_dev_release_port(eth_dev); 2930 2931 return ret; 2932 } 2933 2934 /** 2935 * Callback used by rte_kvargs_process() during argument parsing. 2936 * 2937 * @param key 2938 * Pointer to the parsed key (unused). 2939 * @param value 2940 * Pointer to the parsed value. 2941 * @param extra_args 2942 * Pointer to the extra arguments which contains address of the 2943 * table of pointers to parsed interface names. 2944 * 2945 * @return 2946 * Always 0. 2947 */ 2948 static int 2949 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 2950 void *extra_args) 2951 { 2952 struct mrvl_ifnames *ifnames = extra_args; 2953 2954 ifnames->names[ifnames->idx++] = value; 2955 2956 return 0; 2957 } 2958 2959 /** 2960 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 2961 */ 2962 static void 2963 mrvl_deinit_hifs(void) 2964 { 2965 int i; 2966 2967 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 2968 if (hifs[i]) 2969 pp2_hif_deinit(hifs[i]); 2970 } 2971 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 2972 memset(hifs, 0, sizeof(hifs)); 2973 } 2974 2975 /** 2976 * DPDK callback to register the virtual device. 2977 * 2978 * @param vdev 2979 * Pointer to the virtual device. 2980 * 2981 * @return 2982 * 0 on success, negative error value otherwise. 2983 */ 2984 static int 2985 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 2986 { 2987 struct rte_kvargs *kvlist; 2988 struct mrvl_ifnames ifnames; 2989 int ret = -EINVAL; 2990 uint32_t i, ifnum, cfgnum; 2991 const char *params; 2992 2993 params = rte_vdev_device_args(vdev); 2994 if (!params) 2995 return -EINVAL; 2996 2997 kvlist = rte_kvargs_parse(params, valid_args); 2998 if (!kvlist) 2999 return -EINVAL; 3000 3001 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 3002 if (ifnum > RTE_DIM(ifnames.names)) 3003 goto out_free_kvlist; 3004 3005 ifnames.idx = 0; 3006 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 3007 mrvl_get_ifnames, &ifnames); 3008 3009 3010 /* 3011 * The below system initialization should be done only once, 3012 * on the first provided configuration file 3013 */ 3014 if (!mrvl_qos_cfg) { 3015 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 3016 MRVL_LOG(INFO, "Parsing config file!"); 3017 if (cfgnum > 1) { 3018 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 3019 goto out_free_kvlist; 3020 } else if (cfgnum == 1) { 3021 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 3022 mrvl_get_qoscfg, &mrvl_qos_cfg); 3023 } 3024 } 3025 3026 if (mrvl_dev_num) 3027 goto init_devices; 3028 3029 MRVL_LOG(INFO, "Perform MUSDK initializations"); 3030 3031 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 3032 if (ret) 3033 goto out_free_kvlist; 3034 3035 ret = mrvl_init_pp2(); 3036 if (ret) { 3037 MRVL_LOG(ERR, "Failed to init PP!"); 3038 rte_mvep_deinit(MVEP_MOD_T_PP2); 3039 goto out_free_kvlist; 3040 } 3041 3042 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 3043 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 3044 3045 mrvl_lcore_first = RTE_MAX_LCORE; 3046 mrvl_lcore_last = 0; 3047 3048 init_devices: 3049 for (i = 0; i < ifnum; i++) { 3050 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 3051 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 3052 if (ret) 3053 goto out_cleanup; 3054 mrvl_dev_num++; 3055 } 3056 3057 rte_kvargs_free(kvlist); 3058 3059 return 0; 3060 out_cleanup: 3061 rte_pmd_mrvl_remove(vdev); 3062 3063 out_free_kvlist: 3064 rte_kvargs_free(kvlist); 3065 3066 return ret; 3067 } 3068 3069 /** 3070 * DPDK callback to remove virtual device. 3071 * 3072 * @param vdev 3073 * Pointer to the removed virtual device. 3074 * 3075 * @return 3076 * 0 on success, negative error value otherwise. 3077 */ 3078 static int 3079 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 3080 { 3081 uint16_t port_id; 3082 int ret = 0; 3083 3084 RTE_ETH_FOREACH_DEV(port_id) { 3085 if (rte_eth_devices[port_id].device != &vdev->device) 3086 continue; 3087 ret |= rte_eth_dev_close(port_id); 3088 } 3089 3090 return ret == 0 ? 0 : -EIO; 3091 } 3092 3093 static struct rte_vdev_driver pmd_mrvl_drv = { 3094 .probe = rte_pmd_mrvl_probe, 3095 .remove = rte_pmd_mrvl_remove, 3096 }; 3097 3098 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 3099 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 3100 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE); 3101