1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_string_fns.h> 8 #include <ethdev_driver.h> 9 #include <rte_kvargs.h> 10 #include <rte_log.h> 11 #include <rte_malloc.h> 12 #include <rte_bus_vdev.h> 13 14 #include <fcntl.h> 15 #include <linux/ethtool.h> 16 #include <linux/sockios.h> 17 #include <net/if.h> 18 #include <net/if_arp.h> 19 #include <sys/ioctl.h> 20 #include <sys/socket.h> 21 #include <sys/stat.h> 22 #include <sys/types.h> 23 24 #include <rte_mvep_common.h> 25 #include "mrvl_ethdev.h" 26 #include "mrvl_qos.h" 27 #include "mrvl_flow.h" 28 #include "mrvl_mtr.h" 29 #include "mrvl_tm.h" 30 31 /* bitmask with reserved hifs */ 32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 33 /* bitmask with reserved bpools */ 34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 35 /* bitmask with reserved kernel RSS tables */ 36 #define MRVL_MUSDK_RSS_RESERVED 0x0F 37 /* maximum number of available hifs */ 38 #define MRVL_MUSDK_HIFS_MAX 9 39 40 /* prefetch shift */ 41 #define MRVL_MUSDK_PREFETCH_SHIFT 2 42 43 /* TCAM has 25 entries reserved for uc/mc filter entries */ 44 #define MRVL_MAC_ADDRS_MAX 25 45 #define MRVL_MATCH_LEN 16 46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 47 /* Maximum allowable packet size */ 48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 49 50 #define MRVL_IFACE_NAME_ARG "iface" 51 #define MRVL_CFG_ARG "cfg" 52 53 #define MRVL_BURST_SIZE 64 54 55 #define MRVL_ARP_LENGTH 28 56 57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000 59 60 /** Port Rx offload capabilities */ 61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ 62 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 63 DEV_RX_OFFLOAD_CHECKSUM) 64 65 /** Port Tx offloads capabilities */ 66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 67 DEV_TX_OFFLOAD_UDP_CKSUM | \ 68 DEV_TX_OFFLOAD_TCP_CKSUM | \ 69 DEV_TX_OFFLOAD_MULTI_SEGS) 70 71 static const char * const valid_args[] = { 72 MRVL_IFACE_NAME_ARG, 73 MRVL_CFG_ARG, 74 NULL 75 }; 76 77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 78 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 79 static int used_bpools[PP2_NUM_PKT_PROC] = { 80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 81 }; 82 83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 86 87 struct mrvl_ifnames { 88 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 89 int idx; 90 }; 91 92 /* 93 * To use buffer harvesting based on loopback port shadow queue structure 94 * was introduced for buffers information bookkeeping. 95 * 96 * Before sending the packet, related buffer information (pp2_buff_inf) is 97 * stored in shadow queue. After packet is transmitted no longer used 98 * packet buffer is released back to it's original hardware pool, 99 * on condition it originated from interface. 100 * In case it was generated by application itself i.e: mbuf->port field is 101 * 0xff then its released to software mempool. 102 */ 103 struct mrvl_shadow_txq { 104 int head; /* write index - used when sending buffers */ 105 int tail; /* read index - used when releasing buffers */ 106 u16 size; /* queue occupied size */ 107 u16 num_to_release; /* number of descriptors sent, that can be 108 * released 109 */ 110 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 111 }; 112 113 struct mrvl_rxq { 114 struct mrvl_priv *priv; 115 struct rte_mempool *mp; 116 int queue_id; 117 int port_id; 118 int cksum_enabled; 119 uint64_t bytes_recv; 120 uint64_t drop_mac; 121 }; 122 123 struct mrvl_txq { 124 struct mrvl_priv *priv; 125 int queue_id; 126 int port_id; 127 uint64_t bytes_sent; 128 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 129 int tx_deferred_start; 130 }; 131 132 static int mrvl_lcore_first; 133 static int mrvl_lcore_last; 134 static int mrvl_dev_num; 135 136 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 137 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 138 struct pp2_hif *hif, unsigned int core_id, 139 struct mrvl_shadow_txq *sq, int qid, int force); 140 141 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 142 uint16_t nb_pkts); 143 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 144 uint16_t nb_pkts); 145 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); 146 static void mrvl_deinit_pp2(void); 147 static void mrvl_deinit_hifs(void); 148 149 150 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 151 #name, offsetof(struct pp2_ppio_statistics, name), \ 152 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 153 } 154 155 /* Table with xstats data */ 156 static struct { 157 const char *name; 158 unsigned int offset; 159 unsigned int size; 160 } mrvl_xstats_tbl[] = { 161 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 162 MRVL_XSTATS_TBL_ENTRY(rx_packets), 163 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 164 MRVL_XSTATS_TBL_ENTRY(rx_errors), 165 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 166 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 167 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 168 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 169 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 170 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 171 MRVL_XSTATS_TBL_ENTRY(tx_packets), 172 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 173 MRVL_XSTATS_TBL_ENTRY(tx_errors) 174 }; 175 176 static inline void 177 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) 178 { 179 sq->ent[sq->head].buff.cookie = (uint64_t)buf; 180 sq->ent[sq->head].buff.addr = buf ? 181 rte_mbuf_data_iova_default(buf) : 0; 182 183 sq->ent[sq->head].bpool = 184 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS || 185 buf->refcnt > 1)) ? NULL : 186 mrvl_port_to_bpool_lookup[buf->port]; 187 188 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 189 sq->size++; 190 } 191 192 static inline void 193 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf) 194 { 195 pp2_ppio_outq_desc_reset(desc); 196 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf)); 197 pp2_ppio_outq_desc_set_pkt_offset(desc, 0); 198 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf)); 199 } 200 201 static inline int 202 mrvl_get_bpool_size(int pp2_id, int pool_id) 203 { 204 int i; 205 int size = 0; 206 207 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 208 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 209 210 return size; 211 } 212 213 static inline int 214 mrvl_reserve_bit(int *bitmap, int max) 215 { 216 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 217 218 if (n >= max) 219 return -1; 220 221 *bitmap |= 1 << n; 222 223 return n; 224 } 225 226 static int 227 mrvl_init_hif(int core_id) 228 { 229 struct pp2_hif_params params; 230 char match[MRVL_MATCH_LEN]; 231 int ret; 232 233 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 234 if (ret < 0) { 235 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 236 return ret; 237 } 238 239 snprintf(match, sizeof(match), "hif-%d", ret); 240 memset(¶ms, 0, sizeof(params)); 241 params.match = match; 242 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 243 ret = pp2_hif_init(¶ms, &hifs[core_id]); 244 if (ret) { 245 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 246 return ret; 247 } 248 249 return 0; 250 } 251 252 static inline struct pp2_hif* 253 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 254 { 255 int ret; 256 257 if (likely(hifs[core_id] != NULL)) 258 return hifs[core_id]; 259 260 rte_spinlock_lock(&priv->lock); 261 262 ret = mrvl_init_hif(core_id); 263 if (ret < 0) { 264 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 265 goto out; 266 } 267 268 if (core_id < mrvl_lcore_first) 269 mrvl_lcore_first = core_id; 270 271 if (core_id > mrvl_lcore_last) 272 mrvl_lcore_last = core_id; 273 out: 274 rte_spinlock_unlock(&priv->lock); 275 276 return hifs[core_id]; 277 } 278 279 /** 280 * Set tx burst function according to offload flag 281 * 282 * @param dev 283 * Pointer to Ethernet device structure. 284 */ 285 static void 286 mrvl_set_tx_function(struct rte_eth_dev *dev) 287 { 288 struct mrvl_priv *priv = dev->data->dev_private; 289 290 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 291 if (priv->multiseg) { 292 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n"); 293 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst; 294 } else { 295 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n"); 296 dev->tx_pkt_burst = mrvl_tx_pkt_burst; 297 } 298 } 299 300 /** 301 * Configure rss based on dpdk rss configuration. 302 * 303 * @param priv 304 * Pointer to private structure. 305 * @param rss_conf 306 * Pointer to RSS configuration. 307 * 308 * @return 309 * 0 on success, negative error value otherwise. 310 */ 311 static int 312 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 313 { 314 if (rss_conf->rss_key) 315 MRVL_LOG(WARNING, "Changing hash key is not supported"); 316 317 if (rss_conf->rss_hf == 0) { 318 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 319 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { 320 priv->ppio_params.inqs_params.hash_type = 321 PP2_PPIO_HASH_T_2_TUPLE; 322 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 323 priv->ppio_params.inqs_params.hash_type = 324 PP2_PPIO_HASH_T_5_TUPLE; 325 priv->rss_hf_tcp = 1; 326 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 327 priv->ppio_params.inqs_params.hash_type = 328 PP2_PPIO_HASH_T_5_TUPLE; 329 priv->rss_hf_tcp = 0; 330 } else { 331 return -EINVAL; 332 } 333 334 return 0; 335 } 336 337 /** 338 * Ethernet device configuration. 339 * 340 * Prepare the driver for a given number of TX and RX queues and 341 * configure RSS. 342 * 343 * @param dev 344 * Pointer to Ethernet device structure. 345 * 346 * @return 347 * 0 on success, negative error value otherwise. 348 */ 349 static int 350 mrvl_dev_configure(struct rte_eth_dev *dev) 351 { 352 struct mrvl_priv *priv = dev->data->dev_private; 353 int ret; 354 355 if (priv->ppio) { 356 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 357 return -EINVAL; 358 } 359 360 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && 361 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 362 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 363 dev->data->dev_conf.rxmode.mq_mode); 364 return -EINVAL; 365 } 366 367 if (dev->data->dev_conf.rxmode.split_hdr_size) { 368 MRVL_LOG(INFO, "Split headers not supported"); 369 return -EINVAL; 370 } 371 372 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 373 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 374 MRVL_PP2_ETH_HDRS_LEN; 375 376 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 377 priv->multiseg = 1; 378 379 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 380 dev->data->nb_rx_queues); 381 if (ret < 0) 382 return ret; 383 384 ret = mrvl_configure_txqs(priv, dev->data->port_id, 385 dev->data->nb_tx_queues); 386 if (ret < 0) 387 return ret; 388 389 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 390 priv->ppio_params.maintain_stats = 1; 391 priv->nb_rx_queues = dev->data->nb_rx_queues; 392 393 ret = mrvl_tm_init(dev); 394 if (ret < 0) 395 return ret; 396 397 if (dev->data->nb_rx_queues == 1 && 398 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 399 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 400 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 401 402 return 0; 403 } 404 405 return mrvl_configure_rss(priv, 406 &dev->data->dev_conf.rx_adv_conf.rss_conf); 407 } 408 409 /** 410 * DPDK callback to change the MTU. 411 * 412 * Setting the MTU affects hardware MRU (packets larger than the MRU 413 * will be dropped). 414 * 415 * @param dev 416 * Pointer to Ethernet device structure. 417 * @param mtu 418 * New MTU. 419 * 420 * @return 421 * 0 on success, negative error value otherwise. 422 */ 423 static int 424 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 425 { 426 struct mrvl_priv *priv = dev->data->dev_private; 427 uint16_t mru; 428 uint16_t mbuf_data_size = 0; /* SW buffer size */ 429 int ret; 430 431 mru = MRVL_PP2_MTU_TO_MRU(mtu); 432 /* 433 * min_rx_buf_size is equal to mbuf data size 434 * if pmd didn't set it differently 435 */ 436 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 437 /* Prevent PMD from: 438 * - setting mru greater than the mbuf size resulting in 439 * hw and sw buffer size mismatch 440 * - setting mtu that requires the support of scattered packets 441 * when this feature has not been enabled/supported so far 442 * (TODO check scattered_rx flag here once scattered RX is supported). 443 */ 444 if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) { 445 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS; 446 mtu = MRVL_PP2_MRU_TO_MTU(mru); 447 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted " 448 "by current mbuf size: %u. Set MTU to %u, MRU to %u", 449 mbuf_data_size, mtu, mru); 450 } 451 452 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) { 453 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru); 454 return -EINVAL; 455 } 456 457 dev->data->mtu = mtu; 458 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE; 459 460 if (!priv->ppio) 461 return 0; 462 463 ret = pp2_ppio_set_mru(priv->ppio, mru); 464 if (ret) { 465 MRVL_LOG(ERR, "Failed to change MRU"); 466 return ret; 467 } 468 469 ret = pp2_ppio_set_mtu(priv->ppio, mtu); 470 if (ret) { 471 MRVL_LOG(ERR, "Failed to change MTU"); 472 return ret; 473 } 474 475 return 0; 476 } 477 478 /** 479 * DPDK callback to bring the link up. 480 * 481 * @param dev 482 * Pointer to Ethernet device structure. 483 * 484 * @return 485 * 0 on success, negative error value otherwise. 486 */ 487 static int 488 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 489 { 490 struct mrvl_priv *priv = dev->data->dev_private; 491 int ret; 492 493 if (!priv->ppio) 494 return -EPERM; 495 496 ret = pp2_ppio_enable(priv->ppio); 497 if (ret) 498 return ret; 499 500 /* 501 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 502 * as pp2_ppio_enable() changes port->t_mode from default 0 to 503 * PP2_TRAFFIC_INGRESS_EGRESS. 504 * 505 * Set mtu to default DPDK value here. 506 */ 507 ret = mrvl_mtu_set(dev, dev->data->mtu); 508 if (ret) 509 pp2_ppio_disable(priv->ppio); 510 511 return ret; 512 } 513 514 /** 515 * DPDK callback to bring the link down. 516 * 517 * @param dev 518 * Pointer to Ethernet device structure. 519 * 520 * @return 521 * 0 on success, negative error value otherwise. 522 */ 523 static int 524 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 525 { 526 struct mrvl_priv *priv = dev->data->dev_private; 527 528 if (!priv->ppio) 529 return -EPERM; 530 531 return pp2_ppio_disable(priv->ppio); 532 } 533 534 /** 535 * DPDK callback to start tx queue. 536 * 537 * @param dev 538 * Pointer to Ethernet device structure. 539 * @param queue_id 540 * Transmit queue index. 541 * 542 * @return 543 * 0 on success, negative error value otherwise. 544 */ 545 static int 546 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 547 { 548 struct mrvl_priv *priv = dev->data->dev_private; 549 int ret; 550 551 if (!priv) 552 return -EPERM; 553 554 /* passing 1 enables given tx queue */ 555 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 556 if (ret) { 557 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 558 return ret; 559 } 560 561 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 562 563 return 0; 564 } 565 566 /** 567 * DPDK callback to stop tx queue. 568 * 569 * @param dev 570 * Pointer to Ethernet device structure. 571 * @param queue_id 572 * Transmit queue index. 573 * 574 * @return 575 * 0 on success, negative error value otherwise. 576 */ 577 static int 578 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 579 { 580 struct mrvl_priv *priv = dev->data->dev_private; 581 int ret; 582 583 if (!priv->ppio) 584 return -EPERM; 585 586 /* passing 0 disables given tx queue */ 587 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 588 if (ret) { 589 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 590 return ret; 591 } 592 593 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 594 595 return 0; 596 } 597 598 /** 599 * DPDK callback to start the device. 600 * 601 * @param dev 602 * Pointer to Ethernet device structure. 603 * 604 * @return 605 * 0 on success, negative errno value on failure. 606 */ 607 static int 608 mrvl_dev_start(struct rte_eth_dev *dev) 609 { 610 struct mrvl_priv *priv = dev->data->dev_private; 611 char match[MRVL_MATCH_LEN]; 612 int ret = 0, i, def_init_size; 613 614 if (priv->ppio) 615 return mrvl_dev_set_link_up(dev); 616 617 snprintf(match, sizeof(match), "ppio-%d:%d", 618 priv->pp_id, priv->ppio_id); 619 priv->ppio_params.match = match; 620 621 /* 622 * Calculate the minimum bpool size for refill feature as follows: 623 * 2 default burst sizes multiply by number of rx queues. 624 * If the bpool size will be below this value, new buffers will 625 * be added to the pool. 626 */ 627 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 628 629 /* In case initial bpool size configured in queues setup is 630 * smaller than minimum size add more buffers 631 */ 632 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 633 if (priv->bpool_init_size < def_init_size) { 634 int buffs_to_add = def_init_size - priv->bpool_init_size; 635 636 priv->bpool_init_size += buffs_to_add; 637 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 638 if (ret) 639 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 640 } 641 642 /* 643 * Calculate the maximum bpool size for refill feature as follows: 644 * maximum number of descriptors in rx queue multiply by number 645 * of rx queues plus minimum bpool size. 646 * In case the bpool size will exceed this value, superfluous buffers 647 * will be removed 648 */ 649 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 650 priv->bpool_min_size; 651 652 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 653 if (ret) { 654 MRVL_LOG(ERR, "Failed to init ppio"); 655 return ret; 656 } 657 658 /* 659 * In case there are some some stale uc/mc mac addresses flush them 660 * here. It cannot be done during mrvl_dev_close() as port information 661 * is already gone at that point (due to pp2_ppio_deinit() in 662 * mrvl_dev_stop()). 663 */ 664 if (!priv->uc_mc_flushed) { 665 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 666 if (ret) { 667 MRVL_LOG(ERR, 668 "Failed to flush uc/mc filter list"); 669 goto out; 670 } 671 priv->uc_mc_flushed = 1; 672 } 673 674 ret = mrvl_mtu_set(dev, dev->data->mtu); 675 if (ret) 676 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); 677 678 /* For default QoS config, don't start classifier. */ 679 if (mrvl_qos_cfg && 680 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) { 681 ret = mrvl_start_qos_mapping(priv); 682 if (ret) { 683 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 684 goto out; 685 } 686 } 687 688 ret = mrvl_dev_set_link_up(dev); 689 if (ret) { 690 MRVL_LOG(ERR, "Failed to set link up"); 691 goto out; 692 } 693 694 /* start tx queues */ 695 for (i = 0; i < dev->data->nb_tx_queues; i++) { 696 struct mrvl_txq *txq = dev->data->tx_queues[i]; 697 698 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 699 700 if (!txq->tx_deferred_start) 701 continue; 702 703 /* 704 * All txqs are started by default. Stop them 705 * so that tx_deferred_start works as expected. 706 */ 707 ret = mrvl_tx_queue_stop(dev, i); 708 if (ret) 709 goto out; 710 } 711 712 mrvl_flow_init(dev); 713 mrvl_mtr_init(dev); 714 mrvl_set_tx_function(dev); 715 716 return 0; 717 out: 718 MRVL_LOG(ERR, "Failed to start device"); 719 pp2_ppio_deinit(priv->ppio); 720 return ret; 721 } 722 723 /** 724 * Flush receive queues. 725 * 726 * @param dev 727 * Pointer to Ethernet device structure. 728 */ 729 static void 730 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 731 { 732 int i; 733 734 MRVL_LOG(INFO, "Flushing rx queues"); 735 for (i = 0; i < dev->data->nb_rx_queues; i++) { 736 int ret, num; 737 738 do { 739 struct mrvl_rxq *q = dev->data->rx_queues[i]; 740 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 741 742 num = MRVL_PP2_RXD_MAX; 743 ret = pp2_ppio_recv(q->priv->ppio, 744 q->priv->rxq_map[q->queue_id].tc, 745 q->priv->rxq_map[q->queue_id].inq, 746 descs, (uint16_t *)&num); 747 } while (ret == 0 && num); 748 } 749 } 750 751 /** 752 * Flush transmit shadow queues. 753 * 754 * @param dev 755 * Pointer to Ethernet device structure. 756 */ 757 static void 758 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 759 { 760 int i, j; 761 struct mrvl_txq *txq; 762 763 MRVL_LOG(INFO, "Flushing tx shadow queues"); 764 for (i = 0; i < dev->data->nb_tx_queues; i++) { 765 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 766 767 for (j = 0; j < RTE_MAX_LCORE; j++) { 768 struct mrvl_shadow_txq *sq; 769 770 if (!hifs[j]) 771 continue; 772 773 sq = &txq->shadow_txqs[j]; 774 mrvl_free_sent_buffers(txq->priv->ppio, 775 hifs[j], j, sq, txq->queue_id, 1); 776 while (sq->tail != sq->head) { 777 uint64_t addr = cookie_addr_high | 778 sq->ent[sq->tail].buff.cookie; 779 rte_pktmbuf_free( 780 (struct rte_mbuf *)addr); 781 sq->tail = (sq->tail + 1) & 782 MRVL_PP2_TX_SHADOWQ_MASK; 783 } 784 memset(sq, 0, sizeof(*sq)); 785 } 786 } 787 } 788 789 /** 790 * Flush hardware bpool (buffer-pool). 791 * 792 * @param dev 793 * Pointer to Ethernet device structure. 794 */ 795 static void 796 mrvl_flush_bpool(struct rte_eth_dev *dev) 797 { 798 struct mrvl_priv *priv = dev->data->dev_private; 799 struct pp2_hif *hif; 800 uint32_t num; 801 int ret; 802 unsigned int core_id = rte_lcore_id(); 803 804 if (core_id == LCORE_ID_ANY) 805 core_id = rte_get_main_lcore(); 806 807 hif = mrvl_get_hif(priv, core_id); 808 809 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 810 if (ret) { 811 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 812 return; 813 } 814 815 while (num--) { 816 struct pp2_buff_inf inf; 817 uint64_t addr; 818 819 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 820 if (ret) 821 break; 822 823 addr = cookie_addr_high | inf.cookie; 824 rte_pktmbuf_free((struct rte_mbuf *)addr); 825 } 826 } 827 828 /** 829 * DPDK callback to stop the device. 830 * 831 * @param dev 832 * Pointer to Ethernet device structure. 833 */ 834 static int 835 mrvl_dev_stop(struct rte_eth_dev *dev) 836 { 837 return mrvl_dev_set_link_down(dev); 838 } 839 840 /** 841 * DPDK callback to close the device. 842 * 843 * @param dev 844 * Pointer to Ethernet device structure. 845 */ 846 static int 847 mrvl_dev_close(struct rte_eth_dev *dev) 848 { 849 struct mrvl_priv *priv = dev->data->dev_private; 850 size_t i; 851 852 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 853 return 0; 854 855 mrvl_flush_rx_queues(dev); 856 mrvl_flush_tx_shadow_queues(dev); 857 mrvl_flow_deinit(dev); 858 mrvl_mtr_deinit(dev); 859 860 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 861 struct pp2_ppio_tc_params *tc_params = 862 &priv->ppio_params.inqs_params.tcs_params[i]; 863 864 if (tc_params->inqs_params) { 865 rte_free(tc_params->inqs_params); 866 tc_params->inqs_params = NULL; 867 } 868 } 869 870 if (priv->cls_tbl) { 871 pp2_cls_tbl_deinit(priv->cls_tbl); 872 priv->cls_tbl = NULL; 873 } 874 875 if (priv->qos_tbl) { 876 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 877 priv->qos_tbl = NULL; 878 } 879 880 mrvl_flush_bpool(dev); 881 mrvl_tm_deinit(dev); 882 883 if (priv->ppio) { 884 pp2_ppio_deinit(priv->ppio); 885 priv->ppio = NULL; 886 } 887 888 /* policer must be released after ppio deinitialization */ 889 if (priv->default_policer) { 890 pp2_cls_plcr_deinit(priv->default_policer); 891 priv->default_policer = NULL; 892 } 893 894 895 if (priv->bpool) { 896 pp2_bpool_deinit(priv->bpool); 897 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 898 priv->bpool = NULL; 899 } 900 901 mrvl_dev_num--; 902 903 if (mrvl_dev_num == 0) { 904 MRVL_LOG(INFO, "Perform MUSDK deinit"); 905 mrvl_deinit_hifs(); 906 mrvl_deinit_pp2(); 907 rte_mvep_deinit(MVEP_MOD_T_PP2); 908 } 909 910 return 0; 911 } 912 913 /** 914 * DPDK callback to retrieve physical link information. 915 * 916 * @param dev 917 * Pointer to Ethernet device structure. 918 * @param wait_to_complete 919 * Wait for request completion (ignored). 920 * 921 * @return 922 * 0 on success, negative error value otherwise. 923 */ 924 static int 925 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 926 { 927 /* 928 * TODO 929 * once MUSDK provides necessary API use it here 930 */ 931 struct mrvl_priv *priv = dev->data->dev_private; 932 struct ethtool_cmd edata; 933 struct ifreq req; 934 int ret, fd, link_up; 935 936 if (!priv->ppio) 937 return -EPERM; 938 939 edata.cmd = ETHTOOL_GSET; 940 941 strcpy(req.ifr_name, dev->data->name); 942 req.ifr_data = (void *)&edata; 943 944 fd = socket(AF_INET, SOCK_DGRAM, 0); 945 if (fd == -1) 946 return -EFAULT; 947 948 ret = ioctl(fd, SIOCETHTOOL, &req); 949 if (ret == -1) { 950 close(fd); 951 return -EFAULT; 952 } 953 954 close(fd); 955 956 switch (ethtool_cmd_speed(&edata)) { 957 case SPEED_10: 958 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M; 959 break; 960 case SPEED_100: 961 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M; 962 break; 963 case SPEED_1000: 964 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; 965 break; 966 case SPEED_10000: 967 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; 968 break; 969 default: 970 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; 971 } 972 973 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : 974 ETH_LINK_HALF_DUPLEX; 975 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : 976 ETH_LINK_FIXED; 977 pp2_ppio_get_link_state(priv->ppio, &link_up); 978 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 979 980 return 0; 981 } 982 983 /** 984 * DPDK callback to enable promiscuous mode. 985 * 986 * @param dev 987 * Pointer to Ethernet device structure. 988 * 989 * @return 990 * 0 on success, negative error value otherwise. 991 */ 992 static int 993 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 994 { 995 struct mrvl_priv *priv = dev->data->dev_private; 996 int ret; 997 998 if (priv->isolated) 999 return -ENOTSUP; 1000 1001 if (!priv->ppio) 1002 return 0; 1003 1004 ret = pp2_ppio_set_promisc(priv->ppio, 1); 1005 if (ret) { 1006 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 1007 return -EAGAIN; 1008 } 1009 1010 return 0; 1011 } 1012 1013 /** 1014 * DPDK callback to enable allmulti mode. 1015 * 1016 * @param dev 1017 * Pointer to Ethernet device structure. 1018 * 1019 * @return 1020 * 0 on success, negative error value otherwise. 1021 */ 1022 static int 1023 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 1024 { 1025 struct mrvl_priv *priv = dev->data->dev_private; 1026 int ret; 1027 1028 if (priv->isolated) 1029 return -ENOTSUP; 1030 1031 if (!priv->ppio) 1032 return 0; 1033 1034 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 1035 if (ret) { 1036 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 1037 return -EAGAIN; 1038 } 1039 1040 return 0; 1041 } 1042 1043 /** 1044 * DPDK callback to disable promiscuous mode. 1045 * 1046 * @param dev 1047 * Pointer to Ethernet device structure. 1048 * 1049 * @return 1050 * 0 on success, negative error value otherwise. 1051 */ 1052 static int 1053 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 1054 { 1055 struct mrvl_priv *priv = dev->data->dev_private; 1056 int ret; 1057 1058 if (priv->isolated) 1059 return -ENOTSUP; 1060 1061 if (!priv->ppio) 1062 return 0; 1063 1064 ret = pp2_ppio_set_promisc(priv->ppio, 0); 1065 if (ret) { 1066 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 1067 return -EAGAIN; 1068 } 1069 1070 return 0; 1071 } 1072 1073 /** 1074 * DPDK callback to disable allmulticast mode. 1075 * 1076 * @param dev 1077 * Pointer to Ethernet device structure. 1078 * 1079 * @return 1080 * 0 on success, negative error value otherwise. 1081 */ 1082 static int 1083 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 1084 { 1085 struct mrvl_priv *priv = dev->data->dev_private; 1086 int ret; 1087 1088 if (priv->isolated) 1089 return -ENOTSUP; 1090 1091 if (!priv->ppio) 1092 return 0; 1093 1094 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 1095 if (ret) { 1096 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 1097 return -EAGAIN; 1098 } 1099 1100 return 0; 1101 } 1102 1103 /** 1104 * DPDK callback to remove a MAC address. 1105 * 1106 * @param dev 1107 * Pointer to Ethernet device structure. 1108 * @param index 1109 * MAC address index. 1110 */ 1111 static void 1112 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 1113 { 1114 struct mrvl_priv *priv = dev->data->dev_private; 1115 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1116 int ret; 1117 1118 if (priv->isolated) 1119 return; 1120 1121 if (!priv->ppio) 1122 return; 1123 1124 ret = pp2_ppio_remove_mac_addr(priv->ppio, 1125 dev->data->mac_addrs[index].addr_bytes); 1126 if (ret) { 1127 rte_ether_format_addr(buf, sizeof(buf), 1128 &dev->data->mac_addrs[index]); 1129 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 1130 } 1131 } 1132 1133 /** 1134 * DPDK callback to add a MAC address. 1135 * 1136 * @param dev 1137 * Pointer to Ethernet device structure. 1138 * @param mac_addr 1139 * MAC address to register. 1140 * @param index 1141 * MAC address index. 1142 * @param vmdq 1143 * VMDq pool index to associate address with (unused). 1144 * 1145 * @return 1146 * 0 on success, negative error value otherwise. 1147 */ 1148 static int 1149 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1150 uint32_t index, uint32_t vmdq __rte_unused) 1151 { 1152 struct mrvl_priv *priv = dev->data->dev_private; 1153 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1154 int ret; 1155 1156 if (priv->isolated) 1157 return -ENOTSUP; 1158 1159 if (!priv->ppio) 1160 return 0; 1161 1162 if (index == 0) 1163 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1164 return -1; 1165 1166 /* 1167 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1168 * parameter uc_filter_max. Maximum number of mc addresses is then 1169 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1170 * 21 respectively. 1171 * 1172 * If more than uc_filter_max uc addresses were added to filter list 1173 * then NIC will switch to promiscuous mode automatically. 1174 * 1175 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1176 * were added to filter list then NIC will switch to all-multicast mode 1177 * automatically. 1178 */ 1179 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1180 if (ret) { 1181 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1182 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1183 return -1; 1184 } 1185 1186 return 0; 1187 } 1188 1189 /** 1190 * DPDK callback to set the primary MAC address. 1191 * 1192 * @param dev 1193 * Pointer to Ethernet device structure. 1194 * @param mac_addr 1195 * MAC address to register. 1196 * 1197 * @return 1198 * 0 on success, negative error value otherwise. 1199 */ 1200 static int 1201 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1202 { 1203 struct mrvl_priv *priv = dev->data->dev_private; 1204 int ret; 1205 1206 if (priv->isolated) 1207 return -ENOTSUP; 1208 1209 if (!priv->ppio) 1210 return 0; 1211 1212 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1213 if (ret) { 1214 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1215 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1216 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1217 } 1218 1219 return ret; 1220 } 1221 1222 /** 1223 * DPDK callback to get device statistics. 1224 * 1225 * @param dev 1226 * Pointer to Ethernet device structure. 1227 * @param stats 1228 * Stats structure output buffer. 1229 * 1230 * @return 1231 * 0 on success, negative error value otherwise. 1232 */ 1233 static int 1234 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1235 { 1236 struct mrvl_priv *priv = dev->data->dev_private; 1237 struct pp2_ppio_statistics ppio_stats; 1238 uint64_t drop_mac = 0; 1239 unsigned int i, idx, ret; 1240 1241 if (!priv->ppio) 1242 return -EPERM; 1243 1244 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1245 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1246 struct pp2_ppio_inq_statistics rx_stats; 1247 1248 if (!rxq) 1249 continue; 1250 1251 idx = rxq->queue_id; 1252 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1253 MRVL_LOG(ERR, 1254 "rx queue %d stats out of range (0 - %d)", 1255 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1256 continue; 1257 } 1258 1259 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1260 priv->rxq_map[idx].tc, 1261 priv->rxq_map[idx].inq, 1262 &rx_stats, 0); 1263 if (unlikely(ret)) { 1264 MRVL_LOG(ERR, 1265 "Failed to update rx queue %d stats", idx); 1266 break; 1267 } 1268 1269 stats->q_ibytes[idx] = rxq->bytes_recv; 1270 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1271 stats->q_errors[idx] = rx_stats.drop_early + 1272 rx_stats.drop_fullq + 1273 rx_stats.drop_bm + 1274 rxq->drop_mac; 1275 stats->ibytes += rxq->bytes_recv; 1276 drop_mac += rxq->drop_mac; 1277 } 1278 1279 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1280 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1281 struct pp2_ppio_outq_statistics tx_stats; 1282 1283 if (!txq) 1284 continue; 1285 1286 idx = txq->queue_id; 1287 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1288 MRVL_LOG(ERR, 1289 "tx queue %d stats out of range (0 - %d)", 1290 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1291 } 1292 1293 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1294 &tx_stats, 0); 1295 if (unlikely(ret)) { 1296 MRVL_LOG(ERR, 1297 "Failed to update tx queue %d stats", idx); 1298 break; 1299 } 1300 1301 stats->q_opackets[idx] = tx_stats.deq_desc; 1302 stats->q_obytes[idx] = txq->bytes_sent; 1303 stats->obytes += txq->bytes_sent; 1304 } 1305 1306 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1307 if (unlikely(ret)) { 1308 MRVL_LOG(ERR, "Failed to update port statistics"); 1309 return ret; 1310 } 1311 1312 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1313 stats->opackets += ppio_stats.tx_packets; 1314 stats->imissed += ppio_stats.rx_fullq_dropped + 1315 ppio_stats.rx_bm_dropped + 1316 ppio_stats.rx_early_dropped + 1317 ppio_stats.rx_fifo_dropped + 1318 ppio_stats.rx_cls_dropped; 1319 stats->ierrors = drop_mac; 1320 1321 return 0; 1322 } 1323 1324 /** 1325 * DPDK callback to clear device statistics. 1326 * 1327 * @param dev 1328 * Pointer to Ethernet device structure. 1329 * 1330 * @return 1331 * 0 on success, negative error value otherwise. 1332 */ 1333 static int 1334 mrvl_stats_reset(struct rte_eth_dev *dev) 1335 { 1336 struct mrvl_priv *priv = dev->data->dev_private; 1337 int i; 1338 1339 if (!priv->ppio) 1340 return 0; 1341 1342 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1343 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1344 1345 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1346 priv->rxq_map[i].inq, NULL, 1); 1347 rxq->bytes_recv = 0; 1348 rxq->drop_mac = 0; 1349 } 1350 1351 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1352 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1353 1354 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1355 txq->bytes_sent = 0; 1356 } 1357 1358 return pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1359 } 1360 1361 /** 1362 * DPDK callback to get extended statistics. 1363 * 1364 * @param dev 1365 * Pointer to Ethernet device structure. 1366 * @param stats 1367 * Pointer to xstats table. 1368 * @param n 1369 * Number of entries in xstats table. 1370 * @return 1371 * Negative value on error, number of read xstats otherwise. 1372 */ 1373 static int 1374 mrvl_xstats_get(struct rte_eth_dev *dev, 1375 struct rte_eth_xstat *stats, unsigned int n) 1376 { 1377 struct mrvl_priv *priv = dev->data->dev_private; 1378 struct pp2_ppio_statistics ppio_stats; 1379 unsigned int i; 1380 1381 if (!stats) 1382 return 0; 1383 1384 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1385 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) { 1386 uint64_t val; 1387 1388 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1389 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1390 mrvl_xstats_tbl[i].offset); 1391 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1392 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1393 mrvl_xstats_tbl[i].offset); 1394 else 1395 return -EINVAL; 1396 1397 stats[i].id = i; 1398 stats[i].value = val; 1399 } 1400 1401 return n; 1402 } 1403 1404 /** 1405 * DPDK callback to reset extended statistics. 1406 * 1407 * @param dev 1408 * Pointer to Ethernet device structure. 1409 * 1410 * @return 1411 * 0 on success, negative error value otherwise. 1412 */ 1413 static int 1414 mrvl_xstats_reset(struct rte_eth_dev *dev) 1415 { 1416 return mrvl_stats_reset(dev); 1417 } 1418 1419 /** 1420 * DPDK callback to get extended statistics names. 1421 * 1422 * @param dev (unused) 1423 * Pointer to Ethernet device structure. 1424 * @param xstats_names 1425 * Pointer to xstats names table. 1426 * @param size 1427 * Size of the xstats names table. 1428 * @return 1429 * Number of read names. 1430 */ 1431 static int 1432 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1433 struct rte_eth_xstat_name *xstats_names, 1434 unsigned int size) 1435 { 1436 unsigned int i; 1437 1438 if (!xstats_names) 1439 return RTE_DIM(mrvl_xstats_tbl); 1440 1441 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1442 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name, 1443 RTE_ETH_XSTATS_NAME_SIZE); 1444 1445 return size; 1446 } 1447 1448 /** 1449 * DPDK callback to get information about the device. 1450 * 1451 * @param dev 1452 * Pointer to Ethernet device structure (unused). 1453 * @param info 1454 * Info structure output buffer. 1455 */ 1456 static int 1457 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 1458 struct rte_eth_dev_info *info) 1459 { 1460 info->speed_capa = ETH_LINK_SPEED_10M | 1461 ETH_LINK_SPEED_100M | 1462 ETH_LINK_SPEED_1G | 1463 ETH_LINK_SPEED_10G; 1464 1465 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1466 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1467 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1468 1469 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1470 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1471 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1472 1473 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1474 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1475 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1476 1477 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1478 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1479 1480 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1481 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1482 1483 info->flow_type_rss_offloads = ETH_RSS_IPV4 | 1484 ETH_RSS_NONFRAG_IPV4_TCP | 1485 ETH_RSS_NONFRAG_IPV4_UDP; 1486 1487 /* By default packets are dropped if no descriptors are available */ 1488 info->default_rxconf.rx_drop_en = 1; 1489 1490 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1491 1492 return 0; 1493 } 1494 1495 /** 1496 * Return supported packet types. 1497 * 1498 * @param dev 1499 * Pointer to Ethernet device structure (unused). 1500 * 1501 * @return 1502 * Const pointer to the table with supported packet types. 1503 */ 1504 static const uint32_t * 1505 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1506 { 1507 static const uint32_t ptypes[] = { 1508 RTE_PTYPE_L2_ETHER, 1509 RTE_PTYPE_L2_ETHER_VLAN, 1510 RTE_PTYPE_L2_ETHER_QINQ, 1511 RTE_PTYPE_L3_IPV4, 1512 RTE_PTYPE_L3_IPV4_EXT, 1513 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1514 RTE_PTYPE_L3_IPV6, 1515 RTE_PTYPE_L3_IPV6_EXT, 1516 RTE_PTYPE_L2_ETHER_ARP, 1517 RTE_PTYPE_L4_TCP, 1518 RTE_PTYPE_L4_UDP 1519 }; 1520 1521 return ptypes; 1522 } 1523 1524 /** 1525 * DPDK callback to get information about specific receive queue. 1526 * 1527 * @param dev 1528 * Pointer to Ethernet device structure. 1529 * @param rx_queue_id 1530 * Receive queue index. 1531 * @param qinfo 1532 * Receive queue information structure. 1533 */ 1534 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1535 struct rte_eth_rxq_info *qinfo) 1536 { 1537 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1538 struct mrvl_priv *priv = dev->data->dev_private; 1539 int inq = priv->rxq_map[rx_queue_id].inq; 1540 int tc = priv->rxq_map[rx_queue_id].tc; 1541 struct pp2_ppio_tc_params *tc_params = 1542 &priv->ppio_params.inqs_params.tcs_params[tc]; 1543 1544 qinfo->mp = q->mp; 1545 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1546 } 1547 1548 /** 1549 * DPDK callback to get information about specific transmit queue. 1550 * 1551 * @param dev 1552 * Pointer to Ethernet device structure. 1553 * @param tx_queue_id 1554 * Transmit queue index. 1555 * @param qinfo 1556 * Transmit queue information structure. 1557 */ 1558 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1559 struct rte_eth_txq_info *qinfo) 1560 { 1561 struct mrvl_priv *priv = dev->data->dev_private; 1562 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1563 1564 qinfo->nb_desc = 1565 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1566 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1567 } 1568 1569 /** 1570 * DPDK callback to Configure a VLAN filter. 1571 * 1572 * @param dev 1573 * Pointer to Ethernet device structure. 1574 * @param vlan_id 1575 * VLAN ID to filter. 1576 * @param on 1577 * Toggle filter. 1578 * 1579 * @return 1580 * 0 on success, negative error value otherwise. 1581 */ 1582 static int 1583 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1584 { 1585 struct mrvl_priv *priv = dev->data->dev_private; 1586 1587 if (priv->isolated) 1588 return -ENOTSUP; 1589 1590 if (!priv->ppio) 1591 return 0; 1592 1593 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1594 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1595 } 1596 1597 /** 1598 * Release buffers to hardware bpool (buffer-pool) 1599 * 1600 * @param rxq 1601 * Receive queue pointer. 1602 * @param num 1603 * Number of buffers to release to bpool. 1604 * 1605 * @return 1606 * 0 on success, negative error value otherwise. 1607 */ 1608 static int 1609 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1610 { 1611 struct buff_release_entry entries[num]; 1612 struct rte_mbuf *mbufs[num]; 1613 int i, ret; 1614 unsigned int core_id; 1615 struct pp2_hif *hif; 1616 struct pp2_bpool *bpool; 1617 1618 core_id = rte_lcore_id(); 1619 if (core_id == LCORE_ID_ANY) 1620 core_id = rte_get_main_lcore(); 1621 1622 hif = mrvl_get_hif(rxq->priv, core_id); 1623 if (!hif) 1624 return -1; 1625 1626 bpool = rxq->priv->bpool; 1627 1628 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1629 if (ret) 1630 return ret; 1631 1632 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1633 cookie_addr_high = 1634 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1635 1636 for (i = 0; i < num; i++) { 1637 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1638 != cookie_addr_high) { 1639 MRVL_LOG(ERR, 1640 "mbuf virtual addr high is out of range " 1641 "0x%x instead of 0x%x\n", 1642 (uint32_t)((uint64_t)mbufs[i] >> 32), 1643 (uint32_t)(cookie_addr_high >> 32)); 1644 goto out; 1645 } 1646 1647 entries[i].buff.addr = 1648 rte_mbuf_data_iova_default(mbufs[i]); 1649 entries[i].buff.cookie = (uintptr_t)mbufs[i]; 1650 entries[i].bpool = bpool; 1651 } 1652 1653 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1654 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1655 1656 if (i != num) 1657 goto out; 1658 1659 return 0; 1660 out: 1661 for (; i < num; i++) 1662 rte_pktmbuf_free(mbufs[i]); 1663 1664 return -1; 1665 } 1666 1667 /** 1668 * DPDK callback to configure the receive queue. 1669 * 1670 * @param dev 1671 * Pointer to Ethernet device structure. 1672 * @param idx 1673 * RX queue index. 1674 * @param desc 1675 * Number of descriptors to configure in queue. 1676 * @param socket 1677 * NUMA socket on which memory must be allocated. 1678 * @param conf 1679 * Thresholds parameters. 1680 * @param mp 1681 * Memory pool for buffer allocations. 1682 * 1683 * @return 1684 * 0 on success, negative error value otherwise. 1685 */ 1686 static int 1687 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1688 unsigned int socket, 1689 const struct rte_eth_rxconf *conf, 1690 struct rte_mempool *mp) 1691 { 1692 struct mrvl_priv *priv = dev->data->dev_private; 1693 struct mrvl_rxq *rxq; 1694 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp); 1695 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1696 int ret, tc, inq; 1697 uint64_t offloads; 1698 1699 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1700 1701 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1702 /* 1703 * Unknown TC mapping, mapping will not have a correct queue. 1704 */ 1705 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1706 idx, priv->ppio_id); 1707 return -EFAULT; 1708 } 1709 1710 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - 1711 MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN; 1712 if (frame_size < max_rx_pkt_len) { 1713 MRVL_LOG(WARNING, 1714 "Mbuf size must be increased to %u bytes to hold up " 1715 "to %u bytes of data.", 1716 buf_size + max_rx_pkt_len - frame_size, 1717 max_rx_pkt_len); 1718 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1719 MRVL_LOG(INFO, "Setting max rx pkt len to %u", 1720 dev->data->dev_conf.rxmode.max_rx_pkt_len); 1721 } 1722 1723 if (dev->data->rx_queues[idx]) { 1724 rte_free(dev->data->rx_queues[idx]); 1725 dev->data->rx_queues[idx] = NULL; 1726 } 1727 1728 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 1729 if (!rxq) 1730 return -ENOMEM; 1731 1732 rxq->priv = priv; 1733 rxq->mp = mp; 1734 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; 1735 rxq->queue_id = idx; 1736 rxq->port_id = dev->data->port_id; 1737 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 1738 1739 tc = priv->rxq_map[rxq->queue_id].tc, 1740 inq = priv->rxq_map[rxq->queue_id].inq; 1741 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 1742 desc; 1743 1744 ret = mrvl_fill_bpool(rxq, desc); 1745 if (ret) { 1746 rte_free(rxq); 1747 return ret; 1748 } 1749 1750 priv->bpool_init_size += desc; 1751 1752 dev->data->rx_queues[idx] = rxq; 1753 1754 return 0; 1755 } 1756 1757 /** 1758 * DPDK callback to release the receive queue. 1759 * 1760 * @param rxq 1761 * Generic receive queue pointer. 1762 */ 1763 static void 1764 mrvl_rx_queue_release(void *rxq) 1765 { 1766 struct mrvl_rxq *q = rxq; 1767 struct pp2_ppio_tc_params *tc_params; 1768 int i, num, tc, inq; 1769 struct pp2_hif *hif; 1770 unsigned int core_id = rte_lcore_id(); 1771 1772 if (core_id == LCORE_ID_ANY) 1773 core_id = rte_get_main_lcore(); 1774 1775 if (!q) 1776 return; 1777 1778 hif = mrvl_get_hif(q->priv, core_id); 1779 1780 if (!hif) 1781 return; 1782 1783 tc = q->priv->rxq_map[q->queue_id].tc; 1784 inq = q->priv->rxq_map[q->queue_id].inq; 1785 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 1786 num = tc_params->inqs_params[inq].size; 1787 for (i = 0; i < num; i++) { 1788 struct pp2_buff_inf inf; 1789 uint64_t addr; 1790 1791 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 1792 addr = cookie_addr_high | inf.cookie; 1793 rte_pktmbuf_free((struct rte_mbuf *)addr); 1794 } 1795 1796 rte_free(q); 1797 } 1798 1799 /** 1800 * DPDK callback to configure the transmit queue. 1801 * 1802 * @param dev 1803 * Pointer to Ethernet device structure. 1804 * @param idx 1805 * Transmit queue index. 1806 * @param desc 1807 * Number of descriptors to configure in the queue. 1808 * @param socket 1809 * NUMA socket on which memory must be allocated. 1810 * @param conf 1811 * Tx queue configuration parameters. 1812 * 1813 * @return 1814 * 0 on success, negative error value otherwise. 1815 */ 1816 static int 1817 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1818 unsigned int socket, 1819 const struct rte_eth_txconf *conf) 1820 { 1821 struct mrvl_priv *priv = dev->data->dev_private; 1822 struct mrvl_txq *txq; 1823 1824 if (dev->data->tx_queues[idx]) { 1825 rte_free(dev->data->tx_queues[idx]); 1826 dev->data->tx_queues[idx] = NULL; 1827 } 1828 1829 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 1830 if (!txq) 1831 return -ENOMEM; 1832 1833 txq->priv = priv; 1834 txq->queue_id = idx; 1835 txq->port_id = dev->data->port_id; 1836 txq->tx_deferred_start = conf->tx_deferred_start; 1837 dev->data->tx_queues[idx] = txq; 1838 1839 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 1840 1841 return 0; 1842 } 1843 1844 /** 1845 * DPDK callback to release the transmit queue. 1846 * 1847 * @param txq 1848 * Generic transmit queue pointer. 1849 */ 1850 static void 1851 mrvl_tx_queue_release(void *txq) 1852 { 1853 struct mrvl_txq *q = txq; 1854 1855 if (!q) 1856 return; 1857 1858 rte_free(q); 1859 } 1860 1861 /** 1862 * DPDK callback to get flow control configuration. 1863 * 1864 * @param dev 1865 * Pointer to Ethernet device structure. 1866 * @param fc_conf 1867 * Pointer to the flow control configuration. 1868 * 1869 * @return 1870 * 0 on success, negative error value otherwise. 1871 */ 1872 static int 1873 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1874 { 1875 struct mrvl_priv *priv = dev->data->dev_private; 1876 int ret, en; 1877 1878 if (!priv) 1879 return -EPERM; 1880 1881 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 1882 if (ret) { 1883 MRVL_LOG(ERR, "Failed to read rx pause state"); 1884 return ret; 1885 } 1886 1887 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; 1888 1889 return 0; 1890 } 1891 1892 /** 1893 * DPDK callback to set flow control configuration. 1894 * 1895 * @param dev 1896 * Pointer to Ethernet device structure. 1897 * @param fc_conf 1898 * Pointer to the flow control configuration. 1899 * 1900 * @return 1901 * 0 on success, negative error value otherwise. 1902 */ 1903 static int 1904 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1905 { 1906 struct mrvl_priv *priv = dev->data->dev_private; 1907 1908 if (!priv) 1909 return -EPERM; 1910 1911 if (fc_conf->high_water || 1912 fc_conf->low_water || 1913 fc_conf->pause_time || 1914 fc_conf->mac_ctrl_frame_fwd || 1915 fc_conf->autoneg) { 1916 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 1917 1918 return -EINVAL; 1919 } 1920 1921 if (fc_conf->mode == RTE_FC_NONE || 1922 fc_conf->mode == RTE_FC_RX_PAUSE) { 1923 int ret, en; 1924 1925 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; 1926 ret = pp2_ppio_set_rx_pause(priv->ppio, en); 1927 if (ret) 1928 MRVL_LOG(ERR, 1929 "Failed to change flowctrl on RX side"); 1930 1931 return ret; 1932 } 1933 1934 return 0; 1935 } 1936 1937 /** 1938 * Update RSS hash configuration 1939 * 1940 * @param dev 1941 * Pointer to Ethernet device structure. 1942 * @param rss_conf 1943 * Pointer to RSS configuration. 1944 * 1945 * @return 1946 * 0 on success, negative error value otherwise. 1947 */ 1948 static int 1949 mrvl_rss_hash_update(struct rte_eth_dev *dev, 1950 struct rte_eth_rss_conf *rss_conf) 1951 { 1952 struct mrvl_priv *priv = dev->data->dev_private; 1953 1954 if (priv->isolated) 1955 return -ENOTSUP; 1956 1957 return mrvl_configure_rss(priv, rss_conf); 1958 } 1959 1960 /** 1961 * DPDK callback to get RSS hash configuration. 1962 * 1963 * @param dev 1964 * Pointer to Ethernet device structure. 1965 * @rss_conf 1966 * Pointer to RSS configuration. 1967 * 1968 * @return 1969 * Always 0. 1970 */ 1971 static int 1972 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 1973 struct rte_eth_rss_conf *rss_conf) 1974 { 1975 struct mrvl_priv *priv = dev->data->dev_private; 1976 enum pp2_ppio_hash_type hash_type = 1977 priv->ppio_params.inqs_params.hash_type; 1978 1979 rss_conf->rss_key = NULL; 1980 1981 if (hash_type == PP2_PPIO_HASH_T_NONE) 1982 rss_conf->rss_hf = 0; 1983 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 1984 rss_conf->rss_hf = ETH_RSS_IPV4; 1985 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 1986 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; 1987 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 1988 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; 1989 1990 return 0; 1991 } 1992 1993 /** 1994 * DPDK callback to get rte_flow callbacks. 1995 * 1996 * @param dev 1997 * Pointer to the device structure. 1998 * @param filer_type 1999 * Flow filter type. 2000 * @param filter_op 2001 * Flow filter operation. 2002 * @param arg 2003 * Pointer to pass the flow ops. 2004 * 2005 * @return 2006 * 0 on success, negative error value otherwise. 2007 */ 2008 static int 2009 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 2010 enum rte_filter_type filter_type, 2011 enum rte_filter_op filter_op, void *arg) 2012 { 2013 switch (filter_type) { 2014 case RTE_ETH_FILTER_GENERIC: 2015 if (filter_op != RTE_ETH_FILTER_GET) 2016 return -EINVAL; 2017 *(const void **)arg = &mrvl_flow_ops; 2018 return 0; 2019 default: 2020 MRVL_LOG(WARNING, "Filter type (%d) not supported", 2021 filter_type); 2022 return -EINVAL; 2023 } 2024 } 2025 2026 /** 2027 * DPDK callback to get rte_mtr callbacks. 2028 * 2029 * @param dev 2030 * Pointer to the device structure. 2031 * @param ops 2032 * Pointer to pass the mtr ops. 2033 * 2034 * @return 2035 * Always 0. 2036 */ 2037 static int 2038 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2039 { 2040 *(const void **)ops = &mrvl_mtr_ops; 2041 2042 return 0; 2043 } 2044 2045 /** 2046 * DPDK callback to get rte_tm callbacks. 2047 * 2048 * @param dev 2049 * Pointer to the device structure. 2050 * @param ops 2051 * Pointer to pass the tm ops. 2052 * 2053 * @return 2054 * Always 0. 2055 */ 2056 static int 2057 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2058 { 2059 *(const void **)ops = &mrvl_tm_ops; 2060 2061 return 0; 2062 } 2063 2064 static const struct eth_dev_ops mrvl_ops = { 2065 .dev_configure = mrvl_dev_configure, 2066 .dev_start = mrvl_dev_start, 2067 .dev_stop = mrvl_dev_stop, 2068 .dev_set_link_up = mrvl_dev_set_link_up, 2069 .dev_set_link_down = mrvl_dev_set_link_down, 2070 .dev_close = mrvl_dev_close, 2071 .link_update = mrvl_link_update, 2072 .promiscuous_enable = mrvl_promiscuous_enable, 2073 .allmulticast_enable = mrvl_allmulticast_enable, 2074 .promiscuous_disable = mrvl_promiscuous_disable, 2075 .allmulticast_disable = mrvl_allmulticast_disable, 2076 .mac_addr_remove = mrvl_mac_addr_remove, 2077 .mac_addr_add = mrvl_mac_addr_add, 2078 .mac_addr_set = mrvl_mac_addr_set, 2079 .mtu_set = mrvl_mtu_set, 2080 .stats_get = mrvl_stats_get, 2081 .stats_reset = mrvl_stats_reset, 2082 .xstats_get = mrvl_xstats_get, 2083 .xstats_reset = mrvl_xstats_reset, 2084 .xstats_get_names = mrvl_xstats_get_names, 2085 .dev_infos_get = mrvl_dev_infos_get, 2086 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 2087 .rxq_info_get = mrvl_rxq_info_get, 2088 .txq_info_get = mrvl_txq_info_get, 2089 .vlan_filter_set = mrvl_vlan_filter_set, 2090 .tx_queue_start = mrvl_tx_queue_start, 2091 .tx_queue_stop = mrvl_tx_queue_stop, 2092 .rx_queue_setup = mrvl_rx_queue_setup, 2093 .rx_queue_release = mrvl_rx_queue_release, 2094 .tx_queue_setup = mrvl_tx_queue_setup, 2095 .tx_queue_release = mrvl_tx_queue_release, 2096 .flow_ctrl_get = mrvl_flow_ctrl_get, 2097 .flow_ctrl_set = mrvl_flow_ctrl_set, 2098 .rss_hash_update = mrvl_rss_hash_update, 2099 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 2100 .filter_ctrl = mrvl_eth_filter_ctrl, 2101 .mtr_ops_get = mrvl_mtr_ops_get, 2102 .tm_ops_get = mrvl_tm_ops_get, 2103 }; 2104 2105 /** 2106 * Return packet type information and l3/l4 offsets. 2107 * 2108 * @param desc 2109 * Pointer to the received packet descriptor. 2110 * @param l3_offset 2111 * l3 packet offset. 2112 * @param l4_offset 2113 * l4 packet offset. 2114 * 2115 * @return 2116 * Packet type information. 2117 */ 2118 static inline uint64_t 2119 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 2120 uint8_t *l3_offset, uint8_t *l4_offset) 2121 { 2122 enum pp2_inq_l3_type l3_type; 2123 enum pp2_inq_l4_type l4_type; 2124 enum pp2_inq_vlan_tag vlan_tag; 2125 uint64_t packet_type; 2126 2127 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 2128 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 2129 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 2130 2131 packet_type = RTE_PTYPE_L2_ETHER; 2132 2133 switch (vlan_tag) { 2134 case PP2_INQ_VLAN_TAG_SINGLE: 2135 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 2136 break; 2137 case PP2_INQ_VLAN_TAG_DOUBLE: 2138 case PP2_INQ_VLAN_TAG_TRIPLE: 2139 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 2140 break; 2141 default: 2142 break; 2143 } 2144 2145 switch (l3_type) { 2146 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 2147 packet_type |= RTE_PTYPE_L3_IPV4; 2148 break; 2149 case PP2_INQ_L3_TYPE_IPV4_OK: 2150 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 2151 break; 2152 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 2153 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 2154 break; 2155 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 2156 packet_type |= RTE_PTYPE_L3_IPV6; 2157 break; 2158 case PP2_INQ_L3_TYPE_IPV6_EXT: 2159 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 2160 break; 2161 case PP2_INQ_L3_TYPE_ARP: 2162 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 2163 /* 2164 * In case of ARP l4_offset is set to wrong value. 2165 * Set it to proper one so that later on mbuf->l3_len can be 2166 * calculated subtracting l4_offset and l3_offset. 2167 */ 2168 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 2169 break; 2170 default: 2171 break; 2172 } 2173 2174 switch (l4_type) { 2175 case PP2_INQ_L4_TYPE_TCP: 2176 packet_type |= RTE_PTYPE_L4_TCP; 2177 break; 2178 case PP2_INQ_L4_TYPE_UDP: 2179 packet_type |= RTE_PTYPE_L4_UDP; 2180 break; 2181 default: 2182 break; 2183 } 2184 2185 return packet_type; 2186 } 2187 2188 /** 2189 * Get offload information from the received packet descriptor. 2190 * 2191 * @param desc 2192 * Pointer to the received packet descriptor. 2193 * 2194 * @return 2195 * Mbuf offload flags. 2196 */ 2197 static inline uint64_t 2198 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) 2199 { 2200 uint64_t flags; 2201 enum pp2_inq_desc_status status; 2202 2203 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2204 if (unlikely(status != PP2_DESC_ERR_OK)) 2205 flags = PKT_RX_IP_CKSUM_BAD; 2206 else 2207 flags = PKT_RX_IP_CKSUM_GOOD; 2208 2209 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2210 if (unlikely(status != PP2_DESC_ERR_OK)) 2211 flags |= PKT_RX_L4_CKSUM_BAD; 2212 else 2213 flags |= PKT_RX_L4_CKSUM_GOOD; 2214 2215 return flags; 2216 } 2217 2218 /** 2219 * DPDK callback for receive. 2220 * 2221 * @param rxq 2222 * Generic pointer to the receive queue. 2223 * @param rx_pkts 2224 * Array to store received packets. 2225 * @param nb_pkts 2226 * Maximum number of packets in array. 2227 * 2228 * @return 2229 * Number of packets successfully received. 2230 */ 2231 static uint16_t 2232 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2233 { 2234 struct mrvl_rxq *q = rxq; 2235 struct pp2_ppio_desc descs[nb_pkts]; 2236 struct pp2_bpool *bpool; 2237 int i, ret, rx_done = 0; 2238 int num; 2239 struct pp2_hif *hif; 2240 unsigned int core_id = rte_lcore_id(); 2241 2242 hif = mrvl_get_hif(q->priv, core_id); 2243 2244 if (unlikely(!q->priv->ppio || !hif)) 2245 return 0; 2246 2247 bpool = q->priv->bpool; 2248 2249 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2250 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2251 if (unlikely(ret < 0)) 2252 return 0; 2253 2254 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2255 2256 for (i = 0; i < nb_pkts; i++) { 2257 struct rte_mbuf *mbuf; 2258 uint8_t l3_offset, l4_offset; 2259 enum pp2_inq_desc_status status; 2260 uint64_t addr; 2261 2262 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2263 struct pp2_ppio_desc *pref_desc; 2264 u64 pref_addr; 2265 2266 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2267 pref_addr = cookie_addr_high | 2268 pp2_ppio_inq_desc_get_cookie(pref_desc); 2269 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2270 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2271 } 2272 2273 addr = cookie_addr_high | 2274 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2275 mbuf = (struct rte_mbuf *)addr; 2276 rte_pktmbuf_reset(mbuf); 2277 2278 /* drop packet in case of mac, overrun or resource error */ 2279 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2280 if (unlikely(status != PP2_DESC_ERR_OK)) { 2281 struct pp2_buff_inf binf = { 2282 .addr = rte_mbuf_data_iova_default(mbuf), 2283 .cookie = (uint64_t)mbuf, 2284 }; 2285 2286 pp2_bpool_put_buff(hif, bpool, &binf); 2287 mrvl_port_bpool_size 2288 [bpool->pp2_id][bpool->id][core_id]++; 2289 q->drop_mac++; 2290 continue; 2291 } 2292 2293 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2294 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2295 mbuf->data_len = mbuf->pkt_len; 2296 mbuf->port = q->port_id; 2297 mbuf->packet_type = 2298 mrvl_desc_to_packet_type_and_offset(&descs[i], 2299 &l3_offset, 2300 &l4_offset); 2301 mbuf->l2_len = l3_offset; 2302 mbuf->l3_len = l4_offset - l3_offset; 2303 2304 if (likely(q->cksum_enabled)) 2305 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); 2306 2307 rx_pkts[rx_done++] = mbuf; 2308 q->bytes_recv += mbuf->pkt_len; 2309 } 2310 2311 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2312 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2313 2314 if (unlikely(num <= q->priv->bpool_min_size || 2315 (!rx_done && num < q->priv->bpool_init_size))) { 2316 mrvl_fill_bpool(q, MRVL_BURST_SIZE); 2317 } else if (unlikely(num > q->priv->bpool_max_size)) { 2318 int i; 2319 int pkt_to_remove = num - q->priv->bpool_init_size; 2320 struct rte_mbuf *mbuf; 2321 struct pp2_buff_inf buff; 2322 2323 for (i = 0; i < pkt_to_remove; i++) { 2324 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2325 if (ret) 2326 break; 2327 mbuf = (struct rte_mbuf *) 2328 (cookie_addr_high | buff.cookie); 2329 rte_pktmbuf_free(mbuf); 2330 } 2331 mrvl_port_bpool_size 2332 [bpool->pp2_id][bpool->id][core_id] -= i; 2333 } 2334 rte_spinlock_unlock(&q->priv->lock); 2335 } 2336 2337 return rx_done; 2338 } 2339 2340 /** 2341 * Prepare offload information. 2342 * 2343 * @param ol_flags 2344 * Offload flags. 2345 * @param packet_type 2346 * Packet type bitfield. 2347 * @param l3_type 2348 * Pointer to the pp2_ouq_l3_type structure. 2349 * @param l4_type 2350 * Pointer to the pp2_outq_l4_type structure. 2351 * @param gen_l3_cksum 2352 * Will be set to 1 in case l3 checksum is computed. 2353 * @param l4_cksum 2354 * Will be set to 1 in case l4 checksum is computed. 2355 * 2356 * @return 2357 * 0 on success, negative error value otherwise. 2358 */ 2359 static inline int 2360 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, 2361 enum pp2_outq_l3_type *l3_type, 2362 enum pp2_outq_l4_type *l4_type, 2363 int *gen_l3_cksum, 2364 int *gen_l4_cksum) 2365 { 2366 /* 2367 * Based on ol_flags prepare information 2368 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2369 * for offloading. 2370 */ 2371 if (ol_flags & PKT_TX_IPV4) { 2372 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2373 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; 2374 } else if (ol_flags & PKT_TX_IPV6) { 2375 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2376 /* no checksum for ipv6 header */ 2377 *gen_l3_cksum = 0; 2378 } else { 2379 /* if something different then stop processing */ 2380 return -1; 2381 } 2382 2383 ol_flags &= PKT_TX_L4_MASK; 2384 if ((packet_type & RTE_PTYPE_L4_TCP) && 2385 ol_flags == PKT_TX_TCP_CKSUM) { 2386 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2387 *gen_l4_cksum = 1; 2388 } else if ((packet_type & RTE_PTYPE_L4_UDP) && 2389 ol_flags == PKT_TX_UDP_CKSUM) { 2390 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2391 *gen_l4_cksum = 1; 2392 } else { 2393 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2394 /* no checksum for other type */ 2395 *gen_l4_cksum = 0; 2396 } 2397 2398 return 0; 2399 } 2400 2401 /** 2402 * Release already sent buffers to bpool (buffer-pool). 2403 * 2404 * @param ppio 2405 * Pointer to the port structure. 2406 * @param hif 2407 * Pointer to the MUSDK hardware interface. 2408 * @param sq 2409 * Pointer to the shadow queue. 2410 * @param qid 2411 * Queue id number. 2412 * @param force 2413 * Force releasing packets. 2414 */ 2415 static inline void 2416 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2417 unsigned int core_id, struct mrvl_shadow_txq *sq, 2418 int qid, int force) 2419 { 2420 struct buff_release_entry *entry; 2421 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2422 int i; 2423 2424 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2425 2426 sq->num_to_release += nb_done; 2427 2428 if (likely(!force && 2429 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2430 return; 2431 2432 nb_done = sq->num_to_release; 2433 sq->num_to_release = 0; 2434 2435 for (i = 0; i < nb_done; i++) { 2436 entry = &sq->ent[sq->tail + num]; 2437 if (unlikely(!entry->buff.addr)) { 2438 MRVL_LOG(ERR, 2439 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2440 sq->tail, (u64)entry->buff.cookie, 2441 (u64)entry->buff.addr); 2442 skip_bufs = 1; 2443 goto skip; 2444 } 2445 2446 if (unlikely(!entry->bpool)) { 2447 struct rte_mbuf *mbuf; 2448 2449 mbuf = (struct rte_mbuf *)entry->buff.cookie; 2450 rte_pktmbuf_free(mbuf); 2451 skip_bufs = 1; 2452 goto skip; 2453 } 2454 2455 mrvl_port_bpool_size 2456 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2457 num++; 2458 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2459 goto skip; 2460 continue; 2461 skip: 2462 if (likely(num)) 2463 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2464 num += skip_bufs; 2465 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2466 sq->size -= num; 2467 num = 0; 2468 skip_bufs = 0; 2469 } 2470 2471 if (likely(num)) { 2472 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2473 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2474 sq->size -= num; 2475 } 2476 } 2477 2478 /** 2479 * DPDK callback for transmit. 2480 * 2481 * @param txq 2482 * Generic pointer transmit queue. 2483 * @param tx_pkts 2484 * Packets to transmit. 2485 * @param nb_pkts 2486 * Number of packets in array. 2487 * 2488 * @return 2489 * Number of packets successfully transmitted. 2490 */ 2491 static uint16_t 2492 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2493 { 2494 struct mrvl_txq *q = txq; 2495 struct mrvl_shadow_txq *sq; 2496 struct pp2_hif *hif; 2497 struct pp2_ppio_desc descs[nb_pkts]; 2498 unsigned int core_id = rte_lcore_id(); 2499 int i, ret, bytes_sent = 0; 2500 uint16_t num, sq_free_size; 2501 uint64_t addr; 2502 2503 hif = mrvl_get_hif(q->priv, core_id); 2504 sq = &q->shadow_txqs[core_id]; 2505 2506 if (unlikely(!q->priv->ppio || !hif)) 2507 return 0; 2508 2509 if (sq->size) 2510 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2511 sq, q->queue_id, 0); 2512 2513 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2514 if (unlikely(nb_pkts > sq_free_size)) 2515 nb_pkts = sq_free_size; 2516 2517 for (i = 0; i < nb_pkts; i++) { 2518 struct rte_mbuf *mbuf = tx_pkts[i]; 2519 int gen_l3_cksum, gen_l4_cksum; 2520 enum pp2_outq_l3_type l3_type; 2521 enum pp2_outq_l4_type l4_type; 2522 2523 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2524 struct rte_mbuf *pref_pkt_hdr; 2525 2526 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2527 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2528 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2529 } 2530 2531 mrvl_fill_shadowq(sq, mbuf); 2532 mrvl_fill_desc(&descs[i], mbuf); 2533 2534 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2535 /* 2536 * in case unsupported ol_flags were passed 2537 * do not update descriptor offload information 2538 */ 2539 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2540 &l3_type, &l4_type, &gen_l3_cksum, 2541 &gen_l4_cksum); 2542 if (unlikely(ret)) 2543 continue; 2544 2545 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2546 mbuf->l2_len, 2547 mbuf->l2_len + mbuf->l3_len, 2548 gen_l3_cksum, gen_l4_cksum); 2549 } 2550 2551 num = nb_pkts; 2552 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2553 /* number of packets that were not sent */ 2554 if (unlikely(num > nb_pkts)) { 2555 for (i = nb_pkts; i < num; i++) { 2556 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2557 MRVL_PP2_TX_SHADOWQ_MASK; 2558 addr = sq->ent[sq->head].buff.cookie; 2559 bytes_sent -= 2560 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2561 } 2562 sq->size -= num - nb_pkts; 2563 } 2564 2565 q->bytes_sent += bytes_sent; 2566 2567 return nb_pkts; 2568 } 2569 2570 /** DPDK callback for S/G transmit. 2571 * 2572 * @param txq 2573 * Generic pointer transmit queue. 2574 * @param tx_pkts 2575 * Packets to transmit. 2576 * @param nb_pkts 2577 * Number of packets in array. 2578 * 2579 * @return 2580 * Number of packets successfully transmitted. 2581 */ 2582 static uint16_t 2583 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 2584 uint16_t nb_pkts) 2585 { 2586 struct mrvl_txq *q = txq; 2587 struct mrvl_shadow_txq *sq; 2588 struct pp2_hif *hif; 2589 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS]; 2590 struct pp2_ppio_sg_pkts pkts; 2591 uint8_t frags[nb_pkts]; 2592 unsigned int core_id = rte_lcore_id(); 2593 int i, j, ret, bytes_sent = 0; 2594 int tail, tail_first; 2595 uint16_t num, sq_free_size; 2596 uint16_t nb_segs, total_descs = 0; 2597 uint64_t addr; 2598 2599 hif = mrvl_get_hif(q->priv, core_id); 2600 sq = &q->shadow_txqs[core_id]; 2601 pkts.frags = frags; 2602 pkts.num = 0; 2603 2604 if (unlikely(!q->priv->ppio || !hif)) 2605 return 0; 2606 2607 if (sq->size) 2608 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2609 sq, q->queue_id, 0); 2610 2611 /* Save shadow queue free size */ 2612 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2613 2614 tail = 0; 2615 for (i = 0; i < nb_pkts; i++) { 2616 struct rte_mbuf *mbuf = tx_pkts[i]; 2617 struct rte_mbuf *seg = NULL; 2618 int gen_l3_cksum, gen_l4_cksum; 2619 enum pp2_outq_l3_type l3_type; 2620 enum pp2_outq_l4_type l4_type; 2621 2622 nb_segs = mbuf->nb_segs; 2623 tail_first = tail; 2624 total_descs += nb_segs; 2625 2626 /* 2627 * Check if total_descs does not exceed 2628 * shadow queue free size 2629 */ 2630 if (unlikely(total_descs > sq_free_size)) { 2631 total_descs -= nb_segs; 2632 break; 2633 } 2634 2635 /* Check if nb_segs does not exceed the max nb of desc per 2636 * fragmented packet 2637 */ 2638 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) { 2639 total_descs -= nb_segs; 2640 RTE_LOG(ERR, PMD, 2641 "Too many segments. Packet won't be sent.\n"); 2642 break; 2643 } 2644 2645 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2646 struct rte_mbuf *pref_pkt_hdr; 2647 2648 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2649 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2650 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2651 } 2652 2653 pkts.frags[pkts.num] = nb_segs; 2654 pkts.num++; 2655 2656 seg = mbuf; 2657 for (j = 0; j < nb_segs - 1; j++) { 2658 /* For the subsequent segments, set shadow queue 2659 * buffer to NULL 2660 */ 2661 mrvl_fill_shadowq(sq, NULL); 2662 mrvl_fill_desc(&descs[tail], seg); 2663 2664 tail++; 2665 seg = seg->next; 2666 } 2667 /* Put first mbuf info in last shadow queue entry */ 2668 mrvl_fill_shadowq(sq, mbuf); 2669 /* Update descriptor with last segment */ 2670 mrvl_fill_desc(&descs[tail++], seg); 2671 2672 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2673 /* In case unsupported ol_flags were passed 2674 * do not update descriptor offload information 2675 */ 2676 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2677 &l3_type, &l4_type, &gen_l3_cksum, 2678 &gen_l4_cksum); 2679 if (unlikely(ret)) 2680 continue; 2681 2682 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, 2683 l4_type, mbuf->l2_len, 2684 mbuf->l2_len + mbuf->l3_len, 2685 gen_l3_cksum, gen_l4_cksum); 2686 } 2687 2688 num = total_descs; 2689 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs, 2690 &total_descs, &pkts); 2691 /* number of packets that were not sent */ 2692 if (unlikely(num > total_descs)) { 2693 for (i = total_descs; i < num; i++) { 2694 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2695 MRVL_PP2_TX_SHADOWQ_MASK; 2696 2697 addr = sq->ent[sq->head].buff.cookie; 2698 if (addr) 2699 bytes_sent -= 2700 rte_pktmbuf_pkt_len((struct rte_mbuf *) 2701 (cookie_addr_high | addr)); 2702 } 2703 sq->size -= num - total_descs; 2704 nb_pkts = pkts.num; 2705 } 2706 2707 q->bytes_sent += bytes_sent; 2708 2709 return nb_pkts; 2710 } 2711 2712 /** 2713 * Initialize packet processor. 2714 * 2715 * @return 2716 * 0 on success, negative error value otherwise. 2717 */ 2718 static int 2719 mrvl_init_pp2(void) 2720 { 2721 struct pp2_init_params init_params; 2722 2723 memset(&init_params, 0, sizeof(init_params)); 2724 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 2725 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 2726 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 2727 2728 return pp2_init(&init_params); 2729 } 2730 2731 /** 2732 * Deinitialize packet processor. 2733 * 2734 * @return 2735 * 0 on success, negative error value otherwise. 2736 */ 2737 static void 2738 mrvl_deinit_pp2(void) 2739 { 2740 pp2_deinit(); 2741 } 2742 2743 /** 2744 * Create private device structure. 2745 * 2746 * @param dev_name 2747 * Pointer to the port name passed in the initialization parameters. 2748 * 2749 * @return 2750 * Pointer to the newly allocated private device structure. 2751 */ 2752 static struct mrvl_priv * 2753 mrvl_priv_create(const char *dev_name) 2754 { 2755 struct pp2_bpool_params bpool_params; 2756 char match[MRVL_MATCH_LEN]; 2757 struct mrvl_priv *priv; 2758 int ret, bpool_bit; 2759 2760 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 2761 if (!priv) 2762 return NULL; 2763 2764 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 2765 &priv->pp_id, &priv->ppio_id); 2766 if (ret) 2767 goto out_free_priv; 2768 2769 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 2770 PP2_BPOOL_NUM_POOLS); 2771 if (bpool_bit < 0) 2772 goto out_free_priv; 2773 priv->bpool_bit = bpool_bit; 2774 2775 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 2776 priv->bpool_bit); 2777 memset(&bpool_params, 0, sizeof(bpool_params)); 2778 bpool_params.match = match; 2779 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 2780 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 2781 if (ret) 2782 goto out_clear_bpool_bit; 2783 2784 priv->ppio_params.type = PP2_PPIO_T_NIC; 2785 rte_spinlock_init(&priv->lock); 2786 2787 return priv; 2788 out_clear_bpool_bit: 2789 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2790 out_free_priv: 2791 rte_free(priv); 2792 return NULL; 2793 } 2794 2795 /** 2796 * Create device representing Ethernet port. 2797 * 2798 * @param name 2799 * Pointer to the port's name. 2800 * 2801 * @return 2802 * 0 on success, negative error value otherwise. 2803 */ 2804 static int 2805 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 2806 { 2807 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 2808 struct rte_eth_dev *eth_dev; 2809 struct mrvl_priv *priv; 2810 struct ifreq req; 2811 2812 eth_dev = rte_eth_dev_allocate(name); 2813 if (!eth_dev) 2814 return -ENOMEM; 2815 2816 priv = mrvl_priv_create(name); 2817 if (!priv) { 2818 ret = -ENOMEM; 2819 goto out_free; 2820 } 2821 eth_dev->data->dev_private = priv; 2822 2823 eth_dev->data->mac_addrs = 2824 rte_zmalloc("mac_addrs", 2825 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 2826 if (!eth_dev->data->mac_addrs) { 2827 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 2828 ret = -ENOMEM; 2829 goto out_free; 2830 } 2831 2832 memset(&req, 0, sizeof(req)); 2833 strcpy(req.ifr_name, name); 2834 ret = ioctl(fd, SIOCGIFHWADDR, &req); 2835 if (ret) 2836 goto out_free; 2837 2838 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 2839 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN); 2840 2841 eth_dev->device = &vdev->device; 2842 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 2843 mrvl_set_tx_function(eth_dev); 2844 eth_dev->dev_ops = &mrvl_ops; 2845 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2846 2847 rte_eth_dev_probing_finish(eth_dev); 2848 return 0; 2849 out_free: 2850 rte_eth_dev_release_port(eth_dev); 2851 2852 return ret; 2853 } 2854 2855 /** 2856 * Callback used by rte_kvargs_process() during argument parsing. 2857 * 2858 * @param key 2859 * Pointer to the parsed key (unused). 2860 * @param value 2861 * Pointer to the parsed value. 2862 * @param extra_args 2863 * Pointer to the extra arguments which contains address of the 2864 * table of pointers to parsed interface names. 2865 * 2866 * @return 2867 * Always 0. 2868 */ 2869 static int 2870 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 2871 void *extra_args) 2872 { 2873 struct mrvl_ifnames *ifnames = extra_args; 2874 2875 ifnames->names[ifnames->idx++] = value; 2876 2877 return 0; 2878 } 2879 2880 /** 2881 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 2882 */ 2883 static void 2884 mrvl_deinit_hifs(void) 2885 { 2886 int i; 2887 2888 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 2889 if (hifs[i]) 2890 pp2_hif_deinit(hifs[i]); 2891 } 2892 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 2893 memset(hifs, 0, sizeof(hifs)); 2894 } 2895 2896 /** 2897 * DPDK callback to register the virtual device. 2898 * 2899 * @param vdev 2900 * Pointer to the virtual device. 2901 * 2902 * @return 2903 * 0 on success, negative error value otherwise. 2904 */ 2905 static int 2906 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 2907 { 2908 struct rte_kvargs *kvlist; 2909 struct mrvl_ifnames ifnames; 2910 int ret = -EINVAL; 2911 uint32_t i, ifnum, cfgnum; 2912 const char *params; 2913 2914 params = rte_vdev_device_args(vdev); 2915 if (!params) 2916 return -EINVAL; 2917 2918 kvlist = rte_kvargs_parse(params, valid_args); 2919 if (!kvlist) 2920 return -EINVAL; 2921 2922 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 2923 if (ifnum > RTE_DIM(ifnames.names)) 2924 goto out_free_kvlist; 2925 2926 ifnames.idx = 0; 2927 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 2928 mrvl_get_ifnames, &ifnames); 2929 2930 2931 /* 2932 * The below system initialization should be done only once, 2933 * on the first provided configuration file 2934 */ 2935 if (!mrvl_qos_cfg) { 2936 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 2937 MRVL_LOG(INFO, "Parsing config file!"); 2938 if (cfgnum > 1) { 2939 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 2940 goto out_free_kvlist; 2941 } else if (cfgnum == 1) { 2942 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 2943 mrvl_get_qoscfg, &mrvl_qos_cfg); 2944 } 2945 } 2946 2947 if (mrvl_dev_num) 2948 goto init_devices; 2949 2950 MRVL_LOG(INFO, "Perform MUSDK initializations"); 2951 2952 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 2953 if (ret) 2954 goto out_free_kvlist; 2955 2956 ret = mrvl_init_pp2(); 2957 if (ret) { 2958 MRVL_LOG(ERR, "Failed to init PP!"); 2959 rte_mvep_deinit(MVEP_MOD_T_PP2); 2960 goto out_free_kvlist; 2961 } 2962 2963 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 2964 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 2965 2966 mrvl_lcore_first = RTE_MAX_LCORE; 2967 mrvl_lcore_last = 0; 2968 2969 init_devices: 2970 for (i = 0; i < ifnum; i++) { 2971 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 2972 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 2973 if (ret) 2974 goto out_cleanup; 2975 mrvl_dev_num++; 2976 } 2977 2978 rte_kvargs_free(kvlist); 2979 2980 return 0; 2981 out_cleanup: 2982 rte_pmd_mrvl_remove(vdev); 2983 2984 out_free_kvlist: 2985 rte_kvargs_free(kvlist); 2986 2987 return ret; 2988 } 2989 2990 /** 2991 * DPDK callback to remove virtual device. 2992 * 2993 * @param vdev 2994 * Pointer to the removed virtual device. 2995 * 2996 * @return 2997 * 0 on success, negative error value otherwise. 2998 */ 2999 static int 3000 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 3001 { 3002 uint16_t port_id; 3003 int ret = 0; 3004 3005 RTE_ETH_FOREACH_DEV(port_id) { 3006 if (rte_eth_devices[port_id].device != &vdev->device) 3007 continue; 3008 ret |= rte_eth_dev_close(port_id); 3009 } 3010 3011 return ret == 0 ? 0 : -EIO; 3012 } 3013 3014 static struct rte_vdev_driver pmd_mrvl_drv = { 3015 .probe = rte_pmd_mrvl_probe, 3016 .remove = rte_pmd_mrvl_remove, 3017 }; 3018 3019 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 3020 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 3021 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE); 3022