1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Marvell International Ltd. 3 * Copyright(c) 2017-2021 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_string_fns.h> 8 #include <ethdev_driver.h> 9 #include <rte_kvargs.h> 10 #include <rte_log.h> 11 #include <rte_malloc.h> 12 #include <bus_vdev_driver.h> 13 14 #include <fcntl.h> 15 #include <linux/ethtool.h> 16 #include <linux/sockios.h> 17 #include <net/if.h> 18 #include <net/if_arp.h> 19 #include <sys/ioctl.h> 20 #include <sys/socket.h> 21 #include <sys/stat.h> 22 #include <sys/types.h> 23 24 #include <rte_mvep_common.h> 25 #include "mrvl_ethdev.h" 26 #include "mrvl_qos.h" 27 #include "mrvl_flow.h" 28 #include "mrvl_mtr.h" 29 #include "mrvl_tm.h" 30 31 /* bitmask with reserved hifs */ 32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 33 /* bitmask with reserved bpools */ 34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 35 /* bitmask with reserved kernel RSS tables */ 36 #define MRVL_MUSDK_RSS_RESERVED 0x0F 37 /* maximum number of available hifs */ 38 #define MRVL_MUSDK_HIFS_MAX 9 39 40 /* prefetch shift */ 41 #define MRVL_MUSDK_PREFETCH_SHIFT 2 42 43 /* TCAM has 25 entries reserved for uc/mc filter entries 44 * + 1 for primary mac address 45 */ 46 #define MRVL_MAC_ADDRS_MAX (1 + 25) 47 #define MRVL_MATCH_LEN 16 48 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 49 /* Maximum allowable packet size */ 50 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 51 52 #define MRVL_IFACE_NAME_ARG "iface" 53 #define MRVL_CFG_ARG "cfg" 54 55 #define MRVL_ARP_LENGTH 28 56 57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000 59 60 /** Port Rx offload capabilities */ 61 #define MRVL_RX_OFFLOADS (RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \ 62 RTE_ETH_RX_OFFLOAD_CHECKSUM) 63 64 /** Port Tx offloads capabilities */ 65 #define MRVL_TX_OFFLOAD_CHECKSUM (RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \ 66 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \ 67 RTE_ETH_TX_OFFLOAD_TCP_CKSUM) 68 #define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \ 69 RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 70 71 #define MRVL_TX_PKT_OFFLOADS (RTE_MBUF_F_TX_IP_CKSUM | \ 72 RTE_MBUF_F_TX_TCP_CKSUM | \ 73 RTE_MBUF_F_TX_UDP_CKSUM) 74 75 static const char * const valid_args[] = { 76 MRVL_IFACE_NAME_ARG, 77 MRVL_CFG_ARG, 78 NULL 79 }; 80 81 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 82 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 83 static int used_bpools[PP2_NUM_PKT_PROC] = { 84 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 85 }; 86 87 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 88 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 89 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 90 static int dummy_pool_id[PP2_NUM_PKT_PROC]; 91 struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0}; 92 93 struct mrvl_ifnames { 94 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 95 int idx; 96 }; 97 98 /* 99 * To use buffer harvesting based on loopback port shadow queue structure 100 * was introduced for buffers information bookkeeping. 101 * 102 * Before sending the packet, related buffer information (pp2_buff_inf) is 103 * stored in shadow queue. After packet is transmitted no longer used 104 * packet buffer is released back to it's original hardware pool, 105 * on condition it originated from interface. 106 * In case it was generated by application itself i.e: mbuf->port field is 107 * 0xff then its released to software mempool. 108 */ 109 struct mrvl_shadow_txq { 110 int head; /* write index - used when sending buffers */ 111 int tail; /* read index - used when releasing buffers */ 112 u16 size; /* queue occupied size */ 113 u16 num_to_release; /* number of descriptors sent, that can be 114 * released 115 */ 116 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 117 }; 118 119 struct mrvl_rxq { 120 struct mrvl_priv *priv; 121 struct rte_mempool *mp; 122 int queue_id; 123 int port_id; 124 int cksum_enabled; 125 uint64_t bytes_recv; 126 uint64_t drop_mac; 127 }; 128 129 struct mrvl_txq { 130 struct mrvl_priv *priv; 131 int queue_id; 132 int port_id; 133 uint64_t bytes_sent; 134 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 135 int tx_deferred_start; 136 }; 137 138 static int mrvl_lcore_first; 139 static int mrvl_lcore_last; 140 static int mrvl_dev_num; 141 142 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 143 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 144 struct pp2_hif *hif, unsigned int core_id, 145 struct mrvl_shadow_txq *sq, int qid, int force); 146 147 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 148 uint16_t nb_pkts); 149 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 150 uint16_t nb_pkts); 151 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); 152 static void mrvl_deinit_pp2(void); 153 static void mrvl_deinit_hifs(void); 154 155 static int 156 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 157 uint32_t index, uint32_t vmdq __rte_unused); 158 static int 159 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 160 static int 161 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 162 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev); 163 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev); 164 static int 165 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 166 167 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 168 #name, offsetof(struct pp2_ppio_statistics, name), \ 169 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 170 } 171 172 /* Table with xstats data */ 173 static struct { 174 const char *name; 175 unsigned int offset; 176 unsigned int size; 177 } mrvl_xstats_tbl[] = { 178 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 179 MRVL_XSTATS_TBL_ENTRY(rx_packets), 180 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 181 MRVL_XSTATS_TBL_ENTRY(rx_errors), 182 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 183 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 184 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 185 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 186 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 187 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 188 MRVL_XSTATS_TBL_ENTRY(tx_packets), 189 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 190 MRVL_XSTATS_TBL_ENTRY(tx_errors) 191 }; 192 193 static inline int 194 mrvl_reserve_bit(int *bitmap, int max) 195 { 196 int n = sizeof(*bitmap) * 8 - rte_clz32(*bitmap); 197 198 if (n >= max) 199 return -1; 200 201 *bitmap |= 1 << n; 202 203 return n; 204 } 205 206 static int 207 mrvl_pp2_fixup_init(void) 208 { 209 struct pp2_bpool_params bpool_params; 210 char name[15]; 211 int err, i; 212 213 memset(dummy_pool, 0, sizeof(dummy_pool)); 214 for (i = 0; i < pp2_get_num_inst(); i++) { 215 dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i], 216 PP2_BPOOL_NUM_POOLS); 217 if (dummy_pool_id[i] < 0) { 218 MRVL_LOG(ERR, "Can't find free pool\n"); 219 return -1; 220 } 221 222 memset(name, 0, sizeof(name)); 223 snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]); 224 memset(&bpool_params, 0, sizeof(bpool_params)); 225 bpool_params.match = name; 226 bpool_params.buff_len = MRVL_PKT_OFFS; 227 bpool_params.dummy_short_pool = 1; 228 err = pp2_bpool_init(&bpool_params, &dummy_pool[i]); 229 if (err != 0 || !dummy_pool[i]) { 230 MRVL_LOG(ERR, "BPool init failed!\n"); 231 used_bpools[i] &= ~(1 << dummy_pool_id[i]); 232 return -1; 233 } 234 } 235 236 return 0; 237 } 238 239 /** 240 * Initialize packet processor. 241 * 242 * @return 243 * 0 on success, negative error value otherwise. 244 */ 245 static int 246 mrvl_init_pp2(void) 247 { 248 struct pp2_init_params init_params; 249 int err; 250 251 memset(&init_params, 0, sizeof(init_params)); 252 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 253 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 254 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 255 if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) 256 memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, 257 sizeof(struct pp2_parse_udfs)); 258 err = pp2_init(&init_params); 259 if (err != 0) { 260 MRVL_LOG(ERR, "PP2 init failed"); 261 return -1; 262 } 263 264 err = mrvl_pp2_fixup_init(); 265 if (err != 0) { 266 MRVL_LOG(ERR, "PP2 fixup init failed"); 267 return -1; 268 } 269 270 return 0; 271 } 272 273 static void 274 mrvl_pp2_fixup_deinit(void) 275 { 276 int i; 277 278 for (i = 0; i < PP2_NUM_PKT_PROC; i++) { 279 if (!dummy_pool[i]) 280 continue; 281 pp2_bpool_deinit(dummy_pool[i]); 282 used_bpools[i] &= ~(1 << dummy_pool_id[i]); 283 } 284 } 285 286 /** 287 * Deinitialize packet processor. 288 * 289 * @return 290 * 0 on success, negative error value otherwise. 291 */ 292 static void 293 mrvl_deinit_pp2(void) 294 { 295 mrvl_pp2_fixup_deinit(); 296 pp2_deinit(); 297 } 298 299 static inline void 300 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) 301 { 302 sq->ent[sq->head].buff.cookie = (uint64_t)buf; 303 sq->ent[sq->head].buff.addr = buf ? 304 rte_mbuf_data_iova_default(buf) : 0; 305 306 sq->ent[sq->head].bpool = 307 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS || 308 buf->refcnt > 1)) ? NULL : 309 mrvl_port_to_bpool_lookup[buf->port]; 310 311 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 312 sq->size++; 313 } 314 315 /** 316 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 317 */ 318 static void 319 mrvl_deinit_hifs(void) 320 { 321 int i; 322 323 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 324 if (hifs[i]) 325 pp2_hif_deinit(hifs[i]); 326 } 327 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 328 memset(hifs, 0, sizeof(hifs)); 329 } 330 331 static inline void 332 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf) 333 { 334 pp2_ppio_outq_desc_reset(desc); 335 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf)); 336 pp2_ppio_outq_desc_set_pkt_offset(desc, 0); 337 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf)); 338 } 339 340 static inline int 341 mrvl_get_bpool_size(int pp2_id, int pool_id) 342 { 343 int i; 344 int size = 0; 345 346 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 347 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 348 349 return size; 350 } 351 352 static int 353 mrvl_init_hif(int core_id) 354 { 355 struct pp2_hif_params params; 356 char match[MRVL_MATCH_LEN]; 357 int ret; 358 359 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 360 if (ret < 0) { 361 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 362 return ret; 363 } 364 365 snprintf(match, sizeof(match), "hif-%d", ret); 366 memset(¶ms, 0, sizeof(params)); 367 params.match = match; 368 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 369 ret = pp2_hif_init(¶ms, &hifs[core_id]); 370 if (ret) { 371 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 372 return ret; 373 } 374 375 return 0; 376 } 377 378 static inline struct pp2_hif* 379 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 380 { 381 int ret; 382 383 if (likely(hifs[core_id] != NULL)) 384 return hifs[core_id]; 385 386 rte_spinlock_lock(&priv->lock); 387 388 ret = mrvl_init_hif(core_id); 389 if (ret < 0) { 390 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 391 goto out; 392 } 393 394 if (core_id < mrvl_lcore_first) 395 mrvl_lcore_first = core_id; 396 397 if (core_id > mrvl_lcore_last) 398 mrvl_lcore_last = core_id; 399 out: 400 rte_spinlock_unlock(&priv->lock); 401 402 return hifs[core_id]; 403 } 404 405 /** 406 * Set tx burst function according to offload flag 407 * 408 * @param dev 409 * Pointer to Ethernet device structure. 410 */ 411 static void 412 mrvl_set_tx_function(struct rte_eth_dev *dev) 413 { 414 struct mrvl_priv *priv = dev->data->dev_private; 415 416 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 417 if (priv->multiseg) { 418 MRVL_LOG(INFO, "Using multi-segment tx callback"); 419 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst; 420 } else { 421 MRVL_LOG(INFO, "Using single-segment tx callback"); 422 dev->tx_pkt_burst = mrvl_tx_pkt_burst; 423 } 424 } 425 426 /** 427 * Configure rss based on dpdk rss configuration. 428 * 429 * @param priv 430 * Pointer to private structure. 431 * @param rss_conf 432 * Pointer to RSS configuration. 433 * 434 * @return 435 * 0 on success, negative error value otherwise. 436 */ 437 static int 438 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 439 { 440 if (rss_conf->rss_key) 441 MRVL_LOG(WARNING, "Changing hash key is not supported"); 442 443 if (rss_conf->rss_hf == 0) { 444 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 445 } else if (rss_conf->rss_hf & RTE_ETH_RSS_IPV4) { 446 priv->ppio_params.inqs_params.hash_type = 447 PP2_PPIO_HASH_T_2_TUPLE; 448 } else if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { 449 priv->ppio_params.inqs_params.hash_type = 450 PP2_PPIO_HASH_T_5_TUPLE; 451 priv->rss_hf_tcp = 1; 452 } else if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { 453 priv->ppio_params.inqs_params.hash_type = 454 PP2_PPIO_HASH_T_5_TUPLE; 455 priv->rss_hf_tcp = 0; 456 } else { 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 /** 464 * Ethernet device configuration. 465 * 466 * Prepare the driver for a given number of TX and RX queues and 467 * configure RSS. 468 * 469 * @param dev 470 * Pointer to Ethernet device structure. 471 * 472 * @return 473 * 0 on success, negative error value otherwise. 474 */ 475 static int 476 mrvl_dev_configure(struct rte_eth_dev *dev) 477 { 478 struct mrvl_priv *priv = dev->data->dev_private; 479 int ret; 480 481 if (priv->ppio) { 482 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 483 return -EINVAL; 484 } 485 486 if (dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_NONE && 487 dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_RSS) { 488 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 489 dev->data->dev_conf.rxmode.mq_mode); 490 return -EINVAL; 491 } 492 493 if (dev->data->dev_conf.rxmode.mtu > priv->max_mtu) { 494 MRVL_LOG(ERR, "MTU %u is larger than max_mtu %u\n", 495 dev->data->dev_conf.rxmode.mtu, 496 priv->max_mtu); 497 return -EINVAL; 498 } 499 500 if (dev->data->dev_conf.txmode.offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 501 priv->multiseg = 1; 502 503 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 504 dev->data->nb_rx_queues); 505 if (ret < 0) 506 return ret; 507 508 ret = mrvl_configure_txqs(priv, dev->data->port_id, 509 dev->data->nb_tx_queues); 510 if (ret < 0) 511 return ret; 512 513 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 514 priv->ppio_params.maintain_stats = 1; 515 priv->nb_rx_queues = dev->data->nb_rx_queues; 516 517 ret = mrvl_tm_init(dev); 518 if (ret < 0) 519 return ret; 520 521 if (dev->data->nb_rx_queues == 1 && 522 dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) { 523 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 524 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 525 priv->configured = 1; 526 return 0; 527 } 528 529 ret = mrvl_configure_rss(priv, 530 &dev->data->dev_conf.rx_adv_conf.rss_conf); 531 if (ret < 0) 532 return ret; 533 534 priv->configured = 1; 535 536 return 0; 537 } 538 539 /** 540 * DPDK callback to change the MTU. 541 * 542 * Setting the MTU affects hardware MRU (packets larger than the MRU 543 * will be dropped). 544 * 545 * @param dev 546 * Pointer to Ethernet device structure. 547 * @param mtu 548 * New MTU. 549 * 550 * @return 551 * 0 on success, negative error value otherwise. 552 */ 553 static int 554 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 555 { 556 struct mrvl_priv *priv = dev->data->dev_private; 557 uint16_t mru; 558 uint16_t mbuf_data_size = 0; /* SW buffer size */ 559 int ret; 560 561 mru = MRVL_PP2_MTU_TO_MRU(mtu); 562 /* 563 * min_rx_buf_size is equal to mbuf data size 564 * if pmd didn't set it differently 565 */ 566 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 567 /* Prevent PMD from: 568 * - setting mru greater than the mbuf size resulting in 569 * hw and sw buffer size mismatch 570 * - setting mtu that requires the support of scattered packets 571 * when this feature has not been enabled/supported so far 572 * (TODO check scattered_rx flag here once scattered RX is supported). 573 */ 574 if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) { 575 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS; 576 mtu = MRVL_PP2_MRU_TO_MTU(mru); 577 MRVL_LOG(WARNING, "MTU too big, max MTU possible limited " 578 "by current mbuf size: %u. Set MTU to %u, MRU to %u", 579 mbuf_data_size, mtu, mru); 580 } 581 582 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) { 583 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru); 584 return -EINVAL; 585 } 586 587 if (!priv->ppio) 588 return 0; 589 590 ret = pp2_ppio_set_mru(priv->ppio, mru); 591 if (ret) { 592 MRVL_LOG(ERR, "Failed to change MRU"); 593 return ret; 594 } 595 596 ret = pp2_ppio_set_mtu(priv->ppio, mtu); 597 if (ret) { 598 MRVL_LOG(ERR, "Failed to change MTU"); 599 return ret; 600 } 601 602 return 0; 603 } 604 605 /** 606 * DPDK callback to bring the link up. 607 * 608 * @param dev 609 * Pointer to Ethernet device structure. 610 * 611 * @return 612 * 0 on success, negative error value otherwise. 613 */ 614 static int 615 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 616 { 617 struct mrvl_priv *priv = dev->data->dev_private; 618 int ret; 619 620 if (!priv->ppio) { 621 dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 622 return 0; 623 } 624 625 ret = pp2_ppio_enable(priv->ppio); 626 if (ret) 627 return ret; 628 629 /* 630 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 631 * as pp2_ppio_enable() changes port->t_mode from default 0 to 632 * PP2_TRAFFIC_INGRESS_EGRESS. 633 * 634 * Set mtu to default DPDK value here. 635 */ 636 ret = mrvl_mtu_set(dev, dev->data->mtu); 637 if (ret) { 638 pp2_ppio_disable(priv->ppio); 639 return ret; 640 } 641 642 dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 643 return 0; 644 } 645 646 /** 647 * DPDK callback to bring the link down. 648 * 649 * @param dev 650 * Pointer to Ethernet device structure. 651 * 652 * @return 653 * 0 on success, negative error value otherwise. 654 */ 655 static int 656 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 657 { 658 struct mrvl_priv *priv = dev->data->dev_private; 659 int ret; 660 661 if (!priv->ppio) { 662 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 663 return 0; 664 } 665 ret = pp2_ppio_disable(priv->ppio); 666 if (ret) 667 return ret; 668 669 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 670 return 0; 671 } 672 673 /** 674 * DPDK callback to start tx queue. 675 * 676 * @param dev 677 * Pointer to Ethernet device structure. 678 * @param queue_id 679 * Transmit queue index. 680 * 681 * @return 682 * 0 on success, negative error value otherwise. 683 */ 684 static int 685 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 686 { 687 struct mrvl_priv *priv = dev->data->dev_private; 688 int ret; 689 690 if (!priv) 691 return -EPERM; 692 693 /* passing 1 enables given tx queue */ 694 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 695 if (ret) { 696 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 697 return ret; 698 } 699 700 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 701 702 return 0; 703 } 704 705 /** 706 * DPDK callback to stop tx queue. 707 * 708 * @param dev 709 * Pointer to Ethernet device structure. 710 * @param queue_id 711 * Transmit queue index. 712 * 713 * @return 714 * 0 on success, negative error value otherwise. 715 */ 716 static int 717 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 718 { 719 struct mrvl_priv *priv = dev->data->dev_private; 720 int ret; 721 722 if (!priv->ppio) 723 return -EPERM; 724 725 /* passing 0 disables given tx queue */ 726 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 727 if (ret) { 728 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 729 return ret; 730 } 731 732 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 733 734 return 0; 735 } 736 737 /** 738 * Populate VLAN Filter configuration. 739 * 740 * @param dev 741 * Pointer to Ethernet device structure. 742 * @param on 743 * Toggle filter. 744 * 745 * @return 746 * 0 on success, negative error value otherwise. 747 */ 748 static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on) 749 { 750 uint32_t j; 751 int ret; 752 struct rte_vlan_filter_conf *vfc; 753 754 vfc = &dev->data->vlan_filter_conf; 755 for (j = 0; j < RTE_DIM(vfc->ids); j++) { 756 uint64_t vlan; 757 uint64_t vbit; 758 uint64_t ids = vfc->ids[j]; 759 760 if (ids == 0) 761 continue; 762 763 while (ids) { 764 vlan = 64 * j; 765 /* count trailing zeroes */ 766 vbit = ~ids & (ids - 1); 767 /* clear least significant bit set */ 768 ids ^= (ids ^ (ids - 1)) ^ vbit; 769 for (; vbit; vlan++) 770 vbit >>= 1; 771 ret = mrvl_vlan_filter_set(dev, vlan, on); 772 if (ret) { 773 MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); 774 return ret; 775 } 776 } 777 } 778 779 return 0; 780 } 781 782 /** 783 * DPDK callback to start the device. 784 * 785 * @param dev 786 * Pointer to Ethernet device structure. 787 * 788 * @return 789 * 0 on success, negative errno value on failure. 790 */ 791 static int 792 mrvl_dev_start(struct rte_eth_dev *dev) 793 { 794 struct mrvl_priv *priv = dev->data->dev_private; 795 char match[MRVL_MATCH_LEN]; 796 int ret = 0, i, def_init_size; 797 struct rte_ether_addr *mac_addr; 798 799 if (priv->ppio) 800 return mrvl_dev_set_link_up(dev); 801 802 snprintf(match, sizeof(match), "ppio-%d:%d", 803 priv->pp_id, priv->ppio_id); 804 priv->ppio_params.match = match; 805 priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; 806 priv->forward_bad_frames = 0; 807 priv->fill_bpool_buffs = MRVL_BURST_SIZE; 808 809 if (mrvl_cfg) { 810 priv->ppio_params.eth_start_hdr = 811 mrvl_cfg->port[dev->data->port_id].eth_start_hdr; 812 priv->forward_bad_frames = 813 mrvl_cfg->port[dev->data->port_id].forward_bad_frames; 814 priv->fill_bpool_buffs = 815 mrvl_cfg->port[dev->data->port_id].fill_bpool_buffs; 816 } 817 818 /* 819 * Calculate the minimum bpool size for refill feature as follows: 820 * 2 default burst sizes multiply by number of rx queues. 821 * If the bpool size will be below this value, new buffers will 822 * be added to the pool. 823 */ 824 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 825 826 /* In case initial bpool size configured in queues setup is 827 * smaller than minimum size add more buffers 828 */ 829 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 830 if (priv->bpool_init_size < def_init_size) { 831 int buffs_to_add = def_init_size - priv->bpool_init_size; 832 833 priv->bpool_init_size += buffs_to_add; 834 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 835 if (ret) 836 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 837 } 838 839 /* 840 * Calculate the maximum bpool size for refill feature as follows: 841 * maximum number of descriptors in rx queue multiply by number 842 * of rx queues plus minimum bpool size. 843 * In case the bpool size will exceed this value, superfluous buffers 844 * will be removed 845 */ 846 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 847 priv->bpool_min_size; 848 849 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 850 if (ret) { 851 MRVL_LOG(ERR, "Failed to init ppio"); 852 return ret; 853 } 854 855 /* 856 * In case there are some stale uc/mc mac addresses flush them 857 * here. It cannot be done during mrvl_dev_close() as port information 858 * is already gone at that point (due to pp2_ppio_deinit() in 859 * mrvl_dev_stop()). 860 */ 861 if (!priv->uc_mc_flushed) { 862 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 863 if (ret) { 864 MRVL_LOG(ERR, 865 "Failed to flush uc/mc filter list"); 866 goto out; 867 } 868 priv->uc_mc_flushed = 1; 869 } 870 871 ret = mrvl_mtu_set(dev, dev->data->mtu); 872 if (ret) 873 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); 874 875 if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0])) 876 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]); 877 878 for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) { 879 mac_addr = &dev->data->mac_addrs[i]; 880 881 /* skip zero address */ 882 if (rte_is_zero_ether_addr(mac_addr)) 883 continue; 884 885 mrvl_mac_addr_add(dev, mac_addr, i, 0); 886 } 887 888 if (dev->data->all_multicast == 1) 889 mrvl_allmulticast_enable(dev); 890 891 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 892 ret = mrvl_populate_vlan_table(dev, 1); 893 if (ret) { 894 MRVL_LOG(ERR, "Failed to populate VLAN table"); 895 goto out; 896 } 897 } 898 899 /* For default QoS config, don't start classifier. */ 900 if (mrvl_cfg && 901 mrvl_cfg->port[dev->data->port_id].use_qos_global_defaults == 0) { 902 ret = mrvl_start_qos_mapping(priv); 903 if (ret) { 904 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 905 goto out; 906 } 907 } 908 909 ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode); 910 if (ret) { 911 MRVL_LOG(ERR, "Failed to set loopback"); 912 goto out; 913 } 914 915 if (dev->data->promiscuous == 1) 916 mrvl_promiscuous_enable(dev); 917 918 if (priv->flow_ctrl) { 919 ret = mrvl_flow_ctrl_set(dev, &priv->fc_conf); 920 if (ret) { 921 MRVL_LOG(ERR, "Failed to configure flow control"); 922 goto out; 923 } 924 priv->flow_ctrl = 0; 925 } 926 927 if (dev->data->dev_link.link_status == RTE_ETH_LINK_UP) { 928 ret = mrvl_dev_set_link_up(dev); 929 if (ret) { 930 MRVL_LOG(ERR, "Failed to set link up"); 931 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 932 goto out; 933 } 934 } 935 936 /* start tx queues */ 937 for (i = 0; i < dev->data->nb_tx_queues; i++) { 938 struct mrvl_txq *txq = dev->data->tx_queues[i]; 939 940 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 941 942 if (!txq->tx_deferred_start) 943 continue; 944 945 /* 946 * All txqs are started by default. Stop them 947 * so that tx_deferred_start works as expected. 948 */ 949 ret = mrvl_tx_queue_stop(dev, i); 950 if (ret) 951 goto out; 952 } 953 954 for (i = 0; i < dev->data->nb_rx_queues; i++) 955 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 956 957 mrvl_flow_init(dev); 958 mrvl_mtr_init(dev); 959 mrvl_set_tx_function(dev); 960 961 return 0; 962 out: 963 MRVL_LOG(ERR, "Failed to start device"); 964 pp2_ppio_deinit(priv->ppio); 965 return ret; 966 } 967 968 /** 969 * Flush receive queues. 970 * 971 * @param dev 972 * Pointer to Ethernet device structure. 973 */ 974 static void 975 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 976 { 977 int i; 978 979 MRVL_LOG(INFO, "Flushing rx queues"); 980 for (i = 0; i < dev->data->nb_rx_queues; i++) { 981 int ret, num; 982 983 do { 984 struct mrvl_rxq *q = dev->data->rx_queues[i]; 985 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 986 987 num = MRVL_PP2_RXD_MAX; 988 ret = pp2_ppio_recv(q->priv->ppio, 989 q->priv->rxq_map[q->queue_id].tc, 990 q->priv->rxq_map[q->queue_id].inq, 991 descs, (uint16_t *)&num); 992 } while (ret == 0 && num); 993 } 994 } 995 996 /** 997 * Flush transmit shadow queues. 998 * 999 * @param dev 1000 * Pointer to Ethernet device structure. 1001 */ 1002 static void 1003 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 1004 { 1005 int i, j; 1006 struct mrvl_txq *txq; 1007 1008 MRVL_LOG(INFO, "Flushing tx shadow queues"); 1009 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1010 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 1011 1012 for (j = 0; j < RTE_MAX_LCORE; j++) { 1013 struct mrvl_shadow_txq *sq; 1014 1015 if (!hifs[j]) 1016 continue; 1017 1018 sq = &txq->shadow_txqs[j]; 1019 mrvl_free_sent_buffers(txq->priv->ppio, 1020 hifs[j], j, sq, txq->queue_id, 1); 1021 while (sq->tail != sq->head) { 1022 uint64_t addr = cookie_addr_high | 1023 sq->ent[sq->tail].buff.cookie; 1024 rte_pktmbuf_free( 1025 (struct rte_mbuf *)addr); 1026 sq->tail = (sq->tail + 1) & 1027 MRVL_PP2_TX_SHADOWQ_MASK; 1028 } 1029 memset(sq, 0, sizeof(*sq)); 1030 } 1031 } 1032 } 1033 1034 /** 1035 * Flush hardware bpool (buffer-pool). 1036 * 1037 * @param dev 1038 * Pointer to Ethernet device structure. 1039 */ 1040 static void 1041 mrvl_flush_bpool(struct rte_eth_dev *dev) 1042 { 1043 struct mrvl_priv *priv = dev->data->dev_private; 1044 struct pp2_hif *hif; 1045 uint32_t num; 1046 int ret; 1047 unsigned int core_id = rte_lcore_id(); 1048 1049 if (core_id == LCORE_ID_ANY) 1050 core_id = rte_get_main_lcore(); 1051 1052 hif = mrvl_get_hif(priv, core_id); 1053 1054 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 1055 if (ret) { 1056 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 1057 return; 1058 } 1059 1060 while (num--) { 1061 struct pp2_buff_inf inf; 1062 uint64_t addr; 1063 1064 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 1065 if (ret) 1066 break; 1067 1068 addr = cookie_addr_high | inf.cookie; 1069 rte_pktmbuf_free((struct rte_mbuf *)addr); 1070 } 1071 } 1072 1073 /** 1074 * DPDK callback to stop the device. 1075 * 1076 * @param dev 1077 * Pointer to Ethernet device structure. 1078 */ 1079 static int 1080 mrvl_dev_stop(struct rte_eth_dev *dev) 1081 { 1082 uint16_t i; 1083 1084 for (i = 0; i < dev->data->nb_rx_queues; i++) 1085 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1086 for (i = 0; i < dev->data->nb_tx_queues; i++) 1087 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1088 1089 return mrvl_dev_set_link_down(dev); 1090 } 1091 1092 /** 1093 * DPDK callback to close the device. 1094 * 1095 * @param dev 1096 * Pointer to Ethernet device structure. 1097 */ 1098 static int 1099 mrvl_dev_close(struct rte_eth_dev *dev) 1100 { 1101 struct mrvl_priv *priv = dev->data->dev_private; 1102 size_t i; 1103 1104 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1105 return 0; 1106 1107 mrvl_flush_rx_queues(dev); 1108 mrvl_flush_tx_shadow_queues(dev); 1109 mrvl_flow_deinit(dev); 1110 mrvl_mtr_deinit(dev); 1111 1112 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 1113 struct pp2_ppio_tc_params *tc_params = 1114 &priv->ppio_params.inqs_params.tcs_params[i]; 1115 1116 if (tc_params->inqs_params) { 1117 rte_free(tc_params->inqs_params); 1118 tc_params->inqs_params = NULL; 1119 } 1120 } 1121 1122 if (priv->cls_tbl) { 1123 pp2_cls_tbl_deinit(priv->cls_tbl); 1124 priv->cls_tbl = NULL; 1125 } 1126 1127 if (priv->qos_tbl) { 1128 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 1129 priv->qos_tbl = NULL; 1130 } 1131 1132 mrvl_flush_bpool(dev); 1133 mrvl_tm_deinit(dev); 1134 1135 if (priv->ppio) { 1136 pp2_ppio_deinit(priv->ppio); 1137 priv->ppio = NULL; 1138 } 1139 1140 /* policer must be released after ppio deinitialization */ 1141 if (priv->default_policer) { 1142 pp2_cls_plcr_deinit(priv->default_policer); 1143 priv->default_policer = NULL; 1144 } 1145 1146 1147 if (priv->bpool) { 1148 pp2_bpool_deinit(priv->bpool); 1149 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 1150 priv->bpool = NULL; 1151 } 1152 1153 mrvl_dev_num--; 1154 1155 if (mrvl_dev_num == 0) { 1156 MRVL_LOG(INFO, "Perform MUSDK deinit"); 1157 mrvl_deinit_hifs(); 1158 mrvl_deinit_pp2(); 1159 rte_mvep_deinit(MVEP_MOD_T_PP2); 1160 } 1161 1162 return 0; 1163 } 1164 1165 /** 1166 * DPDK callback to retrieve physical link information. 1167 * 1168 * @param dev 1169 * Pointer to Ethernet device structure. 1170 * @param wait_to_complete 1171 * Wait for request completion (ignored). 1172 * 1173 * @return 1174 * 0 on success, negative error value otherwise. 1175 */ 1176 static int 1177 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 1178 { 1179 /* 1180 * TODO 1181 * once MUSDK provides necessary API use it here 1182 */ 1183 struct mrvl_priv *priv = dev->data->dev_private; 1184 struct ethtool_cmd edata; 1185 struct ifreq req; 1186 int ret, fd, link_up; 1187 1188 if (!priv->ppio) 1189 return -EPERM; 1190 1191 edata.cmd = ETHTOOL_GSET; 1192 1193 strcpy(req.ifr_name, dev->data->name); 1194 req.ifr_data = (void *)&edata; 1195 1196 fd = socket(AF_INET, SOCK_DGRAM, 0); 1197 if (fd == -1) 1198 return -EFAULT; 1199 1200 ret = ioctl(fd, SIOCETHTOOL, &req); 1201 if (ret == -1) { 1202 close(fd); 1203 return -EFAULT; 1204 } 1205 1206 close(fd); 1207 1208 switch (ethtool_cmd_speed(&edata)) { 1209 case SPEED_10: 1210 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_10M; 1211 break; 1212 case SPEED_100: 1213 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_100M; 1214 break; 1215 case SPEED_1000: 1216 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_1G; 1217 break; 1218 case SPEED_2500: 1219 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 1220 break; 1221 case SPEED_10000: 1222 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_10G; 1223 break; 1224 default: 1225 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE; 1226 } 1227 1228 dev->data->dev_link.link_duplex = edata.duplex ? RTE_ETH_LINK_FULL_DUPLEX : 1229 RTE_ETH_LINK_HALF_DUPLEX; 1230 dev->data->dev_link.link_autoneg = edata.autoneg ? RTE_ETH_LINK_AUTONEG : 1231 RTE_ETH_LINK_FIXED; 1232 pp2_ppio_get_link_state(priv->ppio, &link_up); 1233 dev->data->dev_link.link_status = link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 1234 1235 return 0; 1236 } 1237 1238 /** 1239 * DPDK callback to enable promiscuous mode. 1240 * 1241 * @param dev 1242 * Pointer to Ethernet device structure. 1243 * 1244 * @return 1245 * 0 on success, negative error value otherwise. 1246 */ 1247 static int 1248 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 1249 { 1250 struct mrvl_priv *priv = dev->data->dev_private; 1251 int ret; 1252 1253 if (priv->isolated) 1254 return -ENOTSUP; 1255 1256 if (!priv->ppio) 1257 return 0; 1258 1259 ret = pp2_ppio_set_promisc(priv->ppio, 1); 1260 if (ret) { 1261 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 1262 return -EAGAIN; 1263 } 1264 1265 return 0; 1266 } 1267 1268 /** 1269 * DPDK callback to enable allmulti mode. 1270 * 1271 * @param dev 1272 * Pointer to Ethernet device structure. 1273 * 1274 * @return 1275 * 0 on success, negative error value otherwise. 1276 */ 1277 static int 1278 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 1279 { 1280 struct mrvl_priv *priv = dev->data->dev_private; 1281 int ret; 1282 1283 if (priv->isolated) 1284 return -ENOTSUP; 1285 1286 if (!priv->ppio) 1287 return 0; 1288 1289 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 1290 if (ret) { 1291 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 1292 return -EAGAIN; 1293 } 1294 1295 return 0; 1296 } 1297 1298 /** 1299 * DPDK callback to disable promiscuous mode. 1300 * 1301 * @param dev 1302 * Pointer to Ethernet device structure. 1303 * 1304 * @return 1305 * 0 on success, negative error value otherwise. 1306 */ 1307 static int 1308 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 1309 { 1310 struct mrvl_priv *priv = dev->data->dev_private; 1311 int ret; 1312 1313 if (priv->isolated) 1314 return -ENOTSUP; 1315 1316 if (!priv->ppio) 1317 return 0; 1318 1319 ret = pp2_ppio_set_promisc(priv->ppio, 0); 1320 if (ret) { 1321 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 1322 return -EAGAIN; 1323 } 1324 1325 return 0; 1326 } 1327 1328 /** 1329 * DPDK callback to disable allmulticast mode. 1330 * 1331 * @param dev 1332 * Pointer to Ethernet device structure. 1333 * 1334 * @return 1335 * 0 on success, negative error value otherwise. 1336 */ 1337 static int 1338 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 1339 { 1340 struct mrvl_priv *priv = dev->data->dev_private; 1341 int ret; 1342 1343 if (priv->isolated) 1344 return -ENOTSUP; 1345 1346 if (!priv->ppio) 1347 return 0; 1348 1349 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 1350 if (ret) { 1351 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 1352 return -EAGAIN; 1353 } 1354 1355 return 0; 1356 } 1357 1358 /** 1359 * DPDK callback to remove a MAC address. 1360 * 1361 * @param dev 1362 * Pointer to Ethernet device structure. 1363 * @param index 1364 * MAC address index. 1365 */ 1366 static void 1367 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 1368 { 1369 struct mrvl_priv *priv = dev->data->dev_private; 1370 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1371 int ret; 1372 1373 if (priv->isolated) 1374 return; 1375 1376 if (!priv->ppio) 1377 return; 1378 1379 ret = pp2_ppio_remove_mac_addr(priv->ppio, 1380 dev->data->mac_addrs[index].addr_bytes); 1381 if (ret) { 1382 rte_ether_format_addr(buf, sizeof(buf), 1383 &dev->data->mac_addrs[index]); 1384 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 1385 } 1386 } 1387 1388 /** 1389 * DPDK callback to add a MAC address. 1390 * 1391 * @param dev 1392 * Pointer to Ethernet device structure. 1393 * @param mac_addr 1394 * MAC address to register. 1395 * @param index 1396 * MAC address index. 1397 * @param vmdq 1398 * VMDq pool index to associate address with (unused). 1399 * 1400 * @return 1401 * 0 on success, negative error value otherwise. 1402 */ 1403 static int 1404 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1405 uint32_t index, uint32_t vmdq __rte_unused) 1406 { 1407 struct mrvl_priv *priv = dev->data->dev_private; 1408 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1409 int ret; 1410 1411 if (priv->isolated) 1412 return -ENOTSUP; 1413 1414 if (!priv->ppio) 1415 return 0; 1416 1417 if (index == 0) 1418 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1419 return -1; 1420 1421 /* 1422 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1423 * parameter uc_filter_max. Maximum number of mc addresses is then 1424 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1425 * 21 respectively. 1426 * 1427 * If more than uc_filter_max uc addresses were added to filter list 1428 * then NIC will switch to promiscuous mode automatically. 1429 * 1430 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1431 * were added to filter list then NIC will switch to all-multicast mode 1432 * automatically. 1433 */ 1434 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1435 if (ret) { 1436 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1437 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1438 return -1; 1439 } 1440 1441 return 0; 1442 } 1443 1444 /** 1445 * DPDK callback to set the primary MAC address. 1446 * 1447 * @param dev 1448 * Pointer to Ethernet device structure. 1449 * @param mac_addr 1450 * MAC address to register. 1451 * 1452 * @return 1453 * 0 on success, negative error value otherwise. 1454 */ 1455 static int 1456 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1457 { 1458 struct mrvl_priv *priv = dev->data->dev_private; 1459 int ret; 1460 1461 if (priv->isolated) 1462 return -ENOTSUP; 1463 1464 if (!priv->ppio) 1465 return 0; 1466 1467 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1468 if (ret) { 1469 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1470 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1471 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1472 } 1473 1474 return ret; 1475 } 1476 1477 /** 1478 * DPDK callback to get device statistics. 1479 * 1480 * @param dev 1481 * Pointer to Ethernet device structure. 1482 * @param stats 1483 * Stats structure output buffer. 1484 * 1485 * @return 1486 * 0 on success, negative error value otherwise. 1487 */ 1488 static int 1489 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1490 { 1491 struct mrvl_priv *priv = dev->data->dev_private; 1492 struct pp2_ppio_statistics ppio_stats; 1493 uint64_t drop_mac = 0; 1494 unsigned int i, idx, ret; 1495 1496 if (!priv->ppio) 1497 return -EPERM; 1498 1499 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1500 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1501 struct pp2_ppio_inq_statistics rx_stats; 1502 1503 if (!rxq) 1504 continue; 1505 1506 idx = rxq->queue_id; 1507 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1508 MRVL_LOG(ERR, 1509 "rx queue %d stats out of range (0 - %d)", 1510 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1511 continue; 1512 } 1513 1514 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1515 priv->rxq_map[idx].tc, 1516 priv->rxq_map[idx].inq, 1517 &rx_stats, 0); 1518 if (unlikely(ret)) { 1519 MRVL_LOG(ERR, 1520 "Failed to update rx queue %d stats", idx); 1521 break; 1522 } 1523 1524 stats->q_ibytes[idx] = rxq->bytes_recv; 1525 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1526 stats->q_errors[idx] = rx_stats.drop_early + 1527 rx_stats.drop_fullq + 1528 rx_stats.drop_bm + 1529 rxq->drop_mac; 1530 stats->ibytes += rxq->bytes_recv; 1531 drop_mac += rxq->drop_mac; 1532 } 1533 1534 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1535 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1536 struct pp2_ppio_outq_statistics tx_stats; 1537 1538 if (!txq) 1539 continue; 1540 1541 idx = txq->queue_id; 1542 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1543 MRVL_LOG(ERR, 1544 "tx queue %d stats out of range (0 - %d)", 1545 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1546 } 1547 1548 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1549 &tx_stats, 0); 1550 if (unlikely(ret)) { 1551 MRVL_LOG(ERR, 1552 "Failed to update tx queue %d stats", idx); 1553 break; 1554 } 1555 1556 stats->q_opackets[idx] = tx_stats.deq_desc; 1557 stats->q_obytes[idx] = txq->bytes_sent; 1558 stats->obytes += txq->bytes_sent; 1559 } 1560 1561 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1562 if (unlikely(ret)) { 1563 MRVL_LOG(ERR, "Failed to update port statistics"); 1564 return ret; 1565 } 1566 1567 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1568 stats->opackets += ppio_stats.tx_packets; 1569 stats->imissed += ppio_stats.rx_fullq_dropped + 1570 ppio_stats.rx_bm_dropped + 1571 ppio_stats.rx_early_dropped + 1572 ppio_stats.rx_fifo_dropped + 1573 ppio_stats.rx_cls_dropped; 1574 stats->ierrors = drop_mac; 1575 1576 return 0; 1577 } 1578 1579 /** 1580 * DPDK callback to clear device statistics. 1581 * 1582 * @param dev 1583 * Pointer to Ethernet device structure. 1584 * 1585 * @return 1586 * 0 on success, negative error value otherwise. 1587 */ 1588 static int 1589 mrvl_stats_reset(struct rte_eth_dev *dev) 1590 { 1591 struct mrvl_priv *priv = dev->data->dev_private; 1592 int i; 1593 1594 if (!priv->ppio) 1595 return 0; 1596 1597 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1598 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1599 1600 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1601 priv->rxq_map[i].inq, NULL, 1); 1602 rxq->bytes_recv = 0; 1603 rxq->drop_mac = 0; 1604 } 1605 1606 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1607 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1608 1609 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1610 txq->bytes_sent = 0; 1611 } 1612 1613 return pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1614 } 1615 1616 /** 1617 * DPDK callback to get extended statistics. 1618 * 1619 * @param dev 1620 * Pointer to Ethernet device structure. 1621 * @param stats 1622 * Pointer to xstats table. 1623 * @param n 1624 * Number of entries in xstats table. 1625 * @return 1626 * Negative value on error, number of read xstats otherwise. 1627 */ 1628 static int 1629 mrvl_xstats_get(struct rte_eth_dev *dev, 1630 struct rte_eth_xstat *stats, unsigned int n) 1631 { 1632 struct mrvl_priv *priv = dev->data->dev_private; 1633 struct pp2_ppio_statistics ppio_stats; 1634 unsigned int i, count; 1635 1636 count = RTE_DIM(mrvl_xstats_tbl); 1637 if (n < count) 1638 return count; 1639 1640 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1641 for (i = 0; i < count; i++) { 1642 uint64_t val; 1643 1644 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1645 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1646 mrvl_xstats_tbl[i].offset); 1647 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1648 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1649 mrvl_xstats_tbl[i].offset); 1650 else 1651 return -EINVAL; 1652 1653 stats[i].id = i; 1654 stats[i].value = val; 1655 } 1656 1657 return count; 1658 } 1659 1660 /** 1661 * DPDK callback to reset extended statistics. 1662 * 1663 * @param dev 1664 * Pointer to Ethernet device structure. 1665 * 1666 * @return 1667 * 0 on success, negative error value otherwise. 1668 */ 1669 static int 1670 mrvl_xstats_reset(struct rte_eth_dev *dev) 1671 { 1672 return mrvl_stats_reset(dev); 1673 } 1674 1675 /** 1676 * DPDK callback to get extended statistics names. 1677 * 1678 * @param dev (unused) 1679 * Pointer to Ethernet device structure. 1680 * @param xstats_names 1681 * Pointer to xstats names table. 1682 * @param size 1683 * Size of the xstats names table. 1684 * @return 1685 * Number of read names. 1686 */ 1687 static int 1688 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1689 struct rte_eth_xstat_name *xstats_names, 1690 unsigned int size) 1691 { 1692 unsigned int i; 1693 1694 if (!xstats_names) 1695 return RTE_DIM(mrvl_xstats_tbl); 1696 1697 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1698 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name, 1699 RTE_ETH_XSTATS_NAME_SIZE); 1700 1701 return size; 1702 } 1703 1704 /** 1705 * DPDK callback to get information about the device. 1706 * 1707 * @param dev 1708 * Pointer to Ethernet device structure (unused). 1709 * @param info 1710 * Info structure output buffer. 1711 */ 1712 static int 1713 mrvl_dev_infos_get(struct rte_eth_dev *dev, 1714 struct rte_eth_dev_info *info) 1715 { 1716 struct mrvl_priv *priv = dev->data->dev_private; 1717 1718 info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 1719 1720 info->speed_capa = RTE_ETH_LINK_SPEED_10M | 1721 RTE_ETH_LINK_SPEED_100M | 1722 RTE_ETH_LINK_SPEED_1G | 1723 RTE_ETH_LINK_SPEED_2_5G | 1724 RTE_ETH_LINK_SPEED_10G; 1725 1726 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1727 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1728 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1729 1730 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1731 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1732 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1733 1734 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1735 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1736 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1737 1738 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1739 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1740 1741 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1742 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1743 1744 info->flow_type_rss_offloads = RTE_ETH_RSS_IPV4 | 1745 RTE_ETH_RSS_NONFRAG_IPV4_TCP | 1746 RTE_ETH_RSS_NONFRAG_IPV4_UDP; 1747 1748 /* By default packets are dropped if no descriptors are available */ 1749 info->default_rxconf.rx_drop_en = 1; 1750 1751 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1752 info->max_mtu = priv->max_mtu; 1753 1754 return 0; 1755 } 1756 1757 /** 1758 * Return supported packet types. 1759 * 1760 * @param dev 1761 * Pointer to Ethernet device structure (unused). 1762 * 1763 * @return 1764 * Const pointer to the table with supported packet types. 1765 */ 1766 static const uint32_t * 1767 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1768 { 1769 static const uint32_t ptypes[] = { 1770 RTE_PTYPE_L2_ETHER, 1771 RTE_PTYPE_L2_ETHER_VLAN, 1772 RTE_PTYPE_L2_ETHER_QINQ, 1773 RTE_PTYPE_L3_IPV4, 1774 RTE_PTYPE_L3_IPV4_EXT, 1775 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1776 RTE_PTYPE_L3_IPV6, 1777 RTE_PTYPE_L3_IPV6_EXT, 1778 RTE_PTYPE_L2_ETHER_ARP, 1779 RTE_PTYPE_L4_TCP, 1780 RTE_PTYPE_L4_UDP 1781 }; 1782 1783 return ptypes; 1784 } 1785 1786 /** 1787 * DPDK callback to get information about specific receive queue. 1788 * 1789 * @param dev 1790 * Pointer to Ethernet device structure. 1791 * @param rx_queue_id 1792 * Receive queue index. 1793 * @param qinfo 1794 * Receive queue information structure. 1795 */ 1796 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1797 struct rte_eth_rxq_info *qinfo) 1798 { 1799 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1800 struct mrvl_priv *priv = dev->data->dev_private; 1801 int inq = priv->rxq_map[rx_queue_id].inq; 1802 int tc = priv->rxq_map[rx_queue_id].tc; 1803 struct pp2_ppio_tc_params *tc_params = 1804 &priv->ppio_params.inqs_params.tcs_params[tc]; 1805 1806 qinfo->mp = q->mp; 1807 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1808 } 1809 1810 /** 1811 * DPDK callback to get information about specific transmit queue. 1812 * 1813 * @param dev 1814 * Pointer to Ethernet device structure. 1815 * @param tx_queue_id 1816 * Transmit queue index. 1817 * @param qinfo 1818 * Transmit queue information structure. 1819 */ 1820 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1821 struct rte_eth_txq_info *qinfo) 1822 { 1823 struct mrvl_priv *priv = dev->data->dev_private; 1824 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1825 1826 qinfo->nb_desc = 1827 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1828 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1829 } 1830 1831 /** 1832 * DPDK callback to Configure a VLAN filter. 1833 * 1834 * @param dev 1835 * Pointer to Ethernet device structure. 1836 * @param vlan_id 1837 * VLAN ID to filter. 1838 * @param on 1839 * Toggle filter. 1840 * 1841 * @return 1842 * 0 on success, negative error value otherwise. 1843 */ 1844 static int 1845 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1846 { 1847 struct mrvl_priv *priv = dev->data->dev_private; 1848 1849 if (priv->isolated) 1850 return -ENOTSUP; 1851 1852 if (!priv->ppio) 1853 return 0; 1854 1855 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1856 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1857 } 1858 1859 /** 1860 * DPDK callback to Configure VLAN offload. 1861 * 1862 * @param dev 1863 * Pointer to Ethernet device structure. 1864 * @param mask 1865 * VLAN offload mask. 1866 * 1867 * @return 1868 * 0 on success, negative error value otherwise. 1869 */ 1870 static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1871 { 1872 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1873 int ret; 1874 1875 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1876 MRVL_LOG(ERR, "VLAN stripping is not supported\n"); 1877 return -ENOTSUP; 1878 } 1879 1880 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1881 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 1882 ret = mrvl_populate_vlan_table(dev, 1); 1883 else 1884 ret = mrvl_populate_vlan_table(dev, 0); 1885 1886 if (ret) 1887 return ret; 1888 } 1889 1890 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1891 MRVL_LOG(ERR, "Extend VLAN not supported\n"); 1892 return -ENOTSUP; 1893 } 1894 1895 return 0; 1896 } 1897 1898 /** 1899 * Release buffers to hardware bpool (buffer-pool) 1900 * 1901 * @param rxq 1902 * Receive queue pointer. 1903 * @param num 1904 * Number of buffers to release to bpool. 1905 * 1906 * @return 1907 * 0 on success, negative error value otherwise. 1908 */ 1909 static int 1910 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1911 { 1912 struct buff_release_entry entries[num]; 1913 struct rte_mbuf *mbufs[num]; 1914 int i, ret; 1915 unsigned int core_id; 1916 struct pp2_hif *hif; 1917 struct pp2_bpool *bpool; 1918 1919 core_id = rte_lcore_id(); 1920 if (core_id == LCORE_ID_ANY) 1921 core_id = rte_get_main_lcore(); 1922 1923 hif = mrvl_get_hif(rxq->priv, core_id); 1924 if (!hif) 1925 return -1; 1926 1927 bpool = rxq->priv->bpool; 1928 1929 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1930 if (ret) 1931 return ret; 1932 1933 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1934 cookie_addr_high = 1935 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1936 1937 for (i = 0; i < num; i++) { 1938 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1939 != cookie_addr_high) { 1940 MRVL_LOG(ERR, 1941 "mbuf virtual addr high is out of range " 1942 "0x%x instead of 0x%x\n", 1943 (uint32_t)((uint64_t)mbufs[i] >> 32), 1944 (uint32_t)(cookie_addr_high >> 32)); 1945 goto out; 1946 } 1947 1948 entries[i].buff.addr = 1949 rte_mbuf_data_iova_default(mbufs[i]); 1950 entries[i].buff.cookie = (uintptr_t)mbufs[i]; 1951 entries[i].bpool = bpool; 1952 } 1953 1954 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1955 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1956 1957 if (i != num) 1958 goto out; 1959 1960 return 0; 1961 out: 1962 for (; i < num; i++) 1963 rte_pktmbuf_free(mbufs[i]); 1964 1965 return -1; 1966 } 1967 1968 /** 1969 * DPDK callback to configure the receive queue. 1970 * 1971 * @param dev 1972 * Pointer to Ethernet device structure. 1973 * @param idx 1974 * RX queue index. 1975 * @param desc 1976 * Number of descriptors to configure in queue. 1977 * @param socket 1978 * NUMA socket on which memory must be allocated. 1979 * @param conf 1980 * Thresholds parameters. 1981 * @param mp 1982 * Memory pool for buffer allocations. 1983 * 1984 * @return 1985 * 0 on success, negative error value otherwise. 1986 */ 1987 static int 1988 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1989 unsigned int socket, 1990 const struct rte_eth_rxconf *conf, 1991 struct rte_mempool *mp) 1992 { 1993 struct mrvl_priv *priv = dev->data->dev_private; 1994 struct mrvl_rxq *rxq; 1995 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp); 1996 uint32_t max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN; 1997 int ret, tc, inq; 1998 uint64_t offloads; 1999 2000 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 2001 2002 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 2003 /* 2004 * Unknown TC mapping, mapping will not have a correct queue. 2005 */ 2006 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 2007 idx, priv->ppio_id); 2008 return -EFAULT; 2009 } 2010 2011 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS; 2012 if (frame_size < max_rx_pktlen) { 2013 MRVL_LOG(WARNING, 2014 "Mbuf size must be increased to %u bytes to hold up " 2015 "to %u bytes of data.", 2016 max_rx_pktlen + buf_size - frame_size, 2017 max_rx_pktlen); 2018 dev->data->mtu = frame_size - RTE_ETHER_HDR_LEN; 2019 MRVL_LOG(INFO, "Setting MTU to %u", dev->data->mtu); 2020 } 2021 2022 if (dev->data->rx_queues[idx]) { 2023 rte_free(dev->data->rx_queues[idx]); 2024 dev->data->rx_queues[idx] = NULL; 2025 } 2026 2027 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 2028 if (!rxq) 2029 return -ENOMEM; 2030 2031 rxq->priv = priv; 2032 rxq->mp = mp; 2033 rxq->cksum_enabled = offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM; 2034 rxq->queue_id = idx; 2035 rxq->port_id = dev->data->port_id; 2036 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 2037 2038 tc = priv->rxq_map[rxq->queue_id].tc, 2039 inq = priv->rxq_map[rxq->queue_id].inq; 2040 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 2041 desc; 2042 2043 ret = mrvl_fill_bpool(rxq, desc); 2044 if (ret) { 2045 rte_free(rxq); 2046 return ret; 2047 } 2048 2049 priv->bpool_init_size += desc; 2050 2051 dev->data->rx_queues[idx] = rxq; 2052 2053 return 0; 2054 } 2055 2056 /** 2057 * DPDK callback to release the receive queue. 2058 * 2059 * @param dev 2060 * Pointer to Ethernet device structure. 2061 * @param qid 2062 * Receive queue index. 2063 */ 2064 static void 2065 mrvl_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 2066 { 2067 struct mrvl_rxq *q = dev->data->rx_queues[qid]; 2068 struct pp2_ppio_tc_params *tc_params; 2069 int i, num, tc, inq; 2070 struct pp2_hif *hif; 2071 unsigned int core_id = rte_lcore_id(); 2072 2073 if (core_id == LCORE_ID_ANY) 2074 core_id = rte_get_main_lcore(); 2075 2076 if (!q) 2077 return; 2078 2079 hif = mrvl_get_hif(q->priv, core_id); 2080 2081 if (!hif) 2082 return; 2083 2084 tc = q->priv->rxq_map[q->queue_id].tc; 2085 inq = q->priv->rxq_map[q->queue_id].inq; 2086 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 2087 num = tc_params->inqs_params[inq].size; 2088 for (i = 0; i < num; i++) { 2089 struct pp2_buff_inf inf; 2090 uint64_t addr; 2091 2092 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 2093 addr = cookie_addr_high | inf.cookie; 2094 rte_pktmbuf_free((struct rte_mbuf *)addr); 2095 } 2096 2097 rte_free(q); 2098 } 2099 2100 /** 2101 * DPDK callback to configure the transmit queue. 2102 * 2103 * @param dev 2104 * Pointer to Ethernet device structure. 2105 * @param idx 2106 * Transmit queue index. 2107 * @param desc 2108 * Number of descriptors to configure in the queue. 2109 * @param socket 2110 * NUMA socket on which memory must be allocated. 2111 * @param conf 2112 * Tx queue configuration parameters. 2113 * 2114 * @return 2115 * 0 on success, negative error value otherwise. 2116 */ 2117 static int 2118 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 2119 unsigned int socket, 2120 const struct rte_eth_txconf *conf) 2121 { 2122 struct mrvl_priv *priv = dev->data->dev_private; 2123 struct mrvl_txq *txq; 2124 2125 if (dev->data->tx_queues[idx]) { 2126 rte_free(dev->data->tx_queues[idx]); 2127 dev->data->tx_queues[idx] = NULL; 2128 } 2129 2130 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 2131 if (!txq) 2132 return -ENOMEM; 2133 2134 txq->priv = priv; 2135 txq->queue_id = idx; 2136 txq->port_id = dev->data->port_id; 2137 txq->tx_deferred_start = conf->tx_deferred_start; 2138 dev->data->tx_queues[idx] = txq; 2139 2140 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 2141 2142 return 0; 2143 } 2144 2145 /** 2146 * DPDK callback to release the transmit queue. 2147 * 2148 * @param dev 2149 * Pointer to Ethernet device structure. 2150 * @param qid 2151 * Transmit queue index. 2152 */ 2153 static void 2154 mrvl_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 2155 { 2156 struct mrvl_txq *q = dev->data->tx_queues[qid]; 2157 2158 if (!q) 2159 return; 2160 2161 rte_free(q); 2162 } 2163 2164 /** 2165 * DPDK callback to get flow control configuration. 2166 * 2167 * @param dev 2168 * Pointer to Ethernet device structure. 2169 * @param fc_conf 2170 * Pointer to the flow control configuration. 2171 * 2172 * @return 2173 * 0 on success, negative error value otherwise. 2174 */ 2175 static int 2176 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2177 { 2178 struct mrvl_priv *priv = dev->data->dev_private; 2179 int ret, en; 2180 2181 if (!priv->ppio) { 2182 memcpy(fc_conf, &priv->fc_conf, sizeof(struct rte_eth_fc_conf)); 2183 return 0; 2184 } 2185 2186 fc_conf->autoneg = 1; 2187 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 2188 if (ret) { 2189 MRVL_LOG(ERR, "Failed to read rx pause state"); 2190 return ret; 2191 } 2192 2193 fc_conf->mode = en ? RTE_ETH_FC_RX_PAUSE : RTE_ETH_FC_NONE; 2194 2195 ret = pp2_ppio_get_tx_pause(priv->ppio, &en); 2196 if (ret) { 2197 MRVL_LOG(ERR, "Failed to read tx pause state"); 2198 return ret; 2199 } 2200 2201 if (en) { 2202 if (fc_conf->mode == RTE_ETH_FC_NONE) 2203 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2204 else 2205 fc_conf->mode = RTE_ETH_FC_FULL; 2206 } 2207 2208 return 0; 2209 } 2210 2211 /** 2212 * DPDK callback to set flow control configuration. 2213 * 2214 * @param dev 2215 * Pointer to Ethernet device structure. 2216 * @param fc_conf 2217 * Pointer to the flow control configuration. 2218 * 2219 * @return 2220 * 0 on success, negative error value otherwise. 2221 */ 2222 static int 2223 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2224 { 2225 struct mrvl_priv *priv = dev->data->dev_private; 2226 struct pp2_ppio_tx_pause_params mrvl_pause_params; 2227 int ret; 2228 int rx_en, tx_en; 2229 2230 if (fc_conf->high_water || 2231 fc_conf->low_water || 2232 fc_conf->pause_time || 2233 fc_conf->mac_ctrl_frame_fwd) { 2234 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 2235 2236 return -EINVAL; 2237 } 2238 2239 if (fc_conf->autoneg == 0) { 2240 MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported"); 2241 return -EINVAL; 2242 } 2243 2244 if (!priv->ppio) { 2245 memcpy(&priv->fc_conf, fc_conf, sizeof(struct rte_eth_fc_conf)); 2246 priv->flow_ctrl = 1; 2247 return 0; 2248 } 2249 2250 switch (fc_conf->mode) { 2251 case RTE_ETH_FC_FULL: 2252 rx_en = 1; 2253 tx_en = 1; 2254 break; 2255 case RTE_ETH_FC_TX_PAUSE: 2256 rx_en = 0; 2257 tx_en = 1; 2258 break; 2259 case RTE_ETH_FC_RX_PAUSE: 2260 rx_en = 1; 2261 tx_en = 0; 2262 break; 2263 case RTE_ETH_FC_NONE: 2264 rx_en = 0; 2265 tx_en = 0; 2266 break; 2267 default: 2268 MRVL_LOG(ERR, "Incorrect Flow control flag (%d)", 2269 fc_conf->mode); 2270 return -EINVAL; 2271 } 2272 2273 /* Set RX flow control */ 2274 ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en); 2275 if (ret) { 2276 MRVL_LOG(ERR, "Failed to change RX flowctrl"); 2277 return ret; 2278 } 2279 2280 /* Set TX flow control */ 2281 mrvl_pause_params.en = tx_en; 2282 /* all inqs participate in xon/xoff decision */ 2283 mrvl_pause_params.use_tc_pause_inqs = 0; 2284 ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params); 2285 if (ret) { 2286 MRVL_LOG(ERR, "Failed to change TX flowctrl"); 2287 return ret; 2288 } 2289 2290 return 0; 2291 } 2292 2293 /** 2294 * Update RSS hash configuration 2295 * 2296 * @param dev 2297 * Pointer to Ethernet device structure. 2298 * @param rss_conf 2299 * Pointer to RSS configuration. 2300 * 2301 * @return 2302 * 0 on success, negative error value otherwise. 2303 */ 2304 static int 2305 mrvl_rss_hash_update(struct rte_eth_dev *dev, 2306 struct rte_eth_rss_conf *rss_conf) 2307 { 2308 struct mrvl_priv *priv = dev->data->dev_private; 2309 2310 if (priv->isolated) 2311 return -ENOTSUP; 2312 2313 return mrvl_configure_rss(priv, rss_conf); 2314 } 2315 2316 /** 2317 * DPDK callback to get RSS hash configuration. 2318 * 2319 * @param dev 2320 * Pointer to Ethernet device structure. 2321 * @rss_conf 2322 * Pointer to RSS configuration. 2323 * 2324 * @return 2325 * Always 0. 2326 */ 2327 static int 2328 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 2329 struct rte_eth_rss_conf *rss_conf) 2330 { 2331 struct mrvl_priv *priv = dev->data->dev_private; 2332 enum pp2_ppio_hash_type hash_type = 2333 priv->ppio_params.inqs_params.hash_type; 2334 2335 rss_conf->rss_key = NULL; 2336 2337 if (hash_type == PP2_PPIO_HASH_T_NONE) 2338 rss_conf->rss_hf = 0; 2339 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 2340 rss_conf->rss_hf = RTE_ETH_RSS_IPV4; 2341 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 2342 rss_conf->rss_hf = RTE_ETH_RSS_NONFRAG_IPV4_TCP; 2343 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 2344 rss_conf->rss_hf = RTE_ETH_RSS_NONFRAG_IPV4_UDP; 2345 2346 return 0; 2347 } 2348 2349 /** 2350 * DPDK callback to get rte_flow callbacks. 2351 * 2352 * @param dev 2353 * Pointer to the device structure. 2354 * @param ops 2355 * Pointer to pass the flow ops. 2356 * 2357 * @return 2358 * 0 on success, negative error value otherwise. 2359 */ 2360 static int 2361 mrvl_eth_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 2362 const struct rte_flow_ops **ops) 2363 { 2364 *ops = &mrvl_flow_ops; 2365 return 0; 2366 } 2367 2368 /** 2369 * DPDK callback to get rte_mtr callbacks. 2370 * 2371 * @param dev 2372 * Pointer to the device structure. 2373 * @param ops 2374 * Pointer to pass the mtr ops. 2375 * 2376 * @return 2377 * Always 0. 2378 */ 2379 static int 2380 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2381 { 2382 *(const void **)ops = &mrvl_mtr_ops; 2383 2384 return 0; 2385 } 2386 2387 /** 2388 * DPDK callback to get rte_tm callbacks. 2389 * 2390 * @param dev 2391 * Pointer to the device structure. 2392 * @param ops 2393 * Pointer to pass the tm ops. 2394 * 2395 * @return 2396 * Always 0. 2397 */ 2398 static int 2399 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2400 { 2401 *(const void **)ops = &mrvl_tm_ops; 2402 2403 return 0; 2404 } 2405 2406 static const struct eth_dev_ops mrvl_ops = { 2407 .dev_configure = mrvl_dev_configure, 2408 .dev_start = mrvl_dev_start, 2409 .dev_stop = mrvl_dev_stop, 2410 .dev_set_link_up = mrvl_dev_set_link_up, 2411 .dev_set_link_down = mrvl_dev_set_link_down, 2412 .dev_close = mrvl_dev_close, 2413 .link_update = mrvl_link_update, 2414 .promiscuous_enable = mrvl_promiscuous_enable, 2415 .allmulticast_enable = mrvl_allmulticast_enable, 2416 .promiscuous_disable = mrvl_promiscuous_disable, 2417 .allmulticast_disable = mrvl_allmulticast_disable, 2418 .mac_addr_remove = mrvl_mac_addr_remove, 2419 .mac_addr_add = mrvl_mac_addr_add, 2420 .mac_addr_set = mrvl_mac_addr_set, 2421 .mtu_set = mrvl_mtu_set, 2422 .stats_get = mrvl_stats_get, 2423 .stats_reset = mrvl_stats_reset, 2424 .xstats_get = mrvl_xstats_get, 2425 .xstats_reset = mrvl_xstats_reset, 2426 .xstats_get_names = mrvl_xstats_get_names, 2427 .dev_infos_get = mrvl_dev_infos_get, 2428 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 2429 .rxq_info_get = mrvl_rxq_info_get, 2430 .txq_info_get = mrvl_txq_info_get, 2431 .vlan_filter_set = mrvl_vlan_filter_set, 2432 .vlan_offload_set = mrvl_vlan_offload_set, 2433 .tx_queue_start = mrvl_tx_queue_start, 2434 .tx_queue_stop = mrvl_tx_queue_stop, 2435 .rx_queue_setup = mrvl_rx_queue_setup, 2436 .rx_queue_release = mrvl_rx_queue_release, 2437 .tx_queue_setup = mrvl_tx_queue_setup, 2438 .tx_queue_release = mrvl_tx_queue_release, 2439 .flow_ctrl_get = mrvl_flow_ctrl_get, 2440 .flow_ctrl_set = mrvl_flow_ctrl_set, 2441 .rss_hash_update = mrvl_rss_hash_update, 2442 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 2443 .flow_ops_get = mrvl_eth_flow_ops_get, 2444 .mtr_ops_get = mrvl_mtr_ops_get, 2445 .tm_ops_get = mrvl_tm_ops_get, 2446 }; 2447 2448 /** 2449 * Return packet type information and l3/l4 offsets. 2450 * 2451 * @param desc 2452 * Pointer to the received packet descriptor. 2453 * @param l3_offset 2454 * l3 packet offset. 2455 * @param l4_offset 2456 * l4 packet offset. 2457 * 2458 * @return 2459 * Packet type information. 2460 */ 2461 static inline uint64_t 2462 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 2463 uint8_t *l3_offset, uint8_t *l4_offset) 2464 { 2465 enum pp2_inq_l3_type l3_type; 2466 enum pp2_inq_l4_type l4_type; 2467 enum pp2_inq_vlan_tag vlan_tag; 2468 uint64_t packet_type; 2469 2470 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 2471 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 2472 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 2473 2474 packet_type = RTE_PTYPE_L2_ETHER; 2475 2476 switch (vlan_tag) { 2477 case PP2_INQ_VLAN_TAG_SINGLE: 2478 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 2479 break; 2480 case PP2_INQ_VLAN_TAG_DOUBLE: 2481 case PP2_INQ_VLAN_TAG_TRIPLE: 2482 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 2483 break; 2484 default: 2485 break; 2486 } 2487 2488 switch (l3_type) { 2489 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 2490 packet_type |= RTE_PTYPE_L3_IPV4; 2491 break; 2492 case PP2_INQ_L3_TYPE_IPV4_OK: 2493 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 2494 break; 2495 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 2496 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 2497 break; 2498 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 2499 packet_type |= RTE_PTYPE_L3_IPV6; 2500 break; 2501 case PP2_INQ_L3_TYPE_IPV6_EXT: 2502 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 2503 break; 2504 case PP2_INQ_L3_TYPE_ARP: 2505 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 2506 /* 2507 * In case of ARP l4_offset is set to wrong value. 2508 * Set it to proper one so that later on mbuf->l3_len can be 2509 * calculated subtracting l4_offset and l3_offset. 2510 */ 2511 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 2512 break; 2513 default: 2514 break; 2515 } 2516 2517 switch (l4_type) { 2518 case PP2_INQ_L4_TYPE_TCP: 2519 packet_type |= RTE_PTYPE_L4_TCP; 2520 break; 2521 case PP2_INQ_L4_TYPE_UDP: 2522 packet_type |= RTE_PTYPE_L4_UDP; 2523 break; 2524 default: 2525 break; 2526 } 2527 2528 return packet_type; 2529 } 2530 2531 /** 2532 * Get offload information from the received packet descriptor. 2533 * 2534 * @param desc 2535 * Pointer to the received packet descriptor. 2536 * 2537 * @return 2538 * Mbuf offload flags. 2539 */ 2540 static inline uint64_t 2541 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc, uint64_t packet_type) 2542 { 2543 uint64_t flags = 0; 2544 enum pp2_inq_desc_status status; 2545 2546 if (RTE_ETH_IS_IPV4_HDR(packet_type)) { 2547 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2548 if (unlikely(status != PP2_DESC_ERR_OK)) 2549 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; 2550 else 2551 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; 2552 } 2553 2554 if (((packet_type & RTE_PTYPE_L4_UDP) == RTE_PTYPE_L4_UDP) || 2555 ((packet_type & RTE_PTYPE_L4_TCP) == RTE_PTYPE_L4_TCP)) { 2556 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2557 if (unlikely(status != PP2_DESC_ERR_OK)) 2558 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD; 2559 else 2560 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; 2561 } 2562 2563 return flags; 2564 } 2565 2566 /** 2567 * DPDK callback for receive. 2568 * 2569 * @param rxq 2570 * Generic pointer to the receive queue. 2571 * @param rx_pkts 2572 * Array to store received packets. 2573 * @param nb_pkts 2574 * Maximum number of packets in array. 2575 * 2576 * @return 2577 * Number of packets successfully received. 2578 */ 2579 static uint16_t 2580 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2581 { 2582 struct mrvl_rxq *q = rxq; 2583 struct pp2_ppio_desc descs[nb_pkts]; 2584 struct pp2_bpool *bpool; 2585 int i, ret, rx_done = 0; 2586 int num; 2587 struct pp2_hif *hif; 2588 unsigned int core_id = rte_lcore_id(); 2589 2590 hif = mrvl_get_hif(q->priv, core_id); 2591 2592 if (unlikely(!q->priv->ppio || !hif)) 2593 return 0; 2594 2595 bpool = q->priv->bpool; 2596 2597 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2598 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2599 if (unlikely(ret < 0)) 2600 return 0; 2601 2602 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2603 2604 for (i = 0; i < nb_pkts; i++) { 2605 struct rte_mbuf *mbuf; 2606 uint8_t l3_offset, l4_offset; 2607 enum pp2_inq_desc_status status; 2608 uint64_t addr; 2609 2610 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2611 struct pp2_ppio_desc *pref_desc; 2612 u64 pref_addr; 2613 2614 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2615 pref_addr = cookie_addr_high | 2616 pp2_ppio_inq_desc_get_cookie(pref_desc); 2617 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2618 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2619 } 2620 2621 addr = cookie_addr_high | 2622 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2623 mbuf = (struct rte_mbuf *)addr; 2624 rte_pktmbuf_reset(mbuf); 2625 2626 /* drop packet in case of mac, overrun or resource error */ 2627 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2628 if ((unlikely(status != PP2_DESC_ERR_OK)) && 2629 !(q->priv->forward_bad_frames)) { 2630 struct pp2_buff_inf binf = { 2631 .addr = rte_mbuf_data_iova_default(mbuf), 2632 .cookie = (uint64_t)mbuf, 2633 }; 2634 2635 pp2_bpool_put_buff(hif, bpool, &binf); 2636 mrvl_port_bpool_size 2637 [bpool->pp2_id][bpool->id][core_id]++; 2638 q->drop_mac++; 2639 continue; 2640 } 2641 2642 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2643 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2644 mbuf->data_len = mbuf->pkt_len; 2645 mbuf->port = q->port_id; 2646 mbuf->packet_type = 2647 mrvl_desc_to_packet_type_and_offset(&descs[i], 2648 &l3_offset, 2649 &l4_offset); 2650 mbuf->l2_len = l3_offset; 2651 mbuf->l3_len = l4_offset - l3_offset; 2652 2653 if (likely(q->cksum_enabled)) 2654 mbuf->ol_flags = 2655 mrvl_desc_to_ol_flags(&descs[i], 2656 mbuf->packet_type); 2657 2658 rx_pkts[rx_done++] = mbuf; 2659 q->bytes_recv += mbuf->pkt_len; 2660 } 2661 2662 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2663 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2664 2665 if (unlikely(num <= q->priv->bpool_min_size || 2666 (!rx_done && num < q->priv->bpool_init_size))) { 2667 mrvl_fill_bpool(q, q->priv->fill_bpool_buffs); 2668 } else if (unlikely(num > q->priv->bpool_max_size)) { 2669 int i; 2670 int pkt_to_remove = num - q->priv->bpool_init_size; 2671 struct rte_mbuf *mbuf; 2672 struct pp2_buff_inf buff; 2673 2674 for (i = 0; i < pkt_to_remove; i++) { 2675 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2676 if (ret) 2677 break; 2678 mbuf = (struct rte_mbuf *) 2679 (cookie_addr_high | buff.cookie); 2680 rte_pktmbuf_free(mbuf); 2681 } 2682 mrvl_port_bpool_size 2683 [bpool->pp2_id][bpool->id][core_id] -= i; 2684 } 2685 rte_spinlock_unlock(&q->priv->lock); 2686 } 2687 2688 return rx_done; 2689 } 2690 2691 /** 2692 * Prepare offload information. 2693 * 2694 * @param ol_flags 2695 * Offload flags. 2696 * @param l3_type 2697 * Pointer to the pp2_ouq_l3_type structure. 2698 * @param l4_type 2699 * Pointer to the pp2_outq_l4_type structure. 2700 * @param gen_l3_cksum 2701 * Will be set to 1 in case l3 checksum is computed. 2702 * @param l4_cksum 2703 * Will be set to 1 in case l4 checksum is computed. 2704 */ 2705 static inline void 2706 mrvl_prepare_proto_info(uint64_t ol_flags, 2707 enum pp2_outq_l3_type *l3_type, 2708 enum pp2_outq_l4_type *l4_type, 2709 int *gen_l3_cksum, 2710 int *gen_l4_cksum) 2711 { 2712 /* 2713 * Based on ol_flags prepare information 2714 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2715 * for offloading. 2716 * in most of the checksum cases ipv4 must be set, so this is the 2717 * default value 2718 */ 2719 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2720 *gen_l3_cksum = ol_flags & RTE_MBUF_F_TX_IP_CKSUM ? 1 : 0; 2721 2722 if (ol_flags & RTE_MBUF_F_TX_IPV6) { 2723 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2724 /* no checksum for ipv6 header */ 2725 *gen_l3_cksum = 0; 2726 } 2727 2728 if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) { 2729 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2730 *gen_l4_cksum = 1; 2731 } else if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_UDP_CKSUM) { 2732 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2733 *gen_l4_cksum = 1; 2734 } else { 2735 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2736 /* no checksum for other type */ 2737 *gen_l4_cksum = 0; 2738 } 2739 } 2740 2741 /** 2742 * Release already sent buffers to bpool (buffer-pool). 2743 * 2744 * @param ppio 2745 * Pointer to the port structure. 2746 * @param hif 2747 * Pointer to the MUSDK hardware interface. 2748 * @param sq 2749 * Pointer to the shadow queue. 2750 * @param qid 2751 * Queue id number. 2752 * @param force 2753 * Force releasing packets. 2754 */ 2755 static inline void 2756 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2757 unsigned int core_id, struct mrvl_shadow_txq *sq, 2758 int qid, int force) 2759 { 2760 struct buff_release_entry *entry; 2761 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2762 int i; 2763 2764 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2765 2766 sq->num_to_release += nb_done; 2767 2768 if (likely(!force && 2769 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2770 return; 2771 2772 nb_done = sq->num_to_release; 2773 sq->num_to_release = 0; 2774 2775 for (i = 0; i < nb_done; i++) { 2776 entry = &sq->ent[sq->tail + num]; 2777 if (unlikely(!entry->buff.addr)) { 2778 MRVL_LOG(ERR, 2779 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2780 sq->tail, (u64)entry->buff.cookie, 2781 (u64)entry->buff.addr); 2782 skip_bufs = 1; 2783 goto skip; 2784 } 2785 2786 if (unlikely(!entry->bpool)) { 2787 struct rte_mbuf *mbuf; 2788 2789 mbuf = (struct rte_mbuf *)entry->buff.cookie; 2790 rte_pktmbuf_free(mbuf); 2791 skip_bufs = 1; 2792 goto skip; 2793 } 2794 2795 mrvl_port_bpool_size 2796 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2797 num++; 2798 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2799 goto skip; 2800 continue; 2801 skip: 2802 if (likely(num)) 2803 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2804 num += skip_bufs; 2805 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2806 sq->size -= num; 2807 num = 0; 2808 skip_bufs = 0; 2809 } 2810 2811 if (likely(num)) { 2812 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2813 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2814 sq->size -= num; 2815 } 2816 } 2817 2818 /** 2819 * DPDK callback for transmit. 2820 * 2821 * @param txq 2822 * Generic pointer transmit queue. 2823 * @param tx_pkts 2824 * Packets to transmit. 2825 * @param nb_pkts 2826 * Number of packets in array. 2827 * 2828 * @return 2829 * Number of packets successfully transmitted. 2830 */ 2831 static uint16_t 2832 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2833 { 2834 struct mrvl_txq *q = txq; 2835 struct mrvl_shadow_txq *sq; 2836 struct pp2_hif *hif; 2837 struct pp2_ppio_desc descs[nb_pkts]; 2838 unsigned int core_id = rte_lcore_id(); 2839 int i, bytes_sent = 0; 2840 uint16_t num, sq_free_size; 2841 uint64_t addr; 2842 2843 hif = mrvl_get_hif(q->priv, core_id); 2844 sq = &q->shadow_txqs[core_id]; 2845 2846 if (unlikely(!q->priv->ppio || !hif)) 2847 return 0; 2848 2849 if (sq->size) 2850 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2851 sq, q->queue_id, 0); 2852 2853 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2854 if (unlikely(nb_pkts > sq_free_size)) 2855 nb_pkts = sq_free_size; 2856 2857 for (i = 0; i < nb_pkts; i++) { 2858 struct rte_mbuf *mbuf = tx_pkts[i]; 2859 int gen_l3_cksum, gen_l4_cksum; 2860 enum pp2_outq_l3_type l3_type; 2861 enum pp2_outq_l4_type l4_type; 2862 2863 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2864 struct rte_mbuf *pref_pkt_hdr; 2865 2866 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2867 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2868 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2869 } 2870 2871 mrvl_fill_shadowq(sq, mbuf); 2872 mrvl_fill_desc(&descs[i], mbuf); 2873 2874 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2875 /* 2876 * in case unsupported ol_flags were passed 2877 * do not update descriptor offload information 2878 */ 2879 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) 2880 continue; 2881 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, 2882 &gen_l3_cksum, &gen_l4_cksum); 2883 2884 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2885 mbuf->l2_len, 2886 mbuf->l2_len + mbuf->l3_len, 2887 gen_l3_cksum, gen_l4_cksum); 2888 } 2889 2890 num = nb_pkts; 2891 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2892 /* number of packets that were not sent */ 2893 if (unlikely(num > nb_pkts)) { 2894 for (i = nb_pkts; i < num; i++) { 2895 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2896 MRVL_PP2_TX_SHADOWQ_MASK; 2897 addr = sq->ent[sq->head].buff.cookie; 2898 bytes_sent -= 2899 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2900 } 2901 sq->size -= num - nb_pkts; 2902 } 2903 2904 q->bytes_sent += bytes_sent; 2905 2906 return nb_pkts; 2907 } 2908 2909 /** DPDK callback for S/G transmit. 2910 * 2911 * @param txq 2912 * Generic pointer transmit queue. 2913 * @param tx_pkts 2914 * Packets to transmit. 2915 * @param nb_pkts 2916 * Number of packets in array. 2917 * 2918 * @return 2919 * Number of packets successfully transmitted. 2920 */ 2921 static uint16_t 2922 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 2923 uint16_t nb_pkts) 2924 { 2925 struct mrvl_txq *q = txq; 2926 struct mrvl_shadow_txq *sq; 2927 struct pp2_hif *hif; 2928 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS]; 2929 struct pp2_ppio_sg_pkts pkts; 2930 uint8_t frags[nb_pkts]; 2931 unsigned int core_id = rte_lcore_id(); 2932 int i, j, bytes_sent = 0; 2933 int tail, tail_first; 2934 uint16_t num, sq_free_size; 2935 uint16_t nb_segs, total_descs = 0; 2936 uint64_t addr; 2937 2938 hif = mrvl_get_hif(q->priv, core_id); 2939 sq = &q->shadow_txqs[core_id]; 2940 pkts.frags = frags; 2941 pkts.num = 0; 2942 2943 if (unlikely(!q->priv->ppio || !hif)) 2944 return 0; 2945 2946 if (sq->size) 2947 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2948 sq, q->queue_id, 0); 2949 2950 /* Save shadow queue free size */ 2951 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2952 2953 tail = 0; 2954 for (i = 0; i < nb_pkts; i++) { 2955 struct rte_mbuf *mbuf = tx_pkts[i]; 2956 struct rte_mbuf *seg = NULL; 2957 int gen_l3_cksum, gen_l4_cksum; 2958 enum pp2_outq_l3_type l3_type; 2959 enum pp2_outq_l4_type l4_type; 2960 2961 nb_segs = mbuf->nb_segs; 2962 tail_first = tail; 2963 total_descs += nb_segs; 2964 2965 /* 2966 * Check if total_descs does not exceed 2967 * shadow queue free size 2968 */ 2969 if (unlikely(total_descs > sq_free_size)) { 2970 total_descs -= nb_segs; 2971 break; 2972 } 2973 2974 /* Check if nb_segs does not exceed the max nb of desc per 2975 * fragmented packet 2976 */ 2977 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) { 2978 total_descs -= nb_segs; 2979 MRVL_LOG(ERR, "Too many segments. Packet won't be sent."); 2980 break; 2981 } 2982 2983 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2984 struct rte_mbuf *pref_pkt_hdr; 2985 2986 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2987 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2988 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2989 } 2990 2991 pkts.frags[pkts.num] = nb_segs; 2992 pkts.num++; 2993 2994 seg = mbuf; 2995 for (j = 0; j < nb_segs - 1; j++) { 2996 /* For the subsequent segments, set shadow queue 2997 * buffer to NULL 2998 */ 2999 mrvl_fill_shadowq(sq, NULL); 3000 mrvl_fill_desc(&descs[tail], seg); 3001 3002 tail++; 3003 seg = seg->next; 3004 } 3005 /* Put first mbuf info in last shadow queue entry */ 3006 mrvl_fill_shadowq(sq, mbuf); 3007 /* Update descriptor with last segment */ 3008 mrvl_fill_desc(&descs[tail++], seg); 3009 3010 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 3011 /* In case unsupported ol_flags were passed 3012 * do not update descriptor offload information 3013 */ 3014 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) 3015 continue; 3016 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, 3017 &gen_l3_cksum, &gen_l4_cksum); 3018 3019 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, 3020 l4_type, mbuf->l2_len, 3021 mbuf->l2_len + mbuf->l3_len, 3022 gen_l3_cksum, gen_l4_cksum); 3023 } 3024 3025 num = total_descs; 3026 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs, 3027 &total_descs, &pkts); 3028 /* number of packets that were not sent */ 3029 if (unlikely(num > total_descs)) { 3030 for (i = total_descs; i < num; i++) { 3031 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 3032 MRVL_PP2_TX_SHADOWQ_MASK; 3033 3034 addr = sq->ent[sq->head].buff.cookie; 3035 if (addr) 3036 bytes_sent -= 3037 rte_pktmbuf_pkt_len((struct rte_mbuf *) 3038 (cookie_addr_high | addr)); 3039 } 3040 sq->size -= num - total_descs; 3041 nb_pkts = pkts.num; 3042 } 3043 3044 q->bytes_sent += bytes_sent; 3045 3046 return nb_pkts; 3047 } 3048 3049 /** 3050 * Create private device structure. 3051 * 3052 * @param dev_name 3053 * Pointer to the port name passed in the initialization parameters. 3054 * 3055 * @return 3056 * Pointer to the newly allocated private device structure. 3057 */ 3058 static struct mrvl_priv * 3059 mrvl_priv_create(const char *dev_name) 3060 { 3061 struct pp2_bpool_params bpool_params; 3062 char match[MRVL_MATCH_LEN]; 3063 struct mrvl_priv *priv; 3064 uint16_t max_frame_size; 3065 int ret, bpool_bit; 3066 3067 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 3068 if (!priv) 3069 return NULL; 3070 3071 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 3072 &priv->pp_id, &priv->ppio_id); 3073 if (ret) 3074 goto out_free_priv; 3075 3076 ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id, 3077 &max_frame_size); 3078 if (ret) 3079 goto out_free_priv; 3080 3081 priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN - 3082 MRVL_PP2_ETH_HDRS_LEN; 3083 3084 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 3085 PP2_BPOOL_NUM_POOLS); 3086 if (bpool_bit < 0) 3087 goto out_free_priv; 3088 priv->bpool_bit = bpool_bit; 3089 3090 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 3091 priv->bpool_bit); 3092 memset(&bpool_params, 0, sizeof(bpool_params)); 3093 bpool_params.match = match; 3094 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 3095 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 3096 if (ret) 3097 goto out_clear_bpool_bit; 3098 3099 priv->ppio_params.type = PP2_PPIO_T_NIC; 3100 rte_spinlock_init(&priv->lock); 3101 3102 return priv; 3103 out_clear_bpool_bit: 3104 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 3105 out_free_priv: 3106 rte_free(priv); 3107 return NULL; 3108 } 3109 3110 /** 3111 * Create device representing Ethernet port. 3112 * 3113 * @param name 3114 * Pointer to the port's name. 3115 * 3116 * @return 3117 * 0 on success, negative error value otherwise. 3118 */ 3119 static int 3120 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 3121 { 3122 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 3123 struct rte_eth_dev *eth_dev; 3124 struct mrvl_priv *priv; 3125 struct ifreq req; 3126 3127 eth_dev = rte_eth_dev_allocate(name); 3128 if (!eth_dev) 3129 return -ENOMEM; 3130 3131 priv = mrvl_priv_create(name); 3132 if (!priv) { 3133 ret = -ENOMEM; 3134 goto out_free; 3135 } 3136 eth_dev->data->dev_private = priv; 3137 3138 eth_dev->data->mac_addrs = 3139 rte_zmalloc("mac_addrs", 3140 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 3141 if (!eth_dev->data->mac_addrs) { 3142 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 3143 ret = -ENOMEM; 3144 goto out_free; 3145 } 3146 3147 memset(&req, 0, sizeof(req)); 3148 strcpy(req.ifr_name, name); 3149 ret = ioctl(fd, SIOCGIFHWADDR, &req); 3150 if (ret) 3151 goto out_free; 3152 3153 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 3154 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN); 3155 3156 eth_dev->device = &vdev->device; 3157 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 3158 mrvl_set_tx_function(eth_dev); 3159 eth_dev->dev_ops = &mrvl_ops; 3160 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 3161 3162 eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 3163 3164 rte_eth_dev_probing_finish(eth_dev); 3165 return 0; 3166 out_free: 3167 rte_eth_dev_release_port(eth_dev); 3168 3169 return ret; 3170 } 3171 3172 /** 3173 * Callback used by rte_kvargs_process() during argument parsing. 3174 * 3175 * @param key 3176 * Pointer to the parsed key (unused). 3177 * @param value 3178 * Pointer to the parsed value. 3179 * @param extra_args 3180 * Pointer to the extra arguments which contains address of the 3181 * table of pointers to parsed interface names. 3182 * 3183 * @return 3184 * Always 0. 3185 */ 3186 static int 3187 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 3188 void *extra_args) 3189 { 3190 struct mrvl_ifnames *ifnames = extra_args; 3191 3192 ifnames->names[ifnames->idx++] = value; 3193 3194 return 0; 3195 } 3196 3197 /** 3198 * DPDK callback to register the virtual device. 3199 * 3200 * @param vdev 3201 * Pointer to the virtual device. 3202 * 3203 * @return 3204 * 0 on success, negative error value otherwise. 3205 */ 3206 static int 3207 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 3208 { 3209 struct rte_kvargs *kvlist; 3210 struct mrvl_ifnames ifnames; 3211 int ret = -EINVAL; 3212 uint32_t i, ifnum, cfgnum; 3213 const char *params; 3214 3215 params = rte_vdev_device_args(vdev); 3216 if (!params) 3217 return -EINVAL; 3218 3219 kvlist = rte_kvargs_parse(params, valid_args); 3220 if (!kvlist) 3221 return -EINVAL; 3222 3223 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 3224 if (ifnum > RTE_DIM(ifnames.names)) 3225 goto out_free_kvlist; 3226 3227 ifnames.idx = 0; 3228 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 3229 mrvl_get_ifnames, &ifnames); 3230 3231 3232 /* 3233 * The below system initialization should be done only once, 3234 * on the first provided configuration file 3235 */ 3236 if (!mrvl_cfg) { 3237 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 3238 MRVL_LOG(INFO, "Parsing config file!"); 3239 if (cfgnum > 1) { 3240 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 3241 goto out_free_kvlist; 3242 } else if (cfgnum == 1) { 3243 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 3244 mrvl_get_cfg, &mrvl_cfg); 3245 } 3246 } 3247 3248 if (mrvl_dev_num) 3249 goto init_devices; 3250 3251 MRVL_LOG(INFO, "Perform MUSDK initializations"); 3252 3253 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 3254 if (ret) 3255 goto out_free_kvlist; 3256 3257 ret = mrvl_init_pp2(); 3258 if (ret) { 3259 MRVL_LOG(ERR, "Failed to init PP!"); 3260 rte_mvep_deinit(MVEP_MOD_T_PP2); 3261 goto out_free_kvlist; 3262 } 3263 3264 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 3265 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 3266 3267 mrvl_lcore_first = RTE_MAX_LCORE; 3268 mrvl_lcore_last = 0; 3269 3270 init_devices: 3271 for (i = 0; i < ifnum; i++) { 3272 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 3273 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 3274 if (ret) 3275 goto out_cleanup; 3276 mrvl_dev_num++; 3277 } 3278 3279 rte_kvargs_free(kvlist); 3280 3281 return 0; 3282 out_cleanup: 3283 rte_pmd_mrvl_remove(vdev); 3284 3285 out_free_kvlist: 3286 rte_kvargs_free(kvlist); 3287 3288 return ret; 3289 } 3290 3291 /** 3292 * DPDK callback to remove virtual device. 3293 * 3294 * @param vdev 3295 * Pointer to the removed virtual device. 3296 * 3297 * @return 3298 * 0 on success, negative error value otherwise. 3299 */ 3300 static int 3301 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 3302 { 3303 uint16_t port_id; 3304 int ret = 0; 3305 3306 RTE_ETH_FOREACH_DEV(port_id) { 3307 if (rte_eth_devices[port_id].device != &vdev->device) 3308 continue; 3309 ret |= rte_eth_dev_close(port_id); 3310 } 3311 3312 return ret == 0 ? 0 : -EIO; 3313 } 3314 3315 static struct rte_vdev_driver pmd_mrvl_drv = { 3316 .probe = rte_pmd_mrvl_probe, 3317 .remove = rte_pmd_mrvl_remove, 3318 }; 3319 3320 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 3321 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 3322 RTE_LOG_REGISTER_DEFAULT(mrvl_logtype, NOTICE); 3323