1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_ethdev_driver.h> 8 #include <rte_kvargs.h> 9 #include <rte_log.h> 10 #include <rte_malloc.h> 11 #include <rte_bus_vdev.h> 12 13 /* Unluckily, container_of is defined by both DPDK and MUSDK, 14 * we'll declare only one version. 15 * 16 * Note that it is not used in this PMD anyway. 17 */ 18 #ifdef container_of 19 #undef container_of 20 #endif 21 22 #include <fcntl.h> 23 #include <linux/ethtool.h> 24 #include <linux/sockios.h> 25 #include <net/if.h> 26 #include <net/if_arp.h> 27 #include <sys/ioctl.h> 28 #include <sys/socket.h> 29 #include <sys/stat.h> 30 #include <sys/types.h> 31 32 #include <rte_mvep_common.h> 33 #include "mrvl_ethdev.h" 34 #include "mrvl_qos.h" 35 36 /* bitmask with reserved hifs */ 37 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 38 /* bitmask with reserved bpools */ 39 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 40 /* bitmask with reserved kernel RSS tables */ 41 #define MRVL_MUSDK_RSS_RESERVED 0x01 42 /* maximum number of available hifs */ 43 #define MRVL_MUSDK_HIFS_MAX 9 44 45 /* prefetch shift */ 46 #define MRVL_MUSDK_PREFETCH_SHIFT 2 47 48 /* TCAM has 25 entries reserved for uc/mc filter entries */ 49 #define MRVL_MAC_ADDRS_MAX 25 50 #define MRVL_MATCH_LEN 16 51 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 52 /* Maximum allowable packet size */ 53 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 54 55 #define MRVL_IFACE_NAME_ARG "iface" 56 #define MRVL_CFG_ARG "cfg" 57 58 #define MRVL_BURST_SIZE 64 59 60 #define MRVL_ARP_LENGTH 28 61 62 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 63 64 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8) 65 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT) 66 67 /** Port Rx offload capabilities */ 68 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ 69 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 70 DEV_RX_OFFLOAD_CHECKSUM) 71 72 /** Port Tx offloads capabilities */ 73 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 74 DEV_TX_OFFLOAD_UDP_CKSUM | \ 75 DEV_TX_OFFLOAD_TCP_CKSUM) 76 77 static const char * const valid_args[] = { 78 MRVL_IFACE_NAME_ARG, 79 MRVL_CFG_ARG, 80 NULL 81 }; 82 83 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 84 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 85 static int used_bpools[PP2_NUM_PKT_PROC] = { 86 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 87 }; 88 89 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 90 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 91 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 92 93 int mrvl_logtype; 94 95 struct mrvl_ifnames { 96 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 97 int idx; 98 }; 99 100 /* 101 * To use buffer harvesting based on loopback port shadow queue structure 102 * was introduced for buffers information bookkeeping. 103 * 104 * Before sending the packet, related buffer information (pp2_buff_inf) is 105 * stored in shadow queue. After packet is transmitted no longer used 106 * packet buffer is released back to it's original hardware pool, 107 * on condition it originated from interface. 108 * In case it was generated by application itself i.e: mbuf->port field is 109 * 0xff then its released to software mempool. 110 */ 111 struct mrvl_shadow_txq { 112 int head; /* write index - used when sending buffers */ 113 int tail; /* read index - used when releasing buffers */ 114 u16 size; /* queue occupied size */ 115 u16 num_to_release; /* number of buffers sent, that can be released */ 116 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 117 }; 118 119 struct mrvl_rxq { 120 struct mrvl_priv *priv; 121 struct rte_mempool *mp; 122 int queue_id; 123 int port_id; 124 int cksum_enabled; 125 uint64_t bytes_recv; 126 uint64_t drop_mac; 127 }; 128 129 struct mrvl_txq { 130 struct mrvl_priv *priv; 131 int queue_id; 132 int port_id; 133 uint64_t bytes_sent; 134 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 135 int tx_deferred_start; 136 }; 137 138 static int mrvl_lcore_first; 139 static int mrvl_lcore_last; 140 static int mrvl_dev_num; 141 142 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 143 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 144 struct pp2_hif *hif, unsigned int core_id, 145 struct mrvl_shadow_txq *sq, int qid, int force); 146 147 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 148 #name, offsetof(struct pp2_ppio_statistics, name), \ 149 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 150 } 151 152 /* Table with xstats data */ 153 static struct { 154 const char *name; 155 unsigned int offset; 156 unsigned int size; 157 } mrvl_xstats_tbl[] = { 158 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 159 MRVL_XSTATS_TBL_ENTRY(rx_packets), 160 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 161 MRVL_XSTATS_TBL_ENTRY(rx_errors), 162 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 163 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 164 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 165 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 166 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 167 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 168 MRVL_XSTATS_TBL_ENTRY(tx_packets), 169 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 170 MRVL_XSTATS_TBL_ENTRY(tx_errors) 171 }; 172 173 static inline int 174 mrvl_get_bpool_size(int pp2_id, int pool_id) 175 { 176 int i; 177 int size = 0; 178 179 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 180 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 181 182 return size; 183 } 184 185 static inline int 186 mrvl_reserve_bit(int *bitmap, int max) 187 { 188 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 189 190 if (n >= max) 191 return -1; 192 193 *bitmap |= 1 << n; 194 195 return n; 196 } 197 198 static int 199 mrvl_init_hif(int core_id) 200 { 201 struct pp2_hif_params params; 202 char match[MRVL_MATCH_LEN]; 203 int ret; 204 205 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 206 if (ret < 0) { 207 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 208 return ret; 209 } 210 211 snprintf(match, sizeof(match), "hif-%d", ret); 212 memset(¶ms, 0, sizeof(params)); 213 params.match = match; 214 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 215 ret = pp2_hif_init(¶ms, &hifs[core_id]); 216 if (ret) { 217 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 218 return ret; 219 } 220 221 return 0; 222 } 223 224 static inline struct pp2_hif* 225 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 226 { 227 int ret; 228 229 if (likely(hifs[core_id] != NULL)) 230 return hifs[core_id]; 231 232 rte_spinlock_lock(&priv->lock); 233 234 ret = mrvl_init_hif(core_id); 235 if (ret < 0) { 236 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 237 goto out; 238 } 239 240 if (core_id < mrvl_lcore_first) 241 mrvl_lcore_first = core_id; 242 243 if (core_id > mrvl_lcore_last) 244 mrvl_lcore_last = core_id; 245 out: 246 rte_spinlock_unlock(&priv->lock); 247 248 return hifs[core_id]; 249 } 250 251 /** 252 * Configure rss based on dpdk rss configuration. 253 * 254 * @param priv 255 * Pointer to private structure. 256 * @param rss_conf 257 * Pointer to RSS configuration. 258 * 259 * @return 260 * 0 on success, negative error value otherwise. 261 */ 262 static int 263 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 264 { 265 if (rss_conf->rss_key) 266 MRVL_LOG(WARNING, "Changing hash key is not supported"); 267 268 if (rss_conf->rss_hf == 0) { 269 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 270 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { 271 priv->ppio_params.inqs_params.hash_type = 272 PP2_PPIO_HASH_T_2_TUPLE; 273 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 274 priv->ppio_params.inqs_params.hash_type = 275 PP2_PPIO_HASH_T_5_TUPLE; 276 priv->rss_hf_tcp = 1; 277 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 278 priv->ppio_params.inqs_params.hash_type = 279 PP2_PPIO_HASH_T_5_TUPLE; 280 priv->rss_hf_tcp = 0; 281 } else { 282 return -EINVAL; 283 } 284 285 return 0; 286 } 287 288 /** 289 * Ethernet device configuration. 290 * 291 * Prepare the driver for a given number of TX and RX queues and 292 * configure RSS. 293 * 294 * @param dev 295 * Pointer to Ethernet device structure. 296 * 297 * @return 298 * 0 on success, negative error value otherwise. 299 */ 300 static int 301 mrvl_dev_configure(struct rte_eth_dev *dev) 302 { 303 struct mrvl_priv *priv = dev->data->dev_private; 304 int ret; 305 306 if (priv->ppio) { 307 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 308 return -EINVAL; 309 } 310 311 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && 312 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 313 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 314 dev->data->dev_conf.rxmode.mq_mode); 315 return -EINVAL; 316 } 317 318 if (dev->data->dev_conf.rxmode.split_hdr_size) { 319 MRVL_LOG(INFO, "Split headers not supported"); 320 return -EINVAL; 321 } 322 323 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 324 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 325 ETHER_HDR_LEN - ETHER_CRC_LEN; 326 327 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 328 dev->data->nb_rx_queues); 329 if (ret < 0) 330 return ret; 331 332 ret = mrvl_configure_txqs(priv, dev->data->port_id, 333 dev->data->nb_tx_queues); 334 if (ret < 0) 335 return ret; 336 337 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 338 priv->ppio_params.maintain_stats = 1; 339 priv->nb_rx_queues = dev->data->nb_rx_queues; 340 341 if (dev->data->nb_rx_queues == 1 && 342 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 343 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 344 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 345 346 return 0; 347 } 348 349 return mrvl_configure_rss(priv, 350 &dev->data->dev_conf.rx_adv_conf.rss_conf); 351 } 352 353 /** 354 * DPDK callback to change the MTU. 355 * 356 * Setting the MTU affects hardware MRU (packets larger than the MRU 357 * will be dropped). 358 * 359 * @param dev 360 * Pointer to Ethernet device structure. 361 * @param mtu 362 * New MTU. 363 * 364 * @return 365 * 0 on success, negative error value otherwise. 366 */ 367 static int 368 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 369 { 370 struct mrvl_priv *priv = dev->data->dev_private; 371 /* extra MV_MH_SIZE bytes are required for Marvell tag */ 372 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN; 373 int ret; 374 375 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) 376 return -EINVAL; 377 378 if (!priv->ppio) 379 return 0; 380 381 ret = pp2_ppio_set_mru(priv->ppio, mru); 382 if (ret) 383 return ret; 384 385 return pp2_ppio_set_mtu(priv->ppio, mtu); 386 } 387 388 /** 389 * DPDK callback to bring the link up. 390 * 391 * @param dev 392 * Pointer to Ethernet device structure. 393 * 394 * @return 395 * 0 on success, negative error value otherwise. 396 */ 397 static int 398 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 399 { 400 struct mrvl_priv *priv = dev->data->dev_private; 401 int ret; 402 403 if (!priv->ppio) 404 return -EPERM; 405 406 ret = pp2_ppio_enable(priv->ppio); 407 if (ret) 408 return ret; 409 410 /* 411 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 412 * as pp2_ppio_enable() changes port->t_mode from default 0 to 413 * PP2_TRAFFIC_INGRESS_EGRESS. 414 * 415 * Set mtu to default DPDK value here. 416 */ 417 ret = mrvl_mtu_set(dev, dev->data->mtu); 418 if (ret) 419 pp2_ppio_disable(priv->ppio); 420 421 return ret; 422 } 423 424 /** 425 * DPDK callback to bring the link down. 426 * 427 * @param dev 428 * Pointer to Ethernet device structure. 429 * 430 * @return 431 * 0 on success, negative error value otherwise. 432 */ 433 static int 434 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 435 { 436 struct mrvl_priv *priv = dev->data->dev_private; 437 438 if (!priv->ppio) 439 return -EPERM; 440 441 return pp2_ppio_disable(priv->ppio); 442 } 443 444 /** 445 * DPDK callback to start tx queue. 446 * 447 * @param dev 448 * Pointer to Ethernet device structure. 449 * @param queue_id 450 * Transmit queue index. 451 * 452 * @return 453 * 0 on success, negative error value otherwise. 454 */ 455 static int 456 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 457 { 458 struct mrvl_priv *priv = dev->data->dev_private; 459 int ret; 460 461 if (!priv) 462 return -EPERM; 463 464 /* passing 1 enables given tx queue */ 465 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 466 if (ret) { 467 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 468 return ret; 469 } 470 471 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 472 473 return 0; 474 } 475 476 /** 477 * DPDK callback to stop tx queue. 478 * 479 * @param dev 480 * Pointer to Ethernet device structure. 481 * @param queue_id 482 * Transmit queue index. 483 * 484 * @return 485 * 0 on success, negative error value otherwise. 486 */ 487 static int 488 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 489 { 490 struct mrvl_priv *priv = dev->data->dev_private; 491 int ret; 492 493 if (!priv->ppio) 494 return -EPERM; 495 496 /* passing 0 disables given tx queue */ 497 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 498 if (ret) { 499 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 500 return ret; 501 } 502 503 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 504 505 return 0; 506 } 507 508 /** 509 * DPDK callback to start the device. 510 * 511 * @param dev 512 * Pointer to Ethernet device structure. 513 * 514 * @return 515 * 0 on success, negative errno value on failure. 516 */ 517 static int 518 mrvl_dev_start(struct rte_eth_dev *dev) 519 { 520 struct mrvl_priv *priv = dev->data->dev_private; 521 char match[MRVL_MATCH_LEN]; 522 int ret = 0, i, def_init_size; 523 524 if (priv->ppio) 525 return mrvl_dev_set_link_up(dev); 526 527 snprintf(match, sizeof(match), "ppio-%d:%d", 528 priv->pp_id, priv->ppio_id); 529 priv->ppio_params.match = match; 530 531 /* 532 * Calculate the minimum bpool size for refill feature as follows: 533 * 2 default burst sizes multiply by number of rx queues. 534 * If the bpool size will be below this value, new buffers will 535 * be added to the pool. 536 */ 537 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 538 539 /* In case initial bpool size configured in queues setup is 540 * smaller than minimum size add more buffers 541 */ 542 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 543 if (priv->bpool_init_size < def_init_size) { 544 int buffs_to_add = def_init_size - priv->bpool_init_size; 545 546 priv->bpool_init_size += buffs_to_add; 547 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 548 if (ret) 549 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 550 } 551 552 /* 553 * Calculate the maximum bpool size for refill feature as follows: 554 * maximum number of descriptors in rx queue multiply by number 555 * of rx queues plus minimum bpool size. 556 * In case the bpool size will exceed this value, superfluous buffers 557 * will be removed 558 */ 559 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 560 priv->bpool_min_size; 561 562 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 563 if (ret) { 564 MRVL_LOG(ERR, "Failed to init ppio"); 565 return ret; 566 } 567 568 /* 569 * In case there are some some stale uc/mc mac addresses flush them 570 * here. It cannot be done during mrvl_dev_close() as port information 571 * is already gone at that point (due to pp2_ppio_deinit() in 572 * mrvl_dev_stop()). 573 */ 574 if (!priv->uc_mc_flushed) { 575 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 576 if (ret) { 577 MRVL_LOG(ERR, 578 "Failed to flush uc/mc filter list"); 579 goto out; 580 } 581 priv->uc_mc_flushed = 1; 582 } 583 584 if (!priv->vlan_flushed) { 585 ret = pp2_ppio_flush_vlan(priv->ppio); 586 if (ret) { 587 MRVL_LOG(ERR, "Failed to flush vlan list"); 588 /* 589 * TODO 590 * once pp2_ppio_flush_vlan() is supported jump to out 591 * goto out; 592 */ 593 } 594 priv->vlan_flushed = 1; 595 } 596 597 /* For default QoS config, don't start classifier. */ 598 if (mrvl_qos_cfg) { 599 ret = mrvl_start_qos_mapping(priv); 600 if (ret) { 601 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 602 goto out; 603 } 604 } 605 606 ret = mrvl_dev_set_link_up(dev); 607 if (ret) { 608 MRVL_LOG(ERR, "Failed to set link up"); 609 goto out; 610 } 611 612 /* start tx queues */ 613 for (i = 0; i < dev->data->nb_tx_queues; i++) { 614 struct mrvl_txq *txq = dev->data->tx_queues[i]; 615 616 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 617 618 if (!txq->tx_deferred_start) 619 continue; 620 621 /* 622 * All txqs are started by default. Stop them 623 * so that tx_deferred_start works as expected. 624 */ 625 ret = mrvl_tx_queue_stop(dev, i); 626 if (ret) 627 goto out; 628 } 629 630 return 0; 631 out: 632 MRVL_LOG(ERR, "Failed to start device"); 633 pp2_ppio_deinit(priv->ppio); 634 return ret; 635 } 636 637 /** 638 * Flush receive queues. 639 * 640 * @param dev 641 * Pointer to Ethernet device structure. 642 */ 643 static void 644 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 645 { 646 int i; 647 648 MRVL_LOG(INFO, "Flushing rx queues"); 649 for (i = 0; i < dev->data->nb_rx_queues; i++) { 650 int ret, num; 651 652 do { 653 struct mrvl_rxq *q = dev->data->rx_queues[i]; 654 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 655 656 num = MRVL_PP2_RXD_MAX; 657 ret = pp2_ppio_recv(q->priv->ppio, 658 q->priv->rxq_map[q->queue_id].tc, 659 q->priv->rxq_map[q->queue_id].inq, 660 descs, (uint16_t *)&num); 661 } while (ret == 0 && num); 662 } 663 } 664 665 /** 666 * Flush transmit shadow queues. 667 * 668 * @param dev 669 * Pointer to Ethernet device structure. 670 */ 671 static void 672 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 673 { 674 int i, j; 675 struct mrvl_txq *txq; 676 677 MRVL_LOG(INFO, "Flushing tx shadow queues"); 678 for (i = 0; i < dev->data->nb_tx_queues; i++) { 679 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 680 681 for (j = 0; j < RTE_MAX_LCORE; j++) { 682 struct mrvl_shadow_txq *sq; 683 684 if (!hifs[j]) 685 continue; 686 687 sq = &txq->shadow_txqs[j]; 688 mrvl_free_sent_buffers(txq->priv->ppio, 689 hifs[j], j, sq, txq->queue_id, 1); 690 while (sq->tail != sq->head) { 691 uint64_t addr = cookie_addr_high | 692 sq->ent[sq->tail].buff.cookie; 693 rte_pktmbuf_free( 694 (struct rte_mbuf *)addr); 695 sq->tail = (sq->tail + 1) & 696 MRVL_PP2_TX_SHADOWQ_MASK; 697 } 698 memset(sq, 0, sizeof(*sq)); 699 } 700 } 701 } 702 703 /** 704 * Flush hardware bpool (buffer-pool). 705 * 706 * @param dev 707 * Pointer to Ethernet device structure. 708 */ 709 static void 710 mrvl_flush_bpool(struct rte_eth_dev *dev) 711 { 712 struct mrvl_priv *priv = dev->data->dev_private; 713 struct pp2_hif *hif; 714 uint32_t num; 715 int ret; 716 unsigned int core_id = rte_lcore_id(); 717 718 if (core_id == LCORE_ID_ANY) 719 core_id = 0; 720 721 hif = mrvl_get_hif(priv, core_id); 722 723 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 724 if (ret) { 725 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 726 return; 727 } 728 729 while (num--) { 730 struct pp2_buff_inf inf; 731 uint64_t addr; 732 733 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 734 if (ret) 735 break; 736 737 addr = cookie_addr_high | inf.cookie; 738 rte_pktmbuf_free((struct rte_mbuf *)addr); 739 } 740 } 741 742 /** 743 * DPDK callback to stop the device. 744 * 745 * @param dev 746 * Pointer to Ethernet device structure. 747 */ 748 static void 749 mrvl_dev_stop(struct rte_eth_dev *dev) 750 { 751 mrvl_dev_set_link_down(dev); 752 } 753 754 /** 755 * DPDK callback to close the device. 756 * 757 * @param dev 758 * Pointer to Ethernet device structure. 759 */ 760 static void 761 mrvl_dev_close(struct rte_eth_dev *dev) 762 { 763 struct mrvl_priv *priv = dev->data->dev_private; 764 size_t i; 765 766 mrvl_flush_rx_queues(dev); 767 mrvl_flush_tx_shadow_queues(dev); 768 769 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 770 struct pp2_ppio_tc_params *tc_params = 771 &priv->ppio_params.inqs_params.tcs_params[i]; 772 773 if (tc_params->inqs_params) { 774 rte_free(tc_params->inqs_params); 775 tc_params->inqs_params = NULL; 776 } 777 } 778 779 if (priv->cls_tbl) { 780 pp2_cls_tbl_deinit(priv->cls_tbl); 781 priv->cls_tbl = NULL; 782 } 783 784 if (priv->qos_tbl) { 785 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 786 priv->qos_tbl = NULL; 787 } 788 789 mrvl_flush_bpool(dev); 790 791 if (priv->ppio) { 792 pp2_ppio_deinit(priv->ppio); 793 priv->ppio = NULL; 794 } 795 796 /* policer must be released after ppio deinitialization */ 797 if (priv->policer) { 798 pp2_cls_plcr_deinit(priv->policer); 799 priv->policer = NULL; 800 } 801 } 802 803 /** 804 * DPDK callback to retrieve physical link information. 805 * 806 * @param dev 807 * Pointer to Ethernet device structure. 808 * @param wait_to_complete 809 * Wait for request completion (ignored). 810 * 811 * @return 812 * 0 on success, negative error value otherwise. 813 */ 814 static int 815 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 816 { 817 /* 818 * TODO 819 * once MUSDK provides necessary API use it here 820 */ 821 struct mrvl_priv *priv = dev->data->dev_private; 822 struct ethtool_cmd edata; 823 struct ifreq req; 824 int ret, fd, link_up; 825 826 if (!priv->ppio) 827 return -EPERM; 828 829 edata.cmd = ETHTOOL_GSET; 830 831 strcpy(req.ifr_name, dev->data->name); 832 req.ifr_data = (void *)&edata; 833 834 fd = socket(AF_INET, SOCK_DGRAM, 0); 835 if (fd == -1) 836 return -EFAULT; 837 838 ret = ioctl(fd, SIOCETHTOOL, &req); 839 if (ret == -1) { 840 close(fd); 841 return -EFAULT; 842 } 843 844 close(fd); 845 846 switch (ethtool_cmd_speed(&edata)) { 847 case SPEED_10: 848 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M; 849 break; 850 case SPEED_100: 851 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M; 852 break; 853 case SPEED_1000: 854 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; 855 break; 856 case SPEED_10000: 857 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; 858 break; 859 default: 860 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; 861 } 862 863 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : 864 ETH_LINK_HALF_DUPLEX; 865 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : 866 ETH_LINK_FIXED; 867 pp2_ppio_get_link_state(priv->ppio, &link_up); 868 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 869 870 return 0; 871 } 872 873 /** 874 * DPDK callback to enable promiscuous mode. 875 * 876 * @param dev 877 * Pointer to Ethernet device structure. 878 */ 879 static void 880 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 881 { 882 struct mrvl_priv *priv = dev->data->dev_private; 883 int ret; 884 885 if (!priv->ppio) 886 return; 887 888 if (priv->isolated) 889 return; 890 891 ret = pp2_ppio_set_promisc(priv->ppio, 1); 892 if (ret) 893 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 894 } 895 896 /** 897 * DPDK callback to enable allmulti mode. 898 * 899 * @param dev 900 * Pointer to Ethernet device structure. 901 */ 902 static void 903 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 904 { 905 struct mrvl_priv *priv = dev->data->dev_private; 906 int ret; 907 908 if (!priv->ppio) 909 return; 910 911 if (priv->isolated) 912 return; 913 914 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 915 if (ret) 916 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 917 } 918 919 /** 920 * DPDK callback to disable promiscuous mode. 921 * 922 * @param dev 923 * Pointer to Ethernet device structure. 924 */ 925 static void 926 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 927 { 928 struct mrvl_priv *priv = dev->data->dev_private; 929 int ret; 930 931 if (!priv->ppio) 932 return; 933 934 ret = pp2_ppio_set_promisc(priv->ppio, 0); 935 if (ret) 936 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 937 } 938 939 /** 940 * DPDK callback to disable allmulticast mode. 941 * 942 * @param dev 943 * Pointer to Ethernet device structure. 944 */ 945 static void 946 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 947 { 948 struct mrvl_priv *priv = dev->data->dev_private; 949 int ret; 950 951 if (!priv->ppio) 952 return; 953 954 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 955 if (ret) 956 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 957 } 958 959 /** 960 * DPDK callback to remove a MAC address. 961 * 962 * @param dev 963 * Pointer to Ethernet device structure. 964 * @param index 965 * MAC address index. 966 */ 967 static void 968 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 969 { 970 struct mrvl_priv *priv = dev->data->dev_private; 971 char buf[ETHER_ADDR_FMT_SIZE]; 972 int ret; 973 974 if (!priv->ppio) 975 return; 976 977 if (priv->isolated) 978 return; 979 980 ret = pp2_ppio_remove_mac_addr(priv->ppio, 981 dev->data->mac_addrs[index].addr_bytes); 982 if (ret) { 983 ether_format_addr(buf, sizeof(buf), 984 &dev->data->mac_addrs[index]); 985 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 986 } 987 } 988 989 /** 990 * DPDK callback to add a MAC address. 991 * 992 * @param dev 993 * Pointer to Ethernet device structure. 994 * @param mac_addr 995 * MAC address to register. 996 * @param index 997 * MAC address index. 998 * @param vmdq 999 * VMDq pool index to associate address with (unused). 1000 * 1001 * @return 1002 * 0 on success, negative error value otherwise. 1003 */ 1004 static int 1005 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 1006 uint32_t index, uint32_t vmdq __rte_unused) 1007 { 1008 struct mrvl_priv *priv = dev->data->dev_private; 1009 char buf[ETHER_ADDR_FMT_SIZE]; 1010 int ret; 1011 1012 if (priv->isolated) 1013 return -ENOTSUP; 1014 1015 if (index == 0) 1016 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1017 return -1; 1018 1019 if (!priv->ppio) 1020 return 0; 1021 1022 /* 1023 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1024 * parameter uc_filter_max. Maximum number of mc addresses is then 1025 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1026 * 21 respectively. 1027 * 1028 * If more than uc_filter_max uc addresses were added to filter list 1029 * then NIC will switch to promiscuous mode automatically. 1030 * 1031 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1032 * were added to filter list then NIC will switch to all-multicast mode 1033 * automatically. 1034 */ 1035 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1036 if (ret) { 1037 ether_format_addr(buf, sizeof(buf), mac_addr); 1038 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1039 return -1; 1040 } 1041 1042 return 0; 1043 } 1044 1045 /** 1046 * DPDK callback to set the primary MAC address. 1047 * 1048 * @param dev 1049 * Pointer to Ethernet device structure. 1050 * @param mac_addr 1051 * MAC address to register. 1052 * 1053 * @return 1054 * 0 on success, negative error value otherwise. 1055 */ 1056 static int 1057 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 1058 { 1059 struct mrvl_priv *priv = dev->data->dev_private; 1060 int ret; 1061 1062 if (!priv->ppio) 1063 return 0; 1064 1065 if (priv->isolated) 1066 return -ENOTSUP; 1067 1068 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1069 if (ret) { 1070 char buf[ETHER_ADDR_FMT_SIZE]; 1071 ether_format_addr(buf, sizeof(buf), mac_addr); 1072 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1073 } 1074 1075 return ret; 1076 } 1077 1078 /** 1079 * DPDK callback to get device statistics. 1080 * 1081 * @param dev 1082 * Pointer to Ethernet device structure. 1083 * @param stats 1084 * Stats structure output buffer. 1085 * 1086 * @return 1087 * 0 on success, negative error value otherwise. 1088 */ 1089 static int 1090 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1091 { 1092 struct mrvl_priv *priv = dev->data->dev_private; 1093 struct pp2_ppio_statistics ppio_stats; 1094 uint64_t drop_mac = 0; 1095 unsigned int i, idx, ret; 1096 1097 if (!priv->ppio) 1098 return -EPERM; 1099 1100 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1101 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1102 struct pp2_ppio_inq_statistics rx_stats; 1103 1104 if (!rxq) 1105 continue; 1106 1107 idx = rxq->queue_id; 1108 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1109 MRVL_LOG(ERR, 1110 "rx queue %d stats out of range (0 - %d)", 1111 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1112 continue; 1113 } 1114 1115 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1116 priv->rxq_map[idx].tc, 1117 priv->rxq_map[idx].inq, 1118 &rx_stats, 0); 1119 if (unlikely(ret)) { 1120 MRVL_LOG(ERR, 1121 "Failed to update rx queue %d stats", idx); 1122 break; 1123 } 1124 1125 stats->q_ibytes[idx] = rxq->bytes_recv; 1126 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1127 stats->q_errors[idx] = rx_stats.drop_early + 1128 rx_stats.drop_fullq + 1129 rx_stats.drop_bm + 1130 rxq->drop_mac; 1131 stats->ibytes += rxq->bytes_recv; 1132 drop_mac += rxq->drop_mac; 1133 } 1134 1135 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1136 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1137 struct pp2_ppio_outq_statistics tx_stats; 1138 1139 if (!txq) 1140 continue; 1141 1142 idx = txq->queue_id; 1143 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1144 MRVL_LOG(ERR, 1145 "tx queue %d stats out of range (0 - %d)", 1146 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1147 } 1148 1149 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1150 &tx_stats, 0); 1151 if (unlikely(ret)) { 1152 MRVL_LOG(ERR, 1153 "Failed to update tx queue %d stats", idx); 1154 break; 1155 } 1156 1157 stats->q_opackets[idx] = tx_stats.deq_desc; 1158 stats->q_obytes[idx] = txq->bytes_sent; 1159 stats->obytes += txq->bytes_sent; 1160 } 1161 1162 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1163 if (unlikely(ret)) { 1164 MRVL_LOG(ERR, "Failed to update port statistics"); 1165 return ret; 1166 } 1167 1168 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1169 stats->opackets += ppio_stats.tx_packets; 1170 stats->imissed += ppio_stats.rx_fullq_dropped + 1171 ppio_stats.rx_bm_dropped + 1172 ppio_stats.rx_early_dropped + 1173 ppio_stats.rx_fifo_dropped + 1174 ppio_stats.rx_cls_dropped; 1175 stats->ierrors = drop_mac; 1176 1177 return 0; 1178 } 1179 1180 /** 1181 * DPDK callback to clear device statistics. 1182 * 1183 * @param dev 1184 * Pointer to Ethernet device structure. 1185 */ 1186 static void 1187 mrvl_stats_reset(struct rte_eth_dev *dev) 1188 { 1189 struct mrvl_priv *priv = dev->data->dev_private; 1190 int i; 1191 1192 if (!priv->ppio) 1193 return; 1194 1195 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1196 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1197 1198 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1199 priv->rxq_map[i].inq, NULL, 1); 1200 rxq->bytes_recv = 0; 1201 rxq->drop_mac = 0; 1202 } 1203 1204 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1205 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1206 1207 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1208 txq->bytes_sent = 0; 1209 } 1210 1211 pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1212 } 1213 1214 /** 1215 * DPDK callback to get extended statistics. 1216 * 1217 * @param dev 1218 * Pointer to Ethernet device structure. 1219 * @param stats 1220 * Pointer to xstats table. 1221 * @param n 1222 * Number of entries in xstats table. 1223 * @return 1224 * Negative value on error, number of read xstats otherwise. 1225 */ 1226 static int 1227 mrvl_xstats_get(struct rte_eth_dev *dev, 1228 struct rte_eth_xstat *stats, unsigned int n) 1229 { 1230 struct mrvl_priv *priv = dev->data->dev_private; 1231 struct pp2_ppio_statistics ppio_stats; 1232 unsigned int i; 1233 1234 if (!stats) 1235 return 0; 1236 1237 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1238 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) { 1239 uint64_t val; 1240 1241 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1242 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1243 mrvl_xstats_tbl[i].offset); 1244 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1245 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1246 mrvl_xstats_tbl[i].offset); 1247 else 1248 return -EINVAL; 1249 1250 stats[i].id = i; 1251 stats[i].value = val; 1252 } 1253 1254 return n; 1255 } 1256 1257 /** 1258 * DPDK callback to reset extended statistics. 1259 * 1260 * @param dev 1261 * Pointer to Ethernet device structure. 1262 */ 1263 static void 1264 mrvl_xstats_reset(struct rte_eth_dev *dev) 1265 { 1266 mrvl_stats_reset(dev); 1267 } 1268 1269 /** 1270 * DPDK callback to get extended statistics names. 1271 * 1272 * @param dev (unused) 1273 * Pointer to Ethernet device structure. 1274 * @param xstats_names 1275 * Pointer to xstats names table. 1276 * @param size 1277 * Size of the xstats names table. 1278 * @return 1279 * Number of read names. 1280 */ 1281 static int 1282 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1283 struct rte_eth_xstat_name *xstats_names, 1284 unsigned int size) 1285 { 1286 unsigned int i; 1287 1288 if (!xstats_names) 1289 return RTE_DIM(mrvl_xstats_tbl); 1290 1291 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1292 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s", 1293 mrvl_xstats_tbl[i].name); 1294 1295 return size; 1296 } 1297 1298 /** 1299 * DPDK callback to get information about the device. 1300 * 1301 * @param dev 1302 * Pointer to Ethernet device structure (unused). 1303 * @param info 1304 * Info structure output buffer. 1305 */ 1306 static void 1307 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 1308 struct rte_eth_dev_info *info) 1309 { 1310 info->speed_capa = ETH_LINK_SPEED_10M | 1311 ETH_LINK_SPEED_100M | 1312 ETH_LINK_SPEED_1G | 1313 ETH_LINK_SPEED_10G; 1314 1315 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1316 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1317 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1318 1319 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1320 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1321 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1322 1323 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1324 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1325 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1326 1327 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1328 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1329 1330 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1331 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1332 1333 info->flow_type_rss_offloads = ETH_RSS_IPV4 | 1334 ETH_RSS_NONFRAG_IPV4_TCP | 1335 ETH_RSS_NONFRAG_IPV4_UDP; 1336 1337 /* By default packets are dropped if no descriptors are available */ 1338 info->default_rxconf.rx_drop_en = 1; 1339 1340 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1341 } 1342 1343 /** 1344 * Return supported packet types. 1345 * 1346 * @param dev 1347 * Pointer to Ethernet device structure (unused). 1348 * 1349 * @return 1350 * Const pointer to the table with supported packet types. 1351 */ 1352 static const uint32_t * 1353 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1354 { 1355 static const uint32_t ptypes[] = { 1356 RTE_PTYPE_L2_ETHER, 1357 RTE_PTYPE_L2_ETHER_VLAN, 1358 RTE_PTYPE_L2_ETHER_QINQ, 1359 RTE_PTYPE_L3_IPV4, 1360 RTE_PTYPE_L3_IPV4_EXT, 1361 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1362 RTE_PTYPE_L3_IPV6, 1363 RTE_PTYPE_L3_IPV6_EXT, 1364 RTE_PTYPE_L2_ETHER_ARP, 1365 RTE_PTYPE_L4_TCP, 1366 RTE_PTYPE_L4_UDP 1367 }; 1368 1369 return ptypes; 1370 } 1371 1372 /** 1373 * DPDK callback to get information about specific receive queue. 1374 * 1375 * @param dev 1376 * Pointer to Ethernet device structure. 1377 * @param rx_queue_id 1378 * Receive queue index. 1379 * @param qinfo 1380 * Receive queue information structure. 1381 */ 1382 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1383 struct rte_eth_rxq_info *qinfo) 1384 { 1385 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1386 struct mrvl_priv *priv = dev->data->dev_private; 1387 int inq = priv->rxq_map[rx_queue_id].inq; 1388 int tc = priv->rxq_map[rx_queue_id].tc; 1389 struct pp2_ppio_tc_params *tc_params = 1390 &priv->ppio_params.inqs_params.tcs_params[tc]; 1391 1392 qinfo->mp = q->mp; 1393 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1394 } 1395 1396 /** 1397 * DPDK callback to get information about specific transmit queue. 1398 * 1399 * @param dev 1400 * Pointer to Ethernet device structure. 1401 * @param tx_queue_id 1402 * Transmit queue index. 1403 * @param qinfo 1404 * Transmit queue information structure. 1405 */ 1406 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1407 struct rte_eth_txq_info *qinfo) 1408 { 1409 struct mrvl_priv *priv = dev->data->dev_private; 1410 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1411 1412 qinfo->nb_desc = 1413 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1414 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1415 } 1416 1417 /** 1418 * DPDK callback to Configure a VLAN filter. 1419 * 1420 * @param dev 1421 * Pointer to Ethernet device structure. 1422 * @param vlan_id 1423 * VLAN ID to filter. 1424 * @param on 1425 * Toggle filter. 1426 * 1427 * @return 1428 * 0 on success, negative error value otherwise. 1429 */ 1430 static int 1431 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1432 { 1433 struct mrvl_priv *priv = dev->data->dev_private; 1434 1435 if (!priv->ppio) 1436 return -EPERM; 1437 1438 if (priv->isolated) 1439 return -ENOTSUP; 1440 1441 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1442 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1443 } 1444 1445 /** 1446 * Release buffers to hardware bpool (buffer-pool) 1447 * 1448 * @param rxq 1449 * Receive queue pointer. 1450 * @param num 1451 * Number of buffers to release to bpool. 1452 * 1453 * @return 1454 * 0 on success, negative error value otherwise. 1455 */ 1456 static int 1457 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1458 { 1459 struct buff_release_entry entries[MRVL_PP2_RXD_MAX]; 1460 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX]; 1461 int i, ret; 1462 unsigned int core_id; 1463 struct pp2_hif *hif; 1464 struct pp2_bpool *bpool; 1465 1466 core_id = rte_lcore_id(); 1467 if (core_id == LCORE_ID_ANY) 1468 core_id = 0; 1469 1470 hif = mrvl_get_hif(rxq->priv, core_id); 1471 if (!hif) 1472 return -1; 1473 1474 bpool = rxq->priv->bpool; 1475 1476 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1477 if (ret) 1478 return ret; 1479 1480 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1481 cookie_addr_high = 1482 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1483 1484 for (i = 0; i < num; i++) { 1485 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1486 != cookie_addr_high) { 1487 MRVL_LOG(ERR, 1488 "mbuf virtual addr high 0x%lx out of range", 1489 (uint64_t)mbufs[i] >> 32); 1490 goto out; 1491 } 1492 1493 entries[i].buff.addr = 1494 rte_mbuf_data_iova_default(mbufs[i]); 1495 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i]; 1496 entries[i].bpool = bpool; 1497 } 1498 1499 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1500 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1501 1502 if (i != num) 1503 goto out; 1504 1505 return 0; 1506 out: 1507 for (; i < num; i++) 1508 rte_pktmbuf_free(mbufs[i]); 1509 1510 return -1; 1511 } 1512 1513 /** 1514 * DPDK callback to configure the receive queue. 1515 * 1516 * @param dev 1517 * Pointer to Ethernet device structure. 1518 * @param idx 1519 * RX queue index. 1520 * @param desc 1521 * Number of descriptors to configure in queue. 1522 * @param socket 1523 * NUMA socket on which memory must be allocated. 1524 * @param conf 1525 * Thresholds parameters. 1526 * @param mp 1527 * Memory pool for buffer allocations. 1528 * 1529 * @return 1530 * 0 on success, negative error value otherwise. 1531 */ 1532 static int 1533 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1534 unsigned int socket, 1535 const struct rte_eth_rxconf *conf, 1536 struct rte_mempool *mp) 1537 { 1538 struct mrvl_priv *priv = dev->data->dev_private; 1539 struct mrvl_rxq *rxq; 1540 uint32_t min_size, 1541 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1542 int ret, tc, inq; 1543 uint64_t offloads; 1544 1545 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1546 1547 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1548 /* 1549 * Unknown TC mapping, mapping will not have a correct queue. 1550 */ 1551 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1552 idx, priv->ppio_id); 1553 return -EFAULT; 1554 } 1555 1556 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM - 1557 MRVL_PKT_EFFEC_OFFS; 1558 if (min_size < max_rx_pkt_len) { 1559 MRVL_LOG(ERR, 1560 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.", 1561 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM + 1562 MRVL_PKT_EFFEC_OFFS, 1563 max_rx_pkt_len); 1564 return -EINVAL; 1565 } 1566 1567 if (dev->data->rx_queues[idx]) { 1568 rte_free(dev->data->rx_queues[idx]); 1569 dev->data->rx_queues[idx] = NULL; 1570 } 1571 1572 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 1573 if (!rxq) 1574 return -ENOMEM; 1575 1576 rxq->priv = priv; 1577 rxq->mp = mp; 1578 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; 1579 rxq->queue_id = idx; 1580 rxq->port_id = dev->data->port_id; 1581 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 1582 1583 tc = priv->rxq_map[rxq->queue_id].tc, 1584 inq = priv->rxq_map[rxq->queue_id].inq; 1585 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 1586 desc; 1587 1588 ret = mrvl_fill_bpool(rxq, desc); 1589 if (ret) { 1590 rte_free(rxq); 1591 return ret; 1592 } 1593 1594 priv->bpool_init_size += desc; 1595 1596 dev->data->rx_queues[idx] = rxq; 1597 1598 return 0; 1599 } 1600 1601 /** 1602 * DPDK callback to release the receive queue. 1603 * 1604 * @param rxq 1605 * Generic receive queue pointer. 1606 */ 1607 static void 1608 mrvl_rx_queue_release(void *rxq) 1609 { 1610 struct mrvl_rxq *q = rxq; 1611 struct pp2_ppio_tc_params *tc_params; 1612 int i, num, tc, inq; 1613 struct pp2_hif *hif; 1614 unsigned int core_id = rte_lcore_id(); 1615 1616 if (core_id == LCORE_ID_ANY) 1617 core_id = 0; 1618 1619 if (!q) 1620 return; 1621 1622 hif = mrvl_get_hif(q->priv, core_id); 1623 1624 if (!hif) 1625 return; 1626 1627 tc = q->priv->rxq_map[q->queue_id].tc; 1628 inq = q->priv->rxq_map[q->queue_id].inq; 1629 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 1630 num = tc_params->inqs_params[inq].size; 1631 for (i = 0; i < num; i++) { 1632 struct pp2_buff_inf inf; 1633 uint64_t addr; 1634 1635 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 1636 addr = cookie_addr_high | inf.cookie; 1637 rte_pktmbuf_free((struct rte_mbuf *)addr); 1638 } 1639 1640 rte_free(q); 1641 } 1642 1643 /** 1644 * DPDK callback to configure the transmit queue. 1645 * 1646 * @param dev 1647 * Pointer to Ethernet device structure. 1648 * @param idx 1649 * Transmit queue index. 1650 * @param desc 1651 * Number of descriptors to configure in the queue. 1652 * @param socket 1653 * NUMA socket on which memory must be allocated. 1654 * @param conf 1655 * Tx queue configuration parameters. 1656 * 1657 * @return 1658 * 0 on success, negative error value otherwise. 1659 */ 1660 static int 1661 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1662 unsigned int socket, 1663 const struct rte_eth_txconf *conf) 1664 { 1665 struct mrvl_priv *priv = dev->data->dev_private; 1666 struct mrvl_txq *txq; 1667 1668 if (dev->data->tx_queues[idx]) { 1669 rte_free(dev->data->tx_queues[idx]); 1670 dev->data->tx_queues[idx] = NULL; 1671 } 1672 1673 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 1674 if (!txq) 1675 return -ENOMEM; 1676 1677 txq->priv = priv; 1678 txq->queue_id = idx; 1679 txq->port_id = dev->data->port_id; 1680 txq->tx_deferred_start = conf->tx_deferred_start; 1681 dev->data->tx_queues[idx] = txq; 1682 1683 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 1684 1685 return 0; 1686 } 1687 1688 /** 1689 * DPDK callback to release the transmit queue. 1690 * 1691 * @param txq 1692 * Generic transmit queue pointer. 1693 */ 1694 static void 1695 mrvl_tx_queue_release(void *txq) 1696 { 1697 struct mrvl_txq *q = txq; 1698 1699 if (!q) 1700 return; 1701 1702 rte_free(q); 1703 } 1704 1705 /** 1706 * DPDK callback to get flow control configuration. 1707 * 1708 * @param dev 1709 * Pointer to Ethernet device structure. 1710 * @param fc_conf 1711 * Pointer to the flow control configuration. 1712 * 1713 * @return 1714 * 0 on success, negative error value otherwise. 1715 */ 1716 static int 1717 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1718 { 1719 struct mrvl_priv *priv = dev->data->dev_private; 1720 int ret, en; 1721 1722 if (!priv) 1723 return -EPERM; 1724 1725 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 1726 if (ret) { 1727 MRVL_LOG(ERR, "Failed to read rx pause state"); 1728 return ret; 1729 } 1730 1731 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; 1732 1733 return 0; 1734 } 1735 1736 /** 1737 * DPDK callback to set flow control configuration. 1738 * 1739 * @param dev 1740 * Pointer to Ethernet device structure. 1741 * @param fc_conf 1742 * Pointer to the flow control configuration. 1743 * 1744 * @return 1745 * 0 on success, negative error value otherwise. 1746 */ 1747 static int 1748 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1749 { 1750 struct mrvl_priv *priv = dev->data->dev_private; 1751 1752 if (!priv) 1753 return -EPERM; 1754 1755 if (fc_conf->high_water || 1756 fc_conf->low_water || 1757 fc_conf->pause_time || 1758 fc_conf->mac_ctrl_frame_fwd || 1759 fc_conf->autoneg) { 1760 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 1761 1762 return -EINVAL; 1763 } 1764 1765 if (fc_conf->mode == RTE_FC_NONE || 1766 fc_conf->mode == RTE_FC_RX_PAUSE) { 1767 int ret, en; 1768 1769 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; 1770 ret = pp2_ppio_set_rx_pause(priv->ppio, en); 1771 if (ret) 1772 MRVL_LOG(ERR, 1773 "Failed to change flowctrl on RX side"); 1774 1775 return ret; 1776 } 1777 1778 return 0; 1779 } 1780 1781 /** 1782 * Update RSS hash configuration 1783 * 1784 * @param dev 1785 * Pointer to Ethernet device structure. 1786 * @param rss_conf 1787 * Pointer to RSS configuration. 1788 * 1789 * @return 1790 * 0 on success, negative error value otherwise. 1791 */ 1792 static int 1793 mrvl_rss_hash_update(struct rte_eth_dev *dev, 1794 struct rte_eth_rss_conf *rss_conf) 1795 { 1796 struct mrvl_priv *priv = dev->data->dev_private; 1797 1798 if (priv->isolated) 1799 return -ENOTSUP; 1800 1801 return mrvl_configure_rss(priv, rss_conf); 1802 } 1803 1804 /** 1805 * DPDK callback to get RSS hash configuration. 1806 * 1807 * @param dev 1808 * Pointer to Ethernet device structure. 1809 * @rss_conf 1810 * Pointer to RSS configuration. 1811 * 1812 * @return 1813 * Always 0. 1814 */ 1815 static int 1816 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 1817 struct rte_eth_rss_conf *rss_conf) 1818 { 1819 struct mrvl_priv *priv = dev->data->dev_private; 1820 enum pp2_ppio_hash_type hash_type = 1821 priv->ppio_params.inqs_params.hash_type; 1822 1823 rss_conf->rss_key = NULL; 1824 1825 if (hash_type == PP2_PPIO_HASH_T_NONE) 1826 rss_conf->rss_hf = 0; 1827 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 1828 rss_conf->rss_hf = ETH_RSS_IPV4; 1829 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 1830 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; 1831 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 1832 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; 1833 1834 return 0; 1835 } 1836 1837 /** 1838 * DPDK callback to get rte_flow callbacks. 1839 * 1840 * @param dev 1841 * Pointer to the device structure. 1842 * @param filer_type 1843 * Flow filter type. 1844 * @param filter_op 1845 * Flow filter operation. 1846 * @param arg 1847 * Pointer to pass the flow ops. 1848 * 1849 * @return 1850 * 0 on success, negative error value otherwise. 1851 */ 1852 static int 1853 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 1854 enum rte_filter_type filter_type, 1855 enum rte_filter_op filter_op, void *arg) 1856 { 1857 switch (filter_type) { 1858 case RTE_ETH_FILTER_GENERIC: 1859 if (filter_op != RTE_ETH_FILTER_GET) 1860 return -EINVAL; 1861 *(const void **)arg = &mrvl_flow_ops; 1862 return 0; 1863 default: 1864 MRVL_LOG(WARNING, "Filter type (%d) not supported", 1865 filter_type); 1866 return -EINVAL; 1867 } 1868 } 1869 1870 static const struct eth_dev_ops mrvl_ops = { 1871 .dev_configure = mrvl_dev_configure, 1872 .dev_start = mrvl_dev_start, 1873 .dev_stop = mrvl_dev_stop, 1874 .dev_set_link_up = mrvl_dev_set_link_up, 1875 .dev_set_link_down = mrvl_dev_set_link_down, 1876 .dev_close = mrvl_dev_close, 1877 .link_update = mrvl_link_update, 1878 .promiscuous_enable = mrvl_promiscuous_enable, 1879 .allmulticast_enable = mrvl_allmulticast_enable, 1880 .promiscuous_disable = mrvl_promiscuous_disable, 1881 .allmulticast_disable = mrvl_allmulticast_disable, 1882 .mac_addr_remove = mrvl_mac_addr_remove, 1883 .mac_addr_add = mrvl_mac_addr_add, 1884 .mac_addr_set = mrvl_mac_addr_set, 1885 .mtu_set = mrvl_mtu_set, 1886 .stats_get = mrvl_stats_get, 1887 .stats_reset = mrvl_stats_reset, 1888 .xstats_get = mrvl_xstats_get, 1889 .xstats_reset = mrvl_xstats_reset, 1890 .xstats_get_names = mrvl_xstats_get_names, 1891 .dev_infos_get = mrvl_dev_infos_get, 1892 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 1893 .rxq_info_get = mrvl_rxq_info_get, 1894 .txq_info_get = mrvl_txq_info_get, 1895 .vlan_filter_set = mrvl_vlan_filter_set, 1896 .tx_queue_start = mrvl_tx_queue_start, 1897 .tx_queue_stop = mrvl_tx_queue_stop, 1898 .rx_queue_setup = mrvl_rx_queue_setup, 1899 .rx_queue_release = mrvl_rx_queue_release, 1900 .tx_queue_setup = mrvl_tx_queue_setup, 1901 .tx_queue_release = mrvl_tx_queue_release, 1902 .flow_ctrl_get = mrvl_flow_ctrl_get, 1903 .flow_ctrl_set = mrvl_flow_ctrl_set, 1904 .rss_hash_update = mrvl_rss_hash_update, 1905 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 1906 .filter_ctrl = mrvl_eth_filter_ctrl, 1907 }; 1908 1909 /** 1910 * Return packet type information and l3/l4 offsets. 1911 * 1912 * @param desc 1913 * Pointer to the received packet descriptor. 1914 * @param l3_offset 1915 * l3 packet offset. 1916 * @param l4_offset 1917 * l4 packet offset. 1918 * 1919 * @return 1920 * Packet type information. 1921 */ 1922 static inline uint64_t 1923 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 1924 uint8_t *l3_offset, uint8_t *l4_offset) 1925 { 1926 enum pp2_inq_l3_type l3_type; 1927 enum pp2_inq_l4_type l4_type; 1928 enum pp2_inq_vlan_tag vlan_tag; 1929 uint64_t packet_type; 1930 1931 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 1932 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 1933 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 1934 1935 packet_type = RTE_PTYPE_L2_ETHER; 1936 1937 switch (vlan_tag) { 1938 case PP2_INQ_VLAN_TAG_SINGLE: 1939 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 1940 break; 1941 case PP2_INQ_VLAN_TAG_DOUBLE: 1942 case PP2_INQ_VLAN_TAG_TRIPLE: 1943 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 1944 break; 1945 default: 1946 break; 1947 } 1948 1949 switch (l3_type) { 1950 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 1951 packet_type |= RTE_PTYPE_L3_IPV4; 1952 break; 1953 case PP2_INQ_L3_TYPE_IPV4_OK: 1954 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 1955 break; 1956 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 1957 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 1958 break; 1959 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 1960 packet_type |= RTE_PTYPE_L3_IPV6; 1961 break; 1962 case PP2_INQ_L3_TYPE_IPV6_EXT: 1963 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 1964 break; 1965 case PP2_INQ_L3_TYPE_ARP: 1966 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 1967 /* 1968 * In case of ARP l4_offset is set to wrong value. 1969 * Set it to proper one so that later on mbuf->l3_len can be 1970 * calculated subtracting l4_offset and l3_offset. 1971 */ 1972 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 1973 break; 1974 default: 1975 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type"); 1976 break; 1977 } 1978 1979 switch (l4_type) { 1980 case PP2_INQ_L4_TYPE_TCP: 1981 packet_type |= RTE_PTYPE_L4_TCP; 1982 break; 1983 case PP2_INQ_L4_TYPE_UDP: 1984 packet_type |= RTE_PTYPE_L4_UDP; 1985 break; 1986 default: 1987 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type"); 1988 break; 1989 } 1990 1991 return packet_type; 1992 } 1993 1994 /** 1995 * Get offload information from the received packet descriptor. 1996 * 1997 * @param desc 1998 * Pointer to the received packet descriptor. 1999 * 2000 * @return 2001 * Mbuf offload flags. 2002 */ 2003 static inline uint64_t 2004 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) 2005 { 2006 uint64_t flags; 2007 enum pp2_inq_desc_status status; 2008 2009 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2010 if (unlikely(status != PP2_DESC_ERR_OK)) 2011 flags = PKT_RX_IP_CKSUM_BAD; 2012 else 2013 flags = PKT_RX_IP_CKSUM_GOOD; 2014 2015 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2016 if (unlikely(status != PP2_DESC_ERR_OK)) 2017 flags |= PKT_RX_L4_CKSUM_BAD; 2018 else 2019 flags |= PKT_RX_L4_CKSUM_GOOD; 2020 2021 return flags; 2022 } 2023 2024 /** 2025 * DPDK callback for receive. 2026 * 2027 * @param rxq 2028 * Generic pointer to the receive queue. 2029 * @param rx_pkts 2030 * Array to store received packets. 2031 * @param nb_pkts 2032 * Maximum number of packets in array. 2033 * 2034 * @return 2035 * Number of packets successfully received. 2036 */ 2037 static uint16_t 2038 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2039 { 2040 struct mrvl_rxq *q = rxq; 2041 struct pp2_ppio_desc descs[nb_pkts]; 2042 struct pp2_bpool *bpool; 2043 int i, ret, rx_done = 0; 2044 int num; 2045 struct pp2_hif *hif; 2046 unsigned int core_id = rte_lcore_id(); 2047 2048 hif = mrvl_get_hif(q->priv, core_id); 2049 2050 if (unlikely(!q->priv->ppio || !hif)) 2051 return 0; 2052 2053 bpool = q->priv->bpool; 2054 2055 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2056 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2057 if (unlikely(ret < 0)) { 2058 MRVL_LOG(ERR, "Failed to receive packets"); 2059 return 0; 2060 } 2061 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2062 2063 for (i = 0; i < nb_pkts; i++) { 2064 struct rte_mbuf *mbuf; 2065 uint8_t l3_offset, l4_offset; 2066 enum pp2_inq_desc_status status; 2067 uint64_t addr; 2068 2069 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2070 struct pp2_ppio_desc *pref_desc; 2071 u64 pref_addr; 2072 2073 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2074 pref_addr = cookie_addr_high | 2075 pp2_ppio_inq_desc_get_cookie(pref_desc); 2076 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2077 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2078 } 2079 2080 addr = cookie_addr_high | 2081 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2082 mbuf = (struct rte_mbuf *)addr; 2083 rte_pktmbuf_reset(mbuf); 2084 2085 /* drop packet in case of mac, overrun or resource error */ 2086 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2087 if (unlikely(status != PP2_DESC_ERR_OK)) { 2088 struct pp2_buff_inf binf = { 2089 .addr = rte_mbuf_data_iova_default(mbuf), 2090 .cookie = (pp2_cookie_t)(uint64_t)mbuf, 2091 }; 2092 2093 pp2_bpool_put_buff(hif, bpool, &binf); 2094 mrvl_port_bpool_size 2095 [bpool->pp2_id][bpool->id][core_id]++; 2096 q->drop_mac++; 2097 continue; 2098 } 2099 2100 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2101 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2102 mbuf->data_len = mbuf->pkt_len; 2103 mbuf->port = q->port_id; 2104 mbuf->packet_type = 2105 mrvl_desc_to_packet_type_and_offset(&descs[i], 2106 &l3_offset, 2107 &l4_offset); 2108 mbuf->l2_len = l3_offset; 2109 mbuf->l3_len = l4_offset - l3_offset; 2110 2111 if (likely(q->cksum_enabled)) 2112 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); 2113 2114 rx_pkts[rx_done++] = mbuf; 2115 q->bytes_recv += mbuf->pkt_len; 2116 } 2117 2118 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2119 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2120 2121 if (unlikely(num <= q->priv->bpool_min_size || 2122 (!rx_done && num < q->priv->bpool_init_size))) { 2123 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE); 2124 if (ret) 2125 MRVL_LOG(ERR, "Failed to fill bpool"); 2126 } else if (unlikely(num > q->priv->bpool_max_size)) { 2127 int i; 2128 int pkt_to_remove = num - q->priv->bpool_init_size; 2129 struct rte_mbuf *mbuf; 2130 struct pp2_buff_inf buff; 2131 2132 MRVL_LOG(DEBUG, 2133 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)", 2134 bpool->pp2_id, q->priv->ppio->port_id, 2135 bpool->id, pkt_to_remove, num, 2136 q->priv->bpool_init_size); 2137 2138 for (i = 0; i < pkt_to_remove; i++) { 2139 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2140 if (ret) 2141 break; 2142 mbuf = (struct rte_mbuf *) 2143 (cookie_addr_high | buff.cookie); 2144 rte_pktmbuf_free(mbuf); 2145 } 2146 mrvl_port_bpool_size 2147 [bpool->pp2_id][bpool->id][core_id] -= i; 2148 } 2149 rte_spinlock_unlock(&q->priv->lock); 2150 } 2151 2152 return rx_done; 2153 } 2154 2155 /** 2156 * Prepare offload information. 2157 * 2158 * @param ol_flags 2159 * Offload flags. 2160 * @param packet_type 2161 * Packet type bitfield. 2162 * @param l3_type 2163 * Pointer to the pp2_ouq_l3_type structure. 2164 * @param l4_type 2165 * Pointer to the pp2_outq_l4_type structure. 2166 * @param gen_l3_cksum 2167 * Will be set to 1 in case l3 checksum is computed. 2168 * @param l4_cksum 2169 * Will be set to 1 in case l4 checksum is computed. 2170 * 2171 * @return 2172 * 0 on success, negative error value otherwise. 2173 */ 2174 static inline int 2175 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, 2176 enum pp2_outq_l3_type *l3_type, 2177 enum pp2_outq_l4_type *l4_type, 2178 int *gen_l3_cksum, 2179 int *gen_l4_cksum) 2180 { 2181 /* 2182 * Based on ol_flags prepare information 2183 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2184 * for offloading. 2185 */ 2186 if (ol_flags & PKT_TX_IPV4) { 2187 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2188 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; 2189 } else if (ol_flags & PKT_TX_IPV6) { 2190 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2191 /* no checksum for ipv6 header */ 2192 *gen_l3_cksum = 0; 2193 } else { 2194 /* if something different then stop processing */ 2195 return -1; 2196 } 2197 2198 ol_flags &= PKT_TX_L4_MASK; 2199 if ((packet_type & RTE_PTYPE_L4_TCP) && 2200 ol_flags == PKT_TX_TCP_CKSUM) { 2201 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2202 *gen_l4_cksum = 1; 2203 } else if ((packet_type & RTE_PTYPE_L4_UDP) && 2204 ol_flags == PKT_TX_UDP_CKSUM) { 2205 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2206 *gen_l4_cksum = 1; 2207 } else { 2208 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2209 /* no checksum for other type */ 2210 *gen_l4_cksum = 0; 2211 } 2212 2213 return 0; 2214 } 2215 2216 /** 2217 * Release already sent buffers to bpool (buffer-pool). 2218 * 2219 * @param ppio 2220 * Pointer to the port structure. 2221 * @param hif 2222 * Pointer to the MUSDK hardware interface. 2223 * @param sq 2224 * Pointer to the shadow queue. 2225 * @param qid 2226 * Queue id number. 2227 * @param force 2228 * Force releasing packets. 2229 */ 2230 static inline void 2231 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2232 unsigned int core_id, struct mrvl_shadow_txq *sq, 2233 int qid, int force) 2234 { 2235 struct buff_release_entry *entry; 2236 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2237 int i; 2238 2239 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2240 2241 sq->num_to_release += nb_done; 2242 2243 if (likely(!force && 2244 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2245 return; 2246 2247 nb_done = sq->num_to_release; 2248 sq->num_to_release = 0; 2249 2250 for (i = 0; i < nb_done; i++) { 2251 entry = &sq->ent[sq->tail + num]; 2252 if (unlikely(!entry->buff.addr)) { 2253 MRVL_LOG(ERR, 2254 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2255 sq->tail, (u64)entry->buff.cookie, 2256 (u64)entry->buff.addr); 2257 skip_bufs = 1; 2258 goto skip; 2259 } 2260 2261 if (unlikely(!entry->bpool)) { 2262 struct rte_mbuf *mbuf; 2263 2264 mbuf = (struct rte_mbuf *) 2265 (cookie_addr_high | entry->buff.cookie); 2266 rte_pktmbuf_free(mbuf); 2267 skip_bufs = 1; 2268 goto skip; 2269 } 2270 2271 mrvl_port_bpool_size 2272 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2273 num++; 2274 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2275 goto skip; 2276 continue; 2277 skip: 2278 if (likely(num)) 2279 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2280 num += skip_bufs; 2281 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2282 sq->size -= num; 2283 num = 0; 2284 skip_bufs = 0; 2285 } 2286 2287 if (likely(num)) { 2288 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2289 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2290 sq->size -= num; 2291 } 2292 } 2293 2294 /** 2295 * DPDK callback for transmit. 2296 * 2297 * @param txq 2298 * Generic pointer transmit queue. 2299 * @param tx_pkts 2300 * Packets to transmit. 2301 * @param nb_pkts 2302 * Number of packets in array. 2303 * 2304 * @return 2305 * Number of packets successfully transmitted. 2306 */ 2307 static uint16_t 2308 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2309 { 2310 struct mrvl_txq *q = txq; 2311 struct mrvl_shadow_txq *sq; 2312 struct pp2_hif *hif; 2313 struct pp2_ppio_desc descs[nb_pkts]; 2314 unsigned int core_id = rte_lcore_id(); 2315 int i, ret, bytes_sent = 0; 2316 uint16_t num, sq_free_size; 2317 uint64_t addr; 2318 2319 hif = mrvl_get_hif(q->priv, core_id); 2320 sq = &q->shadow_txqs[core_id]; 2321 2322 if (unlikely(!q->priv->ppio || !hif)) 2323 return 0; 2324 2325 if (sq->size) 2326 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2327 sq, q->queue_id, 0); 2328 2329 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2330 if (unlikely(nb_pkts > sq_free_size)) { 2331 MRVL_LOG(DEBUG, 2332 "No room in shadow queue for %d packets! %d packets will be sent.", 2333 nb_pkts, sq_free_size); 2334 nb_pkts = sq_free_size; 2335 } 2336 2337 for (i = 0; i < nb_pkts; i++) { 2338 struct rte_mbuf *mbuf = tx_pkts[i]; 2339 int gen_l3_cksum, gen_l4_cksum; 2340 enum pp2_outq_l3_type l3_type; 2341 enum pp2_outq_l4_type l4_type; 2342 2343 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2344 struct rte_mbuf *pref_pkt_hdr; 2345 2346 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2347 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2348 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2349 } 2350 2351 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf; 2352 sq->ent[sq->head].buff.addr = 2353 rte_mbuf_data_iova_default(mbuf); 2354 sq->ent[sq->head].bpool = 2355 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS || 2356 mbuf->refcnt > 1)) ? NULL : 2357 mrvl_port_to_bpool_lookup[mbuf->port]; 2358 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 2359 sq->size++; 2360 2361 pp2_ppio_outq_desc_reset(&descs[i]); 2362 pp2_ppio_outq_desc_set_phys_addr(&descs[i], 2363 rte_pktmbuf_iova(mbuf)); 2364 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0); 2365 pp2_ppio_outq_desc_set_pkt_len(&descs[i], 2366 rte_pktmbuf_pkt_len(mbuf)); 2367 2368 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2369 /* 2370 * in case unsupported ol_flags were passed 2371 * do not update descriptor offload information 2372 */ 2373 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2374 &l3_type, &l4_type, &gen_l3_cksum, 2375 &gen_l4_cksum); 2376 if (unlikely(ret)) 2377 continue; 2378 2379 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2380 mbuf->l2_len, 2381 mbuf->l2_len + mbuf->l3_len, 2382 gen_l3_cksum, gen_l4_cksum); 2383 } 2384 2385 num = nb_pkts; 2386 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2387 /* number of packets that were not sent */ 2388 if (unlikely(num > nb_pkts)) { 2389 for (i = nb_pkts; i < num; i++) { 2390 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2391 MRVL_PP2_TX_SHADOWQ_MASK; 2392 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie; 2393 bytes_sent -= 2394 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2395 } 2396 sq->size -= num - nb_pkts; 2397 } 2398 2399 q->bytes_sent += bytes_sent; 2400 2401 return nb_pkts; 2402 } 2403 2404 /** 2405 * Initialize packet processor. 2406 * 2407 * @return 2408 * 0 on success, negative error value otherwise. 2409 */ 2410 static int 2411 mrvl_init_pp2(void) 2412 { 2413 struct pp2_init_params init_params; 2414 2415 memset(&init_params, 0, sizeof(init_params)); 2416 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 2417 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 2418 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 2419 2420 return pp2_init(&init_params); 2421 } 2422 2423 /** 2424 * Deinitialize packet processor. 2425 * 2426 * @return 2427 * 0 on success, negative error value otherwise. 2428 */ 2429 static void 2430 mrvl_deinit_pp2(void) 2431 { 2432 pp2_deinit(); 2433 } 2434 2435 /** 2436 * Create private device structure. 2437 * 2438 * @param dev_name 2439 * Pointer to the port name passed in the initialization parameters. 2440 * 2441 * @return 2442 * Pointer to the newly allocated private device structure. 2443 */ 2444 static struct mrvl_priv * 2445 mrvl_priv_create(const char *dev_name) 2446 { 2447 struct pp2_bpool_params bpool_params; 2448 char match[MRVL_MATCH_LEN]; 2449 struct mrvl_priv *priv; 2450 int ret, bpool_bit; 2451 2452 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 2453 if (!priv) 2454 return NULL; 2455 2456 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 2457 &priv->pp_id, &priv->ppio_id); 2458 if (ret) 2459 goto out_free_priv; 2460 2461 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 2462 PP2_BPOOL_NUM_POOLS); 2463 if (bpool_bit < 0) 2464 goto out_free_priv; 2465 priv->bpool_bit = bpool_bit; 2466 2467 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 2468 priv->bpool_bit); 2469 memset(&bpool_params, 0, sizeof(bpool_params)); 2470 bpool_params.match = match; 2471 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 2472 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 2473 if (ret) 2474 goto out_clear_bpool_bit; 2475 2476 priv->ppio_params.type = PP2_PPIO_T_NIC; 2477 rte_spinlock_init(&priv->lock); 2478 2479 return priv; 2480 out_clear_bpool_bit: 2481 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2482 out_free_priv: 2483 rte_free(priv); 2484 return NULL; 2485 } 2486 2487 /** 2488 * Create device representing Ethernet port. 2489 * 2490 * @param name 2491 * Pointer to the port's name. 2492 * 2493 * @return 2494 * 0 on success, negative error value otherwise. 2495 */ 2496 static int 2497 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 2498 { 2499 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 2500 struct rte_eth_dev *eth_dev; 2501 struct mrvl_priv *priv; 2502 struct ifreq req; 2503 2504 eth_dev = rte_eth_dev_allocate(name); 2505 if (!eth_dev) 2506 return -ENOMEM; 2507 2508 priv = mrvl_priv_create(name); 2509 if (!priv) { 2510 ret = -ENOMEM; 2511 goto out_free_dev; 2512 } 2513 2514 eth_dev->data->mac_addrs = 2515 rte_zmalloc("mac_addrs", 2516 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 2517 if (!eth_dev->data->mac_addrs) { 2518 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 2519 ret = -ENOMEM; 2520 goto out_free_priv; 2521 } 2522 2523 memset(&req, 0, sizeof(req)); 2524 strcpy(req.ifr_name, name); 2525 ret = ioctl(fd, SIOCGIFHWADDR, &req); 2526 if (ret) 2527 goto out_free_mac; 2528 2529 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 2530 req.ifr_addr.sa_data, ETHER_ADDR_LEN); 2531 2532 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 2533 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst; 2534 eth_dev->data->kdrv = RTE_KDRV_NONE; 2535 eth_dev->data->dev_private = priv; 2536 eth_dev->device = &vdev->device; 2537 eth_dev->dev_ops = &mrvl_ops; 2538 2539 rte_eth_dev_probing_finish(eth_dev); 2540 return 0; 2541 out_free_mac: 2542 rte_free(eth_dev->data->mac_addrs); 2543 out_free_dev: 2544 rte_eth_dev_release_port(eth_dev); 2545 out_free_priv: 2546 rte_free(priv); 2547 2548 return ret; 2549 } 2550 2551 /** 2552 * Cleanup previously created device representing Ethernet port. 2553 * 2554 * @param name 2555 * Pointer to the port name. 2556 */ 2557 static void 2558 mrvl_eth_dev_destroy(const char *name) 2559 { 2560 struct rte_eth_dev *eth_dev; 2561 struct mrvl_priv *priv; 2562 2563 eth_dev = rte_eth_dev_allocated(name); 2564 if (!eth_dev) 2565 return; 2566 2567 priv = eth_dev->data->dev_private; 2568 pp2_bpool_deinit(priv->bpool); 2569 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2570 rte_free(priv); 2571 rte_free(eth_dev->data->mac_addrs); 2572 rte_eth_dev_release_port(eth_dev); 2573 } 2574 2575 /** 2576 * Callback used by rte_kvargs_process() during argument parsing. 2577 * 2578 * @param key 2579 * Pointer to the parsed key (unused). 2580 * @param value 2581 * Pointer to the parsed value. 2582 * @param extra_args 2583 * Pointer to the extra arguments which contains address of the 2584 * table of pointers to parsed interface names. 2585 * 2586 * @return 2587 * Always 0. 2588 */ 2589 static int 2590 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 2591 void *extra_args) 2592 { 2593 struct mrvl_ifnames *ifnames = extra_args; 2594 2595 ifnames->names[ifnames->idx++] = value; 2596 2597 return 0; 2598 } 2599 2600 /** 2601 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 2602 */ 2603 static void 2604 mrvl_deinit_hifs(void) 2605 { 2606 int i; 2607 2608 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 2609 if (hifs[i]) 2610 pp2_hif_deinit(hifs[i]); 2611 } 2612 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 2613 memset(hifs, 0, sizeof(hifs)); 2614 } 2615 2616 /** 2617 * DPDK callback to register the virtual device. 2618 * 2619 * @param vdev 2620 * Pointer to the virtual device. 2621 * 2622 * @return 2623 * 0 on success, negative error value otherwise. 2624 */ 2625 static int 2626 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 2627 { 2628 struct rte_kvargs *kvlist; 2629 struct mrvl_ifnames ifnames; 2630 int ret = -EINVAL; 2631 uint32_t i, ifnum, cfgnum; 2632 const char *params; 2633 2634 params = rte_vdev_device_args(vdev); 2635 if (!params) 2636 return -EINVAL; 2637 2638 kvlist = rte_kvargs_parse(params, valid_args); 2639 if (!kvlist) 2640 return -EINVAL; 2641 2642 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 2643 if (ifnum > RTE_DIM(ifnames.names)) 2644 goto out_free_kvlist; 2645 2646 ifnames.idx = 0; 2647 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 2648 mrvl_get_ifnames, &ifnames); 2649 2650 2651 /* 2652 * The below system initialization should be done only once, 2653 * on the first provided configuration file 2654 */ 2655 if (!mrvl_qos_cfg) { 2656 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 2657 MRVL_LOG(INFO, "Parsing config file!"); 2658 if (cfgnum > 1) { 2659 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 2660 goto out_free_kvlist; 2661 } else if (cfgnum == 1) { 2662 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 2663 mrvl_get_qoscfg, &mrvl_qos_cfg); 2664 } 2665 } 2666 2667 if (mrvl_dev_num) 2668 goto init_devices; 2669 2670 MRVL_LOG(INFO, "Perform MUSDK initializations"); 2671 2672 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 2673 if (ret) 2674 goto out_free_kvlist; 2675 2676 ret = mrvl_init_pp2(); 2677 if (ret) { 2678 MRVL_LOG(ERR, "Failed to init PP!"); 2679 rte_mvep_deinit(MVEP_MOD_T_PP2); 2680 goto out_free_kvlist; 2681 } 2682 2683 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 2684 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 2685 2686 mrvl_lcore_first = RTE_MAX_LCORE; 2687 mrvl_lcore_last = 0; 2688 2689 init_devices: 2690 for (i = 0; i < ifnum; i++) { 2691 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 2692 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 2693 if (ret) 2694 goto out_cleanup; 2695 } 2696 mrvl_dev_num += ifnum; 2697 2698 rte_kvargs_free(kvlist); 2699 2700 return 0; 2701 out_cleanup: 2702 for (; i > 0; i--) 2703 mrvl_eth_dev_destroy(ifnames.names[i]); 2704 2705 if (mrvl_dev_num == 0) { 2706 mrvl_deinit_pp2(); 2707 rte_mvep_deinit(MVEP_MOD_T_PP2); 2708 } 2709 out_free_kvlist: 2710 rte_kvargs_free(kvlist); 2711 2712 return ret; 2713 } 2714 2715 /** 2716 * DPDK callback to remove virtual device. 2717 * 2718 * @param vdev 2719 * Pointer to the removed virtual device. 2720 * 2721 * @return 2722 * 0 on success, negative error value otherwise. 2723 */ 2724 static int 2725 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 2726 { 2727 int i; 2728 const char *name; 2729 2730 name = rte_vdev_device_name(vdev); 2731 if (!name) 2732 return -EINVAL; 2733 2734 MRVL_LOG(INFO, "Removing %s", name); 2735 2736 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */ 2737 char ifname[RTE_ETH_NAME_MAX_LEN]; 2738 2739 rte_eth_dev_get_name_by_port(i, ifname); 2740 mrvl_eth_dev_destroy(ifname); 2741 mrvl_dev_num--; 2742 } 2743 2744 if (mrvl_dev_num == 0) { 2745 MRVL_LOG(INFO, "Perform MUSDK deinit"); 2746 mrvl_deinit_hifs(); 2747 mrvl_deinit_pp2(); 2748 rte_mvep_deinit(MVEP_MOD_T_PP2); 2749 } 2750 2751 return 0; 2752 } 2753 2754 static struct rte_vdev_driver pmd_mrvl_drv = { 2755 .probe = rte_pmd_mrvl_probe, 2756 .remove = rte_pmd_mrvl_remove, 2757 }; 2758 2759 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 2760 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 2761 2762 RTE_INIT(mrvl_init_log) 2763 { 2764 mrvl_logtype = rte_log_register("pmd.net.mvpp2"); 2765 if (mrvl_logtype >= 0) 2766 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE); 2767 } 2768