1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_ethdev_driver.h> 8 #include <rte_kvargs.h> 9 #include <rte_log.h> 10 #include <rte_malloc.h> 11 #include <rte_bus_vdev.h> 12 13 /* Unluckily, container_of is defined by both DPDK and MUSDK, 14 * we'll declare only one version. 15 * 16 * Note that it is not used in this PMD anyway. 17 */ 18 #ifdef container_of 19 #undef container_of 20 #endif 21 22 #include <fcntl.h> 23 #include <linux/ethtool.h> 24 #include <linux/sockios.h> 25 #include <net/if.h> 26 #include <net/if_arp.h> 27 #include <sys/ioctl.h> 28 #include <sys/socket.h> 29 #include <sys/stat.h> 30 #include <sys/types.h> 31 32 #include "mrvl_ethdev.h" 33 #include "mrvl_qos.h" 34 35 /* bitmask with reserved hifs */ 36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 37 /* bitmask with reserved bpools */ 38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 39 /* bitmask with reserved kernel RSS tables */ 40 #define MRVL_MUSDK_RSS_RESERVED 0x01 41 /* maximum number of available hifs */ 42 #define MRVL_MUSDK_HIFS_MAX 9 43 44 /* prefetch shift */ 45 #define MRVL_MUSDK_PREFETCH_SHIFT 2 46 47 /* TCAM has 25 entries reserved for uc/mc filter entries */ 48 #define MRVL_MAC_ADDRS_MAX 25 49 #define MRVL_MATCH_LEN 16 50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 51 /* Maximum allowable packet size */ 52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 53 54 #define MRVL_IFACE_NAME_ARG "iface" 55 #define MRVL_CFG_ARG "cfg" 56 57 #define MRVL_BURST_SIZE 64 58 59 #define MRVL_ARP_LENGTH 28 60 61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 62 63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8) 64 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT) 65 66 /* Memory size (in bytes) for MUSDK dma buffers */ 67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040 68 69 /** Port Rx offload capabilities */ 70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ 71 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 72 DEV_RX_OFFLOAD_CRC_STRIP | \ 73 DEV_RX_OFFLOAD_CHECKSUM) 74 75 /** Port Tx offloads capabilities */ 76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 77 DEV_TX_OFFLOAD_UDP_CKSUM | \ 78 DEV_TX_OFFLOAD_TCP_CKSUM) 79 80 static const char * const valid_args[] = { 81 MRVL_IFACE_NAME_ARG, 82 MRVL_CFG_ARG, 83 NULL 84 }; 85 86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 87 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 88 static int used_bpools[PP2_NUM_PKT_PROC] = { 89 MRVL_MUSDK_BPOOLS_RESERVED, 90 MRVL_MUSDK_BPOOLS_RESERVED 91 }; 92 93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 96 97 int mrvl_logtype; 98 99 struct mrvl_ifnames { 100 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 101 int idx; 102 }; 103 104 /* 105 * To use buffer harvesting based on loopback port shadow queue structure 106 * was introduced for buffers information bookkeeping. 107 * 108 * Before sending the packet, related buffer information (pp2_buff_inf) is 109 * stored in shadow queue. After packet is transmitted no longer used 110 * packet buffer is released back to it's original hardware pool, 111 * on condition it originated from interface. 112 * In case it was generated by application itself i.e: mbuf->port field is 113 * 0xff then its released to software mempool. 114 */ 115 struct mrvl_shadow_txq { 116 int head; /* write index - used when sending buffers */ 117 int tail; /* read index - used when releasing buffers */ 118 u16 size; /* queue occupied size */ 119 u16 num_to_release; /* number of buffers sent, that can be released */ 120 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 121 }; 122 123 struct mrvl_rxq { 124 struct mrvl_priv *priv; 125 struct rte_mempool *mp; 126 int queue_id; 127 int port_id; 128 int cksum_enabled; 129 uint64_t bytes_recv; 130 uint64_t drop_mac; 131 }; 132 133 struct mrvl_txq { 134 struct mrvl_priv *priv; 135 int queue_id; 136 int port_id; 137 uint64_t bytes_sent; 138 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 139 int tx_deferred_start; 140 }; 141 142 static int mrvl_lcore_first; 143 static int mrvl_lcore_last; 144 static int mrvl_dev_num; 145 146 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 147 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 148 struct pp2_hif *hif, unsigned int core_id, 149 struct mrvl_shadow_txq *sq, int qid, int force); 150 151 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 152 #name, offsetof(struct pp2_ppio_statistics, name), \ 153 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 154 } 155 156 /* Table with xstats data */ 157 static struct { 158 const char *name; 159 unsigned int offset; 160 unsigned int size; 161 } mrvl_xstats_tbl[] = { 162 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 163 MRVL_XSTATS_TBL_ENTRY(rx_packets), 164 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 165 MRVL_XSTATS_TBL_ENTRY(rx_errors), 166 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 167 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 168 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 169 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 170 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 171 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 172 MRVL_XSTATS_TBL_ENTRY(tx_packets), 173 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 174 MRVL_XSTATS_TBL_ENTRY(tx_errors) 175 }; 176 177 static inline int 178 mrvl_get_bpool_size(int pp2_id, int pool_id) 179 { 180 int i; 181 int size = 0; 182 183 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 184 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 185 186 return size; 187 } 188 189 static inline int 190 mrvl_reserve_bit(int *bitmap, int max) 191 { 192 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 193 194 if (n >= max) 195 return -1; 196 197 *bitmap |= 1 << n; 198 199 return n; 200 } 201 202 static int 203 mrvl_init_hif(int core_id) 204 { 205 struct pp2_hif_params params; 206 char match[MRVL_MATCH_LEN]; 207 int ret; 208 209 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 210 if (ret < 0) { 211 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 212 return ret; 213 } 214 215 snprintf(match, sizeof(match), "hif-%d", ret); 216 memset(¶ms, 0, sizeof(params)); 217 params.match = match; 218 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 219 ret = pp2_hif_init(¶ms, &hifs[core_id]); 220 if (ret) { 221 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 222 return ret; 223 } 224 225 return 0; 226 } 227 228 static inline struct pp2_hif* 229 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 230 { 231 int ret; 232 233 if (likely(hifs[core_id] != NULL)) 234 return hifs[core_id]; 235 236 rte_spinlock_lock(&priv->lock); 237 238 ret = mrvl_init_hif(core_id); 239 if (ret < 0) { 240 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 241 goto out; 242 } 243 244 if (core_id < mrvl_lcore_first) 245 mrvl_lcore_first = core_id; 246 247 if (core_id > mrvl_lcore_last) 248 mrvl_lcore_last = core_id; 249 out: 250 rte_spinlock_unlock(&priv->lock); 251 252 return hifs[core_id]; 253 } 254 255 /** 256 * Configure rss based on dpdk rss configuration. 257 * 258 * @param priv 259 * Pointer to private structure. 260 * @param rss_conf 261 * Pointer to RSS configuration. 262 * 263 * @return 264 * 0 on success, negative error value otherwise. 265 */ 266 static int 267 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 268 { 269 if (rss_conf->rss_key) 270 MRVL_LOG(WARNING, "Changing hash key is not supported"); 271 272 if (rss_conf->rss_hf == 0) { 273 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 274 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { 275 priv->ppio_params.inqs_params.hash_type = 276 PP2_PPIO_HASH_T_2_TUPLE; 277 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 278 priv->ppio_params.inqs_params.hash_type = 279 PP2_PPIO_HASH_T_5_TUPLE; 280 priv->rss_hf_tcp = 1; 281 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 282 priv->ppio_params.inqs_params.hash_type = 283 PP2_PPIO_HASH_T_5_TUPLE; 284 priv->rss_hf_tcp = 0; 285 } else { 286 return -EINVAL; 287 } 288 289 return 0; 290 } 291 292 /** 293 * Ethernet device configuration. 294 * 295 * Prepare the driver for a given number of TX and RX queues and 296 * configure RSS. 297 * 298 * @param dev 299 * Pointer to Ethernet device structure. 300 * 301 * @return 302 * 0 on success, negative error value otherwise. 303 */ 304 static int 305 mrvl_dev_configure(struct rte_eth_dev *dev) 306 { 307 struct mrvl_priv *priv = dev->data->dev_private; 308 int ret; 309 310 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && 311 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 312 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 313 dev->data->dev_conf.rxmode.mq_mode); 314 return -EINVAL; 315 } 316 317 if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { 318 MRVL_LOG(INFO, 319 "L2 CRC stripping is always enabled in hw"); 320 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP; 321 } 322 323 if (dev->data->dev_conf.rxmode.split_hdr_size) { 324 MRVL_LOG(INFO, "Split headers not supported"); 325 return -EINVAL; 326 } 327 328 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 329 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 330 ETHER_HDR_LEN - ETHER_CRC_LEN; 331 332 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 333 dev->data->nb_rx_queues); 334 if (ret < 0) 335 return ret; 336 337 ret = mrvl_configure_txqs(priv, dev->data->port_id, 338 dev->data->nb_tx_queues); 339 if (ret < 0) 340 return ret; 341 342 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 343 priv->ppio_params.maintain_stats = 1; 344 priv->nb_rx_queues = dev->data->nb_rx_queues; 345 346 if (dev->data->nb_rx_queues == 1 && 347 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 348 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 349 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 350 351 return 0; 352 } 353 354 return mrvl_configure_rss(priv, 355 &dev->data->dev_conf.rx_adv_conf.rss_conf); 356 } 357 358 /** 359 * DPDK callback to change the MTU. 360 * 361 * Setting the MTU affects hardware MRU (packets larger than the MRU 362 * will be dropped). 363 * 364 * @param dev 365 * Pointer to Ethernet device structure. 366 * @param mtu 367 * New MTU. 368 * 369 * @return 370 * 0 on success, negative error value otherwise. 371 */ 372 static int 373 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 374 { 375 struct mrvl_priv *priv = dev->data->dev_private; 376 /* extra MV_MH_SIZE bytes are required for Marvell tag */ 377 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN; 378 int ret; 379 380 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) 381 return -EINVAL; 382 383 if (!priv->ppio) 384 return 0; 385 386 ret = pp2_ppio_set_mru(priv->ppio, mru); 387 if (ret) 388 return ret; 389 390 return pp2_ppio_set_mtu(priv->ppio, mtu); 391 } 392 393 /** 394 * DPDK callback to bring the link up. 395 * 396 * @param dev 397 * Pointer to Ethernet device structure. 398 * 399 * @return 400 * 0 on success, negative error value otherwise. 401 */ 402 static int 403 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 404 { 405 struct mrvl_priv *priv = dev->data->dev_private; 406 int ret; 407 408 if (!priv->ppio) 409 return -EPERM; 410 411 ret = pp2_ppio_enable(priv->ppio); 412 if (ret) 413 return ret; 414 415 /* 416 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 417 * as pp2_ppio_enable() changes port->t_mode from default 0 to 418 * PP2_TRAFFIC_INGRESS_EGRESS. 419 * 420 * Set mtu to default DPDK value here. 421 */ 422 ret = mrvl_mtu_set(dev, dev->data->mtu); 423 if (ret) 424 pp2_ppio_disable(priv->ppio); 425 426 return ret; 427 } 428 429 /** 430 * DPDK callback to bring the link down. 431 * 432 * @param dev 433 * Pointer to Ethernet device structure. 434 * 435 * @return 436 * 0 on success, negative error value otherwise. 437 */ 438 static int 439 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 440 { 441 struct mrvl_priv *priv = dev->data->dev_private; 442 443 if (!priv->ppio) 444 return -EPERM; 445 446 return pp2_ppio_disable(priv->ppio); 447 } 448 449 /** 450 * DPDK callback to start tx queue. 451 * 452 * @param dev 453 * Pointer to Ethernet device structure. 454 * @param queue_id 455 * Transmit queue index. 456 * 457 * @return 458 * 0 on success, negative error value otherwise. 459 */ 460 static int 461 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 462 { 463 struct mrvl_priv *priv = dev->data->dev_private; 464 int ret; 465 466 if (!priv) 467 return -EPERM; 468 469 /* passing 1 enables given tx queue */ 470 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 471 if (ret) { 472 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 473 return ret; 474 } 475 476 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 477 478 return 0; 479 } 480 481 /** 482 * DPDK callback to stop tx queue. 483 * 484 * @param dev 485 * Pointer to Ethernet device structure. 486 * @param queue_id 487 * Transmit queue index. 488 * 489 * @return 490 * 0 on success, negative error value otherwise. 491 */ 492 static int 493 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 494 { 495 struct mrvl_priv *priv = dev->data->dev_private; 496 int ret; 497 498 if (!priv->ppio) 499 return -EPERM; 500 501 /* passing 0 disables given tx queue */ 502 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 503 if (ret) { 504 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 505 return ret; 506 } 507 508 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 509 510 return 0; 511 } 512 513 /** 514 * DPDK callback to start the device. 515 * 516 * @param dev 517 * Pointer to Ethernet device structure. 518 * 519 * @return 520 * 0 on success, negative errno value on failure. 521 */ 522 static int 523 mrvl_dev_start(struct rte_eth_dev *dev) 524 { 525 struct mrvl_priv *priv = dev->data->dev_private; 526 char match[MRVL_MATCH_LEN]; 527 int ret = 0, i, def_init_size; 528 529 snprintf(match, sizeof(match), "ppio-%d:%d", 530 priv->pp_id, priv->ppio_id); 531 priv->ppio_params.match = match; 532 533 /* 534 * Calculate the minimum bpool size for refill feature as follows: 535 * 2 default burst sizes multiply by number of rx queues. 536 * If the bpool size will be below this value, new buffers will 537 * be added to the pool. 538 */ 539 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 540 541 /* In case initial bpool size configured in queues setup is 542 * smaller than minimum size add more buffers 543 */ 544 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 545 if (priv->bpool_init_size < def_init_size) { 546 int buffs_to_add = def_init_size - priv->bpool_init_size; 547 548 priv->bpool_init_size += buffs_to_add; 549 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 550 if (ret) 551 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 552 } 553 554 /* 555 * Calculate the maximum bpool size for refill feature as follows: 556 * maximum number of descriptors in rx queue multiply by number 557 * of rx queues plus minimum bpool size. 558 * In case the bpool size will exceed this value, superfluous buffers 559 * will be removed 560 */ 561 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 562 priv->bpool_min_size; 563 564 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 565 if (ret) { 566 MRVL_LOG(ERR, "Failed to init ppio"); 567 return ret; 568 } 569 570 /* 571 * In case there are some some stale uc/mc mac addresses flush them 572 * here. It cannot be done during mrvl_dev_close() as port information 573 * is already gone at that point (due to pp2_ppio_deinit() in 574 * mrvl_dev_stop()). 575 */ 576 if (!priv->uc_mc_flushed) { 577 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 578 if (ret) { 579 MRVL_LOG(ERR, 580 "Failed to flush uc/mc filter list"); 581 goto out; 582 } 583 priv->uc_mc_flushed = 1; 584 } 585 586 if (!priv->vlan_flushed) { 587 ret = pp2_ppio_flush_vlan(priv->ppio); 588 if (ret) { 589 MRVL_LOG(ERR, "Failed to flush vlan list"); 590 /* 591 * TODO 592 * once pp2_ppio_flush_vlan() is supported jump to out 593 * goto out; 594 */ 595 } 596 priv->vlan_flushed = 1; 597 } 598 599 /* For default QoS config, don't start classifier. */ 600 if (mrvl_qos_cfg) { 601 ret = mrvl_start_qos_mapping(priv); 602 if (ret) { 603 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 604 goto out; 605 } 606 } 607 608 ret = mrvl_dev_set_link_up(dev); 609 if (ret) { 610 MRVL_LOG(ERR, "Failed to set link up"); 611 goto out; 612 } 613 614 /* start tx queues */ 615 for (i = 0; i < dev->data->nb_tx_queues; i++) { 616 struct mrvl_txq *txq = dev->data->tx_queues[i]; 617 618 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 619 620 if (!txq->tx_deferred_start) 621 continue; 622 623 /* 624 * All txqs are started by default. Stop them 625 * so that tx_deferred_start works as expected. 626 */ 627 ret = mrvl_tx_queue_stop(dev, i); 628 if (ret) 629 goto out; 630 } 631 632 return 0; 633 out: 634 MRVL_LOG(ERR, "Failed to start device"); 635 pp2_ppio_deinit(priv->ppio); 636 return ret; 637 } 638 639 /** 640 * Flush receive queues. 641 * 642 * @param dev 643 * Pointer to Ethernet device structure. 644 */ 645 static void 646 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 647 { 648 int i; 649 650 MRVL_LOG(INFO, "Flushing rx queues"); 651 for (i = 0; i < dev->data->nb_rx_queues; i++) { 652 int ret, num; 653 654 do { 655 struct mrvl_rxq *q = dev->data->rx_queues[i]; 656 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 657 658 num = MRVL_PP2_RXD_MAX; 659 ret = pp2_ppio_recv(q->priv->ppio, 660 q->priv->rxq_map[q->queue_id].tc, 661 q->priv->rxq_map[q->queue_id].inq, 662 descs, (uint16_t *)&num); 663 } while (ret == 0 && num); 664 } 665 } 666 667 /** 668 * Flush transmit shadow queues. 669 * 670 * @param dev 671 * Pointer to Ethernet device structure. 672 */ 673 static void 674 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 675 { 676 int i, j; 677 struct mrvl_txq *txq; 678 679 MRVL_LOG(INFO, "Flushing tx shadow queues"); 680 for (i = 0; i < dev->data->nb_tx_queues; i++) { 681 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 682 683 for (j = 0; j < RTE_MAX_LCORE; j++) { 684 struct mrvl_shadow_txq *sq; 685 686 if (!hifs[j]) 687 continue; 688 689 sq = &txq->shadow_txqs[j]; 690 mrvl_free_sent_buffers(txq->priv->ppio, 691 hifs[j], j, sq, txq->queue_id, 1); 692 while (sq->tail != sq->head) { 693 uint64_t addr = cookie_addr_high | 694 sq->ent[sq->tail].buff.cookie; 695 rte_pktmbuf_free( 696 (struct rte_mbuf *)addr); 697 sq->tail = (sq->tail + 1) & 698 MRVL_PP2_TX_SHADOWQ_MASK; 699 } 700 memset(sq, 0, sizeof(*sq)); 701 } 702 } 703 } 704 705 /** 706 * Flush hardware bpool (buffer-pool). 707 * 708 * @param dev 709 * Pointer to Ethernet device structure. 710 */ 711 static void 712 mrvl_flush_bpool(struct rte_eth_dev *dev) 713 { 714 struct mrvl_priv *priv = dev->data->dev_private; 715 struct pp2_hif *hif; 716 uint32_t num; 717 int ret; 718 unsigned int core_id = rte_lcore_id(); 719 720 if (core_id == LCORE_ID_ANY) 721 core_id = 0; 722 723 hif = mrvl_get_hif(priv, core_id); 724 725 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 726 if (ret) { 727 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 728 return; 729 } 730 731 while (num--) { 732 struct pp2_buff_inf inf; 733 uint64_t addr; 734 735 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 736 if (ret) 737 break; 738 739 addr = cookie_addr_high | inf.cookie; 740 rte_pktmbuf_free((struct rte_mbuf *)addr); 741 } 742 } 743 744 /** 745 * DPDK callback to stop the device. 746 * 747 * @param dev 748 * Pointer to Ethernet device structure. 749 */ 750 static void 751 mrvl_dev_stop(struct rte_eth_dev *dev) 752 { 753 struct mrvl_priv *priv = dev->data->dev_private; 754 755 mrvl_dev_set_link_down(dev); 756 mrvl_flush_rx_queues(dev); 757 mrvl_flush_tx_shadow_queues(dev); 758 if (priv->cls_tbl) { 759 pp2_cls_tbl_deinit(priv->cls_tbl); 760 priv->cls_tbl = NULL; 761 } 762 if (priv->qos_tbl) { 763 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 764 priv->qos_tbl = NULL; 765 } 766 if (priv->ppio) 767 pp2_ppio_deinit(priv->ppio); 768 priv->ppio = NULL; 769 770 /* policer must be released after ppio deinitialization */ 771 if (priv->policer) { 772 pp2_cls_plcr_deinit(priv->policer); 773 priv->policer = NULL; 774 } 775 } 776 777 /** 778 * DPDK callback to close the device. 779 * 780 * @param dev 781 * Pointer to Ethernet device structure. 782 */ 783 static void 784 mrvl_dev_close(struct rte_eth_dev *dev) 785 { 786 struct mrvl_priv *priv = dev->data->dev_private; 787 size_t i; 788 789 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 790 struct pp2_ppio_tc_params *tc_params = 791 &priv->ppio_params.inqs_params.tcs_params[i]; 792 793 if (tc_params->inqs_params) { 794 rte_free(tc_params->inqs_params); 795 tc_params->inqs_params = NULL; 796 } 797 } 798 799 mrvl_flush_bpool(dev); 800 } 801 802 /** 803 * DPDK callback to retrieve physical link information. 804 * 805 * @param dev 806 * Pointer to Ethernet device structure. 807 * @param wait_to_complete 808 * Wait for request completion (ignored). 809 * 810 * @return 811 * 0 on success, negative error value otherwise. 812 */ 813 static int 814 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 815 { 816 /* 817 * TODO 818 * once MUSDK provides necessary API use it here 819 */ 820 struct mrvl_priv *priv = dev->data->dev_private; 821 struct ethtool_cmd edata; 822 struct ifreq req; 823 int ret, fd, link_up; 824 825 if (!priv->ppio) 826 return -EPERM; 827 828 edata.cmd = ETHTOOL_GSET; 829 830 strcpy(req.ifr_name, dev->data->name); 831 req.ifr_data = (void *)&edata; 832 833 fd = socket(AF_INET, SOCK_DGRAM, 0); 834 if (fd == -1) 835 return -EFAULT; 836 837 ret = ioctl(fd, SIOCETHTOOL, &req); 838 if (ret == -1) { 839 close(fd); 840 return -EFAULT; 841 } 842 843 close(fd); 844 845 switch (ethtool_cmd_speed(&edata)) { 846 case SPEED_10: 847 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M; 848 break; 849 case SPEED_100: 850 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M; 851 break; 852 case SPEED_1000: 853 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; 854 break; 855 case SPEED_10000: 856 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; 857 break; 858 default: 859 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; 860 } 861 862 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : 863 ETH_LINK_HALF_DUPLEX; 864 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : 865 ETH_LINK_FIXED; 866 pp2_ppio_get_link_state(priv->ppio, &link_up); 867 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 868 869 return 0; 870 } 871 872 /** 873 * DPDK callback to enable promiscuous mode. 874 * 875 * @param dev 876 * Pointer to Ethernet device structure. 877 */ 878 static void 879 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 880 { 881 struct mrvl_priv *priv = dev->data->dev_private; 882 int ret; 883 884 if (!priv->ppio) 885 return; 886 887 if (priv->isolated) 888 return; 889 890 ret = pp2_ppio_set_promisc(priv->ppio, 1); 891 if (ret) 892 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 893 } 894 895 /** 896 * DPDK callback to enable allmulti mode. 897 * 898 * @param dev 899 * Pointer to Ethernet device structure. 900 */ 901 static void 902 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 903 { 904 struct mrvl_priv *priv = dev->data->dev_private; 905 int ret; 906 907 if (!priv->ppio) 908 return; 909 910 if (priv->isolated) 911 return; 912 913 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 914 if (ret) 915 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 916 } 917 918 /** 919 * DPDK callback to disable promiscuous mode. 920 * 921 * @param dev 922 * Pointer to Ethernet device structure. 923 */ 924 static void 925 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 926 { 927 struct mrvl_priv *priv = dev->data->dev_private; 928 int ret; 929 930 if (!priv->ppio) 931 return; 932 933 ret = pp2_ppio_set_promisc(priv->ppio, 0); 934 if (ret) 935 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 936 } 937 938 /** 939 * DPDK callback to disable allmulticast mode. 940 * 941 * @param dev 942 * Pointer to Ethernet device structure. 943 */ 944 static void 945 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 946 { 947 struct mrvl_priv *priv = dev->data->dev_private; 948 int ret; 949 950 if (!priv->ppio) 951 return; 952 953 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 954 if (ret) 955 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 956 } 957 958 /** 959 * DPDK callback to remove a MAC address. 960 * 961 * @param dev 962 * Pointer to Ethernet device structure. 963 * @param index 964 * MAC address index. 965 */ 966 static void 967 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 968 { 969 struct mrvl_priv *priv = dev->data->dev_private; 970 char buf[ETHER_ADDR_FMT_SIZE]; 971 int ret; 972 973 if (!priv->ppio) 974 return; 975 976 if (priv->isolated) 977 return; 978 979 ret = pp2_ppio_remove_mac_addr(priv->ppio, 980 dev->data->mac_addrs[index].addr_bytes); 981 if (ret) { 982 ether_format_addr(buf, sizeof(buf), 983 &dev->data->mac_addrs[index]); 984 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 985 } 986 } 987 988 /** 989 * DPDK callback to add a MAC address. 990 * 991 * @param dev 992 * Pointer to Ethernet device structure. 993 * @param mac_addr 994 * MAC address to register. 995 * @param index 996 * MAC address index. 997 * @param vmdq 998 * VMDq pool index to associate address with (unused). 999 * 1000 * @return 1001 * 0 on success, negative error value otherwise. 1002 */ 1003 static int 1004 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 1005 uint32_t index, uint32_t vmdq __rte_unused) 1006 { 1007 struct mrvl_priv *priv = dev->data->dev_private; 1008 char buf[ETHER_ADDR_FMT_SIZE]; 1009 int ret; 1010 1011 if (priv->isolated) 1012 return -ENOTSUP; 1013 1014 if (index == 0) 1015 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1016 return -1; 1017 1018 if (!priv->ppio) 1019 return 0; 1020 1021 /* 1022 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1023 * parameter uc_filter_max. Maximum number of mc addresses is then 1024 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1025 * 21 respectively. 1026 * 1027 * If more than uc_filter_max uc addresses were added to filter list 1028 * then NIC will switch to promiscuous mode automatically. 1029 * 1030 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1031 * were added to filter list then NIC will switch to all-multicast mode 1032 * automatically. 1033 */ 1034 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1035 if (ret) { 1036 ether_format_addr(buf, sizeof(buf), mac_addr); 1037 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1038 return -1; 1039 } 1040 1041 return 0; 1042 } 1043 1044 /** 1045 * DPDK callback to set the primary MAC address. 1046 * 1047 * @param dev 1048 * Pointer to Ethernet device structure. 1049 * @param mac_addr 1050 * MAC address to register. 1051 * 1052 * @return 1053 * 0 on success, negative error value otherwise. 1054 */ 1055 static int 1056 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 1057 { 1058 struct mrvl_priv *priv = dev->data->dev_private; 1059 int ret; 1060 1061 if (!priv->ppio) 1062 return 0; 1063 1064 if (priv->isolated) 1065 return -ENOTSUP; 1066 1067 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1068 if (ret) { 1069 char buf[ETHER_ADDR_FMT_SIZE]; 1070 ether_format_addr(buf, sizeof(buf), mac_addr); 1071 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1072 } 1073 1074 return ret; 1075 } 1076 1077 /** 1078 * DPDK callback to get device statistics. 1079 * 1080 * @param dev 1081 * Pointer to Ethernet device structure. 1082 * @param stats 1083 * Stats structure output buffer. 1084 * 1085 * @return 1086 * 0 on success, negative error value otherwise. 1087 */ 1088 static int 1089 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1090 { 1091 struct mrvl_priv *priv = dev->data->dev_private; 1092 struct pp2_ppio_statistics ppio_stats; 1093 uint64_t drop_mac = 0; 1094 unsigned int i, idx, ret; 1095 1096 if (!priv->ppio) 1097 return -EPERM; 1098 1099 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1100 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1101 struct pp2_ppio_inq_statistics rx_stats; 1102 1103 if (!rxq) 1104 continue; 1105 1106 idx = rxq->queue_id; 1107 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1108 MRVL_LOG(ERR, 1109 "rx queue %d stats out of range (0 - %d)", 1110 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1111 continue; 1112 } 1113 1114 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1115 priv->rxq_map[idx].tc, 1116 priv->rxq_map[idx].inq, 1117 &rx_stats, 0); 1118 if (unlikely(ret)) { 1119 MRVL_LOG(ERR, 1120 "Failed to update rx queue %d stats", idx); 1121 break; 1122 } 1123 1124 stats->q_ibytes[idx] = rxq->bytes_recv; 1125 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1126 stats->q_errors[idx] = rx_stats.drop_early + 1127 rx_stats.drop_fullq + 1128 rx_stats.drop_bm + 1129 rxq->drop_mac; 1130 stats->ibytes += rxq->bytes_recv; 1131 drop_mac += rxq->drop_mac; 1132 } 1133 1134 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1135 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1136 struct pp2_ppio_outq_statistics tx_stats; 1137 1138 if (!txq) 1139 continue; 1140 1141 idx = txq->queue_id; 1142 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1143 MRVL_LOG(ERR, 1144 "tx queue %d stats out of range (0 - %d)", 1145 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1146 } 1147 1148 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1149 &tx_stats, 0); 1150 if (unlikely(ret)) { 1151 MRVL_LOG(ERR, 1152 "Failed to update tx queue %d stats", idx); 1153 break; 1154 } 1155 1156 stats->q_opackets[idx] = tx_stats.deq_desc; 1157 stats->q_obytes[idx] = txq->bytes_sent; 1158 stats->obytes += txq->bytes_sent; 1159 } 1160 1161 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1162 if (unlikely(ret)) { 1163 MRVL_LOG(ERR, "Failed to update port statistics"); 1164 return ret; 1165 } 1166 1167 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1168 stats->opackets += ppio_stats.tx_packets; 1169 stats->imissed += ppio_stats.rx_fullq_dropped + 1170 ppio_stats.rx_bm_dropped + 1171 ppio_stats.rx_early_dropped + 1172 ppio_stats.rx_fifo_dropped + 1173 ppio_stats.rx_cls_dropped; 1174 stats->ierrors = drop_mac; 1175 1176 return 0; 1177 } 1178 1179 /** 1180 * DPDK callback to clear device statistics. 1181 * 1182 * @param dev 1183 * Pointer to Ethernet device structure. 1184 */ 1185 static void 1186 mrvl_stats_reset(struct rte_eth_dev *dev) 1187 { 1188 struct mrvl_priv *priv = dev->data->dev_private; 1189 int i; 1190 1191 if (!priv->ppio) 1192 return; 1193 1194 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1195 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1196 1197 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1198 priv->rxq_map[i].inq, NULL, 1); 1199 rxq->bytes_recv = 0; 1200 rxq->drop_mac = 0; 1201 } 1202 1203 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1204 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1205 1206 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1207 txq->bytes_sent = 0; 1208 } 1209 1210 pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1211 } 1212 1213 /** 1214 * DPDK callback to get extended statistics. 1215 * 1216 * @param dev 1217 * Pointer to Ethernet device structure. 1218 * @param stats 1219 * Pointer to xstats table. 1220 * @param n 1221 * Number of entries in xstats table. 1222 * @return 1223 * Negative value on error, number of read xstats otherwise. 1224 */ 1225 static int 1226 mrvl_xstats_get(struct rte_eth_dev *dev, 1227 struct rte_eth_xstat *stats, unsigned int n) 1228 { 1229 struct mrvl_priv *priv = dev->data->dev_private; 1230 struct pp2_ppio_statistics ppio_stats; 1231 unsigned int i; 1232 1233 if (!stats) 1234 return 0; 1235 1236 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1237 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) { 1238 uint64_t val; 1239 1240 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1241 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1242 mrvl_xstats_tbl[i].offset); 1243 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1244 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1245 mrvl_xstats_tbl[i].offset); 1246 else 1247 return -EINVAL; 1248 1249 stats[i].id = i; 1250 stats[i].value = val; 1251 } 1252 1253 return n; 1254 } 1255 1256 /** 1257 * DPDK callback to reset extended statistics. 1258 * 1259 * @param dev 1260 * Pointer to Ethernet device structure. 1261 */ 1262 static void 1263 mrvl_xstats_reset(struct rte_eth_dev *dev) 1264 { 1265 mrvl_stats_reset(dev); 1266 } 1267 1268 /** 1269 * DPDK callback to get extended statistics names. 1270 * 1271 * @param dev (unused) 1272 * Pointer to Ethernet device structure. 1273 * @param xstats_names 1274 * Pointer to xstats names table. 1275 * @param size 1276 * Size of the xstats names table. 1277 * @return 1278 * Number of read names. 1279 */ 1280 static int 1281 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1282 struct rte_eth_xstat_name *xstats_names, 1283 unsigned int size) 1284 { 1285 unsigned int i; 1286 1287 if (!xstats_names) 1288 return RTE_DIM(mrvl_xstats_tbl); 1289 1290 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1291 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s", 1292 mrvl_xstats_tbl[i].name); 1293 1294 return size; 1295 } 1296 1297 /** 1298 * DPDK callback to get information about the device. 1299 * 1300 * @param dev 1301 * Pointer to Ethernet device structure (unused). 1302 * @param info 1303 * Info structure output buffer. 1304 */ 1305 static void 1306 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 1307 struct rte_eth_dev_info *info) 1308 { 1309 info->speed_capa = ETH_LINK_SPEED_10M | 1310 ETH_LINK_SPEED_100M | 1311 ETH_LINK_SPEED_1G | 1312 ETH_LINK_SPEED_10G; 1313 1314 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1315 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1316 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1317 1318 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1319 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1320 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1321 1322 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1323 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1324 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1325 1326 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1327 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1328 1329 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1330 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1331 1332 info->flow_type_rss_offloads = ETH_RSS_IPV4 | 1333 ETH_RSS_NONFRAG_IPV4_TCP | 1334 ETH_RSS_NONFRAG_IPV4_UDP; 1335 1336 /* By default packets are dropped if no descriptors are available */ 1337 info->default_rxconf.rx_drop_en = 1; 1338 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP; 1339 1340 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1341 } 1342 1343 /** 1344 * Return supported packet types. 1345 * 1346 * @param dev 1347 * Pointer to Ethernet device structure (unused). 1348 * 1349 * @return 1350 * Const pointer to the table with supported packet types. 1351 */ 1352 static const uint32_t * 1353 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1354 { 1355 static const uint32_t ptypes[] = { 1356 RTE_PTYPE_L2_ETHER, 1357 RTE_PTYPE_L3_IPV4, 1358 RTE_PTYPE_L3_IPV4_EXT, 1359 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1360 RTE_PTYPE_L3_IPV6, 1361 RTE_PTYPE_L3_IPV6_EXT, 1362 RTE_PTYPE_L2_ETHER_ARP, 1363 RTE_PTYPE_L4_TCP, 1364 RTE_PTYPE_L4_UDP 1365 }; 1366 1367 return ptypes; 1368 } 1369 1370 /** 1371 * DPDK callback to get information about specific receive queue. 1372 * 1373 * @param dev 1374 * Pointer to Ethernet device structure. 1375 * @param rx_queue_id 1376 * Receive queue index. 1377 * @param qinfo 1378 * Receive queue information structure. 1379 */ 1380 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1381 struct rte_eth_rxq_info *qinfo) 1382 { 1383 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1384 struct mrvl_priv *priv = dev->data->dev_private; 1385 int inq = priv->rxq_map[rx_queue_id].inq; 1386 int tc = priv->rxq_map[rx_queue_id].tc; 1387 struct pp2_ppio_tc_params *tc_params = 1388 &priv->ppio_params.inqs_params.tcs_params[tc]; 1389 1390 qinfo->mp = q->mp; 1391 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1392 } 1393 1394 /** 1395 * DPDK callback to get information about specific transmit queue. 1396 * 1397 * @param dev 1398 * Pointer to Ethernet device structure. 1399 * @param tx_queue_id 1400 * Transmit queue index. 1401 * @param qinfo 1402 * Transmit queue information structure. 1403 */ 1404 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1405 struct rte_eth_txq_info *qinfo) 1406 { 1407 struct mrvl_priv *priv = dev->data->dev_private; 1408 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1409 1410 qinfo->nb_desc = 1411 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1412 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1413 } 1414 1415 /** 1416 * DPDK callback to Configure a VLAN filter. 1417 * 1418 * @param dev 1419 * Pointer to Ethernet device structure. 1420 * @param vlan_id 1421 * VLAN ID to filter. 1422 * @param on 1423 * Toggle filter. 1424 * 1425 * @return 1426 * 0 on success, negative error value otherwise. 1427 */ 1428 static int 1429 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1430 { 1431 struct mrvl_priv *priv = dev->data->dev_private; 1432 1433 if (!priv->ppio) 1434 return -EPERM; 1435 1436 if (priv->isolated) 1437 return -ENOTSUP; 1438 1439 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1440 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1441 } 1442 1443 /** 1444 * Release buffers to hardware bpool (buffer-pool) 1445 * 1446 * @param rxq 1447 * Receive queue pointer. 1448 * @param num 1449 * Number of buffers to release to bpool. 1450 * 1451 * @return 1452 * 0 on success, negative error value otherwise. 1453 */ 1454 static int 1455 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1456 { 1457 struct buff_release_entry entries[MRVL_PP2_RXD_MAX]; 1458 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX]; 1459 int i, ret; 1460 unsigned int core_id; 1461 struct pp2_hif *hif; 1462 struct pp2_bpool *bpool; 1463 1464 core_id = rte_lcore_id(); 1465 if (core_id == LCORE_ID_ANY) 1466 core_id = 0; 1467 1468 hif = mrvl_get_hif(rxq->priv, core_id); 1469 if (!hif) 1470 return -1; 1471 1472 bpool = rxq->priv->bpool; 1473 1474 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1475 if (ret) 1476 return ret; 1477 1478 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1479 cookie_addr_high = 1480 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1481 1482 for (i = 0; i < num; i++) { 1483 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1484 != cookie_addr_high) { 1485 MRVL_LOG(ERR, 1486 "mbuf virtual addr high 0x%lx out of range", 1487 (uint64_t)mbufs[i] >> 32); 1488 goto out; 1489 } 1490 1491 entries[i].buff.addr = 1492 rte_mbuf_data_iova_default(mbufs[i]); 1493 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i]; 1494 entries[i].bpool = bpool; 1495 } 1496 1497 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1498 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1499 1500 if (i != num) 1501 goto out; 1502 1503 return 0; 1504 out: 1505 for (; i < num; i++) 1506 rte_pktmbuf_free(mbufs[i]); 1507 1508 return -1; 1509 } 1510 1511 /** 1512 * DPDK callback to configure the receive queue. 1513 * 1514 * @param dev 1515 * Pointer to Ethernet device structure. 1516 * @param idx 1517 * RX queue index. 1518 * @param desc 1519 * Number of descriptors to configure in queue. 1520 * @param socket 1521 * NUMA socket on which memory must be allocated. 1522 * @param conf 1523 * Thresholds parameters. 1524 * @param mp 1525 * Memory pool for buffer allocations. 1526 * 1527 * @return 1528 * 0 on success, negative error value otherwise. 1529 */ 1530 static int 1531 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1532 unsigned int socket, 1533 const struct rte_eth_rxconf *conf, 1534 struct rte_mempool *mp) 1535 { 1536 struct mrvl_priv *priv = dev->data->dev_private; 1537 struct mrvl_rxq *rxq; 1538 uint32_t min_size, 1539 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1540 int ret, tc, inq; 1541 uint64_t offloads; 1542 1543 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1544 1545 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1546 /* 1547 * Unknown TC mapping, mapping will not have a correct queue. 1548 */ 1549 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1550 idx, priv->ppio_id); 1551 return -EFAULT; 1552 } 1553 1554 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM - 1555 MRVL_PKT_EFFEC_OFFS; 1556 if (min_size < max_rx_pkt_len) { 1557 MRVL_LOG(ERR, 1558 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.", 1559 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM + 1560 MRVL_PKT_EFFEC_OFFS, 1561 max_rx_pkt_len); 1562 return -EINVAL; 1563 } 1564 1565 if (dev->data->rx_queues[idx]) { 1566 rte_free(dev->data->rx_queues[idx]); 1567 dev->data->rx_queues[idx] = NULL; 1568 } 1569 1570 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 1571 if (!rxq) 1572 return -ENOMEM; 1573 1574 rxq->priv = priv; 1575 rxq->mp = mp; 1576 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; 1577 rxq->queue_id = idx; 1578 rxq->port_id = dev->data->port_id; 1579 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 1580 1581 tc = priv->rxq_map[rxq->queue_id].tc, 1582 inq = priv->rxq_map[rxq->queue_id].inq; 1583 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 1584 desc; 1585 1586 ret = mrvl_fill_bpool(rxq, desc); 1587 if (ret) { 1588 rte_free(rxq); 1589 return ret; 1590 } 1591 1592 priv->bpool_init_size += desc; 1593 1594 dev->data->rx_queues[idx] = rxq; 1595 1596 return 0; 1597 } 1598 1599 /** 1600 * DPDK callback to release the receive queue. 1601 * 1602 * @param rxq 1603 * Generic receive queue pointer. 1604 */ 1605 static void 1606 mrvl_rx_queue_release(void *rxq) 1607 { 1608 struct mrvl_rxq *q = rxq; 1609 struct pp2_ppio_tc_params *tc_params; 1610 int i, num, tc, inq; 1611 struct pp2_hif *hif; 1612 unsigned int core_id = rte_lcore_id(); 1613 1614 if (core_id == LCORE_ID_ANY) 1615 core_id = 0; 1616 1617 if (!q) 1618 return; 1619 1620 hif = mrvl_get_hif(q->priv, core_id); 1621 1622 if (!hif) 1623 return; 1624 1625 tc = q->priv->rxq_map[q->queue_id].tc; 1626 inq = q->priv->rxq_map[q->queue_id].inq; 1627 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 1628 num = tc_params->inqs_params[inq].size; 1629 for (i = 0; i < num; i++) { 1630 struct pp2_buff_inf inf; 1631 uint64_t addr; 1632 1633 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 1634 addr = cookie_addr_high | inf.cookie; 1635 rte_pktmbuf_free((struct rte_mbuf *)addr); 1636 } 1637 1638 rte_free(q); 1639 } 1640 1641 /** 1642 * DPDK callback to configure the transmit queue. 1643 * 1644 * @param dev 1645 * Pointer to Ethernet device structure. 1646 * @param idx 1647 * Transmit queue index. 1648 * @param desc 1649 * Number of descriptors to configure in the queue. 1650 * @param socket 1651 * NUMA socket on which memory must be allocated. 1652 * @param conf 1653 * Tx queue configuration parameters. 1654 * 1655 * @return 1656 * 0 on success, negative error value otherwise. 1657 */ 1658 static int 1659 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1660 unsigned int socket, 1661 const struct rte_eth_txconf *conf) 1662 { 1663 struct mrvl_priv *priv = dev->data->dev_private; 1664 struct mrvl_txq *txq; 1665 1666 if (dev->data->tx_queues[idx]) { 1667 rte_free(dev->data->tx_queues[idx]); 1668 dev->data->tx_queues[idx] = NULL; 1669 } 1670 1671 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 1672 if (!txq) 1673 return -ENOMEM; 1674 1675 txq->priv = priv; 1676 txq->queue_id = idx; 1677 txq->port_id = dev->data->port_id; 1678 txq->tx_deferred_start = conf->tx_deferred_start; 1679 dev->data->tx_queues[idx] = txq; 1680 1681 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 1682 1683 return 0; 1684 } 1685 1686 /** 1687 * DPDK callback to release the transmit queue. 1688 * 1689 * @param txq 1690 * Generic transmit queue pointer. 1691 */ 1692 static void 1693 mrvl_tx_queue_release(void *txq) 1694 { 1695 struct mrvl_txq *q = txq; 1696 1697 if (!q) 1698 return; 1699 1700 rte_free(q); 1701 } 1702 1703 /** 1704 * DPDK callback to get flow control configuration. 1705 * 1706 * @param dev 1707 * Pointer to Ethernet device structure. 1708 * @param fc_conf 1709 * Pointer to the flow control configuration. 1710 * 1711 * @return 1712 * 0 on success, negative error value otherwise. 1713 */ 1714 static int 1715 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1716 { 1717 struct mrvl_priv *priv = dev->data->dev_private; 1718 int ret, en; 1719 1720 if (!priv) 1721 return -EPERM; 1722 1723 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 1724 if (ret) { 1725 MRVL_LOG(ERR, "Failed to read rx pause state"); 1726 return ret; 1727 } 1728 1729 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; 1730 1731 return 0; 1732 } 1733 1734 /** 1735 * DPDK callback to set flow control configuration. 1736 * 1737 * @param dev 1738 * Pointer to Ethernet device structure. 1739 * @param fc_conf 1740 * Pointer to the flow control configuration. 1741 * 1742 * @return 1743 * 0 on success, negative error value otherwise. 1744 */ 1745 static int 1746 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1747 { 1748 struct mrvl_priv *priv = dev->data->dev_private; 1749 1750 if (!priv) 1751 return -EPERM; 1752 1753 if (fc_conf->high_water || 1754 fc_conf->low_water || 1755 fc_conf->pause_time || 1756 fc_conf->mac_ctrl_frame_fwd || 1757 fc_conf->autoneg) { 1758 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 1759 1760 return -EINVAL; 1761 } 1762 1763 if (fc_conf->mode == RTE_FC_NONE || 1764 fc_conf->mode == RTE_FC_RX_PAUSE) { 1765 int ret, en; 1766 1767 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; 1768 ret = pp2_ppio_set_rx_pause(priv->ppio, en); 1769 if (ret) 1770 MRVL_LOG(ERR, 1771 "Failed to change flowctrl on RX side"); 1772 1773 return ret; 1774 } 1775 1776 return 0; 1777 } 1778 1779 /** 1780 * Update RSS hash configuration 1781 * 1782 * @param dev 1783 * Pointer to Ethernet device structure. 1784 * @param rss_conf 1785 * Pointer to RSS configuration. 1786 * 1787 * @return 1788 * 0 on success, negative error value otherwise. 1789 */ 1790 static int 1791 mrvl_rss_hash_update(struct rte_eth_dev *dev, 1792 struct rte_eth_rss_conf *rss_conf) 1793 { 1794 struct mrvl_priv *priv = dev->data->dev_private; 1795 1796 if (priv->isolated) 1797 return -ENOTSUP; 1798 1799 return mrvl_configure_rss(priv, rss_conf); 1800 } 1801 1802 /** 1803 * DPDK callback to get RSS hash configuration. 1804 * 1805 * @param dev 1806 * Pointer to Ethernet device structure. 1807 * @rss_conf 1808 * Pointer to RSS configuration. 1809 * 1810 * @return 1811 * Always 0. 1812 */ 1813 static int 1814 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 1815 struct rte_eth_rss_conf *rss_conf) 1816 { 1817 struct mrvl_priv *priv = dev->data->dev_private; 1818 enum pp2_ppio_hash_type hash_type = 1819 priv->ppio_params.inqs_params.hash_type; 1820 1821 rss_conf->rss_key = NULL; 1822 1823 if (hash_type == PP2_PPIO_HASH_T_NONE) 1824 rss_conf->rss_hf = 0; 1825 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 1826 rss_conf->rss_hf = ETH_RSS_IPV4; 1827 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 1828 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; 1829 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 1830 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; 1831 1832 return 0; 1833 } 1834 1835 /** 1836 * DPDK callback to get rte_flow callbacks. 1837 * 1838 * @param dev 1839 * Pointer to the device structure. 1840 * @param filer_type 1841 * Flow filter type. 1842 * @param filter_op 1843 * Flow filter operation. 1844 * @param arg 1845 * Pointer to pass the flow ops. 1846 * 1847 * @return 1848 * 0 on success, negative error value otherwise. 1849 */ 1850 static int 1851 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 1852 enum rte_filter_type filter_type, 1853 enum rte_filter_op filter_op, void *arg) 1854 { 1855 switch (filter_type) { 1856 case RTE_ETH_FILTER_GENERIC: 1857 if (filter_op != RTE_ETH_FILTER_GET) 1858 return -EINVAL; 1859 *(const void **)arg = &mrvl_flow_ops; 1860 return 0; 1861 default: 1862 MRVL_LOG(WARNING, "Filter type (%d) not supported", 1863 filter_type); 1864 return -EINVAL; 1865 } 1866 } 1867 1868 static const struct eth_dev_ops mrvl_ops = { 1869 .dev_configure = mrvl_dev_configure, 1870 .dev_start = mrvl_dev_start, 1871 .dev_stop = mrvl_dev_stop, 1872 .dev_set_link_up = mrvl_dev_set_link_up, 1873 .dev_set_link_down = mrvl_dev_set_link_down, 1874 .dev_close = mrvl_dev_close, 1875 .link_update = mrvl_link_update, 1876 .promiscuous_enable = mrvl_promiscuous_enable, 1877 .allmulticast_enable = mrvl_allmulticast_enable, 1878 .promiscuous_disable = mrvl_promiscuous_disable, 1879 .allmulticast_disable = mrvl_allmulticast_disable, 1880 .mac_addr_remove = mrvl_mac_addr_remove, 1881 .mac_addr_add = mrvl_mac_addr_add, 1882 .mac_addr_set = mrvl_mac_addr_set, 1883 .mtu_set = mrvl_mtu_set, 1884 .stats_get = mrvl_stats_get, 1885 .stats_reset = mrvl_stats_reset, 1886 .xstats_get = mrvl_xstats_get, 1887 .xstats_reset = mrvl_xstats_reset, 1888 .xstats_get_names = mrvl_xstats_get_names, 1889 .dev_infos_get = mrvl_dev_infos_get, 1890 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 1891 .rxq_info_get = mrvl_rxq_info_get, 1892 .txq_info_get = mrvl_txq_info_get, 1893 .vlan_filter_set = mrvl_vlan_filter_set, 1894 .tx_queue_start = mrvl_tx_queue_start, 1895 .tx_queue_stop = mrvl_tx_queue_stop, 1896 .rx_queue_setup = mrvl_rx_queue_setup, 1897 .rx_queue_release = mrvl_rx_queue_release, 1898 .tx_queue_setup = mrvl_tx_queue_setup, 1899 .tx_queue_release = mrvl_tx_queue_release, 1900 .flow_ctrl_get = mrvl_flow_ctrl_get, 1901 .flow_ctrl_set = mrvl_flow_ctrl_set, 1902 .rss_hash_update = mrvl_rss_hash_update, 1903 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 1904 .filter_ctrl = mrvl_eth_filter_ctrl, 1905 }; 1906 1907 /** 1908 * Return packet type information and l3/l4 offsets. 1909 * 1910 * @param desc 1911 * Pointer to the received packet descriptor. 1912 * @param l3_offset 1913 * l3 packet offset. 1914 * @param l4_offset 1915 * l4 packet offset. 1916 * 1917 * @return 1918 * Packet type information. 1919 */ 1920 static inline uint64_t 1921 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 1922 uint8_t *l3_offset, uint8_t *l4_offset) 1923 { 1924 enum pp2_inq_l3_type l3_type; 1925 enum pp2_inq_l4_type l4_type; 1926 uint64_t packet_type; 1927 1928 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 1929 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 1930 1931 packet_type = RTE_PTYPE_L2_ETHER; 1932 1933 switch (l3_type) { 1934 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 1935 packet_type |= RTE_PTYPE_L3_IPV4; 1936 break; 1937 case PP2_INQ_L3_TYPE_IPV4_OK: 1938 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 1939 break; 1940 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 1941 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 1942 break; 1943 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 1944 packet_type |= RTE_PTYPE_L3_IPV6; 1945 break; 1946 case PP2_INQ_L3_TYPE_IPV6_EXT: 1947 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 1948 break; 1949 case PP2_INQ_L3_TYPE_ARP: 1950 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 1951 /* 1952 * In case of ARP l4_offset is set to wrong value. 1953 * Set it to proper one so that later on mbuf->l3_len can be 1954 * calculated subtracting l4_offset and l3_offset. 1955 */ 1956 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 1957 break; 1958 default: 1959 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type"); 1960 break; 1961 } 1962 1963 switch (l4_type) { 1964 case PP2_INQ_L4_TYPE_TCP: 1965 packet_type |= RTE_PTYPE_L4_TCP; 1966 break; 1967 case PP2_INQ_L4_TYPE_UDP: 1968 packet_type |= RTE_PTYPE_L4_UDP; 1969 break; 1970 default: 1971 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type"); 1972 break; 1973 } 1974 1975 return packet_type; 1976 } 1977 1978 /** 1979 * Get offload information from the received packet descriptor. 1980 * 1981 * @param desc 1982 * Pointer to the received packet descriptor. 1983 * 1984 * @return 1985 * Mbuf offload flags. 1986 */ 1987 static inline uint64_t 1988 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) 1989 { 1990 uint64_t flags; 1991 enum pp2_inq_desc_status status; 1992 1993 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 1994 if (unlikely(status != PP2_DESC_ERR_OK)) 1995 flags = PKT_RX_IP_CKSUM_BAD; 1996 else 1997 flags = PKT_RX_IP_CKSUM_GOOD; 1998 1999 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2000 if (unlikely(status != PP2_DESC_ERR_OK)) 2001 flags |= PKT_RX_L4_CKSUM_BAD; 2002 else 2003 flags |= PKT_RX_L4_CKSUM_GOOD; 2004 2005 return flags; 2006 } 2007 2008 /** 2009 * DPDK callback for receive. 2010 * 2011 * @param rxq 2012 * Generic pointer to the receive queue. 2013 * @param rx_pkts 2014 * Array to store received packets. 2015 * @param nb_pkts 2016 * Maximum number of packets in array. 2017 * 2018 * @return 2019 * Number of packets successfully received. 2020 */ 2021 static uint16_t 2022 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2023 { 2024 struct mrvl_rxq *q = rxq; 2025 struct pp2_ppio_desc descs[nb_pkts]; 2026 struct pp2_bpool *bpool; 2027 int i, ret, rx_done = 0; 2028 int num; 2029 struct pp2_hif *hif; 2030 unsigned int core_id = rte_lcore_id(); 2031 2032 hif = mrvl_get_hif(q->priv, core_id); 2033 2034 if (unlikely(!q->priv->ppio || !hif)) 2035 return 0; 2036 2037 bpool = q->priv->bpool; 2038 2039 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2040 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2041 if (unlikely(ret < 0)) { 2042 MRVL_LOG(ERR, "Failed to receive packets"); 2043 return 0; 2044 } 2045 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2046 2047 for (i = 0; i < nb_pkts; i++) { 2048 struct rte_mbuf *mbuf; 2049 uint8_t l3_offset, l4_offset; 2050 enum pp2_inq_desc_status status; 2051 uint64_t addr; 2052 2053 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2054 struct pp2_ppio_desc *pref_desc; 2055 u64 pref_addr; 2056 2057 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2058 pref_addr = cookie_addr_high | 2059 pp2_ppio_inq_desc_get_cookie(pref_desc); 2060 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2061 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2062 } 2063 2064 addr = cookie_addr_high | 2065 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2066 mbuf = (struct rte_mbuf *)addr; 2067 rte_pktmbuf_reset(mbuf); 2068 2069 /* drop packet in case of mac, overrun or resource error */ 2070 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2071 if (unlikely(status != PP2_DESC_ERR_OK)) { 2072 struct pp2_buff_inf binf = { 2073 .addr = rte_mbuf_data_iova_default(mbuf), 2074 .cookie = (pp2_cookie_t)(uint64_t)mbuf, 2075 }; 2076 2077 pp2_bpool_put_buff(hif, bpool, &binf); 2078 mrvl_port_bpool_size 2079 [bpool->pp2_id][bpool->id][core_id]++; 2080 q->drop_mac++; 2081 continue; 2082 } 2083 2084 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2085 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2086 mbuf->data_len = mbuf->pkt_len; 2087 mbuf->port = q->port_id; 2088 mbuf->packet_type = 2089 mrvl_desc_to_packet_type_and_offset(&descs[i], 2090 &l3_offset, 2091 &l4_offset); 2092 mbuf->l2_len = l3_offset; 2093 mbuf->l3_len = l4_offset - l3_offset; 2094 2095 if (likely(q->cksum_enabled)) 2096 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); 2097 2098 rx_pkts[rx_done++] = mbuf; 2099 q->bytes_recv += mbuf->pkt_len; 2100 } 2101 2102 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2103 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2104 2105 if (unlikely(num <= q->priv->bpool_min_size || 2106 (!rx_done && num < q->priv->bpool_init_size))) { 2107 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE); 2108 if (ret) 2109 MRVL_LOG(ERR, "Failed to fill bpool"); 2110 } else if (unlikely(num > q->priv->bpool_max_size)) { 2111 int i; 2112 int pkt_to_remove = num - q->priv->bpool_init_size; 2113 struct rte_mbuf *mbuf; 2114 struct pp2_buff_inf buff; 2115 2116 MRVL_LOG(DEBUG, 2117 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)", 2118 bpool->pp2_id, q->priv->ppio->port_id, 2119 bpool->id, pkt_to_remove, num, 2120 q->priv->bpool_init_size); 2121 2122 for (i = 0; i < pkt_to_remove; i++) { 2123 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2124 if (ret) 2125 break; 2126 mbuf = (struct rte_mbuf *) 2127 (cookie_addr_high | buff.cookie); 2128 rte_pktmbuf_free(mbuf); 2129 } 2130 mrvl_port_bpool_size 2131 [bpool->pp2_id][bpool->id][core_id] -= i; 2132 } 2133 rte_spinlock_unlock(&q->priv->lock); 2134 } 2135 2136 return rx_done; 2137 } 2138 2139 /** 2140 * Prepare offload information. 2141 * 2142 * @param ol_flags 2143 * Offload flags. 2144 * @param packet_type 2145 * Packet type bitfield. 2146 * @param l3_type 2147 * Pointer to the pp2_ouq_l3_type structure. 2148 * @param l4_type 2149 * Pointer to the pp2_outq_l4_type structure. 2150 * @param gen_l3_cksum 2151 * Will be set to 1 in case l3 checksum is computed. 2152 * @param l4_cksum 2153 * Will be set to 1 in case l4 checksum is computed. 2154 * 2155 * @return 2156 * 0 on success, negative error value otherwise. 2157 */ 2158 static inline int 2159 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, 2160 enum pp2_outq_l3_type *l3_type, 2161 enum pp2_outq_l4_type *l4_type, 2162 int *gen_l3_cksum, 2163 int *gen_l4_cksum) 2164 { 2165 /* 2166 * Based on ol_flags prepare information 2167 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2168 * for offloading. 2169 */ 2170 if (ol_flags & PKT_TX_IPV4) { 2171 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2172 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; 2173 } else if (ol_flags & PKT_TX_IPV6) { 2174 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2175 /* no checksum for ipv6 header */ 2176 *gen_l3_cksum = 0; 2177 } else { 2178 /* if something different then stop processing */ 2179 return -1; 2180 } 2181 2182 ol_flags &= PKT_TX_L4_MASK; 2183 if ((packet_type & RTE_PTYPE_L4_TCP) && 2184 ol_flags == PKT_TX_TCP_CKSUM) { 2185 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2186 *gen_l4_cksum = 1; 2187 } else if ((packet_type & RTE_PTYPE_L4_UDP) && 2188 ol_flags == PKT_TX_UDP_CKSUM) { 2189 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2190 *gen_l4_cksum = 1; 2191 } else { 2192 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2193 /* no checksum for other type */ 2194 *gen_l4_cksum = 0; 2195 } 2196 2197 return 0; 2198 } 2199 2200 /** 2201 * Release already sent buffers to bpool (buffer-pool). 2202 * 2203 * @param ppio 2204 * Pointer to the port structure. 2205 * @param hif 2206 * Pointer to the MUSDK hardware interface. 2207 * @param sq 2208 * Pointer to the shadow queue. 2209 * @param qid 2210 * Queue id number. 2211 * @param force 2212 * Force releasing packets. 2213 */ 2214 static inline void 2215 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2216 unsigned int core_id, struct mrvl_shadow_txq *sq, 2217 int qid, int force) 2218 { 2219 struct buff_release_entry *entry; 2220 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2221 int i; 2222 2223 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2224 2225 sq->num_to_release += nb_done; 2226 2227 if (likely(!force && 2228 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2229 return; 2230 2231 nb_done = sq->num_to_release; 2232 sq->num_to_release = 0; 2233 2234 for (i = 0; i < nb_done; i++) { 2235 entry = &sq->ent[sq->tail + num]; 2236 if (unlikely(!entry->buff.addr)) { 2237 MRVL_LOG(ERR, 2238 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2239 sq->tail, (u64)entry->buff.cookie, 2240 (u64)entry->buff.addr); 2241 skip_bufs = 1; 2242 goto skip; 2243 } 2244 2245 if (unlikely(!entry->bpool)) { 2246 struct rte_mbuf *mbuf; 2247 2248 mbuf = (struct rte_mbuf *) 2249 (cookie_addr_high | entry->buff.cookie); 2250 rte_pktmbuf_free(mbuf); 2251 skip_bufs = 1; 2252 goto skip; 2253 } 2254 2255 mrvl_port_bpool_size 2256 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2257 num++; 2258 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2259 goto skip; 2260 continue; 2261 skip: 2262 if (likely(num)) 2263 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2264 num += skip_bufs; 2265 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2266 sq->size -= num; 2267 num = 0; 2268 skip_bufs = 0; 2269 } 2270 2271 if (likely(num)) { 2272 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2273 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2274 sq->size -= num; 2275 } 2276 } 2277 2278 /** 2279 * DPDK callback for transmit. 2280 * 2281 * @param txq 2282 * Generic pointer transmit queue. 2283 * @param tx_pkts 2284 * Packets to transmit. 2285 * @param nb_pkts 2286 * Number of packets in array. 2287 * 2288 * @return 2289 * Number of packets successfully transmitted. 2290 */ 2291 static uint16_t 2292 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2293 { 2294 struct mrvl_txq *q = txq; 2295 struct mrvl_shadow_txq *sq; 2296 struct pp2_hif *hif; 2297 struct pp2_ppio_desc descs[nb_pkts]; 2298 unsigned int core_id = rte_lcore_id(); 2299 int i, ret, bytes_sent = 0; 2300 uint16_t num, sq_free_size; 2301 uint64_t addr; 2302 2303 hif = mrvl_get_hif(q->priv, core_id); 2304 sq = &q->shadow_txqs[core_id]; 2305 2306 if (unlikely(!q->priv->ppio || !hif)) 2307 return 0; 2308 2309 if (sq->size) 2310 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2311 sq, q->queue_id, 0); 2312 2313 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2314 if (unlikely(nb_pkts > sq_free_size)) { 2315 MRVL_LOG(DEBUG, 2316 "No room in shadow queue for %d packets! %d packets will be sent.", 2317 nb_pkts, sq_free_size); 2318 nb_pkts = sq_free_size; 2319 } 2320 2321 for (i = 0; i < nb_pkts; i++) { 2322 struct rte_mbuf *mbuf = tx_pkts[i]; 2323 int gen_l3_cksum, gen_l4_cksum; 2324 enum pp2_outq_l3_type l3_type; 2325 enum pp2_outq_l4_type l4_type; 2326 2327 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2328 struct rte_mbuf *pref_pkt_hdr; 2329 2330 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2331 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2332 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2333 } 2334 2335 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf; 2336 sq->ent[sq->head].buff.addr = 2337 rte_mbuf_data_iova_default(mbuf); 2338 sq->ent[sq->head].bpool = 2339 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS || 2340 mbuf->refcnt > 1)) ? NULL : 2341 mrvl_port_to_bpool_lookup[mbuf->port]; 2342 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 2343 sq->size++; 2344 2345 pp2_ppio_outq_desc_reset(&descs[i]); 2346 pp2_ppio_outq_desc_set_phys_addr(&descs[i], 2347 rte_pktmbuf_iova(mbuf)); 2348 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0); 2349 pp2_ppio_outq_desc_set_pkt_len(&descs[i], 2350 rte_pktmbuf_pkt_len(mbuf)); 2351 2352 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2353 /* 2354 * in case unsupported ol_flags were passed 2355 * do not update descriptor offload information 2356 */ 2357 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2358 &l3_type, &l4_type, &gen_l3_cksum, 2359 &gen_l4_cksum); 2360 if (unlikely(ret)) 2361 continue; 2362 2363 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2364 mbuf->l2_len, 2365 mbuf->l2_len + mbuf->l3_len, 2366 gen_l3_cksum, gen_l4_cksum); 2367 } 2368 2369 num = nb_pkts; 2370 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2371 /* number of packets that were not sent */ 2372 if (unlikely(num > nb_pkts)) { 2373 for (i = nb_pkts; i < num; i++) { 2374 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2375 MRVL_PP2_TX_SHADOWQ_MASK; 2376 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie; 2377 bytes_sent -= 2378 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2379 } 2380 sq->size -= num - nb_pkts; 2381 } 2382 2383 q->bytes_sent += bytes_sent; 2384 2385 return nb_pkts; 2386 } 2387 2388 /** 2389 * Initialize packet processor. 2390 * 2391 * @return 2392 * 0 on success, negative error value otherwise. 2393 */ 2394 static int 2395 mrvl_init_pp2(void) 2396 { 2397 struct pp2_init_params init_params; 2398 2399 memset(&init_params, 0, sizeof(init_params)); 2400 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 2401 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 2402 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 2403 2404 return pp2_init(&init_params); 2405 } 2406 2407 /** 2408 * Deinitialize packet processor. 2409 * 2410 * @return 2411 * 0 on success, negative error value otherwise. 2412 */ 2413 static void 2414 mrvl_deinit_pp2(void) 2415 { 2416 pp2_deinit(); 2417 } 2418 2419 /** 2420 * Create private device structure. 2421 * 2422 * @param dev_name 2423 * Pointer to the port name passed in the initialization parameters. 2424 * 2425 * @return 2426 * Pointer to the newly allocated private device structure. 2427 */ 2428 static struct mrvl_priv * 2429 mrvl_priv_create(const char *dev_name) 2430 { 2431 struct pp2_bpool_params bpool_params; 2432 char match[MRVL_MATCH_LEN]; 2433 struct mrvl_priv *priv; 2434 int ret, bpool_bit; 2435 2436 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 2437 if (!priv) 2438 return NULL; 2439 2440 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 2441 &priv->pp_id, &priv->ppio_id); 2442 if (ret) 2443 goto out_free_priv; 2444 2445 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 2446 PP2_BPOOL_NUM_POOLS); 2447 if (bpool_bit < 0) 2448 goto out_free_priv; 2449 priv->bpool_bit = bpool_bit; 2450 2451 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 2452 priv->bpool_bit); 2453 memset(&bpool_params, 0, sizeof(bpool_params)); 2454 bpool_params.match = match; 2455 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 2456 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 2457 if (ret) 2458 goto out_clear_bpool_bit; 2459 2460 priv->ppio_params.type = PP2_PPIO_T_NIC; 2461 rte_spinlock_init(&priv->lock); 2462 2463 return priv; 2464 out_clear_bpool_bit: 2465 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2466 out_free_priv: 2467 rte_free(priv); 2468 return NULL; 2469 } 2470 2471 /** 2472 * Create device representing Ethernet port. 2473 * 2474 * @param name 2475 * Pointer to the port's name. 2476 * 2477 * @return 2478 * 0 on success, negative error value otherwise. 2479 */ 2480 static int 2481 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 2482 { 2483 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 2484 struct rte_eth_dev *eth_dev; 2485 struct mrvl_priv *priv; 2486 struct ifreq req; 2487 2488 eth_dev = rte_eth_dev_allocate(name); 2489 if (!eth_dev) 2490 return -ENOMEM; 2491 2492 priv = mrvl_priv_create(name); 2493 if (!priv) { 2494 ret = -ENOMEM; 2495 goto out_free_dev; 2496 } 2497 2498 eth_dev->data->mac_addrs = 2499 rte_zmalloc("mac_addrs", 2500 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 2501 if (!eth_dev->data->mac_addrs) { 2502 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 2503 ret = -ENOMEM; 2504 goto out_free_priv; 2505 } 2506 2507 memset(&req, 0, sizeof(req)); 2508 strcpy(req.ifr_name, name); 2509 ret = ioctl(fd, SIOCGIFHWADDR, &req); 2510 if (ret) 2511 goto out_free_mac; 2512 2513 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 2514 req.ifr_addr.sa_data, ETHER_ADDR_LEN); 2515 2516 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 2517 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst; 2518 eth_dev->data->kdrv = RTE_KDRV_NONE; 2519 eth_dev->data->dev_private = priv; 2520 eth_dev->device = &vdev->device; 2521 eth_dev->dev_ops = &mrvl_ops; 2522 2523 rte_eth_dev_probing_finish(eth_dev); 2524 return 0; 2525 out_free_mac: 2526 rte_free(eth_dev->data->mac_addrs); 2527 out_free_dev: 2528 rte_eth_dev_release_port(eth_dev); 2529 out_free_priv: 2530 rte_free(priv); 2531 2532 return ret; 2533 } 2534 2535 /** 2536 * Cleanup previously created device representing Ethernet port. 2537 * 2538 * @param name 2539 * Pointer to the port name. 2540 */ 2541 static void 2542 mrvl_eth_dev_destroy(const char *name) 2543 { 2544 struct rte_eth_dev *eth_dev; 2545 struct mrvl_priv *priv; 2546 2547 eth_dev = rte_eth_dev_allocated(name); 2548 if (!eth_dev) 2549 return; 2550 2551 priv = eth_dev->data->dev_private; 2552 pp2_bpool_deinit(priv->bpool); 2553 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2554 rte_free(priv); 2555 rte_free(eth_dev->data->mac_addrs); 2556 rte_eth_dev_release_port(eth_dev); 2557 } 2558 2559 /** 2560 * Callback used by rte_kvargs_process() during argument parsing. 2561 * 2562 * @param key 2563 * Pointer to the parsed key (unused). 2564 * @param value 2565 * Pointer to the parsed value. 2566 * @param extra_args 2567 * Pointer to the extra arguments which contains address of the 2568 * table of pointers to parsed interface names. 2569 * 2570 * @return 2571 * Always 0. 2572 */ 2573 static int 2574 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 2575 void *extra_args) 2576 { 2577 struct mrvl_ifnames *ifnames = extra_args; 2578 2579 ifnames->names[ifnames->idx++] = value; 2580 2581 return 0; 2582 } 2583 2584 /** 2585 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 2586 */ 2587 static void 2588 mrvl_deinit_hifs(void) 2589 { 2590 int i; 2591 2592 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 2593 if (hifs[i]) 2594 pp2_hif_deinit(hifs[i]); 2595 } 2596 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 2597 memset(hifs, 0, sizeof(hifs)); 2598 } 2599 2600 /** 2601 * DPDK callback to register the virtual device. 2602 * 2603 * @param vdev 2604 * Pointer to the virtual device. 2605 * 2606 * @return 2607 * 0 on success, negative error value otherwise. 2608 */ 2609 static int 2610 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 2611 { 2612 struct rte_kvargs *kvlist; 2613 struct mrvl_ifnames ifnames; 2614 int ret = -EINVAL; 2615 uint32_t i, ifnum, cfgnum; 2616 const char *params; 2617 2618 params = rte_vdev_device_args(vdev); 2619 if (!params) 2620 return -EINVAL; 2621 2622 kvlist = rte_kvargs_parse(params, valid_args); 2623 if (!kvlist) 2624 return -EINVAL; 2625 2626 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 2627 if (ifnum > RTE_DIM(ifnames.names)) 2628 goto out_free_kvlist; 2629 2630 ifnames.idx = 0; 2631 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 2632 mrvl_get_ifnames, &ifnames); 2633 2634 2635 /* 2636 * The below system initialization should be done only once, 2637 * on the first provided configuration file 2638 */ 2639 if (!mrvl_qos_cfg) { 2640 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 2641 MRVL_LOG(INFO, "Parsing config file!"); 2642 if (cfgnum > 1) { 2643 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 2644 goto out_free_kvlist; 2645 } else if (cfgnum == 1) { 2646 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 2647 mrvl_get_qoscfg, &mrvl_qos_cfg); 2648 } 2649 } 2650 2651 if (mrvl_dev_num) 2652 goto init_devices; 2653 2654 MRVL_LOG(INFO, "Perform MUSDK initializations"); 2655 /* 2656 * ret == -EEXIST is correct, it means DMA 2657 * has been already initialized (by another PMD). 2658 */ 2659 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE); 2660 if (ret < 0) { 2661 if (ret != -EEXIST) 2662 goto out_free_kvlist; 2663 else 2664 MRVL_LOG(INFO, 2665 "DMA memory has been already initialized by a different driver."); 2666 } 2667 2668 ret = mrvl_init_pp2(); 2669 if (ret) { 2670 MRVL_LOG(ERR, "Failed to init PP!"); 2671 goto out_deinit_dma; 2672 } 2673 2674 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 2675 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 2676 2677 mrvl_lcore_first = RTE_MAX_LCORE; 2678 mrvl_lcore_last = 0; 2679 2680 init_devices: 2681 for (i = 0; i < ifnum; i++) { 2682 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 2683 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 2684 if (ret) 2685 goto out_cleanup; 2686 } 2687 mrvl_dev_num += ifnum; 2688 2689 rte_kvargs_free(kvlist); 2690 2691 return 0; 2692 out_cleanup: 2693 for (; i > 0; i--) 2694 mrvl_eth_dev_destroy(ifnames.names[i]); 2695 2696 if (mrvl_dev_num == 0) 2697 mrvl_deinit_pp2(); 2698 out_deinit_dma: 2699 if (mrvl_dev_num == 0) 2700 mv_sys_dma_mem_destroy(); 2701 out_free_kvlist: 2702 rte_kvargs_free(kvlist); 2703 2704 return ret; 2705 } 2706 2707 /** 2708 * DPDK callback to remove virtual device. 2709 * 2710 * @param vdev 2711 * Pointer to the removed virtual device. 2712 * 2713 * @return 2714 * 0 on success, negative error value otherwise. 2715 */ 2716 static int 2717 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 2718 { 2719 int i; 2720 const char *name; 2721 2722 name = rte_vdev_device_name(vdev); 2723 if (!name) 2724 return -EINVAL; 2725 2726 MRVL_LOG(INFO, "Removing %s", name); 2727 2728 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */ 2729 char ifname[RTE_ETH_NAME_MAX_LEN]; 2730 2731 rte_eth_dev_get_name_by_port(i, ifname); 2732 mrvl_eth_dev_destroy(ifname); 2733 mrvl_dev_num--; 2734 } 2735 2736 if (mrvl_dev_num == 0) { 2737 MRVL_LOG(INFO, "Perform MUSDK deinit"); 2738 mrvl_deinit_hifs(); 2739 mrvl_deinit_pp2(); 2740 mv_sys_dma_mem_destroy(); 2741 } 2742 2743 return 0; 2744 } 2745 2746 static struct rte_vdev_driver pmd_mrvl_drv = { 2747 .probe = rte_pmd_mrvl_probe, 2748 .remove = rte_pmd_mrvl_remove, 2749 }; 2750 2751 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 2752 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 2753 2754 RTE_INIT(mrvl_init_log); 2755 static void 2756 mrvl_init_log(void) 2757 { 2758 mrvl_logtype = rte_log_register("pmd.net.mvpp2"); 2759 if (mrvl_logtype >= 0) 2760 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE); 2761 } 2762