1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Marvell International Ltd. 3 * Copyright(c) 2017-2021 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_string_fns.h> 8 #include <ethdev_driver.h> 9 #include <rte_kvargs.h> 10 #include <rte_log.h> 11 #include <rte_malloc.h> 12 #include <bus_vdev_driver.h> 13 14 #include <fcntl.h> 15 #include <linux/ethtool.h> 16 #include <linux/sockios.h> 17 #include <net/if.h> 18 #include <net/if_arp.h> 19 #include <sys/ioctl.h> 20 #include <sys/socket.h> 21 #include <sys/stat.h> 22 #include <sys/types.h> 23 24 #include <rte_mvep_common.h> 25 #include "mrvl_ethdev.h" 26 #include "mrvl_qos.h" 27 #include "mrvl_flow.h" 28 #include "mrvl_mtr.h" 29 #include "mrvl_tm.h" 30 31 /* bitmask with reserved hifs */ 32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 33 /* bitmask with reserved bpools */ 34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 35 /* bitmask with reserved kernel RSS tables */ 36 #define MRVL_MUSDK_RSS_RESERVED 0x0F 37 /* maximum number of available hifs */ 38 #define MRVL_MUSDK_HIFS_MAX 9 39 40 /* prefetch shift */ 41 #define MRVL_MUSDK_PREFETCH_SHIFT 2 42 43 /* TCAM has 25 entries reserved for uc/mc filter entries 44 * + 1 for primary mac address 45 */ 46 #define MRVL_MAC_ADDRS_MAX (1 + 25) 47 #define MRVL_MATCH_LEN 16 48 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 49 /* Maximum allowable packet size */ 50 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 51 52 #define MRVL_IFACE_NAME_ARG "iface" 53 #define MRVL_CFG_ARG "cfg" 54 55 #define MRVL_ARP_LENGTH 28 56 57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000 59 60 /** Port Rx offload capabilities */ 61 #define MRVL_RX_OFFLOADS (RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \ 62 RTE_ETH_RX_OFFLOAD_CHECKSUM) 63 64 /** Port Tx offloads capabilities */ 65 #define MRVL_TX_OFFLOAD_CHECKSUM (RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \ 66 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \ 67 RTE_ETH_TX_OFFLOAD_TCP_CKSUM) 68 #define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \ 69 RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 70 71 #define MRVL_TX_PKT_OFFLOADS (RTE_MBUF_F_TX_IP_CKSUM | \ 72 RTE_MBUF_F_TX_TCP_CKSUM | \ 73 RTE_MBUF_F_TX_UDP_CKSUM) 74 75 static const char * const valid_args[] = { 76 MRVL_IFACE_NAME_ARG, 77 MRVL_CFG_ARG, 78 NULL 79 }; 80 81 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 82 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 83 static int used_bpools[PP2_NUM_PKT_PROC] = { 84 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 85 }; 86 87 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 88 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 89 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 90 static int dummy_pool_id[PP2_NUM_PKT_PROC]; 91 struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0}; 92 93 struct mrvl_ifnames { 94 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 95 int idx; 96 }; 97 98 /* 99 * To use buffer harvesting based on loopback port shadow queue structure 100 * was introduced for buffers information bookkeeping. 101 * 102 * Before sending the packet, related buffer information (pp2_buff_inf) is 103 * stored in shadow queue. After packet is transmitted no longer used 104 * packet buffer is released back to it's original hardware pool, 105 * on condition it originated from interface. 106 * In case it was generated by application itself i.e: mbuf->port field is 107 * 0xff then its released to software mempool. 108 */ 109 struct mrvl_shadow_txq { 110 int head; /* write index - used when sending buffers */ 111 int tail; /* read index - used when releasing buffers */ 112 u16 size; /* queue occupied size */ 113 u16 num_to_release; /* number of descriptors sent, that can be 114 * released 115 */ 116 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 117 }; 118 119 struct mrvl_rxq { 120 struct mrvl_priv *priv; 121 struct rte_mempool *mp; 122 int queue_id; 123 int port_id; 124 int cksum_enabled; 125 uint64_t bytes_recv; 126 uint64_t drop_mac; 127 }; 128 129 struct mrvl_txq { 130 struct mrvl_priv *priv; 131 int queue_id; 132 int port_id; 133 uint64_t bytes_sent; 134 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 135 int tx_deferred_start; 136 }; 137 138 static int mrvl_lcore_first; 139 static int mrvl_lcore_last; 140 static int mrvl_dev_num; 141 142 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 143 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 144 struct pp2_hif *hif, unsigned int core_id, 145 struct mrvl_shadow_txq *sq, int qid, int force); 146 147 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 148 uint16_t nb_pkts); 149 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 150 uint16_t nb_pkts); 151 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); 152 static void mrvl_deinit_pp2(void); 153 static void mrvl_deinit_hifs(void); 154 155 static int 156 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 157 uint32_t index, uint32_t vmdq __rte_unused); 158 static int 159 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 160 static int 161 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 162 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev); 163 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev); 164 static int 165 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 166 167 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 168 #name, offsetof(struct pp2_ppio_statistics, name), \ 169 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 170 } 171 172 /* Table with xstats data */ 173 static struct { 174 const char *name; 175 unsigned int offset; 176 unsigned int size; 177 } mrvl_xstats_tbl[] = { 178 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 179 MRVL_XSTATS_TBL_ENTRY(rx_packets), 180 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 181 MRVL_XSTATS_TBL_ENTRY(rx_errors), 182 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 183 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 184 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 185 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 186 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 187 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 188 MRVL_XSTATS_TBL_ENTRY(tx_packets), 189 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 190 MRVL_XSTATS_TBL_ENTRY(tx_errors) 191 }; 192 193 static inline int 194 mrvl_reserve_bit(int *bitmap, int max) 195 { 196 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 197 198 if (n >= max) 199 return -1; 200 201 *bitmap |= 1 << n; 202 203 return n; 204 } 205 206 static int 207 mrvl_pp2_fixup_init(void) 208 { 209 struct pp2_bpool_params bpool_params; 210 char name[15]; 211 int err, i; 212 213 memset(dummy_pool, 0, sizeof(dummy_pool)); 214 for (i = 0; i < pp2_get_num_inst(); i++) { 215 dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i], 216 PP2_BPOOL_NUM_POOLS); 217 if (dummy_pool_id[i] < 0) { 218 MRVL_LOG(ERR, "Can't find free pool\n"); 219 return -1; 220 } 221 222 memset(name, 0, sizeof(name)); 223 snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]); 224 memset(&bpool_params, 0, sizeof(bpool_params)); 225 bpool_params.match = name; 226 bpool_params.buff_len = MRVL_PKT_OFFS; 227 bpool_params.dummy_short_pool = 1; 228 err = pp2_bpool_init(&bpool_params, &dummy_pool[i]); 229 if (err != 0 || !dummy_pool[i]) { 230 MRVL_LOG(ERR, "BPool init failed!\n"); 231 used_bpools[i] &= ~(1 << dummy_pool_id[i]); 232 return -1; 233 } 234 } 235 236 return 0; 237 } 238 239 /** 240 * Initialize packet processor. 241 * 242 * @return 243 * 0 on success, negative error value otherwise. 244 */ 245 static int 246 mrvl_init_pp2(void) 247 { 248 struct pp2_init_params init_params; 249 int err; 250 251 memset(&init_params, 0, sizeof(init_params)); 252 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 253 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 254 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 255 if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) 256 memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, 257 sizeof(struct pp2_parse_udfs)); 258 err = pp2_init(&init_params); 259 if (err != 0) { 260 MRVL_LOG(ERR, "PP2 init failed"); 261 return -1; 262 } 263 264 err = mrvl_pp2_fixup_init(); 265 if (err != 0) { 266 MRVL_LOG(ERR, "PP2 fixup init failed"); 267 return -1; 268 } 269 270 return 0; 271 } 272 273 static void 274 mrvl_pp2_fixup_deinit(void) 275 { 276 int i; 277 278 for (i = 0; i < PP2_NUM_PKT_PROC; i++) { 279 if (!dummy_pool[i]) 280 continue; 281 pp2_bpool_deinit(dummy_pool[i]); 282 used_bpools[i] &= ~(1 << dummy_pool_id[i]); 283 } 284 } 285 286 /** 287 * Deinitialize packet processor. 288 * 289 * @return 290 * 0 on success, negative error value otherwise. 291 */ 292 static void 293 mrvl_deinit_pp2(void) 294 { 295 mrvl_pp2_fixup_deinit(); 296 pp2_deinit(); 297 } 298 299 static inline void 300 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) 301 { 302 sq->ent[sq->head].buff.cookie = (uint64_t)buf; 303 sq->ent[sq->head].buff.addr = buf ? 304 rte_mbuf_data_iova_default(buf) : 0; 305 306 sq->ent[sq->head].bpool = 307 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS || 308 buf->refcnt > 1)) ? NULL : 309 mrvl_port_to_bpool_lookup[buf->port]; 310 311 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 312 sq->size++; 313 } 314 315 /** 316 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 317 */ 318 static void 319 mrvl_deinit_hifs(void) 320 { 321 int i; 322 323 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 324 if (hifs[i]) 325 pp2_hif_deinit(hifs[i]); 326 } 327 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 328 memset(hifs, 0, sizeof(hifs)); 329 } 330 331 static inline void 332 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf) 333 { 334 pp2_ppio_outq_desc_reset(desc); 335 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf)); 336 pp2_ppio_outq_desc_set_pkt_offset(desc, 0); 337 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf)); 338 } 339 340 static inline int 341 mrvl_get_bpool_size(int pp2_id, int pool_id) 342 { 343 int i; 344 int size = 0; 345 346 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 347 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 348 349 return size; 350 } 351 352 static int 353 mrvl_init_hif(int core_id) 354 { 355 struct pp2_hif_params params; 356 char match[MRVL_MATCH_LEN]; 357 int ret; 358 359 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 360 if (ret < 0) { 361 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 362 return ret; 363 } 364 365 snprintf(match, sizeof(match), "hif-%d", ret); 366 memset(¶ms, 0, sizeof(params)); 367 params.match = match; 368 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 369 ret = pp2_hif_init(¶ms, &hifs[core_id]); 370 if (ret) { 371 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 372 return ret; 373 } 374 375 return 0; 376 } 377 378 static inline struct pp2_hif* 379 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 380 { 381 int ret; 382 383 if (likely(hifs[core_id] != NULL)) 384 return hifs[core_id]; 385 386 rte_spinlock_lock(&priv->lock); 387 388 ret = mrvl_init_hif(core_id); 389 if (ret < 0) { 390 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 391 goto out; 392 } 393 394 if (core_id < mrvl_lcore_first) 395 mrvl_lcore_first = core_id; 396 397 if (core_id > mrvl_lcore_last) 398 mrvl_lcore_last = core_id; 399 out: 400 rte_spinlock_unlock(&priv->lock); 401 402 return hifs[core_id]; 403 } 404 405 /** 406 * Set tx burst function according to offload flag 407 * 408 * @param dev 409 * Pointer to Ethernet device structure. 410 */ 411 static void 412 mrvl_set_tx_function(struct rte_eth_dev *dev) 413 { 414 struct mrvl_priv *priv = dev->data->dev_private; 415 416 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 417 if (priv->multiseg) { 418 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n"); 419 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst; 420 } else { 421 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n"); 422 dev->tx_pkt_burst = mrvl_tx_pkt_burst; 423 } 424 } 425 426 /** 427 * Configure rss based on dpdk rss configuration. 428 * 429 * @param priv 430 * Pointer to private structure. 431 * @param rss_conf 432 * Pointer to RSS configuration. 433 * 434 * @return 435 * 0 on success, negative error value otherwise. 436 */ 437 static int 438 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 439 { 440 if (rss_conf->rss_key) 441 MRVL_LOG(WARNING, "Changing hash key is not supported"); 442 443 if (rss_conf->rss_hf == 0) { 444 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 445 } else if (rss_conf->rss_hf & RTE_ETH_RSS_IPV4) { 446 priv->ppio_params.inqs_params.hash_type = 447 PP2_PPIO_HASH_T_2_TUPLE; 448 } else if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { 449 priv->ppio_params.inqs_params.hash_type = 450 PP2_PPIO_HASH_T_5_TUPLE; 451 priv->rss_hf_tcp = 1; 452 } else if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { 453 priv->ppio_params.inqs_params.hash_type = 454 PP2_PPIO_HASH_T_5_TUPLE; 455 priv->rss_hf_tcp = 0; 456 } else { 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 /** 464 * Ethernet device configuration. 465 * 466 * Prepare the driver for a given number of TX and RX queues and 467 * configure RSS. 468 * 469 * @param dev 470 * Pointer to Ethernet device structure. 471 * 472 * @return 473 * 0 on success, negative error value otherwise. 474 */ 475 static int 476 mrvl_dev_configure(struct rte_eth_dev *dev) 477 { 478 struct mrvl_priv *priv = dev->data->dev_private; 479 int ret; 480 481 if (priv->ppio) { 482 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 483 return -EINVAL; 484 } 485 486 if (dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_NONE && 487 dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_RSS) { 488 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 489 dev->data->dev_conf.rxmode.mq_mode); 490 return -EINVAL; 491 } 492 493 if (dev->data->dev_conf.rxmode.mtu > priv->max_mtu) { 494 MRVL_LOG(ERR, "MTU %u is larger than max_mtu %u\n", 495 dev->data->dev_conf.rxmode.mtu, 496 priv->max_mtu); 497 return -EINVAL; 498 } 499 500 if (dev->data->dev_conf.txmode.offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 501 priv->multiseg = 1; 502 503 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 504 dev->data->nb_rx_queues); 505 if (ret < 0) 506 return ret; 507 508 ret = mrvl_configure_txqs(priv, dev->data->port_id, 509 dev->data->nb_tx_queues); 510 if (ret < 0) 511 return ret; 512 513 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 514 priv->ppio_params.maintain_stats = 1; 515 priv->nb_rx_queues = dev->data->nb_rx_queues; 516 517 ret = mrvl_tm_init(dev); 518 if (ret < 0) 519 return ret; 520 521 if (dev->data->nb_rx_queues == 1 && 522 dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) { 523 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 524 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 525 priv->configured = 1; 526 return 0; 527 } 528 529 ret = mrvl_configure_rss(priv, 530 &dev->data->dev_conf.rx_adv_conf.rss_conf); 531 if (ret < 0) 532 return ret; 533 534 priv->configured = 1; 535 536 return 0; 537 } 538 539 /** 540 * DPDK callback to change the MTU. 541 * 542 * Setting the MTU affects hardware MRU (packets larger than the MRU 543 * will be dropped). 544 * 545 * @param dev 546 * Pointer to Ethernet device structure. 547 * @param mtu 548 * New MTU. 549 * 550 * @return 551 * 0 on success, negative error value otherwise. 552 */ 553 static int 554 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 555 { 556 struct mrvl_priv *priv = dev->data->dev_private; 557 uint16_t mru; 558 uint16_t mbuf_data_size = 0; /* SW buffer size */ 559 int ret; 560 561 mru = MRVL_PP2_MTU_TO_MRU(mtu); 562 /* 563 * min_rx_buf_size is equal to mbuf data size 564 * if pmd didn't set it differently 565 */ 566 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 567 /* Prevent PMD from: 568 * - setting mru greater than the mbuf size resulting in 569 * hw and sw buffer size mismatch 570 * - setting mtu that requires the support of scattered packets 571 * when this feature has not been enabled/supported so far 572 * (TODO check scattered_rx flag here once scattered RX is supported). 573 */ 574 if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) { 575 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS; 576 mtu = MRVL_PP2_MRU_TO_MTU(mru); 577 MRVL_LOG(WARNING, "MTU too big, max MTU possible limited " 578 "by current mbuf size: %u. Set MTU to %u, MRU to %u", 579 mbuf_data_size, mtu, mru); 580 } 581 582 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) { 583 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru); 584 return -EINVAL; 585 } 586 587 if (!priv->ppio) 588 return 0; 589 590 ret = pp2_ppio_set_mru(priv->ppio, mru); 591 if (ret) { 592 MRVL_LOG(ERR, "Failed to change MRU"); 593 return ret; 594 } 595 596 ret = pp2_ppio_set_mtu(priv->ppio, mtu); 597 if (ret) { 598 MRVL_LOG(ERR, "Failed to change MTU"); 599 return ret; 600 } 601 602 return 0; 603 } 604 605 /** 606 * DPDK callback to bring the link up. 607 * 608 * @param dev 609 * Pointer to Ethernet device structure. 610 * 611 * @return 612 * 0 on success, negative error value otherwise. 613 */ 614 static int 615 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 616 { 617 struct mrvl_priv *priv = dev->data->dev_private; 618 int ret; 619 620 if (!priv->ppio) { 621 dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 622 return 0; 623 } 624 625 ret = pp2_ppio_enable(priv->ppio); 626 if (ret) 627 return ret; 628 629 /* 630 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 631 * as pp2_ppio_enable() changes port->t_mode from default 0 to 632 * PP2_TRAFFIC_INGRESS_EGRESS. 633 * 634 * Set mtu to default DPDK value here. 635 */ 636 ret = mrvl_mtu_set(dev, dev->data->mtu); 637 if (ret) { 638 pp2_ppio_disable(priv->ppio); 639 return ret; 640 } 641 642 dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 643 return 0; 644 } 645 646 /** 647 * DPDK callback to bring the link down. 648 * 649 * @param dev 650 * Pointer to Ethernet device structure. 651 * 652 * @return 653 * 0 on success, negative error value otherwise. 654 */ 655 static int 656 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 657 { 658 struct mrvl_priv *priv = dev->data->dev_private; 659 int ret; 660 661 if (!priv->ppio) { 662 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 663 return 0; 664 } 665 ret = pp2_ppio_disable(priv->ppio); 666 if (ret) 667 return ret; 668 669 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 670 return 0; 671 } 672 673 /** 674 * DPDK callback to start tx queue. 675 * 676 * @param dev 677 * Pointer to Ethernet device structure. 678 * @param queue_id 679 * Transmit queue index. 680 * 681 * @return 682 * 0 on success, negative error value otherwise. 683 */ 684 static int 685 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 686 { 687 struct mrvl_priv *priv = dev->data->dev_private; 688 int ret; 689 690 if (!priv) 691 return -EPERM; 692 693 /* passing 1 enables given tx queue */ 694 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 695 if (ret) { 696 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 697 return ret; 698 } 699 700 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 701 702 return 0; 703 } 704 705 /** 706 * DPDK callback to stop tx queue. 707 * 708 * @param dev 709 * Pointer to Ethernet device structure. 710 * @param queue_id 711 * Transmit queue index. 712 * 713 * @return 714 * 0 on success, negative error value otherwise. 715 */ 716 static int 717 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 718 { 719 struct mrvl_priv *priv = dev->data->dev_private; 720 int ret; 721 722 if (!priv->ppio) 723 return -EPERM; 724 725 /* passing 0 disables given tx queue */ 726 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 727 if (ret) { 728 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 729 return ret; 730 } 731 732 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 733 734 return 0; 735 } 736 737 /** 738 * Populate VLAN Filter configuration. 739 * 740 * @param dev 741 * Pointer to Ethernet device structure. 742 * @param on 743 * Toggle filter. 744 * 745 * @return 746 * 0 on success, negative error value otherwise. 747 */ 748 static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on) 749 { 750 uint32_t j; 751 int ret; 752 struct rte_vlan_filter_conf *vfc; 753 754 vfc = &dev->data->vlan_filter_conf; 755 for (j = 0; j < RTE_DIM(vfc->ids); j++) { 756 uint64_t vlan; 757 uint64_t vbit; 758 uint64_t ids = vfc->ids[j]; 759 760 if (ids == 0) 761 continue; 762 763 while (ids) { 764 vlan = 64 * j; 765 /* count trailing zeroes */ 766 vbit = ~ids & (ids - 1); 767 /* clear least significant bit set */ 768 ids ^= (ids ^ (ids - 1)) ^ vbit; 769 for (; vbit; vlan++) 770 vbit >>= 1; 771 ret = mrvl_vlan_filter_set(dev, vlan, on); 772 if (ret) { 773 MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); 774 return ret; 775 } 776 } 777 } 778 779 return 0; 780 } 781 782 /** 783 * DPDK callback to start the device. 784 * 785 * @param dev 786 * Pointer to Ethernet device structure. 787 * 788 * @return 789 * 0 on success, negative errno value on failure. 790 */ 791 static int 792 mrvl_dev_start(struct rte_eth_dev *dev) 793 { 794 struct mrvl_priv *priv = dev->data->dev_private; 795 char match[MRVL_MATCH_LEN]; 796 int ret = 0, i, def_init_size; 797 struct rte_ether_addr *mac_addr; 798 799 if (priv->ppio) 800 return mrvl_dev_set_link_up(dev); 801 802 snprintf(match, sizeof(match), "ppio-%d:%d", 803 priv->pp_id, priv->ppio_id); 804 priv->ppio_params.match = match; 805 priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; 806 priv->forward_bad_frames = 0; 807 priv->fill_bpool_buffs = MRVL_BURST_SIZE; 808 809 if (mrvl_cfg) { 810 priv->ppio_params.eth_start_hdr = 811 mrvl_cfg->port[dev->data->port_id].eth_start_hdr; 812 priv->forward_bad_frames = 813 mrvl_cfg->port[dev->data->port_id].forward_bad_frames; 814 priv->fill_bpool_buffs = 815 mrvl_cfg->port[dev->data->port_id].fill_bpool_buffs; 816 } 817 818 /* 819 * Calculate the minimum bpool size for refill feature as follows: 820 * 2 default burst sizes multiply by number of rx queues. 821 * If the bpool size will be below this value, new buffers will 822 * be added to the pool. 823 */ 824 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 825 826 /* In case initial bpool size configured in queues setup is 827 * smaller than minimum size add more buffers 828 */ 829 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 830 if (priv->bpool_init_size < def_init_size) { 831 int buffs_to_add = def_init_size - priv->bpool_init_size; 832 833 priv->bpool_init_size += buffs_to_add; 834 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 835 if (ret) 836 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 837 } 838 839 /* 840 * Calculate the maximum bpool size for refill feature as follows: 841 * maximum number of descriptors in rx queue multiply by number 842 * of rx queues plus minimum bpool size. 843 * In case the bpool size will exceed this value, superfluous buffers 844 * will be removed 845 */ 846 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 847 priv->bpool_min_size; 848 849 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 850 if (ret) { 851 MRVL_LOG(ERR, "Failed to init ppio"); 852 return ret; 853 } 854 855 /* 856 * In case there are some stale uc/mc mac addresses flush them 857 * here. It cannot be done during mrvl_dev_close() as port information 858 * is already gone at that point (due to pp2_ppio_deinit() in 859 * mrvl_dev_stop()). 860 */ 861 if (!priv->uc_mc_flushed) { 862 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 863 if (ret) { 864 MRVL_LOG(ERR, 865 "Failed to flush uc/mc filter list"); 866 goto out; 867 } 868 priv->uc_mc_flushed = 1; 869 } 870 871 ret = mrvl_mtu_set(dev, dev->data->mtu); 872 if (ret) 873 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); 874 875 if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0])) 876 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]); 877 878 for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) { 879 mac_addr = &dev->data->mac_addrs[i]; 880 881 /* skip zero address */ 882 if (rte_is_zero_ether_addr(mac_addr)) 883 continue; 884 885 mrvl_mac_addr_add(dev, mac_addr, i, 0); 886 } 887 888 if (dev->data->all_multicast == 1) 889 mrvl_allmulticast_enable(dev); 890 891 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 892 ret = mrvl_populate_vlan_table(dev, 1); 893 if (ret) { 894 MRVL_LOG(ERR, "Failed to populate VLAN table"); 895 goto out; 896 } 897 } 898 899 /* For default QoS config, don't start classifier. */ 900 if (mrvl_cfg && 901 mrvl_cfg->port[dev->data->port_id].use_qos_global_defaults == 0) { 902 ret = mrvl_start_qos_mapping(priv); 903 if (ret) { 904 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 905 goto out; 906 } 907 } 908 909 ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode); 910 if (ret) { 911 MRVL_LOG(ERR, "Failed to set loopback"); 912 goto out; 913 } 914 915 if (dev->data->promiscuous == 1) 916 mrvl_promiscuous_enable(dev); 917 918 if (priv->flow_ctrl) { 919 ret = mrvl_flow_ctrl_set(dev, &priv->fc_conf); 920 if (ret) { 921 MRVL_LOG(ERR, "Failed to configure flow control"); 922 goto out; 923 } 924 priv->flow_ctrl = 0; 925 } 926 927 if (dev->data->dev_link.link_status == RTE_ETH_LINK_UP) { 928 ret = mrvl_dev_set_link_up(dev); 929 if (ret) { 930 MRVL_LOG(ERR, "Failed to set link up"); 931 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 932 goto out; 933 } 934 } 935 936 /* start tx queues */ 937 for (i = 0; i < dev->data->nb_tx_queues; i++) { 938 struct mrvl_txq *txq = dev->data->tx_queues[i]; 939 940 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 941 942 if (!txq->tx_deferred_start) 943 continue; 944 945 /* 946 * All txqs are started by default. Stop them 947 * so that tx_deferred_start works as expected. 948 */ 949 ret = mrvl_tx_queue_stop(dev, i); 950 if (ret) 951 goto out; 952 } 953 954 mrvl_flow_init(dev); 955 mrvl_mtr_init(dev); 956 mrvl_set_tx_function(dev); 957 958 return 0; 959 out: 960 MRVL_LOG(ERR, "Failed to start device"); 961 pp2_ppio_deinit(priv->ppio); 962 return ret; 963 } 964 965 /** 966 * Flush receive queues. 967 * 968 * @param dev 969 * Pointer to Ethernet device structure. 970 */ 971 static void 972 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 973 { 974 int i; 975 976 MRVL_LOG(INFO, "Flushing rx queues"); 977 for (i = 0; i < dev->data->nb_rx_queues; i++) { 978 int ret, num; 979 980 do { 981 struct mrvl_rxq *q = dev->data->rx_queues[i]; 982 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 983 984 num = MRVL_PP2_RXD_MAX; 985 ret = pp2_ppio_recv(q->priv->ppio, 986 q->priv->rxq_map[q->queue_id].tc, 987 q->priv->rxq_map[q->queue_id].inq, 988 descs, (uint16_t *)&num); 989 } while (ret == 0 && num); 990 } 991 } 992 993 /** 994 * Flush transmit shadow queues. 995 * 996 * @param dev 997 * Pointer to Ethernet device structure. 998 */ 999 static void 1000 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 1001 { 1002 int i, j; 1003 struct mrvl_txq *txq; 1004 1005 MRVL_LOG(INFO, "Flushing tx shadow queues"); 1006 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1007 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 1008 1009 for (j = 0; j < RTE_MAX_LCORE; j++) { 1010 struct mrvl_shadow_txq *sq; 1011 1012 if (!hifs[j]) 1013 continue; 1014 1015 sq = &txq->shadow_txqs[j]; 1016 mrvl_free_sent_buffers(txq->priv->ppio, 1017 hifs[j], j, sq, txq->queue_id, 1); 1018 while (sq->tail != sq->head) { 1019 uint64_t addr = cookie_addr_high | 1020 sq->ent[sq->tail].buff.cookie; 1021 rte_pktmbuf_free( 1022 (struct rte_mbuf *)addr); 1023 sq->tail = (sq->tail + 1) & 1024 MRVL_PP2_TX_SHADOWQ_MASK; 1025 } 1026 memset(sq, 0, sizeof(*sq)); 1027 } 1028 } 1029 } 1030 1031 /** 1032 * Flush hardware bpool (buffer-pool). 1033 * 1034 * @param dev 1035 * Pointer to Ethernet device structure. 1036 */ 1037 static void 1038 mrvl_flush_bpool(struct rte_eth_dev *dev) 1039 { 1040 struct mrvl_priv *priv = dev->data->dev_private; 1041 struct pp2_hif *hif; 1042 uint32_t num; 1043 int ret; 1044 unsigned int core_id = rte_lcore_id(); 1045 1046 if (core_id == LCORE_ID_ANY) 1047 core_id = rte_get_main_lcore(); 1048 1049 hif = mrvl_get_hif(priv, core_id); 1050 1051 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 1052 if (ret) { 1053 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 1054 return; 1055 } 1056 1057 while (num--) { 1058 struct pp2_buff_inf inf; 1059 uint64_t addr; 1060 1061 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 1062 if (ret) 1063 break; 1064 1065 addr = cookie_addr_high | inf.cookie; 1066 rte_pktmbuf_free((struct rte_mbuf *)addr); 1067 } 1068 } 1069 1070 /** 1071 * DPDK callback to stop the device. 1072 * 1073 * @param dev 1074 * Pointer to Ethernet device structure. 1075 */ 1076 static int 1077 mrvl_dev_stop(struct rte_eth_dev *dev) 1078 { 1079 return mrvl_dev_set_link_down(dev); 1080 } 1081 1082 /** 1083 * DPDK callback to close the device. 1084 * 1085 * @param dev 1086 * Pointer to Ethernet device structure. 1087 */ 1088 static int 1089 mrvl_dev_close(struct rte_eth_dev *dev) 1090 { 1091 struct mrvl_priv *priv = dev->data->dev_private; 1092 size_t i; 1093 1094 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1095 return 0; 1096 1097 mrvl_flush_rx_queues(dev); 1098 mrvl_flush_tx_shadow_queues(dev); 1099 mrvl_flow_deinit(dev); 1100 mrvl_mtr_deinit(dev); 1101 1102 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 1103 struct pp2_ppio_tc_params *tc_params = 1104 &priv->ppio_params.inqs_params.tcs_params[i]; 1105 1106 if (tc_params->inqs_params) { 1107 rte_free(tc_params->inqs_params); 1108 tc_params->inqs_params = NULL; 1109 } 1110 } 1111 1112 if (priv->cls_tbl) { 1113 pp2_cls_tbl_deinit(priv->cls_tbl); 1114 priv->cls_tbl = NULL; 1115 } 1116 1117 if (priv->qos_tbl) { 1118 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 1119 priv->qos_tbl = NULL; 1120 } 1121 1122 mrvl_flush_bpool(dev); 1123 mrvl_tm_deinit(dev); 1124 1125 if (priv->ppio) { 1126 pp2_ppio_deinit(priv->ppio); 1127 priv->ppio = NULL; 1128 } 1129 1130 /* policer must be released after ppio deinitialization */ 1131 if (priv->default_policer) { 1132 pp2_cls_plcr_deinit(priv->default_policer); 1133 priv->default_policer = NULL; 1134 } 1135 1136 1137 if (priv->bpool) { 1138 pp2_bpool_deinit(priv->bpool); 1139 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 1140 priv->bpool = NULL; 1141 } 1142 1143 mrvl_dev_num--; 1144 1145 if (mrvl_dev_num == 0) { 1146 MRVL_LOG(INFO, "Perform MUSDK deinit"); 1147 mrvl_deinit_hifs(); 1148 mrvl_deinit_pp2(); 1149 rte_mvep_deinit(MVEP_MOD_T_PP2); 1150 } 1151 1152 return 0; 1153 } 1154 1155 /** 1156 * DPDK callback to retrieve physical link information. 1157 * 1158 * @param dev 1159 * Pointer to Ethernet device structure. 1160 * @param wait_to_complete 1161 * Wait for request completion (ignored). 1162 * 1163 * @return 1164 * 0 on success, negative error value otherwise. 1165 */ 1166 static int 1167 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 1168 { 1169 /* 1170 * TODO 1171 * once MUSDK provides necessary API use it here 1172 */ 1173 struct mrvl_priv *priv = dev->data->dev_private; 1174 struct ethtool_cmd edata; 1175 struct ifreq req; 1176 int ret, fd, link_up; 1177 1178 if (!priv->ppio) 1179 return -EPERM; 1180 1181 edata.cmd = ETHTOOL_GSET; 1182 1183 strcpy(req.ifr_name, dev->data->name); 1184 req.ifr_data = (void *)&edata; 1185 1186 fd = socket(AF_INET, SOCK_DGRAM, 0); 1187 if (fd == -1) 1188 return -EFAULT; 1189 1190 ret = ioctl(fd, SIOCETHTOOL, &req); 1191 if (ret == -1) { 1192 close(fd); 1193 return -EFAULT; 1194 } 1195 1196 close(fd); 1197 1198 switch (ethtool_cmd_speed(&edata)) { 1199 case SPEED_10: 1200 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_10M; 1201 break; 1202 case SPEED_100: 1203 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_100M; 1204 break; 1205 case SPEED_1000: 1206 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_1G; 1207 break; 1208 case SPEED_2500: 1209 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 1210 break; 1211 case SPEED_10000: 1212 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_10G; 1213 break; 1214 default: 1215 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE; 1216 } 1217 1218 dev->data->dev_link.link_duplex = edata.duplex ? RTE_ETH_LINK_FULL_DUPLEX : 1219 RTE_ETH_LINK_HALF_DUPLEX; 1220 dev->data->dev_link.link_autoneg = edata.autoneg ? RTE_ETH_LINK_AUTONEG : 1221 RTE_ETH_LINK_FIXED; 1222 pp2_ppio_get_link_state(priv->ppio, &link_up); 1223 dev->data->dev_link.link_status = link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 1224 1225 return 0; 1226 } 1227 1228 /** 1229 * DPDK callback to enable promiscuous mode. 1230 * 1231 * @param dev 1232 * Pointer to Ethernet device structure. 1233 * 1234 * @return 1235 * 0 on success, negative error value otherwise. 1236 */ 1237 static int 1238 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 1239 { 1240 struct mrvl_priv *priv = dev->data->dev_private; 1241 int ret; 1242 1243 if (priv->isolated) 1244 return -ENOTSUP; 1245 1246 if (!priv->ppio) 1247 return 0; 1248 1249 ret = pp2_ppio_set_promisc(priv->ppio, 1); 1250 if (ret) { 1251 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 1252 return -EAGAIN; 1253 } 1254 1255 return 0; 1256 } 1257 1258 /** 1259 * DPDK callback to enable allmulti mode. 1260 * 1261 * @param dev 1262 * Pointer to Ethernet device structure. 1263 * 1264 * @return 1265 * 0 on success, negative error value otherwise. 1266 */ 1267 static int 1268 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 1269 { 1270 struct mrvl_priv *priv = dev->data->dev_private; 1271 int ret; 1272 1273 if (priv->isolated) 1274 return -ENOTSUP; 1275 1276 if (!priv->ppio) 1277 return 0; 1278 1279 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 1280 if (ret) { 1281 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 1282 return -EAGAIN; 1283 } 1284 1285 return 0; 1286 } 1287 1288 /** 1289 * DPDK callback to disable promiscuous mode. 1290 * 1291 * @param dev 1292 * Pointer to Ethernet device structure. 1293 * 1294 * @return 1295 * 0 on success, negative error value otherwise. 1296 */ 1297 static int 1298 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 1299 { 1300 struct mrvl_priv *priv = dev->data->dev_private; 1301 int ret; 1302 1303 if (priv->isolated) 1304 return -ENOTSUP; 1305 1306 if (!priv->ppio) 1307 return 0; 1308 1309 ret = pp2_ppio_set_promisc(priv->ppio, 0); 1310 if (ret) { 1311 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 1312 return -EAGAIN; 1313 } 1314 1315 return 0; 1316 } 1317 1318 /** 1319 * DPDK callback to disable allmulticast mode. 1320 * 1321 * @param dev 1322 * Pointer to Ethernet device structure. 1323 * 1324 * @return 1325 * 0 on success, negative error value otherwise. 1326 */ 1327 static int 1328 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 1329 { 1330 struct mrvl_priv *priv = dev->data->dev_private; 1331 int ret; 1332 1333 if (priv->isolated) 1334 return -ENOTSUP; 1335 1336 if (!priv->ppio) 1337 return 0; 1338 1339 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 1340 if (ret) { 1341 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 1342 return -EAGAIN; 1343 } 1344 1345 return 0; 1346 } 1347 1348 /** 1349 * DPDK callback to remove a MAC address. 1350 * 1351 * @param dev 1352 * Pointer to Ethernet device structure. 1353 * @param index 1354 * MAC address index. 1355 */ 1356 static void 1357 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 1358 { 1359 struct mrvl_priv *priv = dev->data->dev_private; 1360 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1361 int ret; 1362 1363 if (priv->isolated) 1364 return; 1365 1366 if (!priv->ppio) 1367 return; 1368 1369 ret = pp2_ppio_remove_mac_addr(priv->ppio, 1370 dev->data->mac_addrs[index].addr_bytes); 1371 if (ret) { 1372 rte_ether_format_addr(buf, sizeof(buf), 1373 &dev->data->mac_addrs[index]); 1374 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 1375 } 1376 } 1377 1378 /** 1379 * DPDK callback to add a MAC address. 1380 * 1381 * @param dev 1382 * Pointer to Ethernet device structure. 1383 * @param mac_addr 1384 * MAC address to register. 1385 * @param index 1386 * MAC address index. 1387 * @param vmdq 1388 * VMDq pool index to associate address with (unused). 1389 * 1390 * @return 1391 * 0 on success, negative error value otherwise. 1392 */ 1393 static int 1394 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1395 uint32_t index, uint32_t vmdq __rte_unused) 1396 { 1397 struct mrvl_priv *priv = dev->data->dev_private; 1398 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1399 int ret; 1400 1401 if (priv->isolated) 1402 return -ENOTSUP; 1403 1404 if (!priv->ppio) 1405 return 0; 1406 1407 if (index == 0) 1408 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1409 return -1; 1410 1411 /* 1412 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1413 * parameter uc_filter_max. Maximum number of mc addresses is then 1414 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1415 * 21 respectively. 1416 * 1417 * If more than uc_filter_max uc addresses were added to filter list 1418 * then NIC will switch to promiscuous mode automatically. 1419 * 1420 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1421 * were added to filter list then NIC will switch to all-multicast mode 1422 * automatically. 1423 */ 1424 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1425 if (ret) { 1426 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1427 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1428 return -1; 1429 } 1430 1431 return 0; 1432 } 1433 1434 /** 1435 * DPDK callback to set the primary MAC address. 1436 * 1437 * @param dev 1438 * Pointer to Ethernet device structure. 1439 * @param mac_addr 1440 * MAC address to register. 1441 * 1442 * @return 1443 * 0 on success, negative error value otherwise. 1444 */ 1445 static int 1446 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1447 { 1448 struct mrvl_priv *priv = dev->data->dev_private; 1449 int ret; 1450 1451 if (priv->isolated) 1452 return -ENOTSUP; 1453 1454 if (!priv->ppio) 1455 return 0; 1456 1457 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1458 if (ret) { 1459 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1460 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1461 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1462 } 1463 1464 return ret; 1465 } 1466 1467 /** 1468 * DPDK callback to get device statistics. 1469 * 1470 * @param dev 1471 * Pointer to Ethernet device structure. 1472 * @param stats 1473 * Stats structure output buffer. 1474 * 1475 * @return 1476 * 0 on success, negative error value otherwise. 1477 */ 1478 static int 1479 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1480 { 1481 struct mrvl_priv *priv = dev->data->dev_private; 1482 struct pp2_ppio_statistics ppio_stats; 1483 uint64_t drop_mac = 0; 1484 unsigned int i, idx, ret; 1485 1486 if (!priv->ppio) 1487 return -EPERM; 1488 1489 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1490 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1491 struct pp2_ppio_inq_statistics rx_stats; 1492 1493 if (!rxq) 1494 continue; 1495 1496 idx = rxq->queue_id; 1497 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1498 MRVL_LOG(ERR, 1499 "rx queue %d stats out of range (0 - %d)", 1500 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1501 continue; 1502 } 1503 1504 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1505 priv->rxq_map[idx].tc, 1506 priv->rxq_map[idx].inq, 1507 &rx_stats, 0); 1508 if (unlikely(ret)) { 1509 MRVL_LOG(ERR, 1510 "Failed to update rx queue %d stats", idx); 1511 break; 1512 } 1513 1514 stats->q_ibytes[idx] = rxq->bytes_recv; 1515 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1516 stats->q_errors[idx] = rx_stats.drop_early + 1517 rx_stats.drop_fullq + 1518 rx_stats.drop_bm + 1519 rxq->drop_mac; 1520 stats->ibytes += rxq->bytes_recv; 1521 drop_mac += rxq->drop_mac; 1522 } 1523 1524 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1525 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1526 struct pp2_ppio_outq_statistics tx_stats; 1527 1528 if (!txq) 1529 continue; 1530 1531 idx = txq->queue_id; 1532 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1533 MRVL_LOG(ERR, 1534 "tx queue %d stats out of range (0 - %d)", 1535 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1536 } 1537 1538 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1539 &tx_stats, 0); 1540 if (unlikely(ret)) { 1541 MRVL_LOG(ERR, 1542 "Failed to update tx queue %d stats", idx); 1543 break; 1544 } 1545 1546 stats->q_opackets[idx] = tx_stats.deq_desc; 1547 stats->q_obytes[idx] = txq->bytes_sent; 1548 stats->obytes += txq->bytes_sent; 1549 } 1550 1551 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1552 if (unlikely(ret)) { 1553 MRVL_LOG(ERR, "Failed to update port statistics"); 1554 return ret; 1555 } 1556 1557 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1558 stats->opackets += ppio_stats.tx_packets; 1559 stats->imissed += ppio_stats.rx_fullq_dropped + 1560 ppio_stats.rx_bm_dropped + 1561 ppio_stats.rx_early_dropped + 1562 ppio_stats.rx_fifo_dropped + 1563 ppio_stats.rx_cls_dropped; 1564 stats->ierrors = drop_mac; 1565 1566 return 0; 1567 } 1568 1569 /** 1570 * DPDK callback to clear device statistics. 1571 * 1572 * @param dev 1573 * Pointer to Ethernet device structure. 1574 * 1575 * @return 1576 * 0 on success, negative error value otherwise. 1577 */ 1578 static int 1579 mrvl_stats_reset(struct rte_eth_dev *dev) 1580 { 1581 struct mrvl_priv *priv = dev->data->dev_private; 1582 int i; 1583 1584 if (!priv->ppio) 1585 return 0; 1586 1587 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1588 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1589 1590 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1591 priv->rxq_map[i].inq, NULL, 1); 1592 rxq->bytes_recv = 0; 1593 rxq->drop_mac = 0; 1594 } 1595 1596 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1597 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1598 1599 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1600 txq->bytes_sent = 0; 1601 } 1602 1603 return pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1604 } 1605 1606 /** 1607 * DPDK callback to get extended statistics. 1608 * 1609 * @param dev 1610 * Pointer to Ethernet device structure. 1611 * @param stats 1612 * Pointer to xstats table. 1613 * @param n 1614 * Number of entries in xstats table. 1615 * @return 1616 * Negative value on error, number of read xstats otherwise. 1617 */ 1618 static int 1619 mrvl_xstats_get(struct rte_eth_dev *dev, 1620 struct rte_eth_xstat *stats, unsigned int n) 1621 { 1622 struct mrvl_priv *priv = dev->data->dev_private; 1623 struct pp2_ppio_statistics ppio_stats; 1624 unsigned int i, count; 1625 1626 count = RTE_DIM(mrvl_xstats_tbl); 1627 if (n < count) 1628 return count; 1629 1630 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1631 for (i = 0; i < count; i++) { 1632 uint64_t val; 1633 1634 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1635 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1636 mrvl_xstats_tbl[i].offset); 1637 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1638 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1639 mrvl_xstats_tbl[i].offset); 1640 else 1641 return -EINVAL; 1642 1643 stats[i].id = i; 1644 stats[i].value = val; 1645 } 1646 1647 return count; 1648 } 1649 1650 /** 1651 * DPDK callback to reset extended statistics. 1652 * 1653 * @param dev 1654 * Pointer to Ethernet device structure. 1655 * 1656 * @return 1657 * 0 on success, negative error value otherwise. 1658 */ 1659 static int 1660 mrvl_xstats_reset(struct rte_eth_dev *dev) 1661 { 1662 return mrvl_stats_reset(dev); 1663 } 1664 1665 /** 1666 * DPDK callback to get extended statistics names. 1667 * 1668 * @param dev (unused) 1669 * Pointer to Ethernet device structure. 1670 * @param xstats_names 1671 * Pointer to xstats names table. 1672 * @param size 1673 * Size of the xstats names table. 1674 * @return 1675 * Number of read names. 1676 */ 1677 static int 1678 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1679 struct rte_eth_xstat_name *xstats_names, 1680 unsigned int size) 1681 { 1682 unsigned int i; 1683 1684 if (!xstats_names) 1685 return RTE_DIM(mrvl_xstats_tbl); 1686 1687 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1688 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name, 1689 RTE_ETH_XSTATS_NAME_SIZE); 1690 1691 return size; 1692 } 1693 1694 /** 1695 * DPDK callback to get information about the device. 1696 * 1697 * @param dev 1698 * Pointer to Ethernet device structure (unused). 1699 * @param info 1700 * Info structure output buffer. 1701 */ 1702 static int 1703 mrvl_dev_infos_get(struct rte_eth_dev *dev, 1704 struct rte_eth_dev_info *info) 1705 { 1706 struct mrvl_priv *priv = dev->data->dev_private; 1707 1708 info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 1709 1710 info->speed_capa = RTE_ETH_LINK_SPEED_10M | 1711 RTE_ETH_LINK_SPEED_100M | 1712 RTE_ETH_LINK_SPEED_1G | 1713 RTE_ETH_LINK_SPEED_2_5G | 1714 RTE_ETH_LINK_SPEED_10G; 1715 1716 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1717 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1718 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1719 1720 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1721 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1722 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1723 1724 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1725 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1726 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1727 1728 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1729 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1730 1731 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1732 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1733 1734 info->flow_type_rss_offloads = RTE_ETH_RSS_IPV4 | 1735 RTE_ETH_RSS_NONFRAG_IPV4_TCP | 1736 RTE_ETH_RSS_NONFRAG_IPV4_UDP; 1737 1738 /* By default packets are dropped if no descriptors are available */ 1739 info->default_rxconf.rx_drop_en = 1; 1740 1741 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1742 info->max_mtu = priv->max_mtu; 1743 1744 return 0; 1745 } 1746 1747 /** 1748 * Return supported packet types. 1749 * 1750 * @param dev 1751 * Pointer to Ethernet device structure (unused). 1752 * 1753 * @return 1754 * Const pointer to the table with supported packet types. 1755 */ 1756 static const uint32_t * 1757 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1758 { 1759 static const uint32_t ptypes[] = { 1760 RTE_PTYPE_L2_ETHER, 1761 RTE_PTYPE_L2_ETHER_VLAN, 1762 RTE_PTYPE_L2_ETHER_QINQ, 1763 RTE_PTYPE_L3_IPV4, 1764 RTE_PTYPE_L3_IPV4_EXT, 1765 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1766 RTE_PTYPE_L3_IPV6, 1767 RTE_PTYPE_L3_IPV6_EXT, 1768 RTE_PTYPE_L2_ETHER_ARP, 1769 RTE_PTYPE_L4_TCP, 1770 RTE_PTYPE_L4_UDP 1771 }; 1772 1773 return ptypes; 1774 } 1775 1776 /** 1777 * DPDK callback to get information about specific receive queue. 1778 * 1779 * @param dev 1780 * Pointer to Ethernet device structure. 1781 * @param rx_queue_id 1782 * Receive queue index. 1783 * @param qinfo 1784 * Receive queue information structure. 1785 */ 1786 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1787 struct rte_eth_rxq_info *qinfo) 1788 { 1789 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1790 struct mrvl_priv *priv = dev->data->dev_private; 1791 int inq = priv->rxq_map[rx_queue_id].inq; 1792 int tc = priv->rxq_map[rx_queue_id].tc; 1793 struct pp2_ppio_tc_params *tc_params = 1794 &priv->ppio_params.inqs_params.tcs_params[tc]; 1795 1796 qinfo->mp = q->mp; 1797 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1798 } 1799 1800 /** 1801 * DPDK callback to get information about specific transmit queue. 1802 * 1803 * @param dev 1804 * Pointer to Ethernet device structure. 1805 * @param tx_queue_id 1806 * Transmit queue index. 1807 * @param qinfo 1808 * Transmit queue information structure. 1809 */ 1810 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1811 struct rte_eth_txq_info *qinfo) 1812 { 1813 struct mrvl_priv *priv = dev->data->dev_private; 1814 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1815 1816 qinfo->nb_desc = 1817 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1818 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1819 } 1820 1821 /** 1822 * DPDK callback to Configure a VLAN filter. 1823 * 1824 * @param dev 1825 * Pointer to Ethernet device structure. 1826 * @param vlan_id 1827 * VLAN ID to filter. 1828 * @param on 1829 * Toggle filter. 1830 * 1831 * @return 1832 * 0 on success, negative error value otherwise. 1833 */ 1834 static int 1835 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1836 { 1837 struct mrvl_priv *priv = dev->data->dev_private; 1838 1839 if (priv->isolated) 1840 return -ENOTSUP; 1841 1842 if (!priv->ppio) 1843 return 0; 1844 1845 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1846 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1847 } 1848 1849 /** 1850 * DPDK callback to Configure VLAN offload. 1851 * 1852 * @param dev 1853 * Pointer to Ethernet device structure. 1854 * @param mask 1855 * VLAN offload mask. 1856 * 1857 * @return 1858 * 0 on success, negative error value otherwise. 1859 */ 1860 static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1861 { 1862 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1863 int ret; 1864 1865 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1866 MRVL_LOG(ERR, "VLAN stripping is not supported\n"); 1867 return -ENOTSUP; 1868 } 1869 1870 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1871 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 1872 ret = mrvl_populate_vlan_table(dev, 1); 1873 else 1874 ret = mrvl_populate_vlan_table(dev, 0); 1875 1876 if (ret) 1877 return ret; 1878 } 1879 1880 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1881 MRVL_LOG(ERR, "Extend VLAN not supported\n"); 1882 return -ENOTSUP; 1883 } 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * Release buffers to hardware bpool (buffer-pool) 1890 * 1891 * @param rxq 1892 * Receive queue pointer. 1893 * @param num 1894 * Number of buffers to release to bpool. 1895 * 1896 * @return 1897 * 0 on success, negative error value otherwise. 1898 */ 1899 static int 1900 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1901 { 1902 struct buff_release_entry entries[num]; 1903 struct rte_mbuf *mbufs[num]; 1904 int i, ret; 1905 unsigned int core_id; 1906 struct pp2_hif *hif; 1907 struct pp2_bpool *bpool; 1908 1909 core_id = rte_lcore_id(); 1910 if (core_id == LCORE_ID_ANY) 1911 core_id = rte_get_main_lcore(); 1912 1913 hif = mrvl_get_hif(rxq->priv, core_id); 1914 if (!hif) 1915 return -1; 1916 1917 bpool = rxq->priv->bpool; 1918 1919 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1920 if (ret) 1921 return ret; 1922 1923 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1924 cookie_addr_high = 1925 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1926 1927 for (i = 0; i < num; i++) { 1928 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1929 != cookie_addr_high) { 1930 MRVL_LOG(ERR, 1931 "mbuf virtual addr high is out of range " 1932 "0x%x instead of 0x%x\n", 1933 (uint32_t)((uint64_t)mbufs[i] >> 32), 1934 (uint32_t)(cookie_addr_high >> 32)); 1935 goto out; 1936 } 1937 1938 entries[i].buff.addr = 1939 rte_mbuf_data_iova_default(mbufs[i]); 1940 entries[i].buff.cookie = (uintptr_t)mbufs[i]; 1941 entries[i].bpool = bpool; 1942 } 1943 1944 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1945 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1946 1947 if (i != num) 1948 goto out; 1949 1950 return 0; 1951 out: 1952 for (; i < num; i++) 1953 rte_pktmbuf_free(mbufs[i]); 1954 1955 return -1; 1956 } 1957 1958 /** 1959 * DPDK callback to configure the receive queue. 1960 * 1961 * @param dev 1962 * Pointer to Ethernet device structure. 1963 * @param idx 1964 * RX queue index. 1965 * @param desc 1966 * Number of descriptors to configure in queue. 1967 * @param socket 1968 * NUMA socket on which memory must be allocated. 1969 * @param conf 1970 * Thresholds parameters. 1971 * @param mp 1972 * Memory pool for buffer allocations. 1973 * 1974 * @return 1975 * 0 on success, negative error value otherwise. 1976 */ 1977 static int 1978 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1979 unsigned int socket, 1980 const struct rte_eth_rxconf *conf, 1981 struct rte_mempool *mp) 1982 { 1983 struct mrvl_priv *priv = dev->data->dev_private; 1984 struct mrvl_rxq *rxq; 1985 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp); 1986 uint32_t max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN; 1987 int ret, tc, inq; 1988 uint64_t offloads; 1989 1990 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1991 1992 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1993 /* 1994 * Unknown TC mapping, mapping will not have a correct queue. 1995 */ 1996 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1997 idx, priv->ppio_id); 1998 return -EFAULT; 1999 } 2000 2001 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS; 2002 if (frame_size < max_rx_pktlen) { 2003 MRVL_LOG(WARNING, 2004 "Mbuf size must be increased to %u bytes to hold up " 2005 "to %u bytes of data.", 2006 max_rx_pktlen + buf_size - frame_size, 2007 max_rx_pktlen); 2008 dev->data->mtu = frame_size - RTE_ETHER_HDR_LEN; 2009 MRVL_LOG(INFO, "Setting MTU to %u", dev->data->mtu); 2010 } 2011 2012 if (dev->data->rx_queues[idx]) { 2013 rte_free(dev->data->rx_queues[idx]); 2014 dev->data->rx_queues[idx] = NULL; 2015 } 2016 2017 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 2018 if (!rxq) 2019 return -ENOMEM; 2020 2021 rxq->priv = priv; 2022 rxq->mp = mp; 2023 rxq->cksum_enabled = offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM; 2024 rxq->queue_id = idx; 2025 rxq->port_id = dev->data->port_id; 2026 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 2027 2028 tc = priv->rxq_map[rxq->queue_id].tc, 2029 inq = priv->rxq_map[rxq->queue_id].inq; 2030 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 2031 desc; 2032 2033 ret = mrvl_fill_bpool(rxq, desc); 2034 if (ret) { 2035 rte_free(rxq); 2036 return ret; 2037 } 2038 2039 priv->bpool_init_size += desc; 2040 2041 dev->data->rx_queues[idx] = rxq; 2042 2043 return 0; 2044 } 2045 2046 /** 2047 * DPDK callback to release the receive queue. 2048 * 2049 * @param dev 2050 * Pointer to Ethernet device structure. 2051 * @param qid 2052 * Receive queue index. 2053 */ 2054 static void 2055 mrvl_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 2056 { 2057 struct mrvl_rxq *q = dev->data->rx_queues[qid]; 2058 struct pp2_ppio_tc_params *tc_params; 2059 int i, num, tc, inq; 2060 struct pp2_hif *hif; 2061 unsigned int core_id = rte_lcore_id(); 2062 2063 if (core_id == LCORE_ID_ANY) 2064 core_id = rte_get_main_lcore(); 2065 2066 if (!q) 2067 return; 2068 2069 hif = mrvl_get_hif(q->priv, core_id); 2070 2071 if (!hif) 2072 return; 2073 2074 tc = q->priv->rxq_map[q->queue_id].tc; 2075 inq = q->priv->rxq_map[q->queue_id].inq; 2076 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 2077 num = tc_params->inqs_params[inq].size; 2078 for (i = 0; i < num; i++) { 2079 struct pp2_buff_inf inf; 2080 uint64_t addr; 2081 2082 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 2083 addr = cookie_addr_high | inf.cookie; 2084 rte_pktmbuf_free((struct rte_mbuf *)addr); 2085 } 2086 2087 rte_free(q); 2088 } 2089 2090 /** 2091 * DPDK callback to configure the transmit queue. 2092 * 2093 * @param dev 2094 * Pointer to Ethernet device structure. 2095 * @param idx 2096 * Transmit queue index. 2097 * @param desc 2098 * Number of descriptors to configure in the queue. 2099 * @param socket 2100 * NUMA socket on which memory must be allocated. 2101 * @param conf 2102 * Tx queue configuration parameters. 2103 * 2104 * @return 2105 * 0 on success, negative error value otherwise. 2106 */ 2107 static int 2108 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 2109 unsigned int socket, 2110 const struct rte_eth_txconf *conf) 2111 { 2112 struct mrvl_priv *priv = dev->data->dev_private; 2113 struct mrvl_txq *txq; 2114 2115 if (dev->data->tx_queues[idx]) { 2116 rte_free(dev->data->tx_queues[idx]); 2117 dev->data->tx_queues[idx] = NULL; 2118 } 2119 2120 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 2121 if (!txq) 2122 return -ENOMEM; 2123 2124 txq->priv = priv; 2125 txq->queue_id = idx; 2126 txq->port_id = dev->data->port_id; 2127 txq->tx_deferred_start = conf->tx_deferred_start; 2128 dev->data->tx_queues[idx] = txq; 2129 2130 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 2131 2132 return 0; 2133 } 2134 2135 /** 2136 * DPDK callback to release the transmit queue. 2137 * 2138 * @param dev 2139 * Pointer to Ethernet device structure. 2140 * @param qid 2141 * Transmit queue index. 2142 */ 2143 static void 2144 mrvl_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 2145 { 2146 struct mrvl_txq *q = dev->data->tx_queues[qid]; 2147 2148 if (!q) 2149 return; 2150 2151 rte_free(q); 2152 } 2153 2154 /** 2155 * DPDK callback to get flow control configuration. 2156 * 2157 * @param dev 2158 * Pointer to Ethernet device structure. 2159 * @param fc_conf 2160 * Pointer to the flow control configuration. 2161 * 2162 * @return 2163 * 0 on success, negative error value otherwise. 2164 */ 2165 static int 2166 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2167 { 2168 struct mrvl_priv *priv = dev->data->dev_private; 2169 int ret, en; 2170 2171 if (!priv->ppio) { 2172 memcpy(fc_conf, &priv->fc_conf, sizeof(struct rte_eth_fc_conf)); 2173 return 0; 2174 } 2175 2176 fc_conf->autoneg = 1; 2177 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 2178 if (ret) { 2179 MRVL_LOG(ERR, "Failed to read rx pause state"); 2180 return ret; 2181 } 2182 2183 fc_conf->mode = en ? RTE_ETH_FC_RX_PAUSE : RTE_ETH_FC_NONE; 2184 2185 ret = pp2_ppio_get_tx_pause(priv->ppio, &en); 2186 if (ret) { 2187 MRVL_LOG(ERR, "Failed to read tx pause state"); 2188 return ret; 2189 } 2190 2191 if (en) { 2192 if (fc_conf->mode == RTE_ETH_FC_NONE) 2193 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2194 else 2195 fc_conf->mode = RTE_ETH_FC_FULL; 2196 } 2197 2198 return 0; 2199 } 2200 2201 /** 2202 * DPDK callback to set flow control configuration. 2203 * 2204 * @param dev 2205 * Pointer to Ethernet device structure. 2206 * @param fc_conf 2207 * Pointer to the flow control configuration. 2208 * 2209 * @return 2210 * 0 on success, negative error value otherwise. 2211 */ 2212 static int 2213 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2214 { 2215 struct mrvl_priv *priv = dev->data->dev_private; 2216 struct pp2_ppio_tx_pause_params mrvl_pause_params; 2217 int ret; 2218 int rx_en, tx_en; 2219 2220 if (fc_conf->high_water || 2221 fc_conf->low_water || 2222 fc_conf->pause_time || 2223 fc_conf->mac_ctrl_frame_fwd) { 2224 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 2225 2226 return -EINVAL; 2227 } 2228 2229 if (fc_conf->autoneg == 0) { 2230 MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported"); 2231 return -EINVAL; 2232 } 2233 2234 if (!priv->ppio) { 2235 memcpy(&priv->fc_conf, fc_conf, sizeof(struct rte_eth_fc_conf)); 2236 priv->flow_ctrl = 1; 2237 return 0; 2238 } 2239 2240 switch (fc_conf->mode) { 2241 case RTE_ETH_FC_FULL: 2242 rx_en = 1; 2243 tx_en = 1; 2244 break; 2245 case RTE_ETH_FC_TX_PAUSE: 2246 rx_en = 0; 2247 tx_en = 1; 2248 break; 2249 case RTE_ETH_FC_RX_PAUSE: 2250 rx_en = 1; 2251 tx_en = 0; 2252 break; 2253 case RTE_ETH_FC_NONE: 2254 rx_en = 0; 2255 tx_en = 0; 2256 break; 2257 default: 2258 MRVL_LOG(ERR, "Incorrect Flow control flag (%d)", 2259 fc_conf->mode); 2260 return -EINVAL; 2261 } 2262 2263 /* Set RX flow control */ 2264 ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en); 2265 if (ret) { 2266 MRVL_LOG(ERR, "Failed to change RX flowctrl"); 2267 return ret; 2268 } 2269 2270 /* Set TX flow control */ 2271 mrvl_pause_params.en = tx_en; 2272 /* all inqs participate in xon/xoff decision */ 2273 mrvl_pause_params.use_tc_pause_inqs = 0; 2274 ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params); 2275 if (ret) { 2276 MRVL_LOG(ERR, "Failed to change TX flowctrl"); 2277 return ret; 2278 } 2279 2280 return 0; 2281 } 2282 2283 /** 2284 * Update RSS hash configuration 2285 * 2286 * @param dev 2287 * Pointer to Ethernet device structure. 2288 * @param rss_conf 2289 * Pointer to RSS configuration. 2290 * 2291 * @return 2292 * 0 on success, negative error value otherwise. 2293 */ 2294 static int 2295 mrvl_rss_hash_update(struct rte_eth_dev *dev, 2296 struct rte_eth_rss_conf *rss_conf) 2297 { 2298 struct mrvl_priv *priv = dev->data->dev_private; 2299 2300 if (priv->isolated) 2301 return -ENOTSUP; 2302 2303 return mrvl_configure_rss(priv, rss_conf); 2304 } 2305 2306 /** 2307 * DPDK callback to get RSS hash configuration. 2308 * 2309 * @param dev 2310 * Pointer to Ethernet device structure. 2311 * @rss_conf 2312 * Pointer to RSS configuration. 2313 * 2314 * @return 2315 * Always 0. 2316 */ 2317 static int 2318 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 2319 struct rte_eth_rss_conf *rss_conf) 2320 { 2321 struct mrvl_priv *priv = dev->data->dev_private; 2322 enum pp2_ppio_hash_type hash_type = 2323 priv->ppio_params.inqs_params.hash_type; 2324 2325 rss_conf->rss_key = NULL; 2326 2327 if (hash_type == PP2_PPIO_HASH_T_NONE) 2328 rss_conf->rss_hf = 0; 2329 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 2330 rss_conf->rss_hf = RTE_ETH_RSS_IPV4; 2331 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 2332 rss_conf->rss_hf = RTE_ETH_RSS_NONFRAG_IPV4_TCP; 2333 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 2334 rss_conf->rss_hf = RTE_ETH_RSS_NONFRAG_IPV4_UDP; 2335 2336 return 0; 2337 } 2338 2339 /** 2340 * DPDK callback to get rte_flow callbacks. 2341 * 2342 * @param dev 2343 * Pointer to the device structure. 2344 * @param ops 2345 * Pointer to pass the flow ops. 2346 * 2347 * @return 2348 * 0 on success, negative error value otherwise. 2349 */ 2350 static int 2351 mrvl_eth_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 2352 const struct rte_flow_ops **ops) 2353 { 2354 *ops = &mrvl_flow_ops; 2355 return 0; 2356 } 2357 2358 /** 2359 * DPDK callback to get rte_mtr callbacks. 2360 * 2361 * @param dev 2362 * Pointer to the device structure. 2363 * @param ops 2364 * Pointer to pass the mtr ops. 2365 * 2366 * @return 2367 * Always 0. 2368 */ 2369 static int 2370 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2371 { 2372 *(const void **)ops = &mrvl_mtr_ops; 2373 2374 return 0; 2375 } 2376 2377 /** 2378 * DPDK callback to get rte_tm callbacks. 2379 * 2380 * @param dev 2381 * Pointer to the device structure. 2382 * @param ops 2383 * Pointer to pass the tm ops. 2384 * 2385 * @return 2386 * Always 0. 2387 */ 2388 static int 2389 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2390 { 2391 *(const void **)ops = &mrvl_tm_ops; 2392 2393 return 0; 2394 } 2395 2396 static const struct eth_dev_ops mrvl_ops = { 2397 .dev_configure = mrvl_dev_configure, 2398 .dev_start = mrvl_dev_start, 2399 .dev_stop = mrvl_dev_stop, 2400 .dev_set_link_up = mrvl_dev_set_link_up, 2401 .dev_set_link_down = mrvl_dev_set_link_down, 2402 .dev_close = mrvl_dev_close, 2403 .link_update = mrvl_link_update, 2404 .promiscuous_enable = mrvl_promiscuous_enable, 2405 .allmulticast_enable = mrvl_allmulticast_enable, 2406 .promiscuous_disable = mrvl_promiscuous_disable, 2407 .allmulticast_disable = mrvl_allmulticast_disable, 2408 .mac_addr_remove = mrvl_mac_addr_remove, 2409 .mac_addr_add = mrvl_mac_addr_add, 2410 .mac_addr_set = mrvl_mac_addr_set, 2411 .mtu_set = mrvl_mtu_set, 2412 .stats_get = mrvl_stats_get, 2413 .stats_reset = mrvl_stats_reset, 2414 .xstats_get = mrvl_xstats_get, 2415 .xstats_reset = mrvl_xstats_reset, 2416 .xstats_get_names = mrvl_xstats_get_names, 2417 .dev_infos_get = mrvl_dev_infos_get, 2418 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 2419 .rxq_info_get = mrvl_rxq_info_get, 2420 .txq_info_get = mrvl_txq_info_get, 2421 .vlan_filter_set = mrvl_vlan_filter_set, 2422 .vlan_offload_set = mrvl_vlan_offload_set, 2423 .tx_queue_start = mrvl_tx_queue_start, 2424 .tx_queue_stop = mrvl_tx_queue_stop, 2425 .rx_queue_setup = mrvl_rx_queue_setup, 2426 .rx_queue_release = mrvl_rx_queue_release, 2427 .tx_queue_setup = mrvl_tx_queue_setup, 2428 .tx_queue_release = mrvl_tx_queue_release, 2429 .flow_ctrl_get = mrvl_flow_ctrl_get, 2430 .flow_ctrl_set = mrvl_flow_ctrl_set, 2431 .rss_hash_update = mrvl_rss_hash_update, 2432 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 2433 .flow_ops_get = mrvl_eth_flow_ops_get, 2434 .mtr_ops_get = mrvl_mtr_ops_get, 2435 .tm_ops_get = mrvl_tm_ops_get, 2436 }; 2437 2438 /** 2439 * Return packet type information and l3/l4 offsets. 2440 * 2441 * @param desc 2442 * Pointer to the received packet descriptor. 2443 * @param l3_offset 2444 * l3 packet offset. 2445 * @param l4_offset 2446 * l4 packet offset. 2447 * 2448 * @return 2449 * Packet type information. 2450 */ 2451 static inline uint64_t 2452 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 2453 uint8_t *l3_offset, uint8_t *l4_offset) 2454 { 2455 enum pp2_inq_l3_type l3_type; 2456 enum pp2_inq_l4_type l4_type; 2457 enum pp2_inq_vlan_tag vlan_tag; 2458 uint64_t packet_type; 2459 2460 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 2461 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 2462 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 2463 2464 packet_type = RTE_PTYPE_L2_ETHER; 2465 2466 switch (vlan_tag) { 2467 case PP2_INQ_VLAN_TAG_SINGLE: 2468 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 2469 break; 2470 case PP2_INQ_VLAN_TAG_DOUBLE: 2471 case PP2_INQ_VLAN_TAG_TRIPLE: 2472 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 2473 break; 2474 default: 2475 break; 2476 } 2477 2478 switch (l3_type) { 2479 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 2480 packet_type |= RTE_PTYPE_L3_IPV4; 2481 break; 2482 case PP2_INQ_L3_TYPE_IPV4_OK: 2483 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 2484 break; 2485 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 2486 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 2487 break; 2488 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 2489 packet_type |= RTE_PTYPE_L3_IPV6; 2490 break; 2491 case PP2_INQ_L3_TYPE_IPV6_EXT: 2492 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 2493 break; 2494 case PP2_INQ_L3_TYPE_ARP: 2495 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 2496 /* 2497 * In case of ARP l4_offset is set to wrong value. 2498 * Set it to proper one so that later on mbuf->l3_len can be 2499 * calculated subtracting l4_offset and l3_offset. 2500 */ 2501 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 2502 break; 2503 default: 2504 break; 2505 } 2506 2507 switch (l4_type) { 2508 case PP2_INQ_L4_TYPE_TCP: 2509 packet_type |= RTE_PTYPE_L4_TCP; 2510 break; 2511 case PP2_INQ_L4_TYPE_UDP: 2512 packet_type |= RTE_PTYPE_L4_UDP; 2513 break; 2514 default: 2515 break; 2516 } 2517 2518 return packet_type; 2519 } 2520 2521 /** 2522 * Get offload information from the received packet descriptor. 2523 * 2524 * @param desc 2525 * Pointer to the received packet descriptor. 2526 * 2527 * @return 2528 * Mbuf offload flags. 2529 */ 2530 static inline uint64_t 2531 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc, uint64_t packet_type) 2532 { 2533 uint64_t flags = 0; 2534 enum pp2_inq_desc_status status; 2535 2536 if (RTE_ETH_IS_IPV4_HDR(packet_type)) { 2537 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2538 if (unlikely(status != PP2_DESC_ERR_OK)) 2539 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; 2540 else 2541 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; 2542 } 2543 2544 if (((packet_type & RTE_PTYPE_L4_UDP) == RTE_PTYPE_L4_UDP) || 2545 ((packet_type & RTE_PTYPE_L4_TCP) == RTE_PTYPE_L4_TCP)) { 2546 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2547 if (unlikely(status != PP2_DESC_ERR_OK)) 2548 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD; 2549 else 2550 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; 2551 } 2552 2553 return flags; 2554 } 2555 2556 /** 2557 * DPDK callback for receive. 2558 * 2559 * @param rxq 2560 * Generic pointer to the receive queue. 2561 * @param rx_pkts 2562 * Array to store received packets. 2563 * @param nb_pkts 2564 * Maximum number of packets in array. 2565 * 2566 * @return 2567 * Number of packets successfully received. 2568 */ 2569 static uint16_t 2570 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2571 { 2572 struct mrvl_rxq *q = rxq; 2573 struct pp2_ppio_desc descs[nb_pkts]; 2574 struct pp2_bpool *bpool; 2575 int i, ret, rx_done = 0; 2576 int num; 2577 struct pp2_hif *hif; 2578 unsigned int core_id = rte_lcore_id(); 2579 2580 hif = mrvl_get_hif(q->priv, core_id); 2581 2582 if (unlikely(!q->priv->ppio || !hif)) 2583 return 0; 2584 2585 bpool = q->priv->bpool; 2586 2587 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2588 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2589 if (unlikely(ret < 0)) 2590 return 0; 2591 2592 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2593 2594 for (i = 0; i < nb_pkts; i++) { 2595 struct rte_mbuf *mbuf; 2596 uint8_t l3_offset, l4_offset; 2597 enum pp2_inq_desc_status status; 2598 uint64_t addr; 2599 2600 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2601 struct pp2_ppio_desc *pref_desc; 2602 u64 pref_addr; 2603 2604 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2605 pref_addr = cookie_addr_high | 2606 pp2_ppio_inq_desc_get_cookie(pref_desc); 2607 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2608 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2609 } 2610 2611 addr = cookie_addr_high | 2612 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2613 mbuf = (struct rte_mbuf *)addr; 2614 rte_pktmbuf_reset(mbuf); 2615 2616 /* drop packet in case of mac, overrun or resource error */ 2617 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2618 if ((unlikely(status != PP2_DESC_ERR_OK)) && 2619 !(q->priv->forward_bad_frames)) { 2620 struct pp2_buff_inf binf = { 2621 .addr = rte_mbuf_data_iova_default(mbuf), 2622 .cookie = (uint64_t)mbuf, 2623 }; 2624 2625 pp2_bpool_put_buff(hif, bpool, &binf); 2626 mrvl_port_bpool_size 2627 [bpool->pp2_id][bpool->id][core_id]++; 2628 q->drop_mac++; 2629 continue; 2630 } 2631 2632 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2633 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2634 mbuf->data_len = mbuf->pkt_len; 2635 mbuf->port = q->port_id; 2636 mbuf->packet_type = 2637 mrvl_desc_to_packet_type_and_offset(&descs[i], 2638 &l3_offset, 2639 &l4_offset); 2640 mbuf->l2_len = l3_offset; 2641 mbuf->l3_len = l4_offset - l3_offset; 2642 2643 if (likely(q->cksum_enabled)) 2644 mbuf->ol_flags = 2645 mrvl_desc_to_ol_flags(&descs[i], 2646 mbuf->packet_type); 2647 2648 rx_pkts[rx_done++] = mbuf; 2649 q->bytes_recv += mbuf->pkt_len; 2650 } 2651 2652 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2653 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2654 2655 if (unlikely(num <= q->priv->bpool_min_size || 2656 (!rx_done && num < q->priv->bpool_init_size))) { 2657 mrvl_fill_bpool(q, q->priv->fill_bpool_buffs); 2658 } else if (unlikely(num > q->priv->bpool_max_size)) { 2659 int i; 2660 int pkt_to_remove = num - q->priv->bpool_init_size; 2661 struct rte_mbuf *mbuf; 2662 struct pp2_buff_inf buff; 2663 2664 for (i = 0; i < pkt_to_remove; i++) { 2665 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2666 if (ret) 2667 break; 2668 mbuf = (struct rte_mbuf *) 2669 (cookie_addr_high | buff.cookie); 2670 rte_pktmbuf_free(mbuf); 2671 } 2672 mrvl_port_bpool_size 2673 [bpool->pp2_id][bpool->id][core_id] -= i; 2674 } 2675 rte_spinlock_unlock(&q->priv->lock); 2676 } 2677 2678 return rx_done; 2679 } 2680 2681 /** 2682 * Prepare offload information. 2683 * 2684 * @param ol_flags 2685 * Offload flags. 2686 * @param l3_type 2687 * Pointer to the pp2_ouq_l3_type structure. 2688 * @param l4_type 2689 * Pointer to the pp2_outq_l4_type structure. 2690 * @param gen_l3_cksum 2691 * Will be set to 1 in case l3 checksum is computed. 2692 * @param l4_cksum 2693 * Will be set to 1 in case l4 checksum is computed. 2694 */ 2695 static inline void 2696 mrvl_prepare_proto_info(uint64_t ol_flags, 2697 enum pp2_outq_l3_type *l3_type, 2698 enum pp2_outq_l4_type *l4_type, 2699 int *gen_l3_cksum, 2700 int *gen_l4_cksum) 2701 { 2702 /* 2703 * Based on ol_flags prepare information 2704 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2705 * for offloading. 2706 * in most of the checksum cases ipv4 must be set, so this is the 2707 * default value 2708 */ 2709 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2710 *gen_l3_cksum = ol_flags & RTE_MBUF_F_TX_IP_CKSUM ? 1 : 0; 2711 2712 if (ol_flags & RTE_MBUF_F_TX_IPV6) { 2713 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2714 /* no checksum for ipv6 header */ 2715 *gen_l3_cksum = 0; 2716 } 2717 2718 if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) { 2719 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2720 *gen_l4_cksum = 1; 2721 } else if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_UDP_CKSUM) { 2722 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2723 *gen_l4_cksum = 1; 2724 } else { 2725 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2726 /* no checksum for other type */ 2727 *gen_l4_cksum = 0; 2728 } 2729 } 2730 2731 /** 2732 * Release already sent buffers to bpool (buffer-pool). 2733 * 2734 * @param ppio 2735 * Pointer to the port structure. 2736 * @param hif 2737 * Pointer to the MUSDK hardware interface. 2738 * @param sq 2739 * Pointer to the shadow queue. 2740 * @param qid 2741 * Queue id number. 2742 * @param force 2743 * Force releasing packets. 2744 */ 2745 static inline void 2746 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2747 unsigned int core_id, struct mrvl_shadow_txq *sq, 2748 int qid, int force) 2749 { 2750 struct buff_release_entry *entry; 2751 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2752 int i; 2753 2754 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2755 2756 sq->num_to_release += nb_done; 2757 2758 if (likely(!force && 2759 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2760 return; 2761 2762 nb_done = sq->num_to_release; 2763 sq->num_to_release = 0; 2764 2765 for (i = 0; i < nb_done; i++) { 2766 entry = &sq->ent[sq->tail + num]; 2767 if (unlikely(!entry->buff.addr)) { 2768 MRVL_LOG(ERR, 2769 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2770 sq->tail, (u64)entry->buff.cookie, 2771 (u64)entry->buff.addr); 2772 skip_bufs = 1; 2773 goto skip; 2774 } 2775 2776 if (unlikely(!entry->bpool)) { 2777 struct rte_mbuf *mbuf; 2778 2779 mbuf = (struct rte_mbuf *)entry->buff.cookie; 2780 rte_pktmbuf_free(mbuf); 2781 skip_bufs = 1; 2782 goto skip; 2783 } 2784 2785 mrvl_port_bpool_size 2786 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2787 num++; 2788 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2789 goto skip; 2790 continue; 2791 skip: 2792 if (likely(num)) 2793 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2794 num += skip_bufs; 2795 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2796 sq->size -= num; 2797 num = 0; 2798 skip_bufs = 0; 2799 } 2800 2801 if (likely(num)) { 2802 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2803 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2804 sq->size -= num; 2805 } 2806 } 2807 2808 /** 2809 * DPDK callback for transmit. 2810 * 2811 * @param txq 2812 * Generic pointer transmit queue. 2813 * @param tx_pkts 2814 * Packets to transmit. 2815 * @param nb_pkts 2816 * Number of packets in array. 2817 * 2818 * @return 2819 * Number of packets successfully transmitted. 2820 */ 2821 static uint16_t 2822 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2823 { 2824 struct mrvl_txq *q = txq; 2825 struct mrvl_shadow_txq *sq; 2826 struct pp2_hif *hif; 2827 struct pp2_ppio_desc descs[nb_pkts]; 2828 unsigned int core_id = rte_lcore_id(); 2829 int i, bytes_sent = 0; 2830 uint16_t num, sq_free_size; 2831 uint64_t addr; 2832 2833 hif = mrvl_get_hif(q->priv, core_id); 2834 sq = &q->shadow_txqs[core_id]; 2835 2836 if (unlikely(!q->priv->ppio || !hif)) 2837 return 0; 2838 2839 if (sq->size) 2840 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2841 sq, q->queue_id, 0); 2842 2843 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2844 if (unlikely(nb_pkts > sq_free_size)) 2845 nb_pkts = sq_free_size; 2846 2847 for (i = 0; i < nb_pkts; i++) { 2848 struct rte_mbuf *mbuf = tx_pkts[i]; 2849 int gen_l3_cksum, gen_l4_cksum; 2850 enum pp2_outq_l3_type l3_type; 2851 enum pp2_outq_l4_type l4_type; 2852 2853 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2854 struct rte_mbuf *pref_pkt_hdr; 2855 2856 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2857 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2858 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2859 } 2860 2861 mrvl_fill_shadowq(sq, mbuf); 2862 mrvl_fill_desc(&descs[i], mbuf); 2863 2864 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2865 /* 2866 * in case unsupported ol_flags were passed 2867 * do not update descriptor offload information 2868 */ 2869 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) 2870 continue; 2871 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, 2872 &gen_l3_cksum, &gen_l4_cksum); 2873 2874 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2875 mbuf->l2_len, 2876 mbuf->l2_len + mbuf->l3_len, 2877 gen_l3_cksum, gen_l4_cksum); 2878 } 2879 2880 num = nb_pkts; 2881 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2882 /* number of packets that were not sent */ 2883 if (unlikely(num > nb_pkts)) { 2884 for (i = nb_pkts; i < num; i++) { 2885 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2886 MRVL_PP2_TX_SHADOWQ_MASK; 2887 addr = sq->ent[sq->head].buff.cookie; 2888 bytes_sent -= 2889 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2890 } 2891 sq->size -= num - nb_pkts; 2892 } 2893 2894 q->bytes_sent += bytes_sent; 2895 2896 return nb_pkts; 2897 } 2898 2899 /** DPDK callback for S/G transmit. 2900 * 2901 * @param txq 2902 * Generic pointer transmit queue. 2903 * @param tx_pkts 2904 * Packets to transmit. 2905 * @param nb_pkts 2906 * Number of packets in array. 2907 * 2908 * @return 2909 * Number of packets successfully transmitted. 2910 */ 2911 static uint16_t 2912 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 2913 uint16_t nb_pkts) 2914 { 2915 struct mrvl_txq *q = txq; 2916 struct mrvl_shadow_txq *sq; 2917 struct pp2_hif *hif; 2918 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS]; 2919 struct pp2_ppio_sg_pkts pkts; 2920 uint8_t frags[nb_pkts]; 2921 unsigned int core_id = rte_lcore_id(); 2922 int i, j, bytes_sent = 0; 2923 int tail, tail_first; 2924 uint16_t num, sq_free_size; 2925 uint16_t nb_segs, total_descs = 0; 2926 uint64_t addr; 2927 2928 hif = mrvl_get_hif(q->priv, core_id); 2929 sq = &q->shadow_txqs[core_id]; 2930 pkts.frags = frags; 2931 pkts.num = 0; 2932 2933 if (unlikely(!q->priv->ppio || !hif)) 2934 return 0; 2935 2936 if (sq->size) 2937 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2938 sq, q->queue_id, 0); 2939 2940 /* Save shadow queue free size */ 2941 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2942 2943 tail = 0; 2944 for (i = 0; i < nb_pkts; i++) { 2945 struct rte_mbuf *mbuf = tx_pkts[i]; 2946 struct rte_mbuf *seg = NULL; 2947 int gen_l3_cksum, gen_l4_cksum; 2948 enum pp2_outq_l3_type l3_type; 2949 enum pp2_outq_l4_type l4_type; 2950 2951 nb_segs = mbuf->nb_segs; 2952 tail_first = tail; 2953 total_descs += nb_segs; 2954 2955 /* 2956 * Check if total_descs does not exceed 2957 * shadow queue free size 2958 */ 2959 if (unlikely(total_descs > sq_free_size)) { 2960 total_descs -= nb_segs; 2961 break; 2962 } 2963 2964 /* Check if nb_segs does not exceed the max nb of desc per 2965 * fragmented packet 2966 */ 2967 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) { 2968 total_descs -= nb_segs; 2969 RTE_LOG(ERR, PMD, 2970 "Too many segments. Packet won't be sent.\n"); 2971 break; 2972 } 2973 2974 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2975 struct rte_mbuf *pref_pkt_hdr; 2976 2977 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2978 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2979 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2980 } 2981 2982 pkts.frags[pkts.num] = nb_segs; 2983 pkts.num++; 2984 2985 seg = mbuf; 2986 for (j = 0; j < nb_segs - 1; j++) { 2987 /* For the subsequent segments, set shadow queue 2988 * buffer to NULL 2989 */ 2990 mrvl_fill_shadowq(sq, NULL); 2991 mrvl_fill_desc(&descs[tail], seg); 2992 2993 tail++; 2994 seg = seg->next; 2995 } 2996 /* Put first mbuf info in last shadow queue entry */ 2997 mrvl_fill_shadowq(sq, mbuf); 2998 /* Update descriptor with last segment */ 2999 mrvl_fill_desc(&descs[tail++], seg); 3000 3001 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 3002 /* In case unsupported ol_flags were passed 3003 * do not update descriptor offload information 3004 */ 3005 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) 3006 continue; 3007 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, 3008 &gen_l3_cksum, &gen_l4_cksum); 3009 3010 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, 3011 l4_type, mbuf->l2_len, 3012 mbuf->l2_len + mbuf->l3_len, 3013 gen_l3_cksum, gen_l4_cksum); 3014 } 3015 3016 num = total_descs; 3017 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs, 3018 &total_descs, &pkts); 3019 /* number of packets that were not sent */ 3020 if (unlikely(num > total_descs)) { 3021 for (i = total_descs; i < num; i++) { 3022 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 3023 MRVL_PP2_TX_SHADOWQ_MASK; 3024 3025 addr = sq->ent[sq->head].buff.cookie; 3026 if (addr) 3027 bytes_sent -= 3028 rte_pktmbuf_pkt_len((struct rte_mbuf *) 3029 (cookie_addr_high | addr)); 3030 } 3031 sq->size -= num - total_descs; 3032 nb_pkts = pkts.num; 3033 } 3034 3035 q->bytes_sent += bytes_sent; 3036 3037 return nb_pkts; 3038 } 3039 3040 /** 3041 * Create private device structure. 3042 * 3043 * @param dev_name 3044 * Pointer to the port name passed in the initialization parameters. 3045 * 3046 * @return 3047 * Pointer to the newly allocated private device structure. 3048 */ 3049 static struct mrvl_priv * 3050 mrvl_priv_create(const char *dev_name) 3051 { 3052 struct pp2_bpool_params bpool_params; 3053 char match[MRVL_MATCH_LEN]; 3054 struct mrvl_priv *priv; 3055 uint16_t max_frame_size; 3056 int ret, bpool_bit; 3057 3058 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 3059 if (!priv) 3060 return NULL; 3061 3062 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 3063 &priv->pp_id, &priv->ppio_id); 3064 if (ret) 3065 goto out_free_priv; 3066 3067 ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id, 3068 &max_frame_size); 3069 if (ret) 3070 goto out_free_priv; 3071 3072 priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN - 3073 MRVL_PP2_ETH_HDRS_LEN; 3074 3075 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 3076 PP2_BPOOL_NUM_POOLS); 3077 if (bpool_bit < 0) 3078 goto out_free_priv; 3079 priv->bpool_bit = bpool_bit; 3080 3081 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 3082 priv->bpool_bit); 3083 memset(&bpool_params, 0, sizeof(bpool_params)); 3084 bpool_params.match = match; 3085 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 3086 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 3087 if (ret) 3088 goto out_clear_bpool_bit; 3089 3090 priv->ppio_params.type = PP2_PPIO_T_NIC; 3091 rte_spinlock_init(&priv->lock); 3092 3093 return priv; 3094 out_clear_bpool_bit: 3095 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 3096 out_free_priv: 3097 rte_free(priv); 3098 return NULL; 3099 } 3100 3101 /** 3102 * Create device representing Ethernet port. 3103 * 3104 * @param name 3105 * Pointer to the port's name. 3106 * 3107 * @return 3108 * 0 on success, negative error value otherwise. 3109 */ 3110 static int 3111 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 3112 { 3113 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 3114 struct rte_eth_dev *eth_dev; 3115 struct mrvl_priv *priv; 3116 struct ifreq req; 3117 3118 eth_dev = rte_eth_dev_allocate(name); 3119 if (!eth_dev) 3120 return -ENOMEM; 3121 3122 priv = mrvl_priv_create(name); 3123 if (!priv) { 3124 ret = -ENOMEM; 3125 goto out_free; 3126 } 3127 eth_dev->data->dev_private = priv; 3128 3129 eth_dev->data->mac_addrs = 3130 rte_zmalloc("mac_addrs", 3131 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 3132 if (!eth_dev->data->mac_addrs) { 3133 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 3134 ret = -ENOMEM; 3135 goto out_free; 3136 } 3137 3138 memset(&req, 0, sizeof(req)); 3139 strcpy(req.ifr_name, name); 3140 ret = ioctl(fd, SIOCGIFHWADDR, &req); 3141 if (ret) 3142 goto out_free; 3143 3144 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 3145 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN); 3146 3147 eth_dev->device = &vdev->device; 3148 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 3149 mrvl_set_tx_function(eth_dev); 3150 eth_dev->dev_ops = &mrvl_ops; 3151 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 3152 3153 eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 3154 3155 rte_eth_dev_probing_finish(eth_dev); 3156 return 0; 3157 out_free: 3158 rte_eth_dev_release_port(eth_dev); 3159 3160 return ret; 3161 } 3162 3163 /** 3164 * Callback used by rte_kvargs_process() during argument parsing. 3165 * 3166 * @param key 3167 * Pointer to the parsed key (unused). 3168 * @param value 3169 * Pointer to the parsed value. 3170 * @param extra_args 3171 * Pointer to the extra arguments which contains address of the 3172 * table of pointers to parsed interface names. 3173 * 3174 * @return 3175 * Always 0. 3176 */ 3177 static int 3178 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 3179 void *extra_args) 3180 { 3181 struct mrvl_ifnames *ifnames = extra_args; 3182 3183 ifnames->names[ifnames->idx++] = value; 3184 3185 return 0; 3186 } 3187 3188 /** 3189 * DPDK callback to register the virtual device. 3190 * 3191 * @param vdev 3192 * Pointer to the virtual device. 3193 * 3194 * @return 3195 * 0 on success, negative error value otherwise. 3196 */ 3197 static int 3198 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 3199 { 3200 struct rte_kvargs *kvlist; 3201 struct mrvl_ifnames ifnames; 3202 int ret = -EINVAL; 3203 uint32_t i, ifnum, cfgnum; 3204 const char *params; 3205 3206 params = rte_vdev_device_args(vdev); 3207 if (!params) 3208 return -EINVAL; 3209 3210 kvlist = rte_kvargs_parse(params, valid_args); 3211 if (!kvlist) 3212 return -EINVAL; 3213 3214 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 3215 if (ifnum > RTE_DIM(ifnames.names)) 3216 goto out_free_kvlist; 3217 3218 ifnames.idx = 0; 3219 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 3220 mrvl_get_ifnames, &ifnames); 3221 3222 3223 /* 3224 * The below system initialization should be done only once, 3225 * on the first provided configuration file 3226 */ 3227 if (!mrvl_cfg) { 3228 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 3229 MRVL_LOG(INFO, "Parsing config file!"); 3230 if (cfgnum > 1) { 3231 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 3232 goto out_free_kvlist; 3233 } else if (cfgnum == 1) { 3234 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 3235 mrvl_get_cfg, &mrvl_cfg); 3236 } 3237 } 3238 3239 if (mrvl_dev_num) 3240 goto init_devices; 3241 3242 MRVL_LOG(INFO, "Perform MUSDK initializations"); 3243 3244 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 3245 if (ret) 3246 goto out_free_kvlist; 3247 3248 ret = mrvl_init_pp2(); 3249 if (ret) { 3250 MRVL_LOG(ERR, "Failed to init PP!"); 3251 rte_mvep_deinit(MVEP_MOD_T_PP2); 3252 goto out_free_kvlist; 3253 } 3254 3255 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 3256 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 3257 3258 mrvl_lcore_first = RTE_MAX_LCORE; 3259 mrvl_lcore_last = 0; 3260 3261 init_devices: 3262 for (i = 0; i < ifnum; i++) { 3263 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 3264 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 3265 if (ret) 3266 goto out_cleanup; 3267 mrvl_dev_num++; 3268 } 3269 3270 rte_kvargs_free(kvlist); 3271 3272 return 0; 3273 out_cleanup: 3274 rte_pmd_mrvl_remove(vdev); 3275 3276 out_free_kvlist: 3277 rte_kvargs_free(kvlist); 3278 3279 return ret; 3280 } 3281 3282 /** 3283 * DPDK callback to remove virtual device. 3284 * 3285 * @param vdev 3286 * Pointer to the removed virtual device. 3287 * 3288 * @return 3289 * 0 on success, negative error value otherwise. 3290 */ 3291 static int 3292 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 3293 { 3294 uint16_t port_id; 3295 int ret = 0; 3296 3297 RTE_ETH_FOREACH_DEV(port_id) { 3298 if (rte_eth_devices[port_id].device != &vdev->device) 3299 continue; 3300 ret |= rte_eth_dev_close(port_id); 3301 } 3302 3303 return ret == 0 ? 0 : -EIO; 3304 } 3305 3306 static struct rte_vdev_driver pmd_mrvl_drv = { 3307 .probe = rte_pmd_mrvl_probe, 3308 .remove = rte_pmd_mrvl_remove, 3309 }; 3310 3311 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 3312 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 3313 RTE_LOG_REGISTER_DEFAULT(mrvl_logtype, NOTICE); 3314