1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_string_fns.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_kvargs.h> 10 #include <rte_log.h> 11 #include <rte_malloc.h> 12 #include <rte_bus_vdev.h> 13 14 #include <fcntl.h> 15 #include <linux/ethtool.h> 16 #include <linux/sockios.h> 17 #include <net/if.h> 18 #include <net/if_arp.h> 19 #include <sys/ioctl.h> 20 #include <sys/socket.h> 21 #include <sys/stat.h> 22 #include <sys/types.h> 23 24 #include <rte_mvep_common.h> 25 #include "mrvl_ethdev.h" 26 #include "mrvl_qos.h" 27 #include "mrvl_flow.h" 28 #include "mrvl_mtr.h" 29 #include "mrvl_tm.h" 30 31 /* bitmask with reserved hifs */ 32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 33 /* bitmask with reserved bpools */ 34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 35 /* bitmask with reserved kernel RSS tables */ 36 #define MRVL_MUSDK_RSS_RESERVED 0x01 37 /* maximum number of available hifs */ 38 #define MRVL_MUSDK_HIFS_MAX 9 39 40 /* prefetch shift */ 41 #define MRVL_MUSDK_PREFETCH_SHIFT 2 42 43 /* TCAM has 25 entries reserved for uc/mc filter entries */ 44 #define MRVL_MAC_ADDRS_MAX 25 45 #define MRVL_MATCH_LEN 16 46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 47 /* Maximum allowable packet size */ 48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 49 50 #define MRVL_IFACE_NAME_ARG "iface" 51 #define MRVL_CFG_ARG "cfg" 52 53 #define MRVL_BURST_SIZE 64 54 55 #define MRVL_ARP_LENGTH 28 56 57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000 59 60 /** Port Rx offload capabilities */ 61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ 62 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 63 DEV_RX_OFFLOAD_CHECKSUM) 64 65 /** Port Tx offloads capabilities */ 66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 67 DEV_TX_OFFLOAD_UDP_CKSUM | \ 68 DEV_TX_OFFLOAD_TCP_CKSUM | \ 69 DEV_TX_OFFLOAD_MULTI_SEGS) 70 71 static const char * const valid_args[] = { 72 MRVL_IFACE_NAME_ARG, 73 MRVL_CFG_ARG, 74 NULL 75 }; 76 77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 78 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 79 static int used_bpools[PP2_NUM_PKT_PROC] = { 80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 81 }; 82 83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 86 87 struct mrvl_ifnames { 88 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 89 int idx; 90 }; 91 92 /* 93 * To use buffer harvesting based on loopback port shadow queue structure 94 * was introduced for buffers information bookkeeping. 95 * 96 * Before sending the packet, related buffer information (pp2_buff_inf) is 97 * stored in shadow queue. After packet is transmitted no longer used 98 * packet buffer is released back to it's original hardware pool, 99 * on condition it originated from interface. 100 * In case it was generated by application itself i.e: mbuf->port field is 101 * 0xff then its released to software mempool. 102 */ 103 struct mrvl_shadow_txq { 104 int head; /* write index - used when sending buffers */ 105 int tail; /* read index - used when releasing buffers */ 106 u16 size; /* queue occupied size */ 107 u16 num_to_release; /* number of descriptors sent, that can be 108 * released 109 */ 110 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 111 }; 112 113 struct mrvl_rxq { 114 struct mrvl_priv *priv; 115 struct rte_mempool *mp; 116 int queue_id; 117 int port_id; 118 int cksum_enabled; 119 uint64_t bytes_recv; 120 uint64_t drop_mac; 121 }; 122 123 struct mrvl_txq { 124 struct mrvl_priv *priv; 125 int queue_id; 126 int port_id; 127 uint64_t bytes_sent; 128 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 129 int tx_deferred_start; 130 }; 131 132 static int mrvl_lcore_first; 133 static int mrvl_lcore_last; 134 static int mrvl_dev_num; 135 136 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 137 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 138 struct pp2_hif *hif, unsigned int core_id, 139 struct mrvl_shadow_txq *sq, int qid, int force); 140 141 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 142 uint16_t nb_pkts); 143 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 144 uint16_t nb_pkts); 145 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); 146 static void mrvl_deinit_pp2(void); 147 static void mrvl_deinit_hifs(void); 148 149 150 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 151 #name, offsetof(struct pp2_ppio_statistics, name), \ 152 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 153 } 154 155 /* Table with xstats data */ 156 static struct { 157 const char *name; 158 unsigned int offset; 159 unsigned int size; 160 } mrvl_xstats_tbl[] = { 161 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 162 MRVL_XSTATS_TBL_ENTRY(rx_packets), 163 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 164 MRVL_XSTATS_TBL_ENTRY(rx_errors), 165 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 166 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 167 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 168 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 169 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 170 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 171 MRVL_XSTATS_TBL_ENTRY(tx_packets), 172 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 173 MRVL_XSTATS_TBL_ENTRY(tx_errors) 174 }; 175 176 static inline void 177 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) 178 { 179 sq->ent[sq->head].buff.cookie = (uint64_t)buf; 180 sq->ent[sq->head].buff.addr = buf ? 181 rte_mbuf_data_iova_default(buf) : 0; 182 183 sq->ent[sq->head].bpool = 184 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS || 185 buf->refcnt > 1)) ? NULL : 186 mrvl_port_to_bpool_lookup[buf->port]; 187 188 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 189 sq->size++; 190 } 191 192 static inline void 193 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf) 194 { 195 pp2_ppio_outq_desc_reset(desc); 196 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf)); 197 pp2_ppio_outq_desc_set_pkt_offset(desc, 0); 198 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf)); 199 } 200 201 static inline int 202 mrvl_get_bpool_size(int pp2_id, int pool_id) 203 { 204 int i; 205 int size = 0; 206 207 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 208 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 209 210 return size; 211 } 212 213 static inline int 214 mrvl_reserve_bit(int *bitmap, int max) 215 { 216 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 217 218 if (n >= max) 219 return -1; 220 221 *bitmap |= 1 << n; 222 223 return n; 224 } 225 226 static int 227 mrvl_init_hif(int core_id) 228 { 229 struct pp2_hif_params params; 230 char match[MRVL_MATCH_LEN]; 231 int ret; 232 233 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 234 if (ret < 0) { 235 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 236 return ret; 237 } 238 239 snprintf(match, sizeof(match), "hif-%d", ret); 240 memset(¶ms, 0, sizeof(params)); 241 params.match = match; 242 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 243 ret = pp2_hif_init(¶ms, &hifs[core_id]); 244 if (ret) { 245 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 246 return ret; 247 } 248 249 return 0; 250 } 251 252 static inline struct pp2_hif* 253 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 254 { 255 int ret; 256 257 if (likely(hifs[core_id] != NULL)) 258 return hifs[core_id]; 259 260 rte_spinlock_lock(&priv->lock); 261 262 ret = mrvl_init_hif(core_id); 263 if (ret < 0) { 264 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 265 goto out; 266 } 267 268 if (core_id < mrvl_lcore_first) 269 mrvl_lcore_first = core_id; 270 271 if (core_id > mrvl_lcore_last) 272 mrvl_lcore_last = core_id; 273 out: 274 rte_spinlock_unlock(&priv->lock); 275 276 return hifs[core_id]; 277 } 278 279 /** 280 * Set tx burst function according to offload flag 281 * 282 * @param dev 283 * Pointer to Ethernet device structure. 284 */ 285 static void 286 mrvl_set_tx_function(struct rte_eth_dev *dev) 287 { 288 struct mrvl_priv *priv = dev->data->dev_private; 289 290 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 291 if (priv->multiseg) { 292 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n"); 293 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst; 294 } else { 295 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n"); 296 dev->tx_pkt_burst = mrvl_tx_pkt_burst; 297 } 298 } 299 300 /** 301 * Configure rss based on dpdk rss configuration. 302 * 303 * @param priv 304 * Pointer to private structure. 305 * @param rss_conf 306 * Pointer to RSS configuration. 307 * 308 * @return 309 * 0 on success, negative error value otherwise. 310 */ 311 static int 312 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 313 { 314 if (rss_conf->rss_key) 315 MRVL_LOG(WARNING, "Changing hash key is not supported"); 316 317 if (rss_conf->rss_hf == 0) { 318 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 319 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { 320 priv->ppio_params.inqs_params.hash_type = 321 PP2_PPIO_HASH_T_2_TUPLE; 322 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 323 priv->ppio_params.inqs_params.hash_type = 324 PP2_PPIO_HASH_T_5_TUPLE; 325 priv->rss_hf_tcp = 1; 326 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 327 priv->ppio_params.inqs_params.hash_type = 328 PP2_PPIO_HASH_T_5_TUPLE; 329 priv->rss_hf_tcp = 0; 330 } else { 331 return -EINVAL; 332 } 333 334 return 0; 335 } 336 337 /** 338 * Ethernet device configuration. 339 * 340 * Prepare the driver for a given number of TX and RX queues and 341 * configure RSS. 342 * 343 * @param dev 344 * Pointer to Ethernet device structure. 345 * 346 * @return 347 * 0 on success, negative error value otherwise. 348 */ 349 static int 350 mrvl_dev_configure(struct rte_eth_dev *dev) 351 { 352 struct mrvl_priv *priv = dev->data->dev_private; 353 int ret; 354 355 if (priv->ppio) { 356 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 357 return -EINVAL; 358 } 359 360 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && 361 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 362 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 363 dev->data->dev_conf.rxmode.mq_mode); 364 return -EINVAL; 365 } 366 367 if (dev->data->dev_conf.rxmode.split_hdr_size) { 368 MRVL_LOG(INFO, "Split headers not supported"); 369 return -EINVAL; 370 } 371 372 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 373 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 374 MRVL_PP2_ETH_HDRS_LEN; 375 376 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 377 priv->multiseg = 1; 378 379 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 380 dev->data->nb_rx_queues); 381 if (ret < 0) 382 return ret; 383 384 ret = mrvl_configure_txqs(priv, dev->data->port_id, 385 dev->data->nb_tx_queues); 386 if (ret < 0) 387 return ret; 388 389 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 390 priv->ppio_params.maintain_stats = 1; 391 priv->nb_rx_queues = dev->data->nb_rx_queues; 392 393 ret = mrvl_tm_init(dev); 394 if (ret < 0) 395 return ret; 396 397 if (dev->data->nb_rx_queues == 1 && 398 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 399 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 400 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 401 402 return 0; 403 } 404 405 return mrvl_configure_rss(priv, 406 &dev->data->dev_conf.rx_adv_conf.rss_conf); 407 } 408 409 /** 410 * DPDK callback to change the MTU. 411 * 412 * Setting the MTU affects hardware MRU (packets larger than the MRU 413 * will be dropped). 414 * 415 * @param dev 416 * Pointer to Ethernet device structure. 417 * @param mtu 418 * New MTU. 419 * 420 * @return 421 * 0 on success, negative error value otherwise. 422 */ 423 static int 424 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 425 { 426 struct mrvl_priv *priv = dev->data->dev_private; 427 uint16_t mru; 428 uint16_t mbuf_data_size = 0; /* SW buffer size */ 429 int ret; 430 431 mru = MRVL_PP2_MTU_TO_MRU(mtu); 432 /* 433 * min_rx_buf_size is equal to mbuf data size 434 * if pmd didn't set it differently 435 */ 436 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 437 /* Prevent PMD from: 438 * - setting mru greater than the mbuf size resulting in 439 * hw and sw buffer size mismatch 440 * - setting mtu that requires the support of scattered packets 441 * when this feature has not been enabled/supported so far 442 * (TODO check scattered_rx flag here once scattered RX is supported). 443 */ 444 if (mru + MRVL_PKT_OFFS > mbuf_data_size) { 445 mru = mbuf_data_size - MRVL_PKT_OFFS; 446 mtu = MRVL_PP2_MRU_TO_MTU(mru); 447 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted " 448 "by current mbuf size: %u. Set MTU to %u, MRU to %u", 449 mbuf_data_size, mtu, mru); 450 } 451 452 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) { 453 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru); 454 return -EINVAL; 455 } 456 457 dev->data->mtu = mtu; 458 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE; 459 460 if (!priv->ppio) 461 return 0; 462 463 ret = pp2_ppio_set_mru(priv->ppio, mru); 464 if (ret) { 465 MRVL_LOG(ERR, "Failed to change MRU"); 466 return ret; 467 } 468 469 ret = pp2_ppio_set_mtu(priv->ppio, mtu); 470 if (ret) { 471 MRVL_LOG(ERR, "Failed to change MTU"); 472 return ret; 473 } 474 475 return 0; 476 } 477 478 /** 479 * DPDK callback to bring the link up. 480 * 481 * @param dev 482 * Pointer to Ethernet device structure. 483 * 484 * @return 485 * 0 on success, negative error value otherwise. 486 */ 487 static int 488 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 489 { 490 struct mrvl_priv *priv = dev->data->dev_private; 491 int ret; 492 493 if (!priv->ppio) 494 return -EPERM; 495 496 ret = pp2_ppio_enable(priv->ppio); 497 if (ret) 498 return ret; 499 500 /* 501 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 502 * as pp2_ppio_enable() changes port->t_mode from default 0 to 503 * PP2_TRAFFIC_INGRESS_EGRESS. 504 * 505 * Set mtu to default DPDK value here. 506 */ 507 ret = mrvl_mtu_set(dev, dev->data->mtu); 508 if (ret) 509 pp2_ppio_disable(priv->ppio); 510 511 return ret; 512 } 513 514 /** 515 * DPDK callback to bring the link down. 516 * 517 * @param dev 518 * Pointer to Ethernet device structure. 519 * 520 * @return 521 * 0 on success, negative error value otherwise. 522 */ 523 static int 524 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 525 { 526 struct mrvl_priv *priv = dev->data->dev_private; 527 528 if (!priv->ppio) 529 return -EPERM; 530 531 return pp2_ppio_disable(priv->ppio); 532 } 533 534 /** 535 * DPDK callback to start tx queue. 536 * 537 * @param dev 538 * Pointer to Ethernet device structure. 539 * @param queue_id 540 * Transmit queue index. 541 * 542 * @return 543 * 0 on success, negative error value otherwise. 544 */ 545 static int 546 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 547 { 548 struct mrvl_priv *priv = dev->data->dev_private; 549 int ret; 550 551 if (!priv) 552 return -EPERM; 553 554 /* passing 1 enables given tx queue */ 555 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 556 if (ret) { 557 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 558 return ret; 559 } 560 561 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 562 563 return 0; 564 } 565 566 /** 567 * DPDK callback to stop tx queue. 568 * 569 * @param dev 570 * Pointer to Ethernet device structure. 571 * @param queue_id 572 * Transmit queue index. 573 * 574 * @return 575 * 0 on success, negative error value otherwise. 576 */ 577 static int 578 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 579 { 580 struct mrvl_priv *priv = dev->data->dev_private; 581 int ret; 582 583 if (!priv->ppio) 584 return -EPERM; 585 586 /* passing 0 disables given tx queue */ 587 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 588 if (ret) { 589 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 590 return ret; 591 } 592 593 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 594 595 return 0; 596 } 597 598 /** 599 * DPDK callback to start the device. 600 * 601 * @param dev 602 * Pointer to Ethernet device structure. 603 * 604 * @return 605 * 0 on success, negative errno value on failure. 606 */ 607 static int 608 mrvl_dev_start(struct rte_eth_dev *dev) 609 { 610 struct mrvl_priv *priv = dev->data->dev_private; 611 char match[MRVL_MATCH_LEN]; 612 int ret = 0, i, def_init_size; 613 614 if (priv->ppio) 615 return mrvl_dev_set_link_up(dev); 616 617 snprintf(match, sizeof(match), "ppio-%d:%d", 618 priv->pp_id, priv->ppio_id); 619 priv->ppio_params.match = match; 620 621 /* 622 * Calculate the minimum bpool size for refill feature as follows: 623 * 2 default burst sizes multiply by number of rx queues. 624 * If the bpool size will be below this value, new buffers will 625 * be added to the pool. 626 */ 627 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 628 629 /* In case initial bpool size configured in queues setup is 630 * smaller than minimum size add more buffers 631 */ 632 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 633 if (priv->bpool_init_size < def_init_size) { 634 int buffs_to_add = def_init_size - priv->bpool_init_size; 635 636 priv->bpool_init_size += buffs_to_add; 637 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 638 if (ret) 639 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 640 } 641 642 /* 643 * Calculate the maximum bpool size for refill feature as follows: 644 * maximum number of descriptors in rx queue multiply by number 645 * of rx queues plus minimum bpool size. 646 * In case the bpool size will exceed this value, superfluous buffers 647 * will be removed 648 */ 649 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 650 priv->bpool_min_size; 651 652 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 653 if (ret) { 654 MRVL_LOG(ERR, "Failed to init ppio"); 655 return ret; 656 } 657 658 /* 659 * In case there are some some stale uc/mc mac addresses flush them 660 * here. It cannot be done during mrvl_dev_close() as port information 661 * is already gone at that point (due to pp2_ppio_deinit() in 662 * mrvl_dev_stop()). 663 */ 664 if (!priv->uc_mc_flushed) { 665 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 666 if (ret) { 667 MRVL_LOG(ERR, 668 "Failed to flush uc/mc filter list"); 669 goto out; 670 } 671 priv->uc_mc_flushed = 1; 672 } 673 674 if (!priv->vlan_flushed) { 675 ret = pp2_ppio_flush_vlan(priv->ppio); 676 if (ret) { 677 MRVL_LOG(ERR, "Failed to flush vlan list"); 678 /* 679 * TODO 680 * once pp2_ppio_flush_vlan() is supported jump to out 681 * goto out; 682 */ 683 } 684 priv->vlan_flushed = 1; 685 } 686 ret = mrvl_mtu_set(dev, dev->data->mtu); 687 if (ret) 688 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); 689 690 /* For default QoS config, don't start classifier. */ 691 if (mrvl_qos_cfg && 692 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) { 693 ret = mrvl_start_qos_mapping(priv); 694 if (ret) { 695 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 696 goto out; 697 } 698 } 699 700 ret = mrvl_dev_set_link_up(dev); 701 if (ret) { 702 MRVL_LOG(ERR, "Failed to set link up"); 703 goto out; 704 } 705 706 /* start tx queues */ 707 for (i = 0; i < dev->data->nb_tx_queues; i++) { 708 struct mrvl_txq *txq = dev->data->tx_queues[i]; 709 710 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 711 712 if (!txq->tx_deferred_start) 713 continue; 714 715 /* 716 * All txqs are started by default. Stop them 717 * so that tx_deferred_start works as expected. 718 */ 719 ret = mrvl_tx_queue_stop(dev, i); 720 if (ret) 721 goto out; 722 } 723 724 mrvl_flow_init(dev); 725 mrvl_mtr_init(dev); 726 mrvl_set_tx_function(dev); 727 728 return 0; 729 out: 730 MRVL_LOG(ERR, "Failed to start device"); 731 pp2_ppio_deinit(priv->ppio); 732 return ret; 733 } 734 735 /** 736 * Flush receive queues. 737 * 738 * @param dev 739 * Pointer to Ethernet device structure. 740 */ 741 static void 742 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 743 { 744 int i; 745 746 MRVL_LOG(INFO, "Flushing rx queues"); 747 for (i = 0; i < dev->data->nb_rx_queues; i++) { 748 int ret, num; 749 750 do { 751 struct mrvl_rxq *q = dev->data->rx_queues[i]; 752 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 753 754 num = MRVL_PP2_RXD_MAX; 755 ret = pp2_ppio_recv(q->priv->ppio, 756 q->priv->rxq_map[q->queue_id].tc, 757 q->priv->rxq_map[q->queue_id].inq, 758 descs, (uint16_t *)&num); 759 } while (ret == 0 && num); 760 } 761 } 762 763 /** 764 * Flush transmit shadow queues. 765 * 766 * @param dev 767 * Pointer to Ethernet device structure. 768 */ 769 static void 770 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 771 { 772 int i, j; 773 struct mrvl_txq *txq; 774 775 MRVL_LOG(INFO, "Flushing tx shadow queues"); 776 for (i = 0; i < dev->data->nb_tx_queues; i++) { 777 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 778 779 for (j = 0; j < RTE_MAX_LCORE; j++) { 780 struct mrvl_shadow_txq *sq; 781 782 if (!hifs[j]) 783 continue; 784 785 sq = &txq->shadow_txqs[j]; 786 mrvl_free_sent_buffers(txq->priv->ppio, 787 hifs[j], j, sq, txq->queue_id, 1); 788 while (sq->tail != sq->head) { 789 uint64_t addr = cookie_addr_high | 790 sq->ent[sq->tail].buff.cookie; 791 rte_pktmbuf_free( 792 (struct rte_mbuf *)addr); 793 sq->tail = (sq->tail + 1) & 794 MRVL_PP2_TX_SHADOWQ_MASK; 795 } 796 memset(sq, 0, sizeof(*sq)); 797 } 798 } 799 } 800 801 /** 802 * Flush hardware bpool (buffer-pool). 803 * 804 * @param dev 805 * Pointer to Ethernet device structure. 806 */ 807 static void 808 mrvl_flush_bpool(struct rte_eth_dev *dev) 809 { 810 struct mrvl_priv *priv = dev->data->dev_private; 811 struct pp2_hif *hif; 812 uint32_t num; 813 int ret; 814 unsigned int core_id = rte_lcore_id(); 815 816 if (core_id == LCORE_ID_ANY) 817 core_id = rte_get_master_lcore(); 818 819 hif = mrvl_get_hif(priv, core_id); 820 821 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 822 if (ret) { 823 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 824 return; 825 } 826 827 while (num--) { 828 struct pp2_buff_inf inf; 829 uint64_t addr; 830 831 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 832 if (ret) 833 break; 834 835 addr = cookie_addr_high | inf.cookie; 836 rte_pktmbuf_free((struct rte_mbuf *)addr); 837 } 838 } 839 840 /** 841 * DPDK callback to stop the device. 842 * 843 * @param dev 844 * Pointer to Ethernet device structure. 845 */ 846 static void 847 mrvl_dev_stop(struct rte_eth_dev *dev) 848 { 849 mrvl_dev_set_link_down(dev); 850 } 851 852 /** 853 * DPDK callback to close the device. 854 * 855 * @param dev 856 * Pointer to Ethernet device structure. 857 */ 858 static void 859 mrvl_dev_close(struct rte_eth_dev *dev) 860 { 861 struct mrvl_priv *priv = dev->data->dev_private; 862 size_t i; 863 864 mrvl_flush_rx_queues(dev); 865 mrvl_flush_tx_shadow_queues(dev); 866 mrvl_flow_deinit(dev); 867 mrvl_mtr_deinit(dev); 868 869 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 870 struct pp2_ppio_tc_params *tc_params = 871 &priv->ppio_params.inqs_params.tcs_params[i]; 872 873 if (tc_params->inqs_params) { 874 rte_free(tc_params->inqs_params); 875 tc_params->inqs_params = NULL; 876 } 877 } 878 879 if (priv->cls_tbl) { 880 pp2_cls_tbl_deinit(priv->cls_tbl); 881 priv->cls_tbl = NULL; 882 } 883 884 if (priv->qos_tbl) { 885 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 886 priv->qos_tbl = NULL; 887 } 888 889 mrvl_flush_bpool(dev); 890 mrvl_tm_deinit(dev); 891 892 if (priv->ppio) { 893 pp2_ppio_deinit(priv->ppio); 894 priv->ppio = NULL; 895 } 896 897 /* policer must be released after ppio deinitialization */ 898 if (priv->default_policer) { 899 pp2_cls_plcr_deinit(priv->default_policer); 900 priv->default_policer = NULL; 901 } 902 903 904 if (priv->bpool) { 905 pp2_bpool_deinit(priv->bpool); 906 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 907 priv->bpool = NULL; 908 } 909 910 mrvl_dev_num--; 911 912 if (mrvl_dev_num == 0) { 913 MRVL_LOG(INFO, "Perform MUSDK deinit"); 914 mrvl_deinit_hifs(); 915 mrvl_deinit_pp2(); 916 rte_mvep_deinit(MVEP_MOD_T_PP2); 917 } 918 } 919 920 /** 921 * DPDK callback to retrieve physical link information. 922 * 923 * @param dev 924 * Pointer to Ethernet device structure. 925 * @param wait_to_complete 926 * Wait for request completion (ignored). 927 * 928 * @return 929 * 0 on success, negative error value otherwise. 930 */ 931 static int 932 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 933 { 934 /* 935 * TODO 936 * once MUSDK provides necessary API use it here 937 */ 938 struct mrvl_priv *priv = dev->data->dev_private; 939 struct ethtool_cmd edata; 940 struct ifreq req; 941 int ret, fd, link_up; 942 943 if (!priv->ppio) 944 return -EPERM; 945 946 edata.cmd = ETHTOOL_GSET; 947 948 strcpy(req.ifr_name, dev->data->name); 949 req.ifr_data = (void *)&edata; 950 951 fd = socket(AF_INET, SOCK_DGRAM, 0); 952 if (fd == -1) 953 return -EFAULT; 954 955 ret = ioctl(fd, SIOCETHTOOL, &req); 956 if (ret == -1) { 957 close(fd); 958 return -EFAULT; 959 } 960 961 close(fd); 962 963 switch (ethtool_cmd_speed(&edata)) { 964 case SPEED_10: 965 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M; 966 break; 967 case SPEED_100: 968 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M; 969 break; 970 case SPEED_1000: 971 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; 972 break; 973 case SPEED_10000: 974 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; 975 break; 976 default: 977 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; 978 } 979 980 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : 981 ETH_LINK_HALF_DUPLEX; 982 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : 983 ETH_LINK_FIXED; 984 pp2_ppio_get_link_state(priv->ppio, &link_up); 985 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 986 987 return 0; 988 } 989 990 /** 991 * DPDK callback to enable promiscuous mode. 992 * 993 * @param dev 994 * Pointer to Ethernet device structure. 995 * 996 * @return 997 * 0 on success, negative error value otherwise. 998 */ 999 static int 1000 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 1001 { 1002 struct mrvl_priv *priv = dev->data->dev_private; 1003 int ret; 1004 1005 if (!priv->ppio) 1006 return 0; 1007 1008 if (priv->isolated) 1009 return 0; 1010 1011 ret = pp2_ppio_set_promisc(priv->ppio, 1); 1012 if (ret) { 1013 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 1014 return -EAGAIN; 1015 } 1016 1017 return 0; 1018 } 1019 1020 /** 1021 * DPDK callback to enable allmulti mode. 1022 * 1023 * @param dev 1024 * Pointer to Ethernet device structure. 1025 * 1026 * @return 1027 * 0 on success, negative error value otherwise. 1028 */ 1029 static int 1030 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 1031 { 1032 struct mrvl_priv *priv = dev->data->dev_private; 1033 int ret; 1034 1035 if (!priv->ppio) 1036 return 0; 1037 1038 if (priv->isolated) 1039 return 0; 1040 1041 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 1042 if (ret) { 1043 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 1044 return -EAGAIN; 1045 } 1046 1047 return 0; 1048 } 1049 1050 /** 1051 * DPDK callback to disable promiscuous mode. 1052 * 1053 * @param dev 1054 * Pointer to Ethernet device structure. 1055 * 1056 * @return 1057 * 0 on success, negative error value otherwise. 1058 */ 1059 static int 1060 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 1061 { 1062 struct mrvl_priv *priv = dev->data->dev_private; 1063 int ret; 1064 1065 if (!priv->ppio) 1066 return 0; 1067 1068 ret = pp2_ppio_set_promisc(priv->ppio, 0); 1069 if (ret) { 1070 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 1071 return -EAGAIN; 1072 } 1073 1074 return 0; 1075 } 1076 1077 /** 1078 * DPDK callback to disable allmulticast mode. 1079 * 1080 * @param dev 1081 * Pointer to Ethernet device structure. 1082 * 1083 * @return 1084 * 0 on success, negative error value otherwise. 1085 */ 1086 static int 1087 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 1088 { 1089 struct mrvl_priv *priv = dev->data->dev_private; 1090 int ret; 1091 1092 if (!priv->ppio) 1093 return 0; 1094 1095 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 1096 if (ret) { 1097 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 1098 return -EAGAIN; 1099 } 1100 1101 return 0; 1102 } 1103 1104 /** 1105 * DPDK callback to remove a MAC address. 1106 * 1107 * @param dev 1108 * Pointer to Ethernet device structure. 1109 * @param index 1110 * MAC address index. 1111 */ 1112 static void 1113 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 1114 { 1115 struct mrvl_priv *priv = dev->data->dev_private; 1116 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1117 int ret; 1118 1119 if (!priv->ppio) 1120 return; 1121 1122 if (priv->isolated) 1123 return; 1124 1125 ret = pp2_ppio_remove_mac_addr(priv->ppio, 1126 dev->data->mac_addrs[index].addr_bytes); 1127 if (ret) { 1128 rte_ether_format_addr(buf, sizeof(buf), 1129 &dev->data->mac_addrs[index]); 1130 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 1131 } 1132 } 1133 1134 /** 1135 * DPDK callback to add a MAC address. 1136 * 1137 * @param dev 1138 * Pointer to Ethernet device structure. 1139 * @param mac_addr 1140 * MAC address to register. 1141 * @param index 1142 * MAC address index. 1143 * @param vmdq 1144 * VMDq pool index to associate address with (unused). 1145 * 1146 * @return 1147 * 0 on success, negative error value otherwise. 1148 */ 1149 static int 1150 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1151 uint32_t index, uint32_t vmdq __rte_unused) 1152 { 1153 struct mrvl_priv *priv = dev->data->dev_private; 1154 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1155 int ret; 1156 1157 if (priv->isolated) 1158 return -ENOTSUP; 1159 1160 if (index == 0) 1161 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1162 return -1; 1163 1164 if (!priv->ppio) 1165 return 0; 1166 1167 /* 1168 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1169 * parameter uc_filter_max. Maximum number of mc addresses is then 1170 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1171 * 21 respectively. 1172 * 1173 * If more than uc_filter_max uc addresses were added to filter list 1174 * then NIC will switch to promiscuous mode automatically. 1175 * 1176 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1177 * were added to filter list then NIC will switch to all-multicast mode 1178 * automatically. 1179 */ 1180 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1181 if (ret) { 1182 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1183 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1184 return -1; 1185 } 1186 1187 return 0; 1188 } 1189 1190 /** 1191 * DPDK callback to set the primary MAC address. 1192 * 1193 * @param dev 1194 * Pointer to Ethernet device structure. 1195 * @param mac_addr 1196 * MAC address to register. 1197 * 1198 * @return 1199 * 0 on success, negative error value otherwise. 1200 */ 1201 static int 1202 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1203 { 1204 struct mrvl_priv *priv = dev->data->dev_private; 1205 int ret; 1206 1207 if (!priv->ppio) 1208 return 0; 1209 1210 if (priv->isolated) 1211 return -ENOTSUP; 1212 1213 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1214 if (ret) { 1215 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1216 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1217 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1218 } 1219 1220 return ret; 1221 } 1222 1223 /** 1224 * DPDK callback to get device statistics. 1225 * 1226 * @param dev 1227 * Pointer to Ethernet device structure. 1228 * @param stats 1229 * Stats structure output buffer. 1230 * 1231 * @return 1232 * 0 on success, negative error value otherwise. 1233 */ 1234 static int 1235 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1236 { 1237 struct mrvl_priv *priv = dev->data->dev_private; 1238 struct pp2_ppio_statistics ppio_stats; 1239 uint64_t drop_mac = 0; 1240 unsigned int i, idx, ret; 1241 1242 if (!priv->ppio) 1243 return -EPERM; 1244 1245 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1246 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1247 struct pp2_ppio_inq_statistics rx_stats; 1248 1249 if (!rxq) 1250 continue; 1251 1252 idx = rxq->queue_id; 1253 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1254 MRVL_LOG(ERR, 1255 "rx queue %d stats out of range (0 - %d)", 1256 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1257 continue; 1258 } 1259 1260 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1261 priv->rxq_map[idx].tc, 1262 priv->rxq_map[idx].inq, 1263 &rx_stats, 0); 1264 if (unlikely(ret)) { 1265 MRVL_LOG(ERR, 1266 "Failed to update rx queue %d stats", idx); 1267 break; 1268 } 1269 1270 stats->q_ibytes[idx] = rxq->bytes_recv; 1271 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1272 stats->q_errors[idx] = rx_stats.drop_early + 1273 rx_stats.drop_fullq + 1274 rx_stats.drop_bm + 1275 rxq->drop_mac; 1276 stats->ibytes += rxq->bytes_recv; 1277 drop_mac += rxq->drop_mac; 1278 } 1279 1280 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1281 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1282 struct pp2_ppio_outq_statistics tx_stats; 1283 1284 if (!txq) 1285 continue; 1286 1287 idx = txq->queue_id; 1288 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1289 MRVL_LOG(ERR, 1290 "tx queue %d stats out of range (0 - %d)", 1291 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1292 } 1293 1294 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1295 &tx_stats, 0); 1296 if (unlikely(ret)) { 1297 MRVL_LOG(ERR, 1298 "Failed to update tx queue %d stats", idx); 1299 break; 1300 } 1301 1302 stats->q_opackets[idx] = tx_stats.deq_desc; 1303 stats->q_obytes[idx] = txq->bytes_sent; 1304 stats->obytes += txq->bytes_sent; 1305 } 1306 1307 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1308 if (unlikely(ret)) { 1309 MRVL_LOG(ERR, "Failed to update port statistics"); 1310 return ret; 1311 } 1312 1313 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1314 stats->opackets += ppio_stats.tx_packets; 1315 stats->imissed += ppio_stats.rx_fullq_dropped + 1316 ppio_stats.rx_bm_dropped + 1317 ppio_stats.rx_early_dropped + 1318 ppio_stats.rx_fifo_dropped + 1319 ppio_stats.rx_cls_dropped; 1320 stats->ierrors = drop_mac; 1321 1322 return 0; 1323 } 1324 1325 /** 1326 * DPDK callback to clear device statistics. 1327 * 1328 * @param dev 1329 * Pointer to Ethernet device structure. 1330 * 1331 * @return 1332 * 0 on success, negative error value otherwise. 1333 */ 1334 static int 1335 mrvl_stats_reset(struct rte_eth_dev *dev) 1336 { 1337 struct mrvl_priv *priv = dev->data->dev_private; 1338 int i; 1339 1340 if (!priv->ppio) 1341 return 0; 1342 1343 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1344 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1345 1346 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1347 priv->rxq_map[i].inq, NULL, 1); 1348 rxq->bytes_recv = 0; 1349 rxq->drop_mac = 0; 1350 } 1351 1352 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1353 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1354 1355 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1356 txq->bytes_sent = 0; 1357 } 1358 1359 return pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1360 } 1361 1362 /** 1363 * DPDK callback to get extended statistics. 1364 * 1365 * @param dev 1366 * Pointer to Ethernet device structure. 1367 * @param stats 1368 * Pointer to xstats table. 1369 * @param n 1370 * Number of entries in xstats table. 1371 * @return 1372 * Negative value on error, number of read xstats otherwise. 1373 */ 1374 static int 1375 mrvl_xstats_get(struct rte_eth_dev *dev, 1376 struct rte_eth_xstat *stats, unsigned int n) 1377 { 1378 struct mrvl_priv *priv = dev->data->dev_private; 1379 struct pp2_ppio_statistics ppio_stats; 1380 unsigned int i; 1381 1382 if (!stats) 1383 return 0; 1384 1385 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1386 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) { 1387 uint64_t val; 1388 1389 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1390 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1391 mrvl_xstats_tbl[i].offset); 1392 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1393 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1394 mrvl_xstats_tbl[i].offset); 1395 else 1396 return -EINVAL; 1397 1398 stats[i].id = i; 1399 stats[i].value = val; 1400 } 1401 1402 return n; 1403 } 1404 1405 /** 1406 * DPDK callback to reset extended statistics. 1407 * 1408 * @param dev 1409 * Pointer to Ethernet device structure. 1410 * 1411 * @return 1412 * 0 on success, negative error value otherwise. 1413 */ 1414 static int 1415 mrvl_xstats_reset(struct rte_eth_dev *dev) 1416 { 1417 return mrvl_stats_reset(dev); 1418 } 1419 1420 /** 1421 * DPDK callback to get extended statistics names. 1422 * 1423 * @param dev (unused) 1424 * Pointer to Ethernet device structure. 1425 * @param xstats_names 1426 * Pointer to xstats names table. 1427 * @param size 1428 * Size of the xstats names table. 1429 * @return 1430 * Number of read names. 1431 */ 1432 static int 1433 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1434 struct rte_eth_xstat_name *xstats_names, 1435 unsigned int size) 1436 { 1437 unsigned int i; 1438 1439 if (!xstats_names) 1440 return RTE_DIM(mrvl_xstats_tbl); 1441 1442 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1443 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name, 1444 RTE_ETH_XSTATS_NAME_SIZE); 1445 1446 return size; 1447 } 1448 1449 /** 1450 * DPDK callback to get information about the device. 1451 * 1452 * @param dev 1453 * Pointer to Ethernet device structure (unused). 1454 * @param info 1455 * Info structure output buffer. 1456 */ 1457 static int 1458 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 1459 struct rte_eth_dev_info *info) 1460 { 1461 info->speed_capa = ETH_LINK_SPEED_10M | 1462 ETH_LINK_SPEED_100M | 1463 ETH_LINK_SPEED_1G | 1464 ETH_LINK_SPEED_10G; 1465 1466 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1467 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1468 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1469 1470 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1471 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1472 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1473 1474 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1475 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1476 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1477 1478 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1479 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1480 1481 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1482 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1483 1484 info->flow_type_rss_offloads = ETH_RSS_IPV4 | 1485 ETH_RSS_NONFRAG_IPV4_TCP | 1486 ETH_RSS_NONFRAG_IPV4_UDP; 1487 1488 /* By default packets are dropped if no descriptors are available */ 1489 info->default_rxconf.rx_drop_en = 1; 1490 1491 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1492 1493 return 0; 1494 } 1495 1496 /** 1497 * Return supported packet types. 1498 * 1499 * @param dev 1500 * Pointer to Ethernet device structure (unused). 1501 * 1502 * @return 1503 * Const pointer to the table with supported packet types. 1504 */ 1505 static const uint32_t * 1506 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1507 { 1508 static const uint32_t ptypes[] = { 1509 RTE_PTYPE_L2_ETHER, 1510 RTE_PTYPE_L2_ETHER_VLAN, 1511 RTE_PTYPE_L2_ETHER_QINQ, 1512 RTE_PTYPE_L3_IPV4, 1513 RTE_PTYPE_L3_IPV4_EXT, 1514 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1515 RTE_PTYPE_L3_IPV6, 1516 RTE_PTYPE_L3_IPV6_EXT, 1517 RTE_PTYPE_L2_ETHER_ARP, 1518 RTE_PTYPE_L4_TCP, 1519 RTE_PTYPE_L4_UDP 1520 }; 1521 1522 return ptypes; 1523 } 1524 1525 /** 1526 * DPDK callback to get information about specific receive queue. 1527 * 1528 * @param dev 1529 * Pointer to Ethernet device structure. 1530 * @param rx_queue_id 1531 * Receive queue index. 1532 * @param qinfo 1533 * Receive queue information structure. 1534 */ 1535 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1536 struct rte_eth_rxq_info *qinfo) 1537 { 1538 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1539 struct mrvl_priv *priv = dev->data->dev_private; 1540 int inq = priv->rxq_map[rx_queue_id].inq; 1541 int tc = priv->rxq_map[rx_queue_id].tc; 1542 struct pp2_ppio_tc_params *tc_params = 1543 &priv->ppio_params.inqs_params.tcs_params[tc]; 1544 1545 qinfo->mp = q->mp; 1546 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1547 } 1548 1549 /** 1550 * DPDK callback to get information about specific transmit queue. 1551 * 1552 * @param dev 1553 * Pointer to Ethernet device structure. 1554 * @param tx_queue_id 1555 * Transmit queue index. 1556 * @param qinfo 1557 * Transmit queue information structure. 1558 */ 1559 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1560 struct rte_eth_txq_info *qinfo) 1561 { 1562 struct mrvl_priv *priv = dev->data->dev_private; 1563 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1564 1565 qinfo->nb_desc = 1566 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1567 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1568 } 1569 1570 /** 1571 * DPDK callback to Configure a VLAN filter. 1572 * 1573 * @param dev 1574 * Pointer to Ethernet device structure. 1575 * @param vlan_id 1576 * VLAN ID to filter. 1577 * @param on 1578 * Toggle filter. 1579 * 1580 * @return 1581 * 0 on success, negative error value otherwise. 1582 */ 1583 static int 1584 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1585 { 1586 struct mrvl_priv *priv = dev->data->dev_private; 1587 1588 if (!priv->ppio) 1589 return -EPERM; 1590 1591 if (priv->isolated) 1592 return -ENOTSUP; 1593 1594 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1595 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1596 } 1597 1598 /** 1599 * Release buffers to hardware bpool (buffer-pool) 1600 * 1601 * @param rxq 1602 * Receive queue pointer. 1603 * @param num 1604 * Number of buffers to release to bpool. 1605 * 1606 * @return 1607 * 0 on success, negative error value otherwise. 1608 */ 1609 static int 1610 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1611 { 1612 struct buff_release_entry entries[MRVL_PP2_RXD_MAX]; 1613 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX]; 1614 int i, ret; 1615 unsigned int core_id; 1616 struct pp2_hif *hif; 1617 struct pp2_bpool *bpool; 1618 1619 core_id = rte_lcore_id(); 1620 if (core_id == LCORE_ID_ANY) 1621 core_id = rte_get_master_lcore(); 1622 1623 hif = mrvl_get_hif(rxq->priv, core_id); 1624 if (!hif) 1625 return -1; 1626 1627 bpool = rxq->priv->bpool; 1628 1629 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1630 if (ret) 1631 return ret; 1632 1633 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1634 cookie_addr_high = 1635 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1636 1637 for (i = 0; i < num; i++) { 1638 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1639 != cookie_addr_high) { 1640 MRVL_LOG(ERR, 1641 "mbuf virtual addr high 0x%lx out of range", 1642 (uint64_t)mbufs[i] >> 32); 1643 goto out; 1644 } 1645 1646 entries[i].buff.addr = 1647 rte_mbuf_data_iova_default(mbufs[i]); 1648 entries[i].buff.cookie = (uint64_t)mbufs[i]; 1649 entries[i].bpool = bpool; 1650 } 1651 1652 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1653 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1654 1655 if (i != num) 1656 goto out; 1657 1658 return 0; 1659 out: 1660 for (; i < num; i++) 1661 rte_pktmbuf_free(mbufs[i]); 1662 1663 return -1; 1664 } 1665 1666 /** 1667 * DPDK callback to configure the receive queue. 1668 * 1669 * @param dev 1670 * Pointer to Ethernet device structure. 1671 * @param idx 1672 * RX queue index. 1673 * @param desc 1674 * Number of descriptors to configure in queue. 1675 * @param socket 1676 * NUMA socket on which memory must be allocated. 1677 * @param conf 1678 * Thresholds parameters. 1679 * @param mp 1680 * Memory pool for buffer allocations. 1681 * 1682 * @return 1683 * 0 on success, negative error value otherwise. 1684 */ 1685 static int 1686 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1687 unsigned int socket, 1688 const struct rte_eth_rxconf *conf, 1689 struct rte_mempool *mp) 1690 { 1691 struct mrvl_priv *priv = dev->data->dev_private; 1692 struct mrvl_rxq *rxq; 1693 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp); 1694 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1695 int ret, tc, inq; 1696 uint64_t offloads; 1697 1698 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1699 1700 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1701 /* 1702 * Unknown TC mapping, mapping will not have a correct queue. 1703 */ 1704 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1705 idx, priv->ppio_id); 1706 return -EFAULT; 1707 } 1708 1709 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS; 1710 if (frame_size < max_rx_pkt_len) { 1711 MRVL_LOG(WARNING, 1712 "Mbuf size must be increased to %u bytes to hold up " 1713 "to %u bytes of data.", 1714 buf_size + max_rx_pkt_len - frame_size, 1715 max_rx_pkt_len); 1716 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1717 MRVL_LOG(INFO, "Setting max rx pkt len to %u", 1718 dev->data->dev_conf.rxmode.max_rx_pkt_len); 1719 } 1720 1721 if (dev->data->rx_queues[idx]) { 1722 rte_free(dev->data->rx_queues[idx]); 1723 dev->data->rx_queues[idx] = NULL; 1724 } 1725 1726 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 1727 if (!rxq) 1728 return -ENOMEM; 1729 1730 rxq->priv = priv; 1731 rxq->mp = mp; 1732 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; 1733 rxq->queue_id = idx; 1734 rxq->port_id = dev->data->port_id; 1735 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 1736 1737 tc = priv->rxq_map[rxq->queue_id].tc, 1738 inq = priv->rxq_map[rxq->queue_id].inq; 1739 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 1740 desc; 1741 1742 ret = mrvl_fill_bpool(rxq, desc); 1743 if (ret) { 1744 rte_free(rxq); 1745 return ret; 1746 } 1747 1748 priv->bpool_init_size += desc; 1749 1750 dev->data->rx_queues[idx] = rxq; 1751 1752 return 0; 1753 } 1754 1755 /** 1756 * DPDK callback to release the receive queue. 1757 * 1758 * @param rxq 1759 * Generic receive queue pointer. 1760 */ 1761 static void 1762 mrvl_rx_queue_release(void *rxq) 1763 { 1764 struct mrvl_rxq *q = rxq; 1765 struct pp2_ppio_tc_params *tc_params; 1766 int i, num, tc, inq; 1767 struct pp2_hif *hif; 1768 unsigned int core_id = rte_lcore_id(); 1769 1770 if (core_id == LCORE_ID_ANY) 1771 core_id = rte_get_master_lcore(); 1772 1773 if (!q) 1774 return; 1775 1776 hif = mrvl_get_hif(q->priv, core_id); 1777 1778 if (!hif) 1779 return; 1780 1781 tc = q->priv->rxq_map[q->queue_id].tc; 1782 inq = q->priv->rxq_map[q->queue_id].inq; 1783 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 1784 num = tc_params->inqs_params[inq].size; 1785 for (i = 0; i < num; i++) { 1786 struct pp2_buff_inf inf; 1787 uint64_t addr; 1788 1789 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 1790 addr = cookie_addr_high | inf.cookie; 1791 rte_pktmbuf_free((struct rte_mbuf *)addr); 1792 } 1793 1794 rte_free(q); 1795 } 1796 1797 /** 1798 * DPDK callback to configure the transmit queue. 1799 * 1800 * @param dev 1801 * Pointer to Ethernet device structure. 1802 * @param idx 1803 * Transmit queue index. 1804 * @param desc 1805 * Number of descriptors to configure in the queue. 1806 * @param socket 1807 * NUMA socket on which memory must be allocated. 1808 * @param conf 1809 * Tx queue configuration parameters. 1810 * 1811 * @return 1812 * 0 on success, negative error value otherwise. 1813 */ 1814 static int 1815 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1816 unsigned int socket, 1817 const struct rte_eth_txconf *conf) 1818 { 1819 struct mrvl_priv *priv = dev->data->dev_private; 1820 struct mrvl_txq *txq; 1821 1822 if (dev->data->tx_queues[idx]) { 1823 rte_free(dev->data->tx_queues[idx]); 1824 dev->data->tx_queues[idx] = NULL; 1825 } 1826 1827 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 1828 if (!txq) 1829 return -ENOMEM; 1830 1831 txq->priv = priv; 1832 txq->queue_id = idx; 1833 txq->port_id = dev->data->port_id; 1834 txq->tx_deferred_start = conf->tx_deferred_start; 1835 dev->data->tx_queues[idx] = txq; 1836 1837 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 1838 1839 return 0; 1840 } 1841 1842 /** 1843 * DPDK callback to release the transmit queue. 1844 * 1845 * @param txq 1846 * Generic transmit queue pointer. 1847 */ 1848 static void 1849 mrvl_tx_queue_release(void *txq) 1850 { 1851 struct mrvl_txq *q = txq; 1852 1853 if (!q) 1854 return; 1855 1856 rte_free(q); 1857 } 1858 1859 /** 1860 * DPDK callback to get flow control configuration. 1861 * 1862 * @param dev 1863 * Pointer to Ethernet device structure. 1864 * @param fc_conf 1865 * Pointer to the flow control configuration. 1866 * 1867 * @return 1868 * 0 on success, negative error value otherwise. 1869 */ 1870 static int 1871 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1872 { 1873 struct mrvl_priv *priv = dev->data->dev_private; 1874 int ret, en; 1875 1876 if (!priv) 1877 return -EPERM; 1878 1879 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 1880 if (ret) { 1881 MRVL_LOG(ERR, "Failed to read rx pause state"); 1882 return ret; 1883 } 1884 1885 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; 1886 1887 return 0; 1888 } 1889 1890 /** 1891 * DPDK callback to set flow control configuration. 1892 * 1893 * @param dev 1894 * Pointer to Ethernet device structure. 1895 * @param fc_conf 1896 * Pointer to the flow control configuration. 1897 * 1898 * @return 1899 * 0 on success, negative error value otherwise. 1900 */ 1901 static int 1902 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1903 { 1904 struct mrvl_priv *priv = dev->data->dev_private; 1905 1906 if (!priv) 1907 return -EPERM; 1908 1909 if (fc_conf->high_water || 1910 fc_conf->low_water || 1911 fc_conf->pause_time || 1912 fc_conf->mac_ctrl_frame_fwd || 1913 fc_conf->autoneg) { 1914 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 1915 1916 return -EINVAL; 1917 } 1918 1919 if (fc_conf->mode == RTE_FC_NONE || 1920 fc_conf->mode == RTE_FC_RX_PAUSE) { 1921 int ret, en; 1922 1923 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; 1924 ret = pp2_ppio_set_rx_pause(priv->ppio, en); 1925 if (ret) 1926 MRVL_LOG(ERR, 1927 "Failed to change flowctrl on RX side"); 1928 1929 return ret; 1930 } 1931 1932 return 0; 1933 } 1934 1935 /** 1936 * Update RSS hash configuration 1937 * 1938 * @param dev 1939 * Pointer to Ethernet device structure. 1940 * @param rss_conf 1941 * Pointer to RSS configuration. 1942 * 1943 * @return 1944 * 0 on success, negative error value otherwise. 1945 */ 1946 static int 1947 mrvl_rss_hash_update(struct rte_eth_dev *dev, 1948 struct rte_eth_rss_conf *rss_conf) 1949 { 1950 struct mrvl_priv *priv = dev->data->dev_private; 1951 1952 if (priv->isolated) 1953 return -ENOTSUP; 1954 1955 return mrvl_configure_rss(priv, rss_conf); 1956 } 1957 1958 /** 1959 * DPDK callback to get RSS hash configuration. 1960 * 1961 * @param dev 1962 * Pointer to Ethernet device structure. 1963 * @rss_conf 1964 * Pointer to RSS configuration. 1965 * 1966 * @return 1967 * Always 0. 1968 */ 1969 static int 1970 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 1971 struct rte_eth_rss_conf *rss_conf) 1972 { 1973 struct mrvl_priv *priv = dev->data->dev_private; 1974 enum pp2_ppio_hash_type hash_type = 1975 priv->ppio_params.inqs_params.hash_type; 1976 1977 rss_conf->rss_key = NULL; 1978 1979 if (hash_type == PP2_PPIO_HASH_T_NONE) 1980 rss_conf->rss_hf = 0; 1981 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 1982 rss_conf->rss_hf = ETH_RSS_IPV4; 1983 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 1984 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; 1985 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 1986 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; 1987 1988 return 0; 1989 } 1990 1991 /** 1992 * DPDK callback to get rte_flow callbacks. 1993 * 1994 * @param dev 1995 * Pointer to the device structure. 1996 * @param filer_type 1997 * Flow filter type. 1998 * @param filter_op 1999 * Flow filter operation. 2000 * @param arg 2001 * Pointer to pass the flow ops. 2002 * 2003 * @return 2004 * 0 on success, negative error value otherwise. 2005 */ 2006 static int 2007 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 2008 enum rte_filter_type filter_type, 2009 enum rte_filter_op filter_op, void *arg) 2010 { 2011 switch (filter_type) { 2012 case RTE_ETH_FILTER_GENERIC: 2013 if (filter_op != RTE_ETH_FILTER_GET) 2014 return -EINVAL; 2015 *(const void **)arg = &mrvl_flow_ops; 2016 return 0; 2017 default: 2018 MRVL_LOG(WARNING, "Filter type (%d) not supported", 2019 filter_type); 2020 return -EINVAL; 2021 } 2022 } 2023 2024 /** 2025 * DPDK callback to get rte_mtr callbacks. 2026 * 2027 * @param dev 2028 * Pointer to the device structure. 2029 * @param ops 2030 * Pointer to pass the mtr ops. 2031 * 2032 * @return 2033 * Always 0. 2034 */ 2035 static int 2036 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2037 { 2038 *(const void **)ops = &mrvl_mtr_ops; 2039 2040 return 0; 2041 } 2042 2043 /** 2044 * DPDK callback to get rte_tm callbacks. 2045 * 2046 * @param dev 2047 * Pointer to the device structure. 2048 * @param ops 2049 * Pointer to pass the tm ops. 2050 * 2051 * @return 2052 * Always 0. 2053 */ 2054 static int 2055 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2056 { 2057 *(const void **)ops = &mrvl_tm_ops; 2058 2059 return 0; 2060 } 2061 2062 static const struct eth_dev_ops mrvl_ops = { 2063 .dev_configure = mrvl_dev_configure, 2064 .dev_start = mrvl_dev_start, 2065 .dev_stop = mrvl_dev_stop, 2066 .dev_set_link_up = mrvl_dev_set_link_up, 2067 .dev_set_link_down = mrvl_dev_set_link_down, 2068 .dev_close = mrvl_dev_close, 2069 .link_update = mrvl_link_update, 2070 .promiscuous_enable = mrvl_promiscuous_enable, 2071 .allmulticast_enable = mrvl_allmulticast_enable, 2072 .promiscuous_disable = mrvl_promiscuous_disable, 2073 .allmulticast_disable = mrvl_allmulticast_disable, 2074 .mac_addr_remove = mrvl_mac_addr_remove, 2075 .mac_addr_add = mrvl_mac_addr_add, 2076 .mac_addr_set = mrvl_mac_addr_set, 2077 .mtu_set = mrvl_mtu_set, 2078 .stats_get = mrvl_stats_get, 2079 .stats_reset = mrvl_stats_reset, 2080 .xstats_get = mrvl_xstats_get, 2081 .xstats_reset = mrvl_xstats_reset, 2082 .xstats_get_names = mrvl_xstats_get_names, 2083 .dev_infos_get = mrvl_dev_infos_get, 2084 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 2085 .rxq_info_get = mrvl_rxq_info_get, 2086 .txq_info_get = mrvl_txq_info_get, 2087 .vlan_filter_set = mrvl_vlan_filter_set, 2088 .tx_queue_start = mrvl_tx_queue_start, 2089 .tx_queue_stop = mrvl_tx_queue_stop, 2090 .rx_queue_setup = mrvl_rx_queue_setup, 2091 .rx_queue_release = mrvl_rx_queue_release, 2092 .tx_queue_setup = mrvl_tx_queue_setup, 2093 .tx_queue_release = mrvl_tx_queue_release, 2094 .flow_ctrl_get = mrvl_flow_ctrl_get, 2095 .flow_ctrl_set = mrvl_flow_ctrl_set, 2096 .rss_hash_update = mrvl_rss_hash_update, 2097 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 2098 .filter_ctrl = mrvl_eth_filter_ctrl, 2099 .mtr_ops_get = mrvl_mtr_ops_get, 2100 .tm_ops_get = mrvl_tm_ops_get, 2101 }; 2102 2103 /** 2104 * Return packet type information and l3/l4 offsets. 2105 * 2106 * @param desc 2107 * Pointer to the received packet descriptor. 2108 * @param l3_offset 2109 * l3 packet offset. 2110 * @param l4_offset 2111 * l4 packet offset. 2112 * 2113 * @return 2114 * Packet type information. 2115 */ 2116 static inline uint64_t 2117 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 2118 uint8_t *l3_offset, uint8_t *l4_offset) 2119 { 2120 enum pp2_inq_l3_type l3_type; 2121 enum pp2_inq_l4_type l4_type; 2122 enum pp2_inq_vlan_tag vlan_tag; 2123 uint64_t packet_type; 2124 2125 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 2126 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 2127 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 2128 2129 packet_type = RTE_PTYPE_L2_ETHER; 2130 2131 switch (vlan_tag) { 2132 case PP2_INQ_VLAN_TAG_SINGLE: 2133 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 2134 break; 2135 case PP2_INQ_VLAN_TAG_DOUBLE: 2136 case PP2_INQ_VLAN_TAG_TRIPLE: 2137 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 2138 break; 2139 default: 2140 break; 2141 } 2142 2143 switch (l3_type) { 2144 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 2145 packet_type |= RTE_PTYPE_L3_IPV4; 2146 break; 2147 case PP2_INQ_L3_TYPE_IPV4_OK: 2148 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 2149 break; 2150 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 2151 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 2152 break; 2153 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 2154 packet_type |= RTE_PTYPE_L3_IPV6; 2155 break; 2156 case PP2_INQ_L3_TYPE_IPV6_EXT: 2157 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 2158 break; 2159 case PP2_INQ_L3_TYPE_ARP: 2160 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 2161 /* 2162 * In case of ARP l4_offset is set to wrong value. 2163 * Set it to proper one so that later on mbuf->l3_len can be 2164 * calculated subtracting l4_offset and l3_offset. 2165 */ 2166 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 2167 break; 2168 default: 2169 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type"); 2170 break; 2171 } 2172 2173 switch (l4_type) { 2174 case PP2_INQ_L4_TYPE_TCP: 2175 packet_type |= RTE_PTYPE_L4_TCP; 2176 break; 2177 case PP2_INQ_L4_TYPE_UDP: 2178 packet_type |= RTE_PTYPE_L4_UDP; 2179 break; 2180 default: 2181 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type"); 2182 break; 2183 } 2184 2185 return packet_type; 2186 } 2187 2188 /** 2189 * Get offload information from the received packet descriptor. 2190 * 2191 * @param desc 2192 * Pointer to the received packet descriptor. 2193 * 2194 * @return 2195 * Mbuf offload flags. 2196 */ 2197 static inline uint64_t 2198 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) 2199 { 2200 uint64_t flags; 2201 enum pp2_inq_desc_status status; 2202 2203 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2204 if (unlikely(status != PP2_DESC_ERR_OK)) 2205 flags = PKT_RX_IP_CKSUM_BAD; 2206 else 2207 flags = PKT_RX_IP_CKSUM_GOOD; 2208 2209 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2210 if (unlikely(status != PP2_DESC_ERR_OK)) 2211 flags |= PKT_RX_L4_CKSUM_BAD; 2212 else 2213 flags |= PKT_RX_L4_CKSUM_GOOD; 2214 2215 return flags; 2216 } 2217 2218 /** 2219 * DPDK callback for receive. 2220 * 2221 * @param rxq 2222 * Generic pointer to the receive queue. 2223 * @param rx_pkts 2224 * Array to store received packets. 2225 * @param nb_pkts 2226 * Maximum number of packets in array. 2227 * 2228 * @return 2229 * Number of packets successfully received. 2230 */ 2231 static uint16_t 2232 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2233 { 2234 struct mrvl_rxq *q = rxq; 2235 struct pp2_ppio_desc descs[nb_pkts]; 2236 struct pp2_bpool *bpool; 2237 int i, ret, rx_done = 0; 2238 int num; 2239 struct pp2_hif *hif; 2240 unsigned int core_id = rte_lcore_id(); 2241 2242 hif = mrvl_get_hif(q->priv, core_id); 2243 2244 if (unlikely(!q->priv->ppio || !hif)) 2245 return 0; 2246 2247 bpool = q->priv->bpool; 2248 2249 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2250 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2251 if (unlikely(ret < 0)) { 2252 MRVL_LOG(ERR, "Failed to receive packets"); 2253 return 0; 2254 } 2255 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2256 2257 for (i = 0; i < nb_pkts; i++) { 2258 struct rte_mbuf *mbuf; 2259 uint8_t l3_offset, l4_offset; 2260 enum pp2_inq_desc_status status; 2261 uint64_t addr; 2262 2263 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2264 struct pp2_ppio_desc *pref_desc; 2265 u64 pref_addr; 2266 2267 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2268 pref_addr = cookie_addr_high | 2269 pp2_ppio_inq_desc_get_cookie(pref_desc); 2270 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2271 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2272 } 2273 2274 addr = cookie_addr_high | 2275 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2276 mbuf = (struct rte_mbuf *)addr; 2277 rte_pktmbuf_reset(mbuf); 2278 2279 /* drop packet in case of mac, overrun or resource error */ 2280 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2281 if (unlikely(status != PP2_DESC_ERR_OK)) { 2282 struct pp2_buff_inf binf = { 2283 .addr = rte_mbuf_data_iova_default(mbuf), 2284 .cookie = (uint64_t)mbuf, 2285 }; 2286 2287 pp2_bpool_put_buff(hif, bpool, &binf); 2288 mrvl_port_bpool_size 2289 [bpool->pp2_id][bpool->id][core_id]++; 2290 q->drop_mac++; 2291 continue; 2292 } 2293 2294 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2295 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2296 mbuf->data_len = mbuf->pkt_len; 2297 mbuf->port = q->port_id; 2298 mbuf->packet_type = 2299 mrvl_desc_to_packet_type_and_offset(&descs[i], 2300 &l3_offset, 2301 &l4_offset); 2302 mbuf->l2_len = l3_offset; 2303 mbuf->l3_len = l4_offset - l3_offset; 2304 2305 if (likely(q->cksum_enabled)) 2306 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); 2307 2308 rx_pkts[rx_done++] = mbuf; 2309 q->bytes_recv += mbuf->pkt_len; 2310 } 2311 2312 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2313 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2314 2315 if (unlikely(num <= q->priv->bpool_min_size || 2316 (!rx_done && num < q->priv->bpool_init_size))) { 2317 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE); 2318 if (ret) 2319 MRVL_LOG(ERR, "Failed to fill bpool"); 2320 } else if (unlikely(num > q->priv->bpool_max_size)) { 2321 int i; 2322 int pkt_to_remove = num - q->priv->bpool_init_size; 2323 struct rte_mbuf *mbuf; 2324 struct pp2_buff_inf buff; 2325 2326 MRVL_LOG(DEBUG, 2327 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)", 2328 bpool->pp2_id, q->priv->ppio->port_id, 2329 bpool->id, pkt_to_remove, num, 2330 q->priv->bpool_init_size); 2331 2332 for (i = 0; i < pkt_to_remove; i++) { 2333 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2334 if (ret) 2335 break; 2336 mbuf = (struct rte_mbuf *) 2337 (cookie_addr_high | buff.cookie); 2338 rte_pktmbuf_free(mbuf); 2339 } 2340 mrvl_port_bpool_size 2341 [bpool->pp2_id][bpool->id][core_id] -= i; 2342 } 2343 rte_spinlock_unlock(&q->priv->lock); 2344 } 2345 2346 return rx_done; 2347 } 2348 2349 /** 2350 * Prepare offload information. 2351 * 2352 * @param ol_flags 2353 * Offload flags. 2354 * @param packet_type 2355 * Packet type bitfield. 2356 * @param l3_type 2357 * Pointer to the pp2_ouq_l3_type structure. 2358 * @param l4_type 2359 * Pointer to the pp2_outq_l4_type structure. 2360 * @param gen_l3_cksum 2361 * Will be set to 1 in case l3 checksum is computed. 2362 * @param l4_cksum 2363 * Will be set to 1 in case l4 checksum is computed. 2364 * 2365 * @return 2366 * 0 on success, negative error value otherwise. 2367 */ 2368 static inline int 2369 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, 2370 enum pp2_outq_l3_type *l3_type, 2371 enum pp2_outq_l4_type *l4_type, 2372 int *gen_l3_cksum, 2373 int *gen_l4_cksum) 2374 { 2375 /* 2376 * Based on ol_flags prepare information 2377 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2378 * for offloading. 2379 */ 2380 if (ol_flags & PKT_TX_IPV4) { 2381 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2382 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; 2383 } else if (ol_flags & PKT_TX_IPV6) { 2384 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2385 /* no checksum for ipv6 header */ 2386 *gen_l3_cksum = 0; 2387 } else { 2388 /* if something different then stop processing */ 2389 return -1; 2390 } 2391 2392 ol_flags &= PKT_TX_L4_MASK; 2393 if ((packet_type & RTE_PTYPE_L4_TCP) && 2394 ol_flags == PKT_TX_TCP_CKSUM) { 2395 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2396 *gen_l4_cksum = 1; 2397 } else if ((packet_type & RTE_PTYPE_L4_UDP) && 2398 ol_flags == PKT_TX_UDP_CKSUM) { 2399 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2400 *gen_l4_cksum = 1; 2401 } else { 2402 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2403 /* no checksum for other type */ 2404 *gen_l4_cksum = 0; 2405 } 2406 2407 return 0; 2408 } 2409 2410 /** 2411 * Release already sent buffers to bpool (buffer-pool). 2412 * 2413 * @param ppio 2414 * Pointer to the port structure. 2415 * @param hif 2416 * Pointer to the MUSDK hardware interface. 2417 * @param sq 2418 * Pointer to the shadow queue. 2419 * @param qid 2420 * Queue id number. 2421 * @param force 2422 * Force releasing packets. 2423 */ 2424 static inline void 2425 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2426 unsigned int core_id, struct mrvl_shadow_txq *sq, 2427 int qid, int force) 2428 { 2429 struct buff_release_entry *entry; 2430 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2431 int i; 2432 2433 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2434 2435 sq->num_to_release += nb_done; 2436 2437 if (likely(!force && 2438 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2439 return; 2440 2441 nb_done = sq->num_to_release; 2442 sq->num_to_release = 0; 2443 2444 for (i = 0; i < nb_done; i++) { 2445 entry = &sq->ent[sq->tail + num]; 2446 if (unlikely(!entry->buff.addr)) { 2447 MRVL_LOG(ERR, 2448 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2449 sq->tail, (u64)entry->buff.cookie, 2450 (u64)entry->buff.addr); 2451 skip_bufs = 1; 2452 goto skip; 2453 } 2454 2455 if (unlikely(!entry->bpool)) { 2456 struct rte_mbuf *mbuf; 2457 2458 mbuf = (struct rte_mbuf *) 2459 (cookie_addr_high | entry->buff.cookie); 2460 rte_pktmbuf_free(mbuf); 2461 skip_bufs = 1; 2462 goto skip; 2463 } 2464 2465 mrvl_port_bpool_size 2466 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2467 num++; 2468 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2469 goto skip; 2470 continue; 2471 skip: 2472 if (likely(num)) 2473 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2474 num += skip_bufs; 2475 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2476 sq->size -= num; 2477 num = 0; 2478 skip_bufs = 0; 2479 } 2480 2481 if (likely(num)) { 2482 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2483 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2484 sq->size -= num; 2485 } 2486 } 2487 2488 /** 2489 * DPDK callback for transmit. 2490 * 2491 * @param txq 2492 * Generic pointer transmit queue. 2493 * @param tx_pkts 2494 * Packets to transmit. 2495 * @param nb_pkts 2496 * Number of packets in array. 2497 * 2498 * @return 2499 * Number of packets successfully transmitted. 2500 */ 2501 static uint16_t 2502 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2503 { 2504 struct mrvl_txq *q = txq; 2505 struct mrvl_shadow_txq *sq; 2506 struct pp2_hif *hif; 2507 struct pp2_ppio_desc descs[nb_pkts]; 2508 unsigned int core_id = rte_lcore_id(); 2509 int i, ret, bytes_sent = 0; 2510 uint16_t num, sq_free_size; 2511 uint64_t addr; 2512 2513 hif = mrvl_get_hif(q->priv, core_id); 2514 sq = &q->shadow_txqs[core_id]; 2515 2516 if (unlikely(!q->priv->ppio || !hif)) 2517 return 0; 2518 2519 if (sq->size) 2520 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2521 sq, q->queue_id, 0); 2522 2523 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2524 if (unlikely(nb_pkts > sq_free_size)) { 2525 MRVL_LOG(DEBUG, 2526 "No room in shadow queue for %d packets! %d packets will be sent.", 2527 nb_pkts, sq_free_size); 2528 nb_pkts = sq_free_size; 2529 } 2530 2531 for (i = 0; i < nb_pkts; i++) { 2532 struct rte_mbuf *mbuf = tx_pkts[i]; 2533 int gen_l3_cksum, gen_l4_cksum; 2534 enum pp2_outq_l3_type l3_type; 2535 enum pp2_outq_l4_type l4_type; 2536 2537 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2538 struct rte_mbuf *pref_pkt_hdr; 2539 2540 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2541 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2542 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2543 } 2544 2545 mrvl_fill_shadowq(sq, mbuf); 2546 mrvl_fill_desc(&descs[i], mbuf); 2547 2548 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2549 /* 2550 * in case unsupported ol_flags were passed 2551 * do not update descriptor offload information 2552 */ 2553 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2554 &l3_type, &l4_type, &gen_l3_cksum, 2555 &gen_l4_cksum); 2556 if (unlikely(ret)) 2557 continue; 2558 2559 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2560 mbuf->l2_len, 2561 mbuf->l2_len + mbuf->l3_len, 2562 gen_l3_cksum, gen_l4_cksum); 2563 } 2564 2565 num = nb_pkts; 2566 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2567 /* number of packets that were not sent */ 2568 if (unlikely(num > nb_pkts)) { 2569 for (i = nb_pkts; i < num; i++) { 2570 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2571 MRVL_PP2_TX_SHADOWQ_MASK; 2572 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie; 2573 bytes_sent -= 2574 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2575 } 2576 sq->size -= num - nb_pkts; 2577 } 2578 2579 q->bytes_sent += bytes_sent; 2580 2581 return nb_pkts; 2582 } 2583 2584 /** DPDK callback for S/G transmit. 2585 * 2586 * @param txq 2587 * Generic pointer transmit queue. 2588 * @param tx_pkts 2589 * Packets to transmit. 2590 * @param nb_pkts 2591 * Number of packets in array. 2592 * 2593 * @return 2594 * Number of packets successfully transmitted. 2595 */ 2596 static uint16_t 2597 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 2598 uint16_t nb_pkts) 2599 { 2600 struct mrvl_txq *q = txq; 2601 struct mrvl_shadow_txq *sq; 2602 struct pp2_hif *hif; 2603 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS]; 2604 struct pp2_ppio_sg_pkts pkts; 2605 uint8_t frags[nb_pkts]; 2606 unsigned int core_id = rte_lcore_id(); 2607 int i, j, ret, bytes_sent = 0; 2608 int tail, tail_first; 2609 uint16_t num, sq_free_size; 2610 uint16_t nb_segs, total_descs = 0; 2611 uint64_t addr; 2612 2613 hif = mrvl_get_hif(q->priv, core_id); 2614 sq = &q->shadow_txqs[core_id]; 2615 pkts.frags = frags; 2616 pkts.num = 0; 2617 2618 if (unlikely(!q->priv->ppio || !hif)) 2619 return 0; 2620 2621 if (sq->size) 2622 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2623 sq, q->queue_id, 0); 2624 2625 /* Save shadow queue free size */ 2626 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2627 2628 tail = 0; 2629 for (i = 0; i < nb_pkts; i++) { 2630 struct rte_mbuf *mbuf = tx_pkts[i]; 2631 struct rte_mbuf *seg = NULL; 2632 int gen_l3_cksum, gen_l4_cksum; 2633 enum pp2_outq_l3_type l3_type; 2634 enum pp2_outq_l4_type l4_type; 2635 2636 nb_segs = mbuf->nb_segs; 2637 tail_first = tail; 2638 total_descs += nb_segs; 2639 2640 /* 2641 * Check if total_descs does not exceed 2642 * shadow queue free size 2643 */ 2644 if (unlikely(total_descs > sq_free_size)) { 2645 total_descs -= nb_segs; 2646 RTE_LOG(DEBUG, PMD, 2647 "No room in shadow queue for %d packets! " 2648 "%d packets will be sent.\n", 2649 nb_pkts, i); 2650 break; 2651 } 2652 2653 /* Check if nb_segs does not exceed the max nb of desc per 2654 * fragmented packet 2655 */ 2656 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) { 2657 total_descs -= nb_segs; 2658 RTE_LOG(ERR, PMD, 2659 "Too many segments. Packet won't be sent.\n"); 2660 break; 2661 } 2662 2663 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2664 struct rte_mbuf *pref_pkt_hdr; 2665 2666 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2667 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2668 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2669 } 2670 2671 pkts.frags[pkts.num] = nb_segs; 2672 pkts.num++; 2673 2674 seg = mbuf; 2675 for (j = 0; j < nb_segs - 1; j++) { 2676 /* For the subsequent segments, set shadow queue 2677 * buffer to NULL 2678 */ 2679 mrvl_fill_shadowq(sq, NULL); 2680 mrvl_fill_desc(&descs[tail], seg); 2681 2682 tail++; 2683 seg = seg->next; 2684 } 2685 /* Put first mbuf info in last shadow queue entry */ 2686 mrvl_fill_shadowq(sq, mbuf); 2687 /* Update descriptor with last segment */ 2688 mrvl_fill_desc(&descs[tail++], seg); 2689 2690 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2691 /* In case unsupported ol_flags were passed 2692 * do not update descriptor offload information 2693 */ 2694 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, 2695 &l3_type, &l4_type, &gen_l3_cksum, 2696 &gen_l4_cksum); 2697 if (unlikely(ret)) 2698 continue; 2699 2700 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, 2701 l4_type, mbuf->l2_len, 2702 mbuf->l2_len + mbuf->l3_len, 2703 gen_l3_cksum, gen_l4_cksum); 2704 } 2705 2706 num = total_descs; 2707 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs, 2708 &total_descs, &pkts); 2709 /* number of packets that were not sent */ 2710 if (unlikely(num > total_descs)) { 2711 for (i = total_descs; i < num; i++) { 2712 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2713 MRVL_PP2_TX_SHADOWQ_MASK; 2714 2715 addr = sq->ent[sq->head].buff.cookie; 2716 if (addr) 2717 bytes_sent -= 2718 rte_pktmbuf_pkt_len((struct rte_mbuf *) 2719 (cookie_addr_high | addr)); 2720 } 2721 sq->size -= num - total_descs; 2722 nb_pkts = pkts.num; 2723 } 2724 2725 q->bytes_sent += bytes_sent; 2726 2727 return nb_pkts; 2728 } 2729 2730 /** 2731 * Initialize packet processor. 2732 * 2733 * @return 2734 * 0 on success, negative error value otherwise. 2735 */ 2736 static int 2737 mrvl_init_pp2(void) 2738 { 2739 struct pp2_init_params init_params; 2740 2741 memset(&init_params, 0, sizeof(init_params)); 2742 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 2743 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 2744 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 2745 2746 return pp2_init(&init_params); 2747 } 2748 2749 /** 2750 * Deinitialize packet processor. 2751 * 2752 * @return 2753 * 0 on success, negative error value otherwise. 2754 */ 2755 static void 2756 mrvl_deinit_pp2(void) 2757 { 2758 pp2_deinit(); 2759 } 2760 2761 /** 2762 * Create private device structure. 2763 * 2764 * @param dev_name 2765 * Pointer to the port name passed in the initialization parameters. 2766 * 2767 * @return 2768 * Pointer to the newly allocated private device structure. 2769 */ 2770 static struct mrvl_priv * 2771 mrvl_priv_create(const char *dev_name) 2772 { 2773 struct pp2_bpool_params bpool_params; 2774 char match[MRVL_MATCH_LEN]; 2775 struct mrvl_priv *priv; 2776 int ret, bpool_bit; 2777 2778 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 2779 if (!priv) 2780 return NULL; 2781 2782 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 2783 &priv->pp_id, &priv->ppio_id); 2784 if (ret) 2785 goto out_free_priv; 2786 2787 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 2788 PP2_BPOOL_NUM_POOLS); 2789 if (bpool_bit < 0) 2790 goto out_free_priv; 2791 priv->bpool_bit = bpool_bit; 2792 2793 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 2794 priv->bpool_bit); 2795 memset(&bpool_params, 0, sizeof(bpool_params)); 2796 bpool_params.match = match; 2797 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 2798 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 2799 if (ret) 2800 goto out_clear_bpool_bit; 2801 2802 priv->ppio_params.type = PP2_PPIO_T_NIC; 2803 rte_spinlock_init(&priv->lock); 2804 2805 return priv; 2806 out_clear_bpool_bit: 2807 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 2808 out_free_priv: 2809 rte_free(priv); 2810 return NULL; 2811 } 2812 2813 /** 2814 * Create device representing Ethernet port. 2815 * 2816 * @param name 2817 * Pointer to the port's name. 2818 * 2819 * @return 2820 * 0 on success, negative error value otherwise. 2821 */ 2822 static int 2823 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 2824 { 2825 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 2826 struct rte_eth_dev *eth_dev; 2827 struct mrvl_priv *priv; 2828 struct ifreq req; 2829 2830 eth_dev = rte_eth_dev_allocate(name); 2831 if (!eth_dev) 2832 return -ENOMEM; 2833 2834 priv = mrvl_priv_create(name); 2835 if (!priv) { 2836 ret = -ENOMEM; 2837 goto out_free; 2838 } 2839 eth_dev->data->dev_private = priv; 2840 2841 eth_dev->data->mac_addrs = 2842 rte_zmalloc("mac_addrs", 2843 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 2844 if (!eth_dev->data->mac_addrs) { 2845 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 2846 ret = -ENOMEM; 2847 goto out_free; 2848 } 2849 2850 memset(&req, 0, sizeof(req)); 2851 strcpy(req.ifr_name, name); 2852 ret = ioctl(fd, SIOCGIFHWADDR, &req); 2853 if (ret) 2854 goto out_free; 2855 2856 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 2857 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN); 2858 2859 eth_dev->data->kdrv = RTE_KDRV_NONE; 2860 eth_dev->device = &vdev->device; 2861 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 2862 mrvl_set_tx_function(eth_dev); 2863 eth_dev->dev_ops = &mrvl_ops; 2864 2865 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 2866 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 2867 2868 rte_eth_dev_probing_finish(eth_dev); 2869 return 0; 2870 out_free: 2871 rte_eth_dev_release_port(eth_dev); 2872 2873 return ret; 2874 } 2875 2876 /** 2877 * Callback used by rte_kvargs_process() during argument parsing. 2878 * 2879 * @param key 2880 * Pointer to the parsed key (unused). 2881 * @param value 2882 * Pointer to the parsed value. 2883 * @param extra_args 2884 * Pointer to the extra arguments which contains address of the 2885 * table of pointers to parsed interface names. 2886 * 2887 * @return 2888 * Always 0. 2889 */ 2890 static int 2891 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 2892 void *extra_args) 2893 { 2894 struct mrvl_ifnames *ifnames = extra_args; 2895 2896 ifnames->names[ifnames->idx++] = value; 2897 2898 return 0; 2899 } 2900 2901 /** 2902 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 2903 */ 2904 static void 2905 mrvl_deinit_hifs(void) 2906 { 2907 int i; 2908 2909 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 2910 if (hifs[i]) 2911 pp2_hif_deinit(hifs[i]); 2912 } 2913 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 2914 memset(hifs, 0, sizeof(hifs)); 2915 } 2916 2917 /** 2918 * DPDK callback to register the virtual device. 2919 * 2920 * @param vdev 2921 * Pointer to the virtual device. 2922 * 2923 * @return 2924 * 0 on success, negative error value otherwise. 2925 */ 2926 static int 2927 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 2928 { 2929 struct rte_kvargs *kvlist; 2930 struct mrvl_ifnames ifnames; 2931 int ret = -EINVAL; 2932 uint32_t i, ifnum, cfgnum; 2933 const char *params; 2934 2935 params = rte_vdev_device_args(vdev); 2936 if (!params) 2937 return -EINVAL; 2938 2939 kvlist = rte_kvargs_parse(params, valid_args); 2940 if (!kvlist) 2941 return -EINVAL; 2942 2943 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 2944 if (ifnum > RTE_DIM(ifnames.names)) 2945 goto out_free_kvlist; 2946 2947 ifnames.idx = 0; 2948 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 2949 mrvl_get_ifnames, &ifnames); 2950 2951 2952 /* 2953 * The below system initialization should be done only once, 2954 * on the first provided configuration file 2955 */ 2956 if (!mrvl_qos_cfg) { 2957 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 2958 MRVL_LOG(INFO, "Parsing config file!"); 2959 if (cfgnum > 1) { 2960 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 2961 goto out_free_kvlist; 2962 } else if (cfgnum == 1) { 2963 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 2964 mrvl_get_qoscfg, &mrvl_qos_cfg); 2965 } 2966 } 2967 2968 if (mrvl_dev_num) 2969 goto init_devices; 2970 2971 MRVL_LOG(INFO, "Perform MUSDK initializations"); 2972 2973 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 2974 if (ret) 2975 goto out_free_kvlist; 2976 2977 ret = mrvl_init_pp2(); 2978 if (ret) { 2979 MRVL_LOG(ERR, "Failed to init PP!"); 2980 rte_mvep_deinit(MVEP_MOD_T_PP2); 2981 goto out_free_kvlist; 2982 } 2983 2984 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 2985 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 2986 2987 mrvl_lcore_first = RTE_MAX_LCORE; 2988 mrvl_lcore_last = 0; 2989 2990 init_devices: 2991 for (i = 0; i < ifnum; i++) { 2992 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 2993 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 2994 if (ret) 2995 goto out_cleanup; 2996 mrvl_dev_num++; 2997 } 2998 2999 rte_kvargs_free(kvlist); 3000 3001 return 0; 3002 out_cleanup: 3003 rte_pmd_mrvl_remove(vdev); 3004 3005 out_free_kvlist: 3006 rte_kvargs_free(kvlist); 3007 3008 return ret; 3009 } 3010 3011 /** 3012 * DPDK callback to remove virtual device. 3013 * 3014 * @param vdev 3015 * Pointer to the removed virtual device. 3016 * 3017 * @return 3018 * 0 on success, negative error value otherwise. 3019 */ 3020 static int 3021 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 3022 { 3023 uint16_t port_id; 3024 3025 RTE_ETH_FOREACH_DEV(port_id) { 3026 if (rte_eth_devices[port_id].device != &vdev->device) 3027 continue; 3028 rte_eth_dev_close(port_id); 3029 } 3030 3031 return 0; 3032 } 3033 3034 static struct rte_vdev_driver pmd_mrvl_drv = { 3035 .probe = rte_pmd_mrvl_probe, 3036 .remove = rte_pmd_mrvl_remove, 3037 }; 3038 3039 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 3040 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 3041 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE); 3042