1d0b3ef1aSTal Shnaiderman /* SPDX-License-Identifier: BSD-3-Clause 2d0b3ef1aSTal Shnaiderman * Copyright 2020 Mellanox Technologies, Ltd 3d0b3ef1aSTal Shnaiderman */ 4d0b3ef1aSTal Shnaiderman 5d0b3ef1aSTal Shnaiderman #ifndef RTE_PMD_MLX5_OS_H_ 6d0b3ef1aSTal Shnaiderman #define RTE_PMD_MLX5_OS_H_ 7d0b3ef1aSTal Shnaiderman 8d0b3ef1aSTal Shnaiderman #include "mlx5_win_ext.h" 9d0b3ef1aSTal Shnaiderman 10d0b3ef1aSTal Shnaiderman enum { 11d0b3ef1aSTal Shnaiderman MLX5_FS_NAME_MAX = MLX5_DEVX_DEVICE_NAME_SIZE + 1, 12d0b3ef1aSTal Shnaiderman MLX5_FS_PATH_MAX = MLX5_DEVX_DEVICE_PNP_SIZE + 1 13d0b3ef1aSTal Shnaiderman }; 14d0b3ef1aSTal Shnaiderman 15d0b3ef1aSTal Shnaiderman #define PCI_DRV_FLAGS 0 16d0b3ef1aSTal Shnaiderman 1728743807STal Shnaiderman #define MLX5_NAMESIZE MLX5_FS_NAME_MAX 1828743807STal Shnaiderman 19d47fe9daSTal Shnaiderman enum mlx5_sw_parsing_offloads { 20d47fe9daSTal Shnaiderman MLX5_SW_PARSING_CAP = 1 << 0, 21d47fe9daSTal Shnaiderman MLX5_SW_PARSING_CSUM_CAP = 1 << 1, 22d47fe9daSTal Shnaiderman MLX5_SW_PARSING_TSO_CAP = 1 << 2, 23d47fe9daSTal Shnaiderman }; 24d47fe9daSTal Shnaiderman 25*c1a320bfSTal Shnaiderman enum mlx5_tunnel_offloads { 26*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 1 << 0, 27*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_GRE_CAP = 1 << 1, 28*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2, 29*c1a320bfSTal Shnaiderman }; 30*c1a320bfSTal Shnaiderman 31d0b3ef1aSTal Shnaiderman #endif /* RTE_PMD_MLX5_OS_H_ */ 32