1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <errno.h> 6 #include <stdalign.h> 7 #include <stddef.h> 8 #include <stdint.h> 9 #include <stdlib.h> 10 11 #include <rte_windows.h> 12 #include <ethdev_pci.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_devx_cmds.h> 16 #include <mlx5_common.h> 17 #include <mlx5_common_mp.h> 18 #include <mlx5_common_mr.h> 19 #include <mlx5_malloc.h> 20 21 #include "mlx5_defs.h" 22 #include "mlx5.h" 23 #include "mlx5_common_os.h" 24 #include "mlx5_utils.h" 25 #include "mlx5_rxtx.h" 26 #include "mlx5_autoconf.h" 27 #include "mlx5_mr.h" 28 #include "mlx5_flow.h" 29 #include "mlx5_devx.h" 30 31 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 32 33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 34 35 /* Spinlock for mlx5_shared_data allocation. */ 36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 37 38 /** 39 * Initialize shared data between primary and secondary process. 40 * 41 * A memzone is reserved by primary process and secondary processes attach to 42 * the memzone. 43 * 44 * @return 45 * 0 on success, a negative errno value otherwise and rte_errno is set. 46 */ 47 static int 48 mlx5_init_shared_data(void) 49 { 50 const struct rte_memzone *mz; 51 int ret = 0; 52 53 rte_spinlock_lock(&mlx5_shared_data_lock); 54 if (mlx5_shared_data == NULL) { 55 /* Allocate shared memory. */ 56 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 57 sizeof(*mlx5_shared_data), 58 SOCKET_ID_ANY, 0); 59 if (mz == NULL) { 60 DRV_LOG(ERR, 61 "Cannot allocate mlx5 shared data"); 62 ret = -rte_errno; 63 goto error; 64 } 65 mlx5_shared_data = mz->addr; 66 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 67 rte_spinlock_init(&mlx5_shared_data->lock); 68 } 69 error: 70 rte_spinlock_unlock(&mlx5_shared_data_lock); 71 return ret; 72 } 73 74 /** 75 * PMD global initialization. 76 * 77 * Independent from individual device, this function initializes global 78 * per-PMD data structures distinguishing primary and secondary processes. 79 * Hence, each initialization is called once per a process. 80 * 81 * @return 82 * 0 on success, a negative errno value otherwise and rte_errno is set. 83 */ 84 static int 85 mlx5_init_once(void) 86 { 87 if (mlx5_init_shared_data()) 88 return -rte_errno; 89 return 0; 90 } 91 92 /** 93 * Get mlx5 device attributes. 94 * 95 * @param ctx 96 * Pointer to device context. 97 * 98 * @param device_attr 99 * Pointer to mlx5 device attributes. 100 * 101 * @return 102 * 0 on success, non zero error number otherwise 103 */ 104 int 105 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 106 { 107 struct mlx5_context *mlx5_ctx; 108 struct mlx5_hca_attr hca_attr; 109 void *pv_iseg = NULL; 110 u32 cb_iseg = 0; 111 int err = 0; 112 113 if (!ctx) 114 return -EINVAL; 115 mlx5_ctx = (struct mlx5_context *)ctx; 116 memset(device_attr, 0, sizeof(*device_attr)); 117 err = mlx5_devx_cmd_query_hca_attr(mlx5_ctx, &hca_attr); 118 if (err) { 119 DRV_LOG(ERR, "Failed to get device hca_cap"); 120 return err; 121 } 122 device_attr->max_cq = 1 << hca_attr.log_max_cq; 123 device_attr->max_qp = 1 << hca_attr.log_max_qp; 124 device_attr->max_qp_wr = 1 << hca_attr.log_max_qp_sz; 125 device_attr->max_cqe = 1 << hca_attr.log_max_cq_sz; 126 device_attr->max_mr = 1 << hca_attr.log_max_mrw_sz; 127 device_attr->max_pd = 1 << hca_attr.log_max_pd; 128 device_attr->max_srq = 1 << hca_attr.log_max_srq; 129 device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz; 130 if (hca_attr.rss_ind_tbl_cap) { 131 device_attr->max_rwq_indirection_table_size = 132 1 << hca_attr.rss_ind_tbl_cap; 133 } 134 pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg); 135 if (pv_iseg == NULL) { 136 DRV_LOG(ERR, "Failed to get device hca_iseg"); 137 return errno; 138 } 139 if (!err) { 140 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x", 141 MLX5_GET(initial_seg, pv_iseg, fw_rev_major), 142 MLX5_GET(initial_seg, pv_iseg, fw_rev_minor), 143 MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor)); 144 } 145 return err; 146 } 147 148 /** 149 * Initialize DR related data within private structure. 150 * Routine checks the reference counter and does actual 151 * resources creation/initialization only if counter is zero. 152 * 153 * @param[in] priv 154 * Pointer to the private device data structure. 155 * 156 * @return 157 * Zero on success, positive error code otherwise. 158 */ 159 static int 160 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 161 { 162 struct mlx5_dev_ctx_shared *sh = priv->sh; 163 int err = 0; 164 165 if (!sh->flow_tbls) 166 err = mlx5_alloc_table_hash_list(priv); 167 else 168 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse", 169 (void *)sh->flow_tbls); 170 return err; 171 } 172 /** 173 * Destroy DR related data within private structure. 174 * 175 * @param[in] priv 176 * Pointer to the private device data structure. 177 */ 178 void 179 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 180 { 181 mlx5_free_table_hash_list(priv); 182 } 183 184 /** 185 * Set the completion channel file descriptor interrupt as non-blocking. 186 * Currently it has no support under Windows. 187 * 188 * @param[in] rxq_obj 189 * Pointer to RQ channel object, which includes the channel fd 190 * 191 * @param[out] fd 192 * The file descriptor (representing the intetrrupt) used in this channel. 193 * 194 * @return 195 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 196 */ 197 int 198 mlx5_os_set_nonblock_channel_fd(int fd) 199 { 200 (void)fd; 201 DRV_LOG(WARNING, "%s: is not supported", __func__); 202 return -ENOTSUP; 203 } 204 205 /** 206 * Function API open device under Windows 207 * 208 * This function calls the Windows glue APIs to open a device. 209 * 210 * @param[in] spawn 211 * Pointer to the device attributes (name, port, etc). 212 * @param[out] config 213 * Pointer to device configuration structure. 214 * @param[out] sh 215 * Pointer to shared context structure. 216 * 217 * @return 218 * 0 on success, a positive error value otherwise. 219 */ 220 int 221 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 222 const struct mlx5_dev_config *config, 223 struct mlx5_dev_ctx_shared *sh) 224 { 225 RTE_SET_USED(config); 226 int err = 0; 227 struct mlx5_context *mlx5_ctx; 228 229 pthread_mutex_init(&sh->txpp.mutex, NULL); 230 /* Set numa node from pci probe */ 231 sh->numa_node = spawn->pci_dev->device.numa_node; 232 233 /* Try to open device with DevX */ 234 rte_errno = 0; 235 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 236 if (!sh->ctx) { 237 DRV_LOG(ERR, "open_device failed"); 238 err = errno; 239 return err; 240 } 241 sh->devx = 1; 242 mlx5_ctx = (struct mlx5_context *)sh->ctx; 243 err = mlx5_glue->query_device(spawn->phys_dev, &mlx5_ctx->mlx5_dev); 244 if (err) 245 DRV_LOG(ERR, "Failed to query device context fields."); 246 return err; 247 } 248 249 /** 250 * DV flow counter mode detect and config. 251 * 252 * @param dev 253 * Pointer to rte_eth_dev structure. 254 * 255 */ 256 static void 257 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 258 { 259 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 260 struct mlx5_priv *priv = dev->data->dev_private; 261 struct mlx5_dev_ctx_shared *sh = priv->sh; 262 bool fallback; 263 264 #ifndef HAVE_IBV_DEVX_ASYNC 265 fallback = true; 266 #else 267 fallback = false; 268 if (!priv->config.devx || !priv->config.dv_flow_en || 269 !priv->config.hca_attr.flow_counters_dump || 270 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 271 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 272 fallback = true; 273 #endif 274 if (fallback) 275 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 276 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 277 priv->config.hca_attr.flow_counters_dump, 278 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 279 /* Initialize fallback mode only on the port initializes sh. */ 280 if (sh->refcnt == 1) 281 sh->cmng.counter_fallback = fallback; 282 else if (fallback != sh->cmng.counter_fallback) 283 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 284 "with others:%d.", PORT_ID(priv), fallback); 285 #endif 286 } 287 288 /** 289 * Spawn an Ethernet device from Verbs information. 290 * 291 * @param dpdk_dev 292 * Backing DPDK device. 293 * @param spawn 294 * Verbs device parameters (name, port, switch_info) to spawn. 295 * @param config 296 * Device configuration parameters. 297 * 298 * @return 299 * A valid Ethernet device object on success, NULL otherwise and rte_errno 300 * is set. The following errors are defined: 301 * 302 * EEXIST: device is already spawned 303 */ 304 static struct rte_eth_dev * 305 mlx5_dev_spawn(struct rte_device *dpdk_dev, 306 struct mlx5_dev_spawn_data *spawn, 307 struct mlx5_dev_config *config) 308 { 309 const struct mlx5_switch_info *switch_info = &spawn->info; 310 struct mlx5_dev_ctx_shared *sh = NULL; 311 struct mlx5_dev_attr device_attr; 312 struct rte_eth_dev *eth_dev = NULL; 313 struct mlx5_priv *priv = NULL; 314 int err = 0; 315 unsigned int cqe_comp; 316 struct rte_ether_addr mac; 317 char name[RTE_ETH_NAME_MAX_LEN]; 318 int own_domain_id = 0; 319 uint16_t port_id; 320 321 /* Build device name. */ 322 strlcpy(name, dpdk_dev->name, sizeof(name)); 323 /* check if the device is already spawned */ 324 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 325 rte_errno = EEXIST; 326 return NULL; 327 } 328 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 329 /* 330 * Some parameters are needed in advance to create device context. We 331 * process the devargs here to get ones, and later process devargs 332 * again to override some hardware settings. 333 */ 334 err = mlx5_args(config, dpdk_dev->devargs); 335 if (err) { 336 err = rte_errno; 337 DRV_LOG(ERR, "failed to process device arguments: %s", 338 strerror(rte_errno)); 339 goto error; 340 } 341 mlx5_malloc_mem_select(config->sys_mem_en); 342 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 343 if (!sh) 344 return NULL; 345 config->devx = sh->devx; 346 /* Initialize the shutdown event in mlx5_dev_spawn to 347 * support mlx5_is_removed for Windows. 348 */ 349 err = mlx5_glue->devx_init_showdown_event(sh->ctx); 350 if (err) { 351 DRV_LOG(ERR, "failed to init showdown event: %s", 352 strerror(errno)); 353 goto error; 354 } 355 DRV_LOG(DEBUG, "MPW isn't supported"); 356 mlx5_os_get_dev_attr(sh->ctx, &device_attr); 357 config->swp = 0; 358 config->ind_table_max_size = 359 sh->device_attr.max_rwq_indirection_table_size; 360 if (RTE_CACHE_LINE_SIZE == 128 && 361 !(device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 362 cqe_comp = 0; 363 else 364 cqe_comp = 1; 365 config->cqe_comp = cqe_comp; 366 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 367 config->tunnel_en = 0; 368 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported"); 369 config->mpls_en = 0; 370 /* Allocate private eth device data. */ 371 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 372 sizeof(*priv), 373 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 374 if (priv == NULL) { 375 DRV_LOG(ERR, "priv allocation failure"); 376 err = ENOMEM; 377 goto error; 378 } 379 priv->sh = sh; 380 priv->dev_port = spawn->phys_port; 381 priv->pci_dev = spawn->pci_dev; 382 priv->mtu = RTE_ETHER_MTU; 383 priv->mp_id.port_id = port_id; 384 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 385 priv->representor = !!switch_info->representor; 386 priv->master = !!switch_info->master; 387 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 388 priv->vport_meta_tag = 0; 389 priv->vport_meta_mask = 0; 390 priv->pf_bond = spawn->pf_bond; 391 priv->vport_id = -1; 392 /* representor_id field keeps the unmodified VF index. */ 393 priv->representor_id = -1; 394 /* 395 * Look for sibling devices in order to reuse their switch domain 396 * if any, otherwise allocate one. 397 */ 398 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 399 const struct mlx5_priv *opriv = 400 rte_eth_devices[port_id].data->dev_private; 401 402 if (!opriv || 403 opriv->sh != priv->sh || 404 opriv->domain_id == 405 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 406 continue; 407 priv->domain_id = opriv->domain_id; 408 break; 409 } 410 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 411 err = rte_eth_switch_domain_alloc(&priv->domain_id); 412 if (err) { 413 err = rte_errno; 414 DRV_LOG(ERR, "unable to allocate switch domain: %s", 415 strerror(rte_errno)); 416 goto error; 417 } 418 own_domain_id = 1; 419 } 420 /* Override some values set by hardware configuration. */ 421 mlx5_args(config, dpdk_dev->devargs); 422 err = mlx5_dev_check_sibling_config(priv, config); 423 if (err) 424 goto error; 425 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 426 IBV_DEVICE_RAW_IP_CSUM); 427 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 428 (config->hw_csum ? "" : "not ")); 429 DRV_LOG(DEBUG, "counters are not supported"); 430 config->ind_table_max_size = 431 sh->device_attr.max_rwq_indirection_table_size; 432 /* 433 * Remove this check once DPDK supports larger/variable 434 * indirection tables. 435 */ 436 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 437 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 438 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 439 config->ind_table_max_size); 440 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 441 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 442 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 443 (config->hw_vlan_strip ? "" : "not ")); 444 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 445 IBV_RAW_PACKET_CAP_SCATTER_FCS); 446 if (config->hw_padding) { 447 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 448 config->hw_padding = 0; 449 } 450 config->tso = (sh->device_attr.max_tso > 0 && 451 (sh->device_attr.tso_supported_qpts & 452 (1 << IBV_QPT_RAW_PACKET))); 453 if (config->tso) 454 config->tso_max_payload_sz = sh->device_attr.max_tso; 455 DRV_LOG(DEBUG, "%sMPS is %s.", 456 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 457 config->mps == MLX5_MPW ? "legacy " : "", 458 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 459 if (config->cqe_comp && !cqe_comp) { 460 DRV_LOG(WARNING, "Rx CQE compression isn't supported."); 461 config->cqe_comp = 0; 462 } 463 if (config->devx) { 464 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 465 if (err) { 466 err = -err; 467 goto error; 468 } 469 /* Check relax ordering support. */ 470 sh->cmng.relaxed_ordering_read = 0; 471 sh->cmng.relaxed_ordering_write = 0; 472 if (!haswell_broadwell_cpu) { 473 sh->cmng.relaxed_ordering_write = 474 config->hca_attr.relaxed_ordering_write; 475 sh->cmng.relaxed_ordering_read = 476 config->hca_attr.relaxed_ordering_read; 477 } 478 } 479 if (config->devx) { 480 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 481 482 err = config->hca_attr.access_register_user ? 483 mlx5_devx_cmd_register_read 484 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 485 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 486 if (!err) { 487 uint32_t ts_mode; 488 489 /* MTUTC register is read successfully. */ 490 ts_mode = MLX5_GET(register_mtutc, reg, 491 time_stamp_mode); 492 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 493 config->rt_timestamp = 1; 494 } else { 495 /* Kernel does not support register reading. */ 496 if (config->hca_attr.dev_freq_khz == 497 (NS_PER_S / MS_PER_S)) 498 config->rt_timestamp = 1; 499 } 500 sh->rq_ts_format = config->hca_attr.rq_ts_format; 501 sh->sq_ts_format = config->hca_attr.sq_ts_format; 502 sh->qp_ts_format = config->hca_attr.qp_ts_format; 503 } 504 if (config->mprq.enabled) { 505 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 506 config->mprq.enabled = 0; 507 } 508 if (config->max_dump_files_num == 0) 509 config->max_dump_files_num = 128; 510 eth_dev = rte_eth_dev_allocate(name); 511 if (eth_dev == NULL) { 512 DRV_LOG(ERR, "can not allocate rte ethdev"); 513 err = ENOMEM; 514 goto error; 515 } 516 if (priv->representor) { 517 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 518 eth_dev->data->representor_id = priv->representor_id; 519 } 520 /* 521 * Store associated network device interface index. This index 522 * is permanent throughout the lifetime of device. So, we may store 523 * the ifindex here and use the cached value further. 524 */ 525 MLX5_ASSERT(spawn->ifindex); 526 priv->if_index = spawn->ifindex; 527 eth_dev->data->dev_private = priv; 528 priv->dev_data = eth_dev->data; 529 eth_dev->data->mac_addrs = priv->mac; 530 eth_dev->device = dpdk_dev; 531 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 532 /* Configure the first MAC address by default. */ 533 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 534 DRV_LOG(ERR, 535 "port %u cannot get MAC address, is mlx5_en" 536 " loaded? (errno: %s).", 537 eth_dev->data->port_id, strerror(rte_errno)); 538 err = ENODEV; 539 goto error; 540 } 541 DRV_LOG(INFO, 542 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 543 eth_dev->data->port_id, 544 mac.addr_bytes[0], mac.addr_bytes[1], 545 mac.addr_bytes[2], mac.addr_bytes[3], 546 mac.addr_bytes[4], mac.addr_bytes[5]); 547 #ifdef RTE_LIBRTE_MLX5_DEBUG 548 { 549 char ifname[MLX5_NAMESIZE]; 550 551 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 552 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 553 eth_dev->data->port_id, ifname); 554 else 555 DRV_LOG(DEBUG, "port %u ifname is unknown.", 556 eth_dev->data->port_id); 557 } 558 #endif 559 /* Get actual MTU if possible. */ 560 err = mlx5_get_mtu(eth_dev, &priv->mtu); 561 if (err) { 562 err = rte_errno; 563 goto error; 564 } 565 DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id, 566 priv->mtu); 567 /* Initialize burst functions to prevent crashes before link-up. */ 568 eth_dev->rx_pkt_burst = removed_rx_burst; 569 eth_dev->tx_pkt_burst = removed_tx_burst; 570 eth_dev->dev_ops = &mlx5_dev_ops; 571 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 572 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 573 eth_dev->rx_queue_count = mlx5_rx_queue_count; 574 /* Register MAC address. */ 575 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 576 priv->flows = 0; 577 priv->ctrl_flows = 0; 578 TAILQ_INIT(&priv->flow_meters); 579 TAILQ_INIT(&priv->flow_meter_profiles); 580 /* Bring Ethernet device up. */ 581 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.", 582 eth_dev->data->port_id); 583 /* nl calls are unsupported - set to -1 not to fail on release */ 584 priv->nl_socket_rdma = -1; 585 priv->nl_socket_route = -1; 586 mlx5_set_link_up(eth_dev); 587 /* 588 * Even though the interrupt handler is not installed yet, 589 * interrupts will still trigger on the async_fd from 590 * Verbs context returned by ibv_open_device(). 591 */ 592 mlx5_link_update(eth_dev, 0); 593 config->dv_esw_en = 0; 594 /* Detect minimal data bytes to inline. */ 595 mlx5_set_min_inline(spawn, config); 596 /* Store device configuration on private structure. */ 597 priv->config = *config; 598 /* Create context for virtual machine VLAN workaround. */ 599 priv->vmwa_context = NULL; 600 if (config->dv_flow_en) { 601 err = mlx5_alloc_shared_dr(priv); 602 if (err) 603 goto error; 604 } 605 /* No supported flow priority number detection. */ 606 priv->config.flow_prio = -1; 607 if (!priv->config.dv_esw_en && 608 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 609 DRV_LOG(WARNING, "metadata mode %u is not supported " 610 "(no E-Switch)", priv->config.dv_xmeta_en); 611 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 612 } 613 mlx5_set_metadata_mask(eth_dev); 614 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 615 !priv->sh->dv_regc0_mask) { 616 DRV_LOG(ERR, "metadata mode %u is not supported " 617 "(no metadata reg_c[0] is available).", 618 priv->config.dv_xmeta_en); 619 err = ENOTSUP; 620 goto error; 621 } 622 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 623 mlx5_hrxq_create_cb, 624 mlx5_hrxq_match_cb, 625 mlx5_hrxq_remove_cb); 626 /* Query availability of metadata reg_c's. */ 627 err = mlx5_flow_discover_mreg_c(eth_dev); 628 if (err < 0) { 629 err = -err; 630 goto error; 631 } 632 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 633 DRV_LOG(DEBUG, 634 "port %u extensive metadata register is not supported.", 635 eth_dev->data->port_id); 636 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 637 DRV_LOG(ERR, "metadata mode %u is not supported " 638 "(no metadata registers available).", 639 priv->config.dv_xmeta_en); 640 err = ENOTSUP; 641 goto error; 642 } 643 } 644 if (config->devx && config->dv_flow_en) { 645 priv->obj_ops = devx_obj_ops; 646 } else { 647 DRV_LOG(ERR, "Flow mode %u is not supported " 648 "(Windows flow must be DevX with DV flow enabled).", 649 priv->config.dv_flow_en); 650 err = ENOTSUP; 651 goto error; 652 } 653 mlx5_flow_counter_mode_config(eth_dev); 654 return eth_dev; 655 error: 656 if (priv) { 657 if (own_domain_id) 658 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 659 mlx5_free(priv); 660 if (eth_dev != NULL) 661 eth_dev->data->dev_private = NULL; 662 } 663 if (eth_dev != NULL) { 664 /* mac_addrs must not be freed alone because part of 665 * dev_private 666 **/ 667 eth_dev->data->mac_addrs = NULL; 668 rte_eth_dev_release_port(eth_dev); 669 } 670 if (sh) 671 mlx5_free_shared_dev_ctx(sh); 672 MLX5_ASSERT(err > 0); 673 rte_errno = err; 674 return NULL; 675 } 676 677 /** 678 * This function should share events between multiple ports of single IB 679 * device. Currently it has no support under Windows. 680 * 681 * @param sh 682 * Pointer to mlx5_dev_ctx_shared object. 683 */ 684 void 685 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 686 { 687 (void)sh; 688 DRV_LOG(WARNING, "%s: is not supported", __func__); 689 } 690 691 /** 692 * This function should share events between multiple ports of single IB 693 * device. Currently it has no support under Windows. 694 * 695 * @param dev 696 * Pointer to mlx5_dev_ctx_shared object. 697 */ 698 void 699 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 700 { 701 (void)sh; 702 DRV_LOG(WARNING, "%s: is not supported", __func__); 703 } 704 705 /** 706 * Read statistics by a named counter. 707 * 708 * @param[in] priv 709 * Pointer to the private device data structure. 710 * @param[in] ctr_name 711 * Pointer to the name of the statistic counter to read 712 * @param[out] stat 713 * Pointer to read statistic value. 714 * @return 715 * 0 on success and stat is valud, 1 if failed to read the value 716 * rte_errno is set. 717 * 718 */ 719 int 720 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 721 uint64_t *stat) 722 { 723 RTE_SET_USED(priv); 724 RTE_SET_USED(ctr_name); 725 RTE_SET_USED(stat); 726 DRV_LOG(WARNING, "%s: is not supported", __func__); 727 return -ENOTSUP; 728 } 729 730 /** 731 * Flush device MAC addresses 732 * Currently it has no support under Windows. 733 * 734 * @param dev 735 * Pointer to Ethernet device structure. 736 * 737 */ 738 void 739 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 740 { 741 (void)dev; 742 DRV_LOG(WARNING, "%s: is not supported", __func__); 743 } 744 745 /** 746 * Remove a MAC address from device 747 * Currently it has no support under Windows. 748 * 749 * @param dev 750 * Pointer to Ethernet device structure. 751 * @param index 752 * MAC address index. 753 */ 754 void 755 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 756 { 757 (void)dev; 758 (void)(index); 759 DRV_LOG(WARNING, "%s: is not supported", __func__); 760 } 761 762 /** 763 * Adds a MAC address to the device 764 * Currently it has no support under Windows. 765 * 766 * @param dev 767 * Pointer to Ethernet device structure. 768 * @param mac_addr 769 * MAC address to register. 770 * @param index 771 * MAC address index. 772 * 773 * @return 774 * 0 on success, a negative errno value otherwise 775 */ 776 int 777 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 778 uint32_t index) 779 { 780 (void)index; 781 struct rte_ether_addr lmac; 782 783 if (mlx5_get_mac(dev, &lmac.addr_bytes)) { 784 DRV_LOG(ERR, 785 "port %u cannot get MAC address, is mlx5_en" 786 " loaded? (errno: %s)", 787 dev->data->port_id, strerror(rte_errno)); 788 return rte_errno; 789 } 790 if (!rte_is_same_ether_addr(&lmac, mac)) { 791 DRV_LOG(ERR, 792 "adding new mac address to device is unsupported"); 793 return -ENOTSUP; 794 } 795 return 0; 796 } 797 798 /** 799 * Modify a VF MAC address 800 * Currently it has no support under Windows. 801 * 802 * @param priv 803 * Pointer to device private data. 804 * @param mac_addr 805 * MAC address to modify into. 806 * @param iface_idx 807 * Net device interface index 808 * @param vf_index 809 * VF index 810 * 811 * @return 812 * 0 on success, a negative errno value otherwise 813 */ 814 int 815 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 816 unsigned int iface_idx, 817 struct rte_ether_addr *mac_addr, 818 int vf_index) 819 { 820 (void)priv; 821 (void)iface_idx; 822 (void)mac_addr; 823 (void)vf_index; 824 DRV_LOG(WARNING, "%s: is not supported", __func__); 825 return -ENOTSUP; 826 } 827 828 /** 829 * Set device promiscuous mode 830 * Currently it has no support under Windows. 831 * 832 * @param dev 833 * Pointer to Ethernet device structure. 834 * @param enable 835 * 0 - promiscuous is disabled, otherwise - enabled 836 * 837 * @return 838 * 0 on success, a negative error value otherwise 839 */ 840 int 841 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 842 { 843 (void)dev; 844 (void)enable; 845 DRV_LOG(WARNING, "%s: is not supported", __func__); 846 return -ENOTSUP; 847 } 848 849 /** 850 * Set device allmulti mode 851 * 852 * @param dev 853 * Pointer to Ethernet device structure. 854 * @param enable 855 * 0 - all multicase is disabled, otherwise - enabled 856 * 857 * @return 858 * 0 on success, a negative error value otherwise 859 */ 860 int 861 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 862 { 863 (void)dev; 864 (void)enable; 865 DRV_LOG(WARNING, "%s: is not supported", __func__); 866 return -ENOTSUP; 867 } 868 869 /** 870 * Detect if a devx_device_bdf object has identical DBDF values to the 871 * rte_pci_addr found in bus/pci probing 872 * 873 * @param[in] devx_bdf 874 * Pointer to the devx_device_bdf structure. 875 * @param[in] addr 876 * Pointer to the rte_pci_addr structure. 877 * 878 * @return 879 * 1 on Device match, 0 on mismatch. 880 */ 881 static int 882 mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf, 883 struct rte_pci_addr *addr) 884 { 885 if (addr->domain != (devx_bdf->bus_id >> 8) || 886 addr->bus != (devx_bdf->bus_id & 0xff) || 887 addr->devid != devx_bdf->dev_id || 888 addr->function != devx_bdf->fnc_id) { 889 return 0; 890 } 891 return 1; 892 } 893 894 /** 895 * Detect if a devx_device_bdf object matches the rte_pci_addr 896 * found in bus/pci probing 897 * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF. 898 * 899 * @param[in] devx_bdf 900 * Pointer to the devx_device_bdf structure. 901 * @param[in] addr 902 * Pointer to the rte_pci_addr structure. 903 * 904 * @return 905 * 1 on Device match, 0 on mismatch, rte_errno code on failure. 906 */ 907 static int 908 mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, 909 struct rte_pci_addr *addr) 910 { 911 int err; 912 struct devx_device mlx5_dev; 913 914 if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr)) 915 return 1; 916 /** 917 * Didn't match on Native/PF BDF, could still 918 * Match a VF BDF, check it next 919 */ 920 err = mlx5_glue->query_device(devx_bdf, &mlx5_dev); 921 if (err) { 922 DRV_LOG(ERR, "query_device failed"); 923 rte_errno = err; 924 return rte_errno; 925 } 926 if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr)) 927 return 1; 928 return 0; 929 } 930 931 /** 932 * DPDK callback to register a PCI device. 933 * 934 * This function spawns Ethernet devices out of a given PCI device. 935 * 936 * @param[in] pci_drv 937 * PCI driver structure (mlx5_driver). 938 * @param[in] pci_dev 939 * PCI device information. 940 * 941 * @return 942 * 0 on success, a negative errno value otherwise and rte_errno is set. 943 */ 944 int 945 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 946 struct rte_pci_device *pci_dev) 947 { 948 struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs; 949 /* 950 * Number of found IB Devices matching with requested PCI BDF. 951 * nd != 1 means there are multiple IB devices over the same 952 * PCI device and we have representors and master. 953 */ 954 unsigned int nd = 0; 955 /* 956 * Number of found IB device Ports. nd = 1 and np = 1..n means 957 * we have the single multiport IB device, and there may be 958 * representors attached to some of found ports. 959 * Currently not supported. 960 * unsigned int np = 0; 961 */ 962 963 /* 964 * Number of DPDK ethernet devices to Spawn - either over 965 * multiple IB devices or multiple ports of single IB device. 966 * Actually this is the number of iterations to spawn. 967 */ 968 unsigned int ns = 0; 969 /* 970 * Bonding device 971 * < 0 - no bonding device (single one) 972 * >= 0 - bonding device (value is slave PF index) 973 */ 974 int bd = -1; 975 struct mlx5_dev_spawn_data *list = NULL; 976 struct mlx5_dev_config dev_config; 977 unsigned int dev_config_vf; 978 int ret, err; 979 uint32_t restore; 980 981 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 982 DRV_LOG(ERR, "Secondary process is not supported on Windows."); 983 return -ENOTSUP; 984 } 985 ret = mlx5_init_once(); 986 if (ret) { 987 DRV_LOG(ERR, "unable to init PMD global data: %s", 988 strerror(rte_errno)); 989 return -rte_errno; 990 } 991 errno = 0; 992 devx_bdf_devs = mlx5_glue->get_device_list(&ret); 993 orig_devx_bdf_devs = devx_bdf_devs; 994 if (!devx_bdf_devs) { 995 rte_errno = errno ? errno : ENOSYS; 996 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 997 return -rte_errno; 998 } 999 /* 1000 * First scan the list of all Infiniband devices to find 1001 * matching ones, gathering into the list. 1002 */ 1003 struct devx_device_bdf *devx_bdf_match[ret + 1]; 1004 1005 while (ret-- > 0) { 1006 err = mlx5_match_devx_devices_to_addr(devx_bdf_devs, 1007 &pci_dev->addr); 1008 if (!err) { 1009 devx_bdf_devs++; 1010 continue; 1011 } 1012 if (err != 1) { 1013 ret = -err; 1014 goto exit; 1015 } 1016 devx_bdf_match[nd++] = devx_bdf_devs; 1017 } 1018 devx_bdf_match[nd] = NULL; 1019 if (!nd) { 1020 /* No device matches, just complain and bail out. */ 1021 DRV_LOG(WARNING, 1022 "no DevX device matches PCI device " PCI_PRI_FMT "," 1023 " is DevX Configured?", 1024 pci_dev->addr.domain, pci_dev->addr.bus, 1025 pci_dev->addr.devid, pci_dev->addr.function); 1026 rte_errno = ENOENT; 1027 ret = -rte_errno; 1028 goto exit; 1029 } 1030 /* 1031 * Now we can determine the maximal 1032 * amount of devices to be spawned. 1033 */ 1034 list = mlx5_malloc(MLX5_MEM_ZERO, 1035 sizeof(struct mlx5_dev_spawn_data), 1036 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1037 if (!list) { 1038 DRV_LOG(ERR, "spawn data array allocation failure"); 1039 rte_errno = ENOMEM; 1040 ret = -rte_errno; 1041 goto exit; 1042 } 1043 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1044 list[ns].max_port = 1; 1045 list[ns].phys_port = 1; 1046 list[ns].phys_dev = devx_bdf_match[ns]; 1047 list[ns].eth_dev = NULL; 1048 list[ns].pci_dev = pci_dev; 1049 list[ns].pf_bond = bd; 1050 list[ns].ifindex = -1; /* Spawn will assign */ 1051 list[ns].info = 1052 (struct mlx5_switch_info){ 1053 .master = 0, 1054 .representor = 0, 1055 .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK, 1056 .port_name = 0, 1057 .switch_id = 0, 1058 }; 1059 /* Device specific configuration. */ 1060 switch (pci_dev->id.device_id) { 1061 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1062 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1063 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1064 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1065 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 1066 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 1067 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 1068 dev_config_vf = 1; 1069 break; 1070 default: 1071 dev_config_vf = 0; 1072 break; 1073 } 1074 /* Default configuration. */ 1075 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 1076 dev_config.vf = dev_config_vf; 1077 dev_config.mps = 0; 1078 dev_config.dbnc = MLX5_ARG_UNSET; 1079 dev_config.rx_vec_en = 1; 1080 dev_config.txq_inline_max = MLX5_ARG_UNSET; 1081 dev_config.txq_inline_min = MLX5_ARG_UNSET; 1082 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 1083 dev_config.txqs_inline = MLX5_ARG_UNSET; 1084 dev_config.vf_nl_en = 0; 1085 dev_config.mr_ext_memseg_en = 1; 1086 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 1087 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 1088 dev_config.dv_esw_en = 0; 1089 dev_config.dv_flow_en = 1; 1090 dev_config.decap_en = 0; 1091 dev_config.log_hp_size = MLX5_ARG_UNSET; 1092 list[ns].eth_dev = mlx5_dev_spawn(&pci_dev->device, 1093 &list[ns], 1094 &dev_config); 1095 if (!list[ns].eth_dev) 1096 goto exit; 1097 restore = list[ns].eth_dev->data->dev_flags; 1098 rte_eth_copy_pci_info(list[ns].eth_dev, pci_dev); 1099 /* Restore non-PCI flags cleared by the above call. */ 1100 list[ns].eth_dev->data->dev_flags |= restore; 1101 rte_eth_dev_probing_finish(list[ns].eth_dev); 1102 ret = 0; 1103 exit: 1104 /* 1105 * Do the routine cleanup: 1106 * - free allocated spawn data array 1107 * - free the device list 1108 */ 1109 if (list) 1110 mlx5_free(list); 1111 MLX5_ASSERT(orig_devx_bdf_devs); 1112 mlx5_glue->free_device_list(orig_devx_bdf_devs); 1113 return ret; 1114 } 1115 1116 /** 1117 * Set the reg_mr and dereg_mr call backs 1118 * 1119 * @param reg_mr_cb[out] 1120 * Pointer to reg_mr func 1121 * @param dereg_mr_cb[out] 1122 * Pointer to dereg_mr func 1123 * 1124 */ 1125 void 1126 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1127 mlx5_dereg_mr_t *dereg_mr_cb) 1128 { 1129 *reg_mr_cb = mlx5_os_reg_mr; 1130 *dereg_mr_cb = mlx5_os_dereg_mr; 1131 } 1132 1133 /** 1134 * Extract pdn of PD object using DevX 1135 * 1136 * @param[in] pd 1137 * Pointer to the DevX PD object. 1138 * @param[out] pdn 1139 * Pointer to the PD object number variable. 1140 * 1141 * @return 1142 * 0 on success, error value otherwise. 1143 */ 1144 int 1145 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 1146 { 1147 if (!pd) 1148 return -EINVAL; 1149 1150 *pdn = ((struct mlx5_pd *)pd)->pdn; 1151 return 0; 1152 } 1153 1154 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0}; 1155