1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <assert.h> 36 #include <errno.h> 37 #include <string.h> 38 #include <stdint.h> 39 #include <unistd.h> 40 #include <sys/mman.h> 41 42 /* Verbs header. */ 43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 44 #ifdef PEDANTIC 45 #pragma GCC diagnostic ignored "-Wpedantic" 46 #endif 47 #include <infiniband/verbs.h> 48 #ifdef PEDANTIC 49 #pragma GCC diagnostic error "-Wpedantic" 50 #endif 51 52 #include <rte_mbuf.h> 53 #include <rte_malloc.h> 54 #include <rte_ethdev_driver.h> 55 #include <rte_common.h> 56 57 #include "mlx5_utils.h" 58 #include "mlx5_defs.h" 59 #include "mlx5.h" 60 #include "mlx5_rxtx.h" 61 #include "mlx5_autoconf.h" 62 63 /** 64 * Allocate TX queue elements. 65 * 66 * @param txq_ctrl 67 * Pointer to TX queue structure. 68 */ 69 void 70 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl) 71 { 72 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n; 73 unsigned int i; 74 75 for (i = 0; (i != elts_n); ++i) 76 (*txq_ctrl->txq.elts)[i] = NULL; 77 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n); 78 txq_ctrl->txq.elts_head = 0; 79 txq_ctrl->txq.elts_tail = 0; 80 txq_ctrl->txq.elts_comp = 0; 81 } 82 83 /** 84 * Free TX queue elements. 85 * 86 * @param txq_ctrl 87 * Pointer to TX queue structure. 88 */ 89 static void 90 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl) 91 { 92 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n; 93 const uint16_t elts_m = elts_n - 1; 94 uint16_t elts_head = txq_ctrl->txq.elts_head; 95 uint16_t elts_tail = txq_ctrl->txq.elts_tail; 96 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts; 97 98 DEBUG("%p: freeing WRs", (void *)txq_ctrl); 99 txq_ctrl->txq.elts_head = 0; 100 txq_ctrl->txq.elts_tail = 0; 101 txq_ctrl->txq.elts_comp = 0; 102 103 while (elts_tail != elts_head) { 104 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m]; 105 106 assert(elt != NULL); 107 rte_pktmbuf_free_seg(elt); 108 #ifndef NDEBUG 109 /* Poisoning. */ 110 memset(&(*elts)[elts_tail & elts_m], 111 0x77, 112 sizeof((*elts)[elts_tail & elts_m])); 113 #endif 114 ++elts_tail; 115 } 116 } 117 118 /** 119 * Returns the per-port supported offloads. 120 * 121 * @param priv 122 * Pointer to private structure. 123 * 124 * @return 125 * Supported Tx offloads. 126 */ 127 uint64_t 128 mlx5_priv_get_tx_port_offloads(struct priv *priv) 129 { 130 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS | 131 DEV_TX_OFFLOAD_VLAN_INSERT); 132 struct mlx5_dev_config *config = &priv->config; 133 134 if (config->hw_csum) 135 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM | 136 DEV_TX_OFFLOAD_UDP_CKSUM | 137 DEV_TX_OFFLOAD_TCP_CKSUM); 138 if (config->tso) 139 offloads |= DEV_TX_OFFLOAD_TCP_TSO; 140 if (config->tunnel_en) { 141 if (config->hw_csum) 142 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 143 if (config->tso) 144 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 145 DEV_TX_OFFLOAD_GRE_TNL_TSO); 146 } 147 return offloads; 148 } 149 150 /** 151 * Checks if the per-queue offload configuration is valid. 152 * 153 * @param priv 154 * Pointer to private structure. 155 * @param offloads 156 * Per-queue offloads configuration. 157 * 158 * @return 159 * 1 if the configuration is valid, 0 otherwise. 160 */ 161 static int 162 priv_is_tx_queue_offloads_allowed(struct priv *priv, uint64_t offloads) 163 { 164 uint64_t port_offloads = priv->dev->data->dev_conf.txmode.offloads; 165 uint64_t port_supp_offloads = mlx5_priv_get_tx_port_offloads(priv); 166 167 /* There are no Tx offloads which are per queue. */ 168 if ((offloads & port_supp_offloads) != offloads) 169 return 0; 170 if ((port_offloads ^ offloads) & port_supp_offloads) 171 return 0; 172 return 1; 173 } 174 175 /** 176 * DPDK callback to configure a TX queue. 177 * 178 * @param dev 179 * Pointer to Ethernet device structure. 180 * @param idx 181 * TX queue index. 182 * @param desc 183 * Number of descriptors to configure in queue. 184 * @param socket 185 * NUMA socket on which memory must be allocated. 186 * @param[in] conf 187 * Thresholds parameters. 188 * 189 * @return 190 * 0 on success, negative errno value on failure. 191 */ 192 int 193 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 194 unsigned int socket, const struct rte_eth_txconf *conf) 195 { 196 struct priv *priv = dev->data->dev_private; 197 struct mlx5_txq_data *txq = (*priv->txqs)[idx]; 198 struct mlx5_txq_ctrl *txq_ctrl = 199 container_of(txq, struct mlx5_txq_ctrl, txq); 200 int ret = 0; 201 202 priv_lock(priv); 203 /* 204 * Don't verify port offloads for application which 205 * use the old API. 206 */ 207 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) && 208 !priv_is_tx_queue_offloads_allowed(priv, conf->offloads)) { 209 ret = ENOTSUP; 210 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port " 211 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64, 212 (void *)dev, conf->offloads, 213 dev->data->dev_conf.txmode.offloads, 214 mlx5_priv_get_tx_port_offloads(priv)); 215 goto out; 216 } 217 if (desc <= MLX5_TX_COMP_THRESH) { 218 WARN("%p: number of descriptors requested for TX queue %u" 219 " must be higher than MLX5_TX_COMP_THRESH, using" 220 " %u instead of %u", 221 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc); 222 desc = MLX5_TX_COMP_THRESH + 1; 223 } 224 if (!rte_is_power_of_2(desc)) { 225 desc = 1 << log2above(desc); 226 WARN("%p: increased number of descriptors in TX queue %u" 227 " to the next power of two (%d)", 228 (void *)dev, idx, desc); 229 } 230 DEBUG("%p: configuring queue %u for %u descriptors", 231 (void *)dev, idx, desc); 232 if (idx >= priv->txqs_n) { 233 ERROR("%p: queue index out of range (%u >= %u)", 234 (void *)dev, idx, priv->txqs_n); 235 priv_unlock(priv); 236 return -EOVERFLOW; 237 } 238 if (!mlx5_priv_txq_releasable(priv, idx)) { 239 ret = EBUSY; 240 ERROR("%p: unable to release queue index %u", 241 (void *)dev, idx); 242 goto out; 243 } 244 mlx5_priv_txq_release(priv, idx); 245 txq_ctrl = mlx5_priv_txq_new(priv, idx, desc, socket, conf); 246 if (!txq_ctrl) { 247 ERROR("%p: unable to allocate queue index %u", 248 (void *)dev, idx); 249 ret = ENOMEM; 250 goto out; 251 } 252 DEBUG("%p: adding TX queue %p to list", 253 (void *)dev, (void *)txq_ctrl); 254 (*priv->txqs)[idx] = &txq_ctrl->txq; 255 out: 256 priv_unlock(priv); 257 return -ret; 258 } 259 260 /** 261 * DPDK callback to release a TX queue. 262 * 263 * @param dpdk_txq 264 * Generic TX queue pointer. 265 */ 266 void 267 mlx5_tx_queue_release(void *dpdk_txq) 268 { 269 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; 270 struct mlx5_txq_ctrl *txq_ctrl; 271 struct priv *priv; 272 unsigned int i; 273 274 if (txq == NULL) 275 return; 276 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); 277 priv = txq_ctrl->priv; 278 priv_lock(priv); 279 for (i = 0; (i != priv->txqs_n); ++i) 280 if ((*priv->txqs)[i] == txq) { 281 DEBUG("%p: removing TX queue %p from list", 282 (void *)priv->dev, (void *)txq_ctrl); 283 mlx5_priv_txq_release(priv, i); 284 break; 285 } 286 priv_unlock(priv); 287 } 288 289 290 /** 291 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space. 292 * Both primary and secondary process do mmap to make UAR address 293 * aligned. 294 * 295 * @param[in] priv 296 * Pointer to private structure. 297 * @param fd 298 * Verbs file descriptor to map UAR pages. 299 * 300 * @return 301 * 0 on success, errno value on failure. 302 */ 303 int 304 priv_tx_uar_remap(struct priv *priv, int fd) 305 { 306 unsigned int i, j; 307 uintptr_t pages[priv->txqs_n]; 308 unsigned int pages_n = 0; 309 uintptr_t uar_va; 310 uintptr_t off; 311 void *addr; 312 void *ret; 313 struct mlx5_txq_data *txq; 314 struct mlx5_txq_ctrl *txq_ctrl; 315 int already_mapped; 316 size_t page_size = sysconf(_SC_PAGESIZE); 317 int r; 318 319 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t)); 320 /* 321 * As rdma-core, UARs are mapped in size of OS page size. 322 * Use aligned address to avoid duplicate mmap. 323 * Ref to libmlx5 function: mlx5_init_context() 324 */ 325 for (i = 0; i != priv->txqs_n; ++i) { 326 txq = (*priv->txqs)[i]; 327 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); 328 /* UAR addr form verbs used to find dup and offset in page. */ 329 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig; 330 off = uar_va & (page_size - 1); /* offset in page. */ 331 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */ 332 already_mapped = 0; 333 for (j = 0; j != pages_n; ++j) { 334 if (pages[j] == uar_va) { 335 already_mapped = 1; 336 break; 337 } 338 } 339 /* new address in reserved UAR address space. */ 340 addr = RTE_PTR_ADD(priv->uar_base, 341 uar_va & (MLX5_UAR_SIZE - 1)); 342 if (!already_mapped) { 343 pages[pages_n++] = uar_va; 344 /* fixed mmap to specified address in reserved 345 * address space. 346 */ 347 ret = mmap(addr, page_size, 348 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd, 349 txq_ctrl->uar_mmap_offset); 350 if (ret != addr) { 351 /* fixed mmap have to return same address */ 352 ERROR("call to mmap failed on UAR for txq %d\n", 353 i); 354 r = ENXIO; 355 return r; 356 } 357 } 358 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */ 359 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off); 360 else 361 assert(txq_ctrl->txq.bf_reg == 362 RTE_PTR_ADD((void *)addr, off)); 363 } 364 return 0; 365 } 366 367 /** 368 * Check if the burst function is using eMPW. 369 * 370 * @param tx_pkt_burst 371 * Tx burst function pointer. 372 * 373 * @return 374 * 1 if the burst function is using eMPW, 0 otherwise. 375 */ 376 static int 377 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst) 378 { 379 if (tx_pkt_burst == mlx5_tx_burst_raw_vec || 380 tx_pkt_burst == mlx5_tx_burst_vec || 381 tx_pkt_burst == mlx5_tx_burst_empw) 382 return 1; 383 return 0; 384 } 385 386 /** 387 * Create the Tx queue Verbs object. 388 * 389 * @param priv 390 * Pointer to private structure. 391 * @param idx 392 * Queue index in DPDK Rx queue array 393 * 394 * @return 395 * The Verbs object initialised if it can be created. 396 */ 397 struct mlx5_txq_ibv* 398 mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx) 399 { 400 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 401 struct mlx5_txq_ctrl *txq_ctrl = 402 container_of(txq_data, struct mlx5_txq_ctrl, txq); 403 struct mlx5_txq_ibv tmpl; 404 struct mlx5_txq_ibv *txq_ibv; 405 union { 406 struct ibv_qp_init_attr_ex init; 407 struct ibv_cq_init_attr_ex cq; 408 struct ibv_qp_attr mod; 409 struct ibv_cq_ex cq_attr; 410 } attr; 411 unsigned int cqe_n; 412 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET }; 413 struct mlx5dv_cq cq_info; 414 struct mlx5dv_obj obj; 415 const int desc = 1 << txq_data->elts_n; 416 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev); 417 int ret = 0; 418 419 assert(txq_data); 420 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE; 421 priv->verbs_alloc_ctx.obj = txq_ctrl; 422 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) { 423 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set"); 424 goto error; 425 } 426 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv)); 427 /* MRs will be registered in mp2mr[] later. */ 428 attr.cq = (struct ibv_cq_init_attr_ex){ 429 .comp_mask = 0, 430 }; 431 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ? 432 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1; 433 if (is_empw_burst_func(tx_pkt_burst)) 434 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV; 435 tmpl.cq = ibv_create_cq(priv->ctx, cqe_n, NULL, NULL, 0); 436 if (tmpl.cq == NULL) { 437 ERROR("%p: CQ creation failure", (void *)txq_ctrl); 438 goto error; 439 } 440 attr.init = (struct ibv_qp_init_attr_ex){ 441 /* CQ to be associated with the send queue. */ 442 .send_cq = tmpl.cq, 443 /* CQ to be associated with the receive queue. */ 444 .recv_cq = tmpl.cq, 445 .cap = { 446 /* Max number of outstanding WRs. */ 447 .max_send_wr = 448 ((priv->device_attr.orig_attr.max_qp_wr < 449 desc) ? 450 priv->device_attr.orig_attr.max_qp_wr : 451 desc), 452 /* 453 * Max number of scatter/gather elements in a WR, 454 * must be 1 to prevent libmlx5 from trying to affect 455 * too much memory. TX gather is not impacted by the 456 * priv->device_attr.max_sge limit and will still work 457 * properly. 458 */ 459 .max_send_sge = 1, 460 }, 461 .qp_type = IBV_QPT_RAW_PACKET, 462 /* 463 * Do *NOT* enable this, completions events are managed per 464 * Tx burst. 465 */ 466 .sq_sig_all = 0, 467 .pd = priv->pd, 468 .comp_mask = IBV_QP_INIT_ATTR_PD, 469 }; 470 if (txq_data->max_inline) 471 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data; 472 if (txq_data->tso_en) { 473 attr.init.max_tso_header = txq_ctrl->max_tso_header; 474 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER; 475 } 476 tmpl.qp = ibv_create_qp_ex(priv->ctx, &attr.init); 477 if (tmpl.qp == NULL) { 478 ERROR("%p: QP creation failure", (void *)txq_ctrl); 479 goto error; 480 } 481 attr.mod = (struct ibv_qp_attr){ 482 /* Move the QP to this state. */ 483 .qp_state = IBV_QPS_INIT, 484 /* Primary port number. */ 485 .port_num = priv->port 486 }; 487 ret = ibv_modify_qp(tmpl.qp, &attr.mod, (IBV_QP_STATE | IBV_QP_PORT)); 488 if (ret) { 489 ERROR("%p: QP state to IBV_QPS_INIT failed", (void *)txq_ctrl); 490 goto error; 491 } 492 attr.mod = (struct ibv_qp_attr){ 493 .qp_state = IBV_QPS_RTR 494 }; 495 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE); 496 if (ret) { 497 ERROR("%p: QP state to IBV_QPS_RTR failed", (void *)txq_ctrl); 498 goto error; 499 } 500 attr.mod.qp_state = IBV_QPS_RTS; 501 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE); 502 if (ret) { 503 ERROR("%p: QP state to IBV_QPS_RTS failed", (void *)txq_ctrl); 504 goto error; 505 } 506 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0, 507 txq_ctrl->socket); 508 if (!txq_ibv) { 509 ERROR("%p: cannot allocate memory", (void *)txq_ctrl); 510 goto error; 511 } 512 obj.cq.in = tmpl.cq; 513 obj.cq.out = &cq_info; 514 obj.qp.in = tmpl.qp; 515 obj.qp.out = &qp; 516 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP); 517 if (ret != 0) 518 goto error; 519 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) { 520 ERROR("Wrong MLX5_CQE_SIZE environment variable value: " 521 "it should be set to %u", RTE_CACHE_LINE_SIZE); 522 goto error; 523 } 524 txq_data->cqe_n = log2above(cq_info.cqe_cnt); 525 txq_data->qp_num_8s = tmpl.qp->qp_num << 8; 526 txq_data->wqes = qp.sq.buf; 527 txq_data->wqe_n = log2above(qp.sq.wqe_cnt); 528 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR]; 529 txq_ctrl->bf_reg_orig = qp.bf.reg; 530 txq_data->cq_db = cq_info.dbrec; 531 txq_data->cqes = 532 (volatile struct mlx5_cqe (*)[]) 533 (uintptr_t)cq_info.buf; 534 txq_data->cq_ci = 0; 535 #ifndef NDEBUG 536 txq_data->cq_pi = 0; 537 #endif 538 txq_data->wqe_ci = 0; 539 txq_data->wqe_pi = 0; 540 txq_ibv->qp = tmpl.qp; 541 txq_ibv->cq = tmpl.cq; 542 rte_atomic32_inc(&txq_ibv->refcnt); 543 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) { 544 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset; 545 } else { 546 ERROR("Failed to retrieve UAR info, invalid libmlx5.so version"); 547 goto error; 548 } 549 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv, 550 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt)); 551 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next); 552 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 553 return txq_ibv; 554 error: 555 if (tmpl.cq) 556 claim_zero(ibv_destroy_cq(tmpl.cq)); 557 if (tmpl.qp) 558 claim_zero(ibv_destroy_qp(tmpl.qp)); 559 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 560 return NULL; 561 } 562 563 /** 564 * Get an Tx queue Verbs object. 565 * 566 * @param priv 567 * Pointer to private structure. 568 * @param idx 569 * Queue index in DPDK Rx queue array 570 * 571 * @return 572 * The Verbs object if it exists. 573 */ 574 struct mlx5_txq_ibv* 575 mlx5_priv_txq_ibv_get(struct priv *priv, uint16_t idx) 576 { 577 struct mlx5_txq_ctrl *txq_ctrl; 578 579 if (idx >= priv->txqs_n) 580 return NULL; 581 if (!(*priv->txqs)[idx]) 582 return NULL; 583 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); 584 if (txq_ctrl->ibv) { 585 rte_atomic32_inc(&txq_ctrl->ibv->refcnt); 586 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv, 587 (void *)txq_ctrl->ibv, 588 rte_atomic32_read(&txq_ctrl->ibv->refcnt)); 589 } 590 return txq_ctrl->ibv; 591 } 592 593 /** 594 * Release an Tx verbs queue object. 595 * 596 * @param priv 597 * Pointer to private structure. 598 * @param txq_ibv 599 * Verbs Tx queue object. 600 * 601 * @return 602 * 0 on success, errno on failure. 603 */ 604 int 605 mlx5_priv_txq_ibv_release(struct priv *priv, struct mlx5_txq_ibv *txq_ibv) 606 { 607 (void)priv; 608 assert(txq_ibv); 609 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv, 610 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt)); 611 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) { 612 claim_zero(ibv_destroy_qp(txq_ibv->qp)); 613 claim_zero(ibv_destroy_cq(txq_ibv->cq)); 614 LIST_REMOVE(txq_ibv, next); 615 rte_free(txq_ibv); 616 return 0; 617 } 618 return EBUSY; 619 } 620 621 /** 622 * Return true if a single reference exists on the object. 623 * 624 * @param priv 625 * Pointer to private structure. 626 * @param txq_ibv 627 * Verbs Tx queue object. 628 */ 629 int 630 mlx5_priv_txq_ibv_releasable(struct priv *priv, struct mlx5_txq_ibv *txq_ibv) 631 { 632 (void)priv; 633 assert(txq_ibv); 634 return (rte_atomic32_read(&txq_ibv->refcnt) == 1); 635 } 636 637 /** 638 * Verify the Verbs Tx queue list is empty 639 * 640 * @param priv 641 * Pointer to private structure. 642 * 643 * @return the number of object not released. 644 */ 645 int 646 mlx5_priv_txq_ibv_verify(struct priv *priv) 647 { 648 int ret = 0; 649 struct mlx5_txq_ibv *txq_ibv; 650 651 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) { 652 DEBUG("%p: Verbs Tx queue %p still referenced", (void *)priv, 653 (void *)txq_ibv); 654 ++ret; 655 } 656 return ret; 657 } 658 659 /** 660 * Set Tx queue parameters from device configuration. 661 * 662 * @param txq_ctrl 663 * Pointer to Tx queue control structure. 664 */ 665 static void 666 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl) 667 { 668 struct priv *priv = txq_ctrl->priv; 669 struct mlx5_dev_config *config = &priv->config; 670 const unsigned int max_tso_inline = 671 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) / 672 RTE_CACHE_LINE_SIZE); 673 unsigned int txq_inline; 674 unsigned int txqs_inline; 675 unsigned int inline_max_packet_sz; 676 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev); 677 int is_empw_func = is_empw_burst_func(tx_pkt_burst); 678 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO); 679 680 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ? 681 0 : config->txq_inline; 682 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ? 683 0 : config->txqs_inline; 684 inline_max_packet_sz = 685 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ? 686 0 : config->inline_max_packet_sz; 687 if (is_empw_func) { 688 if (config->txq_inline == MLX5_ARG_UNSET) 689 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE; 690 if (config->txqs_inline == MLX5_ARG_UNSET) 691 txqs_inline = MLX5_EMPW_MIN_TXQS; 692 if (config->inline_max_packet_sz == MLX5_ARG_UNSET) 693 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN; 694 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg; 695 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz; 696 } 697 if (txq_inline && priv->txqs_n >= txqs_inline) { 698 unsigned int ds_cnt; 699 700 txq_ctrl->txq.max_inline = 701 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) / 702 RTE_CACHE_LINE_SIZE); 703 if (is_empw_func) { 704 /* To minimize the size of data set, avoid requesting 705 * too large WQ. 706 */ 707 txq_ctrl->max_inline_data = 708 ((RTE_MIN(txq_inline, 709 inline_max_packet_sz) + 710 (RTE_CACHE_LINE_SIZE - 1)) / 711 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE; 712 } else if (tso) { 713 int inline_diff = txq_ctrl->txq.max_inline - 714 max_tso_inline; 715 716 /* 717 * Adjust inline value as Verbs aggregates 718 * tso_inline and txq_inline fields. 719 */ 720 txq_ctrl->max_inline_data = inline_diff > 0 ? 721 inline_diff * 722 RTE_CACHE_LINE_SIZE : 723 0; 724 } else { 725 txq_ctrl->max_inline_data = 726 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE; 727 } 728 /* 729 * Check if the inline size is too large in a way which 730 * can make the WQE DS to overflow. 731 * Considering in calculation: 732 * WQE CTRL (1 DS) 733 * WQE ETH (1 DS) 734 * Inline part (N DS) 735 */ 736 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE); 737 if (ds_cnt > MLX5_DSEG_MAX) { 738 unsigned int max_inline = (MLX5_DSEG_MAX - 2) * 739 MLX5_WQE_DWORD_SIZE; 740 741 max_inline = max_inline - (max_inline % 742 RTE_CACHE_LINE_SIZE); 743 WARN("txq inline is too large (%d) setting it to " 744 "the maximum possible: %d\n", 745 txq_inline, max_inline); 746 txq_ctrl->txq.max_inline = max_inline / 747 RTE_CACHE_LINE_SIZE; 748 } 749 } 750 if (tso) { 751 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE; 752 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline, 753 max_tso_inline); 754 txq_ctrl->txq.tso_en = 1; 755 } 756 txq_ctrl->txq.tunnel_en = config->tunnel_en; 757 } 758 759 /** 760 * Create a DPDK Tx queue. 761 * 762 * @param priv 763 * Pointer to private structure. 764 * @param idx 765 * TX queue index. 766 * @param desc 767 * Number of descriptors to configure in queue. 768 * @param socket 769 * NUMA socket on which memory must be allocated. 770 * @param[in] conf 771 * Thresholds parameters. 772 * 773 * @return 774 * A DPDK queue object on success. 775 */ 776 struct mlx5_txq_ctrl* 777 mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc, 778 unsigned int socket, 779 const struct rte_eth_txconf *conf) 780 { 781 struct mlx5_txq_ctrl *tmpl; 782 783 tmpl = rte_calloc_socket("TXQ", 1, 784 sizeof(*tmpl) + 785 desc * sizeof(struct rte_mbuf *), 786 0, socket); 787 if (!tmpl) 788 return NULL; 789 assert(desc > MLX5_TX_COMP_THRESH); 790 tmpl->txq.offloads = conf->offloads; 791 tmpl->priv = priv; 792 tmpl->socket = socket; 793 tmpl->txq.elts_n = log2above(desc); 794 txq_set_params(tmpl); 795 /* MRs will be registered in mp2mr[] later. */ 796 DEBUG("priv->device_attr.max_qp_wr is %d", 797 priv->device_attr.orig_attr.max_qp_wr); 798 DEBUG("priv->device_attr.max_sge is %d", 799 priv->device_attr.orig_attr.max_sge); 800 tmpl->txq.elts = 801 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1); 802 tmpl->txq.stats.idx = idx; 803 rte_atomic32_inc(&tmpl->refcnt); 804 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv, 805 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt)); 806 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next); 807 return tmpl; 808 } 809 810 /** 811 * Get a Tx queue. 812 * 813 * @param priv 814 * Pointer to private structure. 815 * @param idx 816 * TX queue index. 817 * 818 * @return 819 * A pointer to the queue if it exists. 820 */ 821 struct mlx5_txq_ctrl* 822 mlx5_priv_txq_get(struct priv *priv, uint16_t idx) 823 { 824 struct mlx5_txq_ctrl *ctrl = NULL; 825 826 if ((*priv->txqs)[idx]) { 827 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, 828 txq); 829 unsigned int i; 830 831 mlx5_priv_txq_ibv_get(priv, idx); 832 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) { 833 struct mlx5_mr *mr = NULL; 834 835 (void)mr; 836 if (ctrl->txq.mp2mr[i]) { 837 mr = priv_mr_get(priv, ctrl->txq.mp2mr[i]->mp); 838 assert(mr); 839 } 840 } 841 rte_atomic32_inc(&ctrl->refcnt); 842 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv, 843 (void *)ctrl, rte_atomic32_read(&ctrl->refcnt)); 844 } 845 return ctrl; 846 } 847 848 /** 849 * Release a Tx queue. 850 * 851 * @param priv 852 * Pointer to private structure. 853 * @param idx 854 * TX queue index. 855 * 856 * @return 857 * 0 on success, errno on failure. 858 */ 859 int 860 mlx5_priv_txq_release(struct priv *priv, uint16_t idx) 861 { 862 unsigned int i; 863 struct mlx5_txq_ctrl *txq; 864 size_t page_size = sysconf(_SC_PAGESIZE); 865 866 if (!(*priv->txqs)[idx]) 867 return 0; 868 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); 869 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv, 870 (void *)txq, rte_atomic32_read(&txq->refcnt)); 871 if (txq->ibv) { 872 int ret; 873 874 ret = mlx5_priv_txq_ibv_release(priv, txq->ibv); 875 if (!ret) 876 txq->ibv = NULL; 877 } 878 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) { 879 if (txq->txq.mp2mr[i]) { 880 priv_mr_release(priv, txq->txq.mp2mr[i]); 881 txq->txq.mp2mr[i] = NULL; 882 } 883 } 884 if (priv->uar_base) 885 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg, 886 page_size), page_size); 887 if (rte_atomic32_dec_and_test(&txq->refcnt)) { 888 txq_free_elts(txq); 889 LIST_REMOVE(txq, next); 890 rte_free(txq); 891 (*priv->txqs)[idx] = NULL; 892 return 0; 893 } 894 return EBUSY; 895 } 896 897 /** 898 * Verify if the queue can be released. 899 * 900 * @param priv 901 * Pointer to private structure. 902 * @param idx 903 * TX queue index. 904 * 905 * @return 906 * 1 if the queue can be released. 907 */ 908 int 909 mlx5_priv_txq_releasable(struct priv *priv, uint16_t idx) 910 { 911 struct mlx5_txq_ctrl *txq; 912 913 if (!(*priv->txqs)[idx]) 914 return -1; 915 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); 916 return (rte_atomic32_read(&txq->refcnt) == 1); 917 } 918 919 /** 920 * Verify the Tx Queue list is empty 921 * 922 * @param priv 923 * Pointer to private structure. 924 * 925 * @return the number of object not released. 926 */ 927 int 928 mlx5_priv_txq_verify(struct priv *priv) 929 { 930 struct mlx5_txq_ctrl *txq; 931 int ret = 0; 932 933 LIST_FOREACH(txq, &priv->txqsctrl, next) { 934 DEBUG("%p: Tx Queue %p still referenced", (void *)priv, 935 (void *)txq); 936 ++ret; 937 } 938 return ret; 939 } 940