1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 #include <stdint.h> 11 #include <unistd.h> 12 #include <sys/mman.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_mbuf.h> 25 #include <rte_malloc.h> 26 #include <rte_ethdev_driver.h> 27 #include <rte_common.h> 28 29 #include "mlx5_utils.h" 30 #include "mlx5_defs.h" 31 #include "mlx5.h" 32 #include "mlx5_rxtx.h" 33 #include "mlx5_autoconf.h" 34 #include "mlx5_glue.h" 35 36 /** 37 * Allocate TX queue elements. 38 * 39 * @param txq_ctrl 40 * Pointer to TX queue structure. 41 */ 42 void 43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl) 44 { 45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n; 46 unsigned int i; 47 48 for (i = 0; (i != elts_n); ++i) 49 (*txq_ctrl->txq.elts)[i] = NULL; 50 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs", 51 PORT_ID(txq_ctrl->priv), txq_ctrl->idx, elts_n); 52 txq_ctrl->txq.elts_head = 0; 53 txq_ctrl->txq.elts_tail = 0; 54 txq_ctrl->txq.elts_comp = 0; 55 } 56 57 /** 58 * Free TX queue elements. 59 * 60 * @param txq_ctrl 61 * Pointer to TX queue structure. 62 */ 63 static void 64 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl) 65 { 66 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n; 67 const uint16_t elts_m = elts_n - 1; 68 uint16_t elts_head = txq_ctrl->txq.elts_head; 69 uint16_t elts_tail = txq_ctrl->txq.elts_tail; 70 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts; 71 72 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs", 73 PORT_ID(txq_ctrl->priv), txq_ctrl->idx); 74 txq_ctrl->txq.elts_head = 0; 75 txq_ctrl->txq.elts_tail = 0; 76 txq_ctrl->txq.elts_comp = 0; 77 78 while (elts_tail != elts_head) { 79 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m]; 80 81 assert(elt != NULL); 82 rte_pktmbuf_free_seg(elt); 83 #ifndef NDEBUG 84 /* Poisoning. */ 85 memset(&(*elts)[elts_tail & elts_m], 86 0x77, 87 sizeof((*elts)[elts_tail & elts_m])); 88 #endif 89 ++elts_tail; 90 } 91 } 92 93 /** 94 * Returns the per-port supported offloads. 95 * 96 * @param dev 97 * Pointer to Ethernet device. 98 * 99 * @return 100 * Supported Tx offloads. 101 */ 102 uint64_t 103 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) 104 { 105 struct mlx5_priv *priv = dev->data->dev_private; 106 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS | 107 DEV_TX_OFFLOAD_VLAN_INSERT); 108 struct mlx5_dev_config *config = &priv->config; 109 110 if (config->hw_csum) 111 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM | 112 DEV_TX_OFFLOAD_UDP_CKSUM | 113 DEV_TX_OFFLOAD_TCP_CKSUM); 114 if (config->tso) 115 offloads |= DEV_TX_OFFLOAD_TCP_TSO; 116 if (config->swp) { 117 if (config->hw_csum) 118 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 119 if (config->tso) 120 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO | 121 DEV_TX_OFFLOAD_UDP_TNL_TSO); 122 } 123 if (config->tunnel_en) { 124 if (config->hw_csum) 125 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 126 if (config->tso) 127 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 128 DEV_TX_OFFLOAD_GRE_TNL_TSO); 129 } 130 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 131 if (config->dv_flow_en) 132 offloads |= DEV_TX_OFFLOAD_MATCH_METADATA; 133 #endif 134 return offloads; 135 } 136 137 /** 138 * DPDK callback to configure a TX queue. 139 * 140 * @param dev 141 * Pointer to Ethernet device structure. 142 * @param idx 143 * TX queue index. 144 * @param desc 145 * Number of descriptors to configure in queue. 146 * @param socket 147 * NUMA socket on which memory must be allocated. 148 * @param[in] conf 149 * Thresholds parameters. 150 * 151 * @return 152 * 0 on success, a negative errno value otherwise and rte_errno is set. 153 */ 154 int 155 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 156 unsigned int socket, const struct rte_eth_txconf *conf) 157 { 158 struct mlx5_priv *priv = dev->data->dev_private; 159 struct mlx5_txq_data *txq = (*priv->txqs)[idx]; 160 struct mlx5_txq_ctrl *txq_ctrl = 161 container_of(txq, struct mlx5_txq_ctrl, txq); 162 163 if (desc <= MLX5_TX_COMP_THRESH) { 164 DRV_LOG(WARNING, 165 "port %u number of descriptors requested for Tx queue" 166 " %u must be higher than MLX5_TX_COMP_THRESH, using %u" 167 " instead of %u", 168 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc); 169 desc = MLX5_TX_COMP_THRESH + 1; 170 } 171 if (!rte_is_power_of_2(desc)) { 172 desc = 1 << log2above(desc); 173 DRV_LOG(WARNING, 174 "port %u increased number of descriptors in Tx queue" 175 " %u to the next power of two (%d)", 176 dev->data->port_id, idx, desc); 177 } 178 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors", 179 dev->data->port_id, idx, desc); 180 if (idx >= priv->txqs_n) { 181 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)", 182 dev->data->port_id, idx, priv->txqs_n); 183 rte_errno = EOVERFLOW; 184 return -rte_errno; 185 } 186 if (!mlx5_txq_releasable(dev, idx)) { 187 rte_errno = EBUSY; 188 DRV_LOG(ERR, "port %u unable to release queue index %u", 189 dev->data->port_id, idx); 190 return -rte_errno; 191 } 192 mlx5_txq_release(dev, idx); 193 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf); 194 if (!txq_ctrl) { 195 DRV_LOG(ERR, "port %u unable to allocate queue index %u", 196 dev->data->port_id, idx); 197 return -rte_errno; 198 } 199 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list", 200 dev->data->port_id, idx); 201 (*priv->txqs)[idx] = &txq_ctrl->txq; 202 return 0; 203 } 204 205 /** 206 * DPDK callback to release a TX queue. 207 * 208 * @param dpdk_txq 209 * Generic TX queue pointer. 210 */ 211 void 212 mlx5_tx_queue_release(void *dpdk_txq) 213 { 214 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; 215 struct mlx5_txq_ctrl *txq_ctrl; 216 struct mlx5_priv *priv; 217 unsigned int i; 218 219 if (txq == NULL) 220 return; 221 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); 222 priv = txq_ctrl->priv; 223 for (i = 0; (i != priv->txqs_n); ++i) 224 if ((*priv->txqs)[i] == txq) { 225 mlx5_txq_release(ETH_DEV(priv), i); 226 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list", 227 PORT_ID(priv), txq_ctrl->idx); 228 break; 229 } 230 } 231 232 233 /** 234 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space. 235 * Both primary and secondary process do mmap to make UAR address 236 * aligned. 237 * 238 * @param[in] dev 239 * Pointer to Ethernet device. 240 * @param fd 241 * Verbs file descriptor to map UAR pages. 242 * 243 * @return 244 * 0 on success, a negative errno value otherwise and rte_errno is set. 245 */ 246 int 247 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd) 248 { 249 struct mlx5_priv *priv = dev->data->dev_private; 250 unsigned int i, j; 251 uintptr_t pages[priv->txqs_n]; 252 unsigned int pages_n = 0; 253 uintptr_t uar_va; 254 uintptr_t off; 255 void *addr; 256 void *ret; 257 struct mlx5_txq_data *txq; 258 struct mlx5_txq_ctrl *txq_ctrl; 259 int already_mapped; 260 size_t page_size = sysconf(_SC_PAGESIZE); 261 #ifndef RTE_ARCH_64 262 unsigned int lock_idx; 263 #endif 264 265 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t)); 266 /* 267 * As rdma-core, UARs are mapped in size of OS page size. 268 * Use aligned address to avoid duplicate mmap. 269 * Ref to libmlx5 function: mlx5_init_context() 270 */ 271 for (i = 0; i != priv->txqs_n; ++i) { 272 if (!(*priv->txqs)[i]) 273 continue; 274 txq = (*priv->txqs)[i]; 275 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); 276 assert(txq_ctrl->idx == (uint16_t)i); 277 /* UAR addr form verbs used to find dup and offset in page. */ 278 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig; 279 off = uar_va & (page_size - 1); /* offset in page. */ 280 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */ 281 already_mapped = 0; 282 for (j = 0; j != pages_n; ++j) { 283 if (pages[j] == uar_va) { 284 already_mapped = 1; 285 break; 286 } 287 } 288 /* new address in reserved UAR address space. */ 289 addr = RTE_PTR_ADD(priv->uar_base, 290 uar_va & (uintptr_t)(MLX5_UAR_SIZE - 1)); 291 if (!already_mapped) { 292 pages[pages_n++] = uar_va; 293 /* fixed mmap to specified address in reserved 294 * address space. 295 */ 296 ret = mmap(addr, page_size, 297 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd, 298 txq_ctrl->uar_mmap_offset); 299 if (ret != addr) { 300 /* fixed mmap have to return same address */ 301 DRV_LOG(ERR, 302 "port %u call to mmap failed on UAR" 303 " for txq %u", 304 dev->data->port_id, txq_ctrl->idx); 305 rte_errno = ENXIO; 306 return -rte_errno; 307 } 308 } 309 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */ 310 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off); 311 else 312 assert(txq_ctrl->txq.bf_reg == 313 RTE_PTR_ADD((void *)addr, off)); 314 #ifndef RTE_ARCH_64 315 /* Assign a UAR lock according to UAR page number */ 316 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) & 317 MLX5_UAR_PAGE_NUM_MASK; 318 txq->uar_lock = &priv->uar_lock[lock_idx]; 319 #endif 320 } 321 return 0; 322 } 323 324 /** 325 * Check if the burst function is using eMPW. 326 * 327 * @param tx_pkt_burst 328 * Tx burst function pointer. 329 * 330 * @return 331 * 1 if the burst function is using eMPW, 0 otherwise. 332 */ 333 static int 334 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst) 335 { 336 if (tx_pkt_burst == mlx5_tx_burst_raw_vec || 337 tx_pkt_burst == mlx5_tx_burst_vec || 338 tx_pkt_burst == mlx5_tx_burst_empw) 339 return 1; 340 return 0; 341 } 342 343 /** 344 * Create the Tx queue Verbs object. 345 * 346 * @param dev 347 * Pointer to Ethernet device. 348 * @param idx 349 * Queue index in DPDK Rx queue array 350 * 351 * @return 352 * The Verbs object initialised, NULL otherwise and rte_errno is set. 353 */ 354 struct mlx5_txq_ibv * 355 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx) 356 { 357 struct mlx5_priv *priv = dev->data->dev_private; 358 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 359 struct mlx5_txq_ctrl *txq_ctrl = 360 container_of(txq_data, struct mlx5_txq_ctrl, txq); 361 struct mlx5_txq_ibv tmpl; 362 struct mlx5_txq_ibv *txq_ibv; 363 union { 364 struct ibv_qp_init_attr_ex init; 365 struct ibv_cq_init_attr_ex cq; 366 struct ibv_qp_attr mod; 367 struct ibv_cq_ex cq_attr; 368 } attr; 369 unsigned int cqe_n; 370 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET }; 371 struct mlx5dv_cq cq_info; 372 struct mlx5dv_obj obj; 373 const int desc = 1 << txq_data->elts_n; 374 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev); 375 int ret = 0; 376 377 assert(txq_data); 378 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE; 379 priv->verbs_alloc_ctx.obj = txq_ctrl; 380 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) { 381 DRV_LOG(ERR, 382 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set", 383 dev->data->port_id); 384 rte_errno = EINVAL; 385 return NULL; 386 } 387 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv)); 388 attr.cq = (struct ibv_cq_init_attr_ex){ 389 .comp_mask = 0, 390 }; 391 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ? 392 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1; 393 if (is_empw_burst_func(tx_pkt_burst)) 394 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV; 395 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0); 396 if (tmpl.cq == NULL) { 397 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure", 398 dev->data->port_id, idx); 399 rte_errno = errno; 400 goto error; 401 } 402 attr.init = (struct ibv_qp_init_attr_ex){ 403 /* CQ to be associated with the send queue. */ 404 .send_cq = tmpl.cq, 405 /* CQ to be associated with the receive queue. */ 406 .recv_cq = tmpl.cq, 407 .cap = { 408 /* Max number of outstanding WRs. */ 409 .max_send_wr = 410 ((priv->sh->device_attr.orig_attr.max_qp_wr < 411 desc) ? 412 priv->sh->device_attr.orig_attr.max_qp_wr : 413 desc), 414 /* 415 * Max number of scatter/gather elements in a WR, 416 * must be 1 to prevent libmlx5 from trying to affect 417 * too much memory. TX gather is not impacted by the 418 * device_attr.max_sge limit and will still work 419 * properly. 420 */ 421 .max_send_sge = 1, 422 }, 423 .qp_type = IBV_QPT_RAW_PACKET, 424 /* 425 * Do *NOT* enable this, completions events are managed per 426 * Tx burst. 427 */ 428 .sq_sig_all = 0, 429 .pd = priv->sh->pd, 430 .comp_mask = IBV_QP_INIT_ATTR_PD, 431 }; 432 if (txq_data->max_inline) 433 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data; 434 if (txq_data->tso_en) { 435 attr.init.max_tso_header = txq_ctrl->max_tso_header; 436 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER; 437 } 438 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init); 439 if (tmpl.qp == NULL) { 440 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure", 441 dev->data->port_id, idx); 442 rte_errno = errno; 443 goto error; 444 } 445 attr.mod = (struct ibv_qp_attr){ 446 /* Move the QP to this state. */ 447 .qp_state = IBV_QPS_INIT, 448 /* IB device port number. */ 449 .port_num = (uint8_t)priv->ibv_port, 450 }; 451 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, 452 (IBV_QP_STATE | IBV_QP_PORT)); 453 if (ret) { 454 DRV_LOG(ERR, 455 "port %u Tx queue %u QP state to IBV_QPS_INIT failed", 456 dev->data->port_id, idx); 457 rte_errno = errno; 458 goto error; 459 } 460 attr.mod = (struct ibv_qp_attr){ 461 .qp_state = IBV_QPS_RTR 462 }; 463 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE); 464 if (ret) { 465 DRV_LOG(ERR, 466 "port %u Tx queue %u QP state to IBV_QPS_RTR failed", 467 dev->data->port_id, idx); 468 rte_errno = errno; 469 goto error; 470 } 471 attr.mod.qp_state = IBV_QPS_RTS; 472 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE); 473 if (ret) { 474 DRV_LOG(ERR, 475 "port %u Tx queue %u QP state to IBV_QPS_RTS failed", 476 dev->data->port_id, idx); 477 rte_errno = errno; 478 goto error; 479 } 480 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0, 481 txq_ctrl->socket); 482 if (!txq_ibv) { 483 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory", 484 dev->data->port_id, idx); 485 rte_errno = ENOMEM; 486 goto error; 487 } 488 obj.cq.in = tmpl.cq; 489 obj.cq.out = &cq_info; 490 obj.qp.in = tmpl.qp; 491 obj.qp.out = &qp; 492 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP); 493 if (ret != 0) { 494 rte_errno = errno; 495 goto error; 496 } 497 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) { 498 DRV_LOG(ERR, 499 "port %u wrong MLX5_CQE_SIZE environment variable" 500 " value: it should be set to %u", 501 dev->data->port_id, RTE_CACHE_LINE_SIZE); 502 rte_errno = EINVAL; 503 goto error; 504 } 505 txq_data->cqe_n = log2above(cq_info.cqe_cnt); 506 txq_data->qp_num_8s = tmpl.qp->qp_num << 8; 507 txq_data->wqes = qp.sq.buf; 508 txq_data->wqe_n = log2above(qp.sq.wqe_cnt); 509 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR]; 510 txq_ctrl->bf_reg_orig = qp.bf.reg; 511 txq_data->cq_db = cq_info.dbrec; 512 txq_data->cqes = 513 (volatile struct mlx5_cqe (*)[]) 514 (uintptr_t)cq_info.buf; 515 txq_data->cq_ci = 0; 516 #ifndef NDEBUG 517 txq_data->cq_pi = 0; 518 #endif 519 txq_data->wqe_ci = 0; 520 txq_data->wqe_pi = 0; 521 txq_ibv->qp = tmpl.qp; 522 txq_ibv->cq = tmpl.cq; 523 rte_atomic32_inc(&txq_ibv->refcnt); 524 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) { 525 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset; 526 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%lx", 527 dev->data->port_id, txq_ctrl->uar_mmap_offset); 528 } else { 529 DRV_LOG(ERR, 530 "port %u failed to retrieve UAR info, invalid" 531 " libmlx5.so", 532 dev->data->port_id); 533 rte_errno = EINVAL; 534 goto error; 535 } 536 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next); 537 txq_ibv->txq_ctrl = txq_ctrl; 538 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 539 return txq_ibv; 540 error: 541 ret = rte_errno; /* Save rte_errno before cleanup. */ 542 if (tmpl.cq) 543 claim_zero(mlx5_glue->destroy_cq(tmpl.cq)); 544 if (tmpl.qp) 545 claim_zero(mlx5_glue->destroy_qp(tmpl.qp)); 546 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 547 rte_errno = ret; /* Restore rte_errno. */ 548 return NULL; 549 } 550 551 /** 552 * Get an Tx queue Verbs object. 553 * 554 * @param dev 555 * Pointer to Ethernet device. 556 * @param idx 557 * Queue index in DPDK Rx queue array 558 * 559 * @return 560 * The Verbs object if it exists. 561 */ 562 struct mlx5_txq_ibv * 563 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx) 564 { 565 struct mlx5_priv *priv = dev->data->dev_private; 566 struct mlx5_txq_ctrl *txq_ctrl; 567 568 if (idx >= priv->txqs_n) 569 return NULL; 570 if (!(*priv->txqs)[idx]) 571 return NULL; 572 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); 573 if (txq_ctrl->ibv) 574 rte_atomic32_inc(&txq_ctrl->ibv->refcnt); 575 return txq_ctrl->ibv; 576 } 577 578 /** 579 * Release an Tx verbs queue object. 580 * 581 * @param txq_ibv 582 * Verbs Tx queue object. 583 * 584 * @return 585 * 1 while a reference on it exists, 0 when freed. 586 */ 587 int 588 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv) 589 { 590 assert(txq_ibv); 591 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) { 592 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp)); 593 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq)); 594 LIST_REMOVE(txq_ibv, next); 595 rte_free(txq_ibv); 596 return 0; 597 } 598 return 1; 599 } 600 601 /** 602 * Return true if a single reference exists on the object. 603 * 604 * @param txq_ibv 605 * Verbs Tx queue object. 606 */ 607 int 608 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv) 609 { 610 assert(txq_ibv); 611 return (rte_atomic32_read(&txq_ibv->refcnt) == 1); 612 } 613 614 /** 615 * Verify the Verbs Tx queue list is empty 616 * 617 * @param dev 618 * Pointer to Ethernet device. 619 * 620 * @return 621 * The number of object not released. 622 */ 623 int 624 mlx5_txq_ibv_verify(struct rte_eth_dev *dev) 625 { 626 struct mlx5_priv *priv = dev->data->dev_private; 627 int ret = 0; 628 struct mlx5_txq_ibv *txq_ibv; 629 630 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) { 631 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced", 632 dev->data->port_id, txq_ibv->txq_ctrl->idx); 633 ++ret; 634 } 635 return ret; 636 } 637 638 /** 639 * Set Tx queue parameters from device configuration. 640 * 641 * @param txq_ctrl 642 * Pointer to Tx queue control structure. 643 */ 644 static void 645 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl) 646 { 647 struct mlx5_priv *priv = txq_ctrl->priv; 648 struct mlx5_dev_config *config = &priv->config; 649 const unsigned int max_tso_inline = 650 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) / 651 RTE_CACHE_LINE_SIZE); 652 unsigned int txq_inline; 653 unsigned int txqs_inline; 654 unsigned int inline_max_packet_sz; 655 eth_tx_burst_t tx_pkt_burst = 656 mlx5_select_tx_function(ETH_DEV(priv)); 657 int is_empw_func = is_empw_burst_func(tx_pkt_burst); 658 int tso = !!(txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO | 659 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 660 DEV_TX_OFFLOAD_GRE_TNL_TSO | 661 DEV_TX_OFFLOAD_IP_TNL_TSO | 662 DEV_TX_OFFLOAD_UDP_TNL_TSO)); 663 664 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ? 665 0 : config->txq_inline; 666 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ? 667 0 : config->txqs_inline; 668 inline_max_packet_sz = 669 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ? 670 0 : config->inline_max_packet_sz; 671 if (is_empw_func) { 672 if (config->txq_inline == MLX5_ARG_UNSET) 673 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE; 674 if (config->txqs_inline == MLX5_ARG_UNSET) 675 txqs_inline = MLX5_EMPW_MIN_TXQS; 676 if (config->inline_max_packet_sz == MLX5_ARG_UNSET) 677 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN; 678 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg; 679 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz; 680 } 681 if (txq_inline && priv->txqs_n >= txqs_inline) { 682 unsigned int ds_cnt; 683 684 txq_ctrl->txq.max_inline = 685 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) / 686 RTE_CACHE_LINE_SIZE); 687 if (is_empw_func) { 688 /* To minimize the size of data set, avoid requesting 689 * too large WQ. 690 */ 691 txq_ctrl->max_inline_data = 692 ((RTE_MIN(txq_inline, 693 inline_max_packet_sz) + 694 (RTE_CACHE_LINE_SIZE - 1)) / 695 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE; 696 } else { 697 txq_ctrl->max_inline_data = 698 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE; 699 } 700 /* 701 * Check if the inline size is too large in a way which 702 * can make the WQE DS to overflow. 703 * Considering in calculation: 704 * WQE CTRL (1 DS) 705 * WQE ETH (1 DS) 706 * Inline part (N DS) 707 */ 708 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE); 709 if (ds_cnt > MLX5_DSEG_MAX) { 710 unsigned int max_inline = (MLX5_DSEG_MAX - 2) * 711 MLX5_WQE_DWORD_SIZE; 712 713 max_inline = max_inline - (max_inline % 714 RTE_CACHE_LINE_SIZE); 715 DRV_LOG(WARNING, 716 "port %u txq inline is too large (%d) setting" 717 " it to the maximum possible: %d\n", 718 PORT_ID(priv), txq_inline, max_inline); 719 txq_ctrl->txq.max_inline = max_inline / 720 RTE_CACHE_LINE_SIZE; 721 } 722 } 723 if (tso) { 724 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE; 725 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline, 726 max_tso_inline); 727 txq_ctrl->txq.tso_en = 1; 728 } 729 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp; 730 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO | 731 DEV_TX_OFFLOAD_UDP_TNL_TSO | 732 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) & 733 txq_ctrl->txq.offloads) && config->swp; 734 } 735 736 /** 737 * Create a DPDK Tx queue. 738 * 739 * @param dev 740 * Pointer to Ethernet device. 741 * @param idx 742 * TX queue index. 743 * @param desc 744 * Number of descriptors to configure in queue. 745 * @param socket 746 * NUMA socket on which memory must be allocated. 747 * @param[in] conf 748 * Thresholds parameters. 749 * 750 * @return 751 * A DPDK queue object on success, NULL otherwise and rte_errno is set. 752 */ 753 struct mlx5_txq_ctrl * 754 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 755 unsigned int socket, const struct rte_eth_txconf *conf) 756 { 757 struct mlx5_priv *priv = dev->data->dev_private; 758 struct mlx5_txq_ctrl *tmpl; 759 760 tmpl = rte_calloc_socket("TXQ", 1, 761 sizeof(*tmpl) + 762 desc * sizeof(struct rte_mbuf *), 763 0, socket); 764 if (!tmpl) { 765 rte_errno = ENOMEM; 766 return NULL; 767 } 768 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh, 769 MLX5_MR_BTREE_CACHE_N, socket)) { 770 /* rte_errno is already set. */ 771 goto error; 772 } 773 /* Save pointer of global generation number to check memory event. */ 774 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->mr.dev_gen; 775 assert(desc > MLX5_TX_COMP_THRESH); 776 tmpl->txq.offloads = conf->offloads | 777 dev->data->dev_conf.txmode.offloads; 778 tmpl->priv = priv; 779 tmpl->socket = socket; 780 tmpl->txq.elts_n = log2above(desc); 781 tmpl->idx = idx; 782 txq_set_params(tmpl); 783 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d", 784 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr); 785 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d", 786 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge); 787 tmpl->txq.elts = 788 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1); 789 tmpl->txq.stats.idx = idx; 790 rte_atomic32_inc(&tmpl->refcnt); 791 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next); 792 return tmpl; 793 error: 794 rte_free(tmpl); 795 return NULL; 796 } 797 798 /** 799 * Get a Tx queue. 800 * 801 * @param dev 802 * Pointer to Ethernet device. 803 * @param idx 804 * TX queue index. 805 * 806 * @return 807 * A pointer to the queue if it exists. 808 */ 809 struct mlx5_txq_ctrl * 810 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx) 811 { 812 struct mlx5_priv *priv = dev->data->dev_private; 813 struct mlx5_txq_ctrl *ctrl = NULL; 814 815 if ((*priv->txqs)[idx]) { 816 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, 817 txq); 818 mlx5_txq_ibv_get(dev, idx); 819 rte_atomic32_inc(&ctrl->refcnt); 820 } 821 return ctrl; 822 } 823 824 /** 825 * Release a Tx queue. 826 * 827 * @param dev 828 * Pointer to Ethernet device. 829 * @param idx 830 * TX queue index. 831 * 832 * @return 833 * 1 while a reference on it exists, 0 when freed. 834 */ 835 int 836 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx) 837 { 838 struct mlx5_priv *priv = dev->data->dev_private; 839 struct mlx5_txq_ctrl *txq; 840 size_t page_size = sysconf(_SC_PAGESIZE); 841 842 if (!(*priv->txqs)[idx]) 843 return 0; 844 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); 845 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv)) 846 txq->ibv = NULL; 847 if (priv->uar_base) 848 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg, 849 page_size), page_size); 850 if (rte_atomic32_dec_and_test(&txq->refcnt)) { 851 txq_free_elts(txq); 852 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh); 853 LIST_REMOVE(txq, next); 854 rte_free(txq); 855 (*priv->txqs)[idx] = NULL; 856 return 0; 857 } 858 return 1; 859 } 860 861 /** 862 * Verify if the queue can be released. 863 * 864 * @param dev 865 * Pointer to Ethernet device. 866 * @param idx 867 * TX queue index. 868 * 869 * @return 870 * 1 if the queue can be released. 871 */ 872 int 873 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx) 874 { 875 struct mlx5_priv *priv = dev->data->dev_private; 876 struct mlx5_txq_ctrl *txq; 877 878 if (!(*priv->txqs)[idx]) 879 return -1; 880 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); 881 return (rte_atomic32_read(&txq->refcnt) == 1); 882 } 883 884 /** 885 * Verify the Tx Queue list is empty 886 * 887 * @param dev 888 * Pointer to Ethernet device. 889 * 890 * @return 891 * The number of object not released. 892 */ 893 int 894 mlx5_txq_verify(struct rte_eth_dev *dev) 895 { 896 struct mlx5_priv *priv = dev->data->dev_private; 897 struct mlx5_txq_ctrl *txq; 898 int ret = 0; 899 900 LIST_FOREACH(txq, &priv->txqsctrl, next) { 901 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced", 902 dev->data->port_id, txq->idx); 903 ++ret; 904 } 905 return ret; 906 } 907