1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <unistd.h> 7 8 #include <rte_ether.h> 9 #include <rte_ethdev_driver.h> 10 #include <rte_interrupts.h> 11 #include <rte_alarm.h> 12 13 #include "mlx5.h" 14 #include "mlx5_mr.h" 15 #include "mlx5_rxtx.h" 16 #include "mlx5_utils.h" 17 #include "rte_pmd_mlx5.h" 18 19 /** 20 * Stop traffic on Tx queues. 21 * 22 * @param dev 23 * Pointer to Ethernet device structure. 24 */ 25 static void 26 mlx5_txq_stop(struct rte_eth_dev *dev) 27 { 28 struct mlx5_priv *priv = dev->data->dev_private; 29 unsigned int i; 30 31 for (i = 0; i != priv->txqs_n; ++i) 32 mlx5_txq_release(dev, i); 33 } 34 35 /** 36 * Start traffic on Tx queues. 37 * 38 * @param dev 39 * Pointer to Ethernet device structure. 40 * 41 * @return 42 * 0 on success, a negative errno value otherwise and rte_errno is set. 43 */ 44 static int 45 mlx5_txq_start(struct rte_eth_dev *dev) 46 { 47 struct mlx5_priv *priv = dev->data->dev_private; 48 unsigned int i; 49 int ret; 50 51 for (i = 0; i != priv->txqs_n; ++i) { 52 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i); 53 54 if (!txq_ctrl) 55 continue; 56 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 57 txq_ctrl->obj = mlx5_txq_obj_new 58 (dev, i, MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN); 59 } else { 60 txq_alloc_elts(txq_ctrl); 61 txq_ctrl->obj = mlx5_txq_obj_new 62 (dev, i, MLX5_TXQ_OBJ_TYPE_IBV); 63 } 64 if (!txq_ctrl->obj) { 65 rte_errno = ENOMEM; 66 goto error; 67 } 68 } 69 return 0; 70 error: 71 ret = rte_errno; /* Save rte_errno before cleanup. */ 72 do { 73 mlx5_txq_release(dev, i); 74 } while (i-- != 0); 75 rte_errno = ret; /* Restore rte_errno. */ 76 return -rte_errno; 77 } 78 79 /** 80 * Stop traffic on Rx queues. 81 * 82 * @param dev 83 * Pointer to Ethernet device structure. 84 */ 85 static void 86 mlx5_rxq_stop(struct rte_eth_dev *dev) 87 { 88 struct mlx5_priv *priv = dev->data->dev_private; 89 unsigned int i; 90 91 for (i = 0; i != priv->rxqs_n; ++i) 92 mlx5_rxq_release(dev, i); 93 } 94 95 /** 96 * Start traffic on Rx queues. 97 * 98 * @param dev 99 * Pointer to Ethernet device structure. 100 * 101 * @return 102 * 0 on success, a negative errno value otherwise and rte_errno is set. 103 */ 104 static int 105 mlx5_rxq_start(struct rte_eth_dev *dev) 106 { 107 struct mlx5_priv *priv = dev->data->dev_private; 108 unsigned int i; 109 int ret = 0; 110 enum mlx5_rxq_obj_type obj_type = MLX5_RXQ_OBJ_TYPE_IBV; 111 struct mlx5_rxq_data *rxq = NULL; 112 113 for (i = 0; i < priv->rxqs_n; ++i) { 114 rxq = (*priv->rxqs)[i]; 115 if (rxq && rxq->lro) { 116 obj_type = MLX5_RXQ_OBJ_TYPE_DEVX_RQ; 117 break; 118 } 119 } 120 /* Allocate/reuse/resize mempool for Multi-Packet RQ. */ 121 if (mlx5_mprq_alloc_mp(dev)) { 122 /* Should not release Rx queues but return immediately. */ 123 return -rte_errno; 124 } 125 for (i = 0; i != priv->rxqs_n; ++i) { 126 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i); 127 struct rte_mempool *mp; 128 129 if (!rxq_ctrl) 130 continue; 131 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) { 132 rxq_ctrl->obj = mlx5_rxq_obj_new 133 (dev, i, MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN); 134 if (!rxq_ctrl->obj) 135 goto error; 136 continue; 137 } 138 /* Pre-register Rx mempool. */ 139 mp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ? 140 rxq_ctrl->rxq.mprq_mp : rxq_ctrl->rxq.mp; 141 DRV_LOG(DEBUG, 142 "port %u Rx queue %u registering" 143 " mp %s having %u chunks", 144 dev->data->port_id, rxq_ctrl->rxq.idx, 145 mp->name, mp->nb_mem_chunks); 146 mlx5_mr_update_mp(dev, &rxq_ctrl->rxq.mr_ctrl, mp); 147 ret = rxq_alloc_elts(rxq_ctrl); 148 if (ret) 149 goto error; 150 rxq_ctrl->obj = mlx5_rxq_obj_new(dev, i, obj_type); 151 if (!rxq_ctrl->obj) 152 goto error; 153 if (obj_type == MLX5_RXQ_OBJ_TYPE_IBV) 154 rxq_ctrl->wqn = rxq_ctrl->obj->wq->wq_num; 155 else if (obj_type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) 156 rxq_ctrl->wqn = rxq_ctrl->obj->rq->id; 157 } 158 return 0; 159 error: 160 ret = rte_errno; /* Save rte_errno before cleanup. */ 161 do { 162 mlx5_rxq_release(dev, i); 163 } while (i-- != 0); 164 rte_errno = ret; /* Restore rte_errno. */ 165 return -rte_errno; 166 } 167 168 /** 169 * Binds Tx queues to Rx queues for hairpin. 170 * 171 * Binds Tx queues to the target Rx queues. 172 * 173 * @param dev 174 * Pointer to Ethernet device structure. 175 * 176 * @return 177 * 0 on success, a negative errno value otherwise and rte_errno is set. 178 */ 179 static int 180 mlx5_hairpin_bind(struct rte_eth_dev *dev) 181 { 182 struct mlx5_priv *priv = dev->data->dev_private; 183 struct mlx5_devx_modify_sq_attr sq_attr = { 0 }; 184 struct mlx5_devx_modify_rq_attr rq_attr = { 0 }; 185 struct mlx5_txq_ctrl *txq_ctrl; 186 struct mlx5_rxq_ctrl *rxq_ctrl; 187 struct mlx5_devx_obj *sq; 188 struct mlx5_devx_obj *rq; 189 unsigned int i; 190 int ret = 0; 191 192 for (i = 0; i != priv->txqs_n; ++i) { 193 txq_ctrl = mlx5_txq_get(dev, i); 194 if (!txq_ctrl) 195 continue; 196 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) { 197 mlx5_txq_release(dev, i); 198 continue; 199 } 200 if (!txq_ctrl->obj) { 201 rte_errno = ENOMEM; 202 DRV_LOG(ERR, "port %u no txq object found: %d", 203 dev->data->port_id, i); 204 mlx5_txq_release(dev, i); 205 return -rte_errno; 206 } 207 sq = txq_ctrl->obj->sq; 208 rxq_ctrl = mlx5_rxq_get(dev, 209 txq_ctrl->hairpin_conf.peers[0].queue); 210 if (!rxq_ctrl) { 211 mlx5_txq_release(dev, i); 212 rte_errno = EINVAL; 213 DRV_LOG(ERR, "port %u no rxq object found: %d", 214 dev->data->port_id, 215 txq_ctrl->hairpin_conf.peers[0].queue); 216 return -rte_errno; 217 } 218 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN || 219 rxq_ctrl->hairpin_conf.peers[0].queue != i) { 220 rte_errno = ENOMEM; 221 DRV_LOG(ERR, "port %u Tx queue %d can't be binded to " 222 "Rx queue %d", dev->data->port_id, 223 i, txq_ctrl->hairpin_conf.peers[0].queue); 224 goto error; 225 } 226 rq = rxq_ctrl->obj->rq; 227 if (!rq) { 228 rte_errno = ENOMEM; 229 DRV_LOG(ERR, "port %u hairpin no matching rxq: %d", 230 dev->data->port_id, 231 txq_ctrl->hairpin_conf.peers[0].queue); 232 goto error; 233 } 234 sq_attr.state = MLX5_SQC_STATE_RDY; 235 sq_attr.sq_state = MLX5_SQC_STATE_RST; 236 sq_attr.hairpin_peer_rq = rq->id; 237 sq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id; 238 ret = mlx5_devx_cmd_modify_sq(sq, &sq_attr); 239 if (ret) 240 goto error; 241 rq_attr.state = MLX5_SQC_STATE_RDY; 242 rq_attr.rq_state = MLX5_SQC_STATE_RST; 243 rq_attr.hairpin_peer_sq = sq->id; 244 rq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id; 245 ret = mlx5_devx_cmd_modify_rq(rq, &rq_attr); 246 if (ret) 247 goto error; 248 mlx5_txq_release(dev, i); 249 mlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue); 250 } 251 return 0; 252 error: 253 mlx5_txq_release(dev, i); 254 mlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue); 255 return -rte_errno; 256 } 257 258 /** 259 * DPDK callback to start the device. 260 * 261 * Simulate device start by attaching all configured flows. 262 * 263 * @param dev 264 * Pointer to Ethernet device structure. 265 * 266 * @return 267 * 0 on success, a negative errno value otherwise and rte_errno is set. 268 */ 269 int 270 mlx5_dev_start(struct rte_eth_dev *dev) 271 { 272 int ret; 273 int fine_inline; 274 275 DRV_LOG(DEBUG, "port %u starting device", dev->data->port_id); 276 fine_inline = rte_mbuf_dynflag_lookup 277 (RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, NULL); 278 if (fine_inline > 0) 279 rte_net_mlx5_dynf_inline_mask = 1UL << fine_inline; 280 else 281 rte_net_mlx5_dynf_inline_mask = 0; 282 if (dev->data->nb_rx_queues > 0) { 283 ret = mlx5_dev_configure_rss_reta(dev); 284 if (ret) { 285 DRV_LOG(ERR, "port %u reta config failed: %s", 286 dev->data->port_id, strerror(rte_errno)); 287 return -rte_errno; 288 } 289 } 290 ret = mlx5_txq_start(dev); 291 if (ret) { 292 DRV_LOG(ERR, "port %u Tx queue allocation failed: %s", 293 dev->data->port_id, strerror(rte_errno)); 294 return -rte_errno; 295 } 296 ret = mlx5_rxq_start(dev); 297 if (ret) { 298 DRV_LOG(ERR, "port %u Rx queue allocation failed: %s", 299 dev->data->port_id, strerror(rte_errno)); 300 mlx5_txq_stop(dev); 301 return -rte_errno; 302 } 303 ret = mlx5_hairpin_bind(dev); 304 if (ret) { 305 DRV_LOG(ERR, "port %u hairpin binding failed: %s", 306 dev->data->port_id, strerror(rte_errno)); 307 mlx5_txq_stop(dev); 308 return -rte_errno; 309 } 310 /* Set started flag here for the following steps like control flow. */ 311 dev->data->dev_started = 1; 312 ret = mlx5_rx_intr_vec_enable(dev); 313 if (ret) { 314 DRV_LOG(ERR, "port %u Rx interrupt vector creation failed", 315 dev->data->port_id); 316 goto error; 317 } 318 mlx5_stats_init(dev); 319 ret = mlx5_traffic_enable(dev); 320 if (ret) { 321 DRV_LOG(ERR, "port %u failed to set defaults flows", 322 dev->data->port_id); 323 goto error; 324 } 325 /* Set a mask and offset of dynamic metadata flows into Rx queues*/ 326 mlx5_flow_rxq_dynf_metadata_set(dev); 327 /* 328 * In non-cached mode, it only needs to start the default mreg copy 329 * action and no flow created by application exists anymore. 330 * But it is worth wrapping the interface for further usage. 331 */ 332 ret = mlx5_flow_start_default(dev); 333 if (ret) { 334 DRV_LOG(DEBUG, "port %u failed to start default actions: %s", 335 dev->data->port_id, strerror(rte_errno)); 336 goto error; 337 } 338 rte_wmb(); 339 dev->tx_pkt_burst = mlx5_select_tx_function(dev); 340 dev->rx_pkt_burst = mlx5_select_rx_function(dev); 341 /* Enable datapath on secondary process. */ 342 mlx5_mp_req_start_rxtx(dev); 343 mlx5_dev_interrupt_handler_install(dev); 344 return 0; 345 error: 346 ret = rte_errno; /* Save rte_errno before cleanup. */ 347 /* Rollback. */ 348 dev->data->dev_started = 0; 349 mlx5_flow_stop_default(dev); 350 mlx5_traffic_disable(dev); 351 mlx5_txq_stop(dev); 352 mlx5_rxq_stop(dev); 353 rte_errno = ret; /* Restore rte_errno. */ 354 return -rte_errno; 355 } 356 357 /** 358 * DPDK callback to stop the device. 359 * 360 * Simulate device stop by detaching all configured flows. 361 * 362 * @param dev 363 * Pointer to Ethernet device structure. 364 */ 365 void 366 mlx5_dev_stop(struct rte_eth_dev *dev) 367 { 368 struct mlx5_priv *priv = dev->data->dev_private; 369 370 dev->data->dev_started = 0; 371 /* Prevent crashes when queues are still in use. */ 372 dev->rx_pkt_burst = removed_rx_burst; 373 dev->tx_pkt_burst = removed_tx_burst; 374 rte_wmb(); 375 /* Disable datapath on secondary process. */ 376 mlx5_mp_req_stop_rxtx(dev); 377 usleep(1000 * priv->rxqs_n); 378 DRV_LOG(DEBUG, "port %u stopping device", dev->data->port_id); 379 mlx5_flow_stop_default(dev); 380 /* Control flows for default traffic can be removed firstly. */ 381 mlx5_traffic_disable(dev); 382 /* All RX queue flags will be cleared in the flush interface. */ 383 mlx5_flow_list_flush(dev, &priv->flows, true); 384 mlx5_rx_intr_vec_disable(dev); 385 mlx5_dev_interrupt_handler_uninstall(dev); 386 mlx5_txq_stop(dev); 387 mlx5_rxq_stop(dev); 388 } 389 390 /** 391 * Enable traffic flows configured by control plane 392 * 393 * @param dev 394 * Pointer to Ethernet device private data. 395 * @param dev 396 * Pointer to Ethernet device structure. 397 * 398 * @return 399 * 0 on success, a negative errno value otherwise and rte_errno is set. 400 */ 401 int 402 mlx5_traffic_enable(struct rte_eth_dev *dev) 403 { 404 struct mlx5_priv *priv = dev->data->dev_private; 405 struct rte_flow_item_eth bcast = { 406 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 407 }; 408 struct rte_flow_item_eth ipv6_multi_spec = { 409 .dst.addr_bytes = "\x33\x33\x00\x00\x00\x00", 410 }; 411 struct rte_flow_item_eth ipv6_multi_mask = { 412 .dst.addr_bytes = "\xff\xff\x00\x00\x00\x00", 413 }; 414 struct rte_flow_item_eth unicast = { 415 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 416 }; 417 struct rte_flow_item_eth unicast_mask = { 418 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 419 }; 420 const unsigned int vlan_filter_n = priv->vlan_filter_n; 421 const struct rte_ether_addr cmp = { 422 .addr_bytes = "\x00\x00\x00\x00\x00\x00", 423 }; 424 unsigned int i; 425 unsigned int j; 426 int ret; 427 428 /* 429 * Hairpin txq default flow should be created no matter if it is 430 * isolation mode. Or else all the packets to be sent will be sent 431 * out directly without the TX flow actions, e.g. encapsulation. 432 */ 433 for (i = 0; i != priv->txqs_n; ++i) { 434 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i); 435 if (!txq_ctrl) 436 continue; 437 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 438 ret = mlx5_ctrl_flow_source_queue(dev, i); 439 if (ret) { 440 mlx5_txq_release(dev, i); 441 goto error; 442 } 443 } 444 mlx5_txq_release(dev, i); 445 } 446 if (priv->config.dv_esw_en && !priv->config.vf) { 447 if (mlx5_flow_create_esw_table_zero_flow(dev)) 448 priv->fdb_def_rule = 1; 449 else 450 DRV_LOG(INFO, "port %u FDB default rule cannot be" 451 " configured - only Eswitch group 0 flows are" 452 " supported.", dev->data->port_id); 453 } 454 if (priv->isolated) 455 return 0; 456 if (dev->data->promiscuous) { 457 struct rte_flow_item_eth promisc = { 458 .dst.addr_bytes = "\x00\x00\x00\x00\x00\x00", 459 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 460 .type = 0, 461 }; 462 463 ret = mlx5_ctrl_flow(dev, &promisc, &promisc); 464 if (ret) 465 goto error; 466 } 467 if (dev->data->all_multicast) { 468 struct rte_flow_item_eth multicast = { 469 .dst.addr_bytes = "\x01\x00\x00\x00\x00\x00", 470 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 471 .type = 0, 472 }; 473 474 ret = mlx5_ctrl_flow(dev, &multicast, &multicast); 475 if (ret) 476 goto error; 477 } else { 478 /* Add broadcast/multicast flows. */ 479 for (i = 0; i != vlan_filter_n; ++i) { 480 uint16_t vlan = priv->vlan_filter[i]; 481 482 struct rte_flow_item_vlan vlan_spec = { 483 .tci = rte_cpu_to_be_16(vlan), 484 }; 485 struct rte_flow_item_vlan vlan_mask = 486 rte_flow_item_vlan_mask; 487 488 ret = mlx5_ctrl_flow_vlan(dev, &bcast, &bcast, 489 &vlan_spec, &vlan_mask); 490 if (ret) 491 goto error; 492 ret = mlx5_ctrl_flow_vlan(dev, &ipv6_multi_spec, 493 &ipv6_multi_mask, 494 &vlan_spec, &vlan_mask); 495 if (ret) 496 goto error; 497 } 498 if (!vlan_filter_n) { 499 ret = mlx5_ctrl_flow(dev, &bcast, &bcast); 500 if (ret) 501 goto error; 502 ret = mlx5_ctrl_flow(dev, &ipv6_multi_spec, 503 &ipv6_multi_mask); 504 if (ret) 505 goto error; 506 } 507 } 508 /* Add MAC address flows. */ 509 for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) { 510 struct rte_ether_addr *mac = &dev->data->mac_addrs[i]; 511 512 if (!memcmp(mac, &cmp, sizeof(*mac))) 513 continue; 514 memcpy(&unicast.dst.addr_bytes, 515 mac->addr_bytes, 516 RTE_ETHER_ADDR_LEN); 517 for (j = 0; j != vlan_filter_n; ++j) { 518 uint16_t vlan = priv->vlan_filter[j]; 519 520 struct rte_flow_item_vlan vlan_spec = { 521 .tci = rte_cpu_to_be_16(vlan), 522 }; 523 struct rte_flow_item_vlan vlan_mask = 524 rte_flow_item_vlan_mask; 525 526 ret = mlx5_ctrl_flow_vlan(dev, &unicast, 527 &unicast_mask, 528 &vlan_spec, 529 &vlan_mask); 530 if (ret) 531 goto error; 532 } 533 if (!vlan_filter_n) { 534 ret = mlx5_ctrl_flow(dev, &unicast, &unicast_mask); 535 if (ret) 536 goto error; 537 } 538 } 539 return 0; 540 error: 541 ret = rte_errno; /* Save rte_errno before cleanup. */ 542 mlx5_flow_list_flush(dev, &priv->ctrl_flows, false); 543 rte_errno = ret; /* Restore rte_errno. */ 544 return -rte_errno; 545 } 546 547 548 /** 549 * Disable traffic flows configured by control plane 550 * 551 * @param dev 552 * Pointer to Ethernet device private data. 553 */ 554 void 555 mlx5_traffic_disable(struct rte_eth_dev *dev) 556 { 557 struct mlx5_priv *priv = dev->data->dev_private; 558 559 mlx5_flow_list_flush(dev, &priv->ctrl_flows, false); 560 } 561 562 /** 563 * Restart traffic flows configured by control plane 564 * 565 * @param dev 566 * Pointer to Ethernet device private data. 567 * 568 * @return 569 * 0 on success, a negative errno value otherwise and rte_errno is set. 570 */ 571 int 572 mlx5_traffic_restart(struct rte_eth_dev *dev) 573 { 574 if (dev->data->dev_started) { 575 mlx5_traffic_disable(dev); 576 return mlx5_traffic_enable(dev); 577 } 578 return 0; 579 } 580