1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox. 4 */ 5 6 #include <unistd.h> 7 8 #include <rte_ether.h> 9 #include <rte_ethdev_driver.h> 10 #include <rte_interrupts.h> 11 #include <rte_alarm.h> 12 13 #include "mlx5.h" 14 #include "mlx5_rxtx.h" 15 #include "mlx5_utils.h" 16 17 /** 18 * Stop traffic on Tx queues. 19 * 20 * @param dev 21 * Pointer to Ethernet device structure. 22 */ 23 static void 24 mlx5_txq_stop(struct rte_eth_dev *dev) 25 { 26 struct priv *priv = dev->data->dev_private; 27 unsigned int i; 28 29 for (i = 0; i != priv->txqs_n; ++i) 30 mlx5_txq_release(dev, i); 31 } 32 33 /** 34 * Start traffic on Tx queues. 35 * 36 * @param dev 37 * Pointer to Ethernet device structure. 38 * 39 * @return 40 * 0 on success, a negative errno value otherwise and rte_errno is set. 41 */ 42 static int 43 mlx5_txq_start(struct rte_eth_dev *dev) 44 { 45 struct priv *priv = dev->data->dev_private; 46 unsigned int i; 47 int ret; 48 49 /* Add memory regions to Tx queues. */ 50 for (i = 0; i != priv->txqs_n; ++i) { 51 unsigned int idx = 0; 52 struct mlx5_mr *mr; 53 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i); 54 55 if (!txq_ctrl) 56 continue; 57 LIST_FOREACH(mr, &priv->mr, next) { 58 mlx5_txq_mp2mr_reg(&txq_ctrl->txq, mr->mp, idx++); 59 if (idx == MLX5_PMD_TX_MP_CACHE) 60 break; 61 } 62 txq_alloc_elts(txq_ctrl); 63 txq_ctrl->ibv = mlx5_txq_ibv_new(dev, i); 64 if (!txq_ctrl->ibv) { 65 rte_errno = ENOMEM; 66 goto error; 67 } 68 } 69 ret = mlx5_tx_uar_remap(dev, priv->ctx->cmd_fd); 70 if (ret) 71 goto error; 72 return 0; 73 error: 74 ret = rte_errno; /* Save rte_errno before cleanup. */ 75 mlx5_txq_stop(dev); 76 rte_errno = ret; /* Restore rte_errno. */ 77 return -rte_errno; 78 } 79 80 /** 81 * Stop traffic on Rx queues. 82 * 83 * @param dev 84 * Pointer to Ethernet device structure. 85 */ 86 static void 87 mlx5_rxq_stop(struct rte_eth_dev *dev) 88 { 89 struct priv *priv = dev->data->dev_private; 90 unsigned int i; 91 92 for (i = 0; i != priv->rxqs_n; ++i) 93 mlx5_rxq_release(dev, i); 94 } 95 96 /** 97 * Start traffic on Rx queues. 98 * 99 * @param dev 100 * Pointer to Ethernet device structure. 101 * 102 * @return 103 * 0 on success, a negative errno value otherwise and rte_errno is set. 104 */ 105 static int 106 mlx5_rxq_start(struct rte_eth_dev *dev) 107 { 108 struct priv *priv = dev->data->dev_private; 109 unsigned int i; 110 int ret = 0; 111 112 for (i = 0; i != priv->rxqs_n; ++i) { 113 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i); 114 115 if (!rxq_ctrl) 116 continue; 117 ret = rxq_alloc_elts(rxq_ctrl); 118 if (ret) 119 goto error; 120 rxq_ctrl->ibv = mlx5_rxq_ibv_new(dev, i); 121 if (!rxq_ctrl->ibv) 122 goto error; 123 } 124 return 0; 125 error: 126 ret = rte_errno; /* Save rte_errno before cleanup. */ 127 mlx5_rxq_stop(dev); 128 rte_errno = ret; /* Restore rte_errno. */ 129 return -rte_errno; 130 } 131 132 /** 133 * DPDK callback to start the device. 134 * 135 * Simulate device start by attaching all configured flows. 136 * 137 * @param dev 138 * Pointer to Ethernet device structure. 139 * 140 * @return 141 * 0 on success, a negative errno value otherwise and rte_errno is set. 142 */ 143 int 144 mlx5_dev_start(struct rte_eth_dev *dev) 145 { 146 struct priv *priv = dev->data->dev_private; 147 struct mlx5_mr *mr = NULL; 148 int ret; 149 150 dev->data->dev_started = 1; 151 ret = mlx5_flow_create_drop_queue(dev); 152 if (ret) { 153 ERROR("%p: Drop queue allocation failed: %s", 154 (void *)dev, strerror(rte_errno)); 155 goto error; 156 } 157 DEBUG("%p: allocating and configuring hash RX queues", (void *)dev); 158 rte_mempool_walk(mlx5_mp2mr_iter, priv); 159 ret = mlx5_txq_start(dev); 160 if (ret) { 161 ERROR("%p: Tx Queue allocation failed: %s", 162 (void *)dev, strerror(rte_errno)); 163 goto error; 164 } 165 ret = mlx5_rxq_start(dev); 166 if (ret) { 167 ERROR("%p: Rx Queue allocation failed: %s", 168 (void *)dev, strerror(rte_errno)); 169 goto error; 170 } 171 ret = mlx5_rx_intr_vec_enable(dev); 172 if (ret) { 173 ERROR("%p: Rx interrupt vector creation failed", 174 (void *)dev); 175 goto error; 176 } 177 mlx5_xstats_init(dev); 178 /* Update link status and Tx/Rx callbacks for the first time. */ 179 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 180 INFO("Forcing port %u link to be up", dev->data->port_id); 181 ret = mlx5_force_link_status_change(dev, ETH_LINK_UP); 182 if (ret) { 183 DEBUG("Failed to set port %u link to be up", 184 dev->data->port_id); 185 goto error; 186 } 187 mlx5_dev_interrupt_handler_install(dev); 188 return 0; 189 error: 190 ret = rte_errno; /* Save rte_errno before cleanup. */ 191 /* Rollback. */ 192 dev->data->dev_started = 0; 193 for (mr = LIST_FIRST(&priv->mr); mr; mr = LIST_FIRST(&priv->mr)) 194 mlx5_mr_release(mr); 195 mlx5_flow_stop(dev, &priv->flows); 196 mlx5_traffic_disable(dev); 197 mlx5_txq_stop(dev); 198 mlx5_rxq_stop(dev); 199 mlx5_flow_delete_drop_queue(dev); 200 rte_errno = ret; /* Restore rte_errno. */ 201 return -rte_errno; 202 } 203 204 /** 205 * DPDK callback to stop the device. 206 * 207 * Simulate device stop by detaching all configured flows. 208 * 209 * @param dev 210 * Pointer to Ethernet device structure. 211 */ 212 void 213 mlx5_dev_stop(struct rte_eth_dev *dev) 214 { 215 struct priv *priv = dev->data->dev_private; 216 struct mlx5_mr *mr; 217 218 dev->data->dev_started = 0; 219 /* Prevent crashes when queues are still in use. */ 220 dev->rx_pkt_burst = removed_rx_burst; 221 dev->tx_pkt_burst = removed_tx_burst; 222 rte_wmb(); 223 usleep(1000 * priv->rxqs_n); 224 DEBUG("%p: cleaning up and destroying hash RX queues", (void *)dev); 225 mlx5_flow_stop(dev, &priv->flows); 226 mlx5_traffic_disable(dev); 227 mlx5_rx_intr_vec_disable(dev); 228 mlx5_dev_interrupt_handler_uninstall(dev); 229 mlx5_txq_stop(dev); 230 mlx5_rxq_stop(dev); 231 for (mr = LIST_FIRST(&priv->mr); mr; mr = LIST_FIRST(&priv->mr)) 232 mlx5_mr_release(mr); 233 mlx5_flow_delete_drop_queue(dev); 234 } 235 236 /** 237 * Enable traffic flows configured by control plane 238 * 239 * @param dev 240 * Pointer to Ethernet device private data. 241 * @param dev 242 * Pointer to Ethernet device structure. 243 * 244 * @return 245 * 0 on success, a negative errno value otherwise and rte_errno is set. 246 */ 247 int 248 mlx5_traffic_enable(struct rte_eth_dev *dev) 249 { 250 struct priv *priv = dev->data->dev_private; 251 struct rte_flow_item_eth bcast = { 252 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 253 }; 254 struct rte_flow_item_eth ipv6_multi_spec = { 255 .dst.addr_bytes = "\x33\x33\x00\x00\x00\x00", 256 }; 257 struct rte_flow_item_eth ipv6_multi_mask = { 258 .dst.addr_bytes = "\xff\xff\x00\x00\x00\x00", 259 }; 260 struct rte_flow_item_eth unicast = { 261 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 262 }; 263 struct rte_flow_item_eth unicast_mask = { 264 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 265 }; 266 const unsigned int vlan_filter_n = priv->vlan_filter_n; 267 const struct ether_addr cmp = { 268 .addr_bytes = "\x00\x00\x00\x00\x00\x00", 269 }; 270 unsigned int i; 271 unsigned int j; 272 int ret; 273 274 if (priv->isolated) 275 return 0; 276 if (dev->data->promiscuous) { 277 struct rte_flow_item_eth promisc = { 278 .dst.addr_bytes = "\x00\x00\x00\x00\x00\x00", 279 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 280 .type = 0, 281 }; 282 283 ret = mlx5_ctrl_flow(dev, &promisc, &promisc); 284 if (ret) 285 goto error; 286 } 287 if (dev->data->all_multicast) { 288 struct rte_flow_item_eth multicast = { 289 .dst.addr_bytes = "\x01\x00\x00\x00\x00\x00", 290 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 291 .type = 0, 292 }; 293 294 ret = mlx5_ctrl_flow(dev, &multicast, &multicast); 295 if (ret) 296 goto error; 297 } else { 298 /* Add broadcast/multicast flows. */ 299 for (i = 0; i != vlan_filter_n; ++i) { 300 uint16_t vlan = priv->vlan_filter[i]; 301 302 struct rte_flow_item_vlan vlan_spec = { 303 .tci = rte_cpu_to_be_16(vlan), 304 }; 305 struct rte_flow_item_vlan vlan_mask = { 306 .tci = 0xffff, 307 }; 308 309 ret = mlx5_ctrl_flow_vlan(dev, &bcast, &bcast, 310 &vlan_spec, &vlan_mask); 311 if (ret) 312 goto error; 313 ret = mlx5_ctrl_flow_vlan(dev, &ipv6_multi_spec, 314 &ipv6_multi_mask, 315 &vlan_spec, &vlan_mask); 316 if (ret) 317 goto error; 318 } 319 if (!vlan_filter_n) { 320 ret = mlx5_ctrl_flow(dev, &bcast, &bcast); 321 if (ret) 322 goto error; 323 ret = mlx5_ctrl_flow(dev, &ipv6_multi_spec, 324 &ipv6_multi_mask); 325 if (ret) 326 goto error; 327 } 328 } 329 /* Add MAC address flows. */ 330 for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) { 331 struct ether_addr *mac = &dev->data->mac_addrs[i]; 332 333 if (!memcmp(mac, &cmp, sizeof(*mac))) 334 continue; 335 memcpy(&unicast.dst.addr_bytes, 336 mac->addr_bytes, 337 ETHER_ADDR_LEN); 338 for (j = 0; j != vlan_filter_n; ++j) { 339 uint16_t vlan = priv->vlan_filter[j]; 340 341 struct rte_flow_item_vlan vlan_spec = { 342 .tci = rte_cpu_to_be_16(vlan), 343 }; 344 struct rte_flow_item_vlan vlan_mask = { 345 .tci = 0xffff, 346 }; 347 348 ret = mlx5_ctrl_flow_vlan(dev, &unicast, 349 &unicast_mask, 350 &vlan_spec, 351 &vlan_mask); 352 if (ret) 353 goto error; 354 } 355 if (!vlan_filter_n) { 356 ret = mlx5_ctrl_flow(dev, &unicast, &unicast_mask); 357 if (ret) 358 goto error; 359 } 360 } 361 return 0; 362 error: 363 ret = rte_errno; /* Save rte_errno before cleanup. */ 364 mlx5_flow_list_flush(dev, &priv->ctrl_flows); 365 rte_errno = ret; /* Restore rte_errno. */ 366 return -rte_errno; 367 } 368 369 370 /** 371 * Disable traffic flows configured by control plane 372 * 373 * @param dev 374 * Pointer to Ethernet device private data. 375 */ 376 void 377 mlx5_traffic_disable(struct rte_eth_dev *dev) 378 { 379 struct priv *priv = dev->data->dev_private; 380 381 mlx5_flow_list_flush(dev, &priv->ctrl_flows); 382 } 383 384 /** 385 * Restart traffic flows configured by control plane 386 * 387 * @param dev 388 * Pointer to Ethernet device private data. 389 * 390 * @return 391 * 0 on success, a negative errno value otherwise and rte_errno is set. 392 */ 393 int 394 mlx5_traffic_restart(struct rte_eth_dev *dev) 395 { 396 if (dev->data->dev_started) { 397 mlx5_traffic_disable(dev); 398 return mlx5_traffic_enable(dev); 399 } 400 return 0; 401 } 402