1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <smmintrin.h> 13 14 #include <rte_mbuf.h> 15 #include <rte_mempool.h> 16 #include <rte_prefetch.h> 17 18 #include <mlx5_prm.h> 19 20 #include "mlx5_defs.h" 21 #include "mlx5.h" 22 #include "mlx5_utils.h" 23 #include "mlx5_rxtx.h" 24 #include "mlx5_rxtx_vec.h" 25 #include "mlx5_autoconf.h" 26 27 #ifndef __INTEL_COMPILER 28 #pragma GCC diagnostic ignored "-Wcast-qual" 29 #endif 30 31 /** 32 * Store free buffers to RX SW ring. 33 * 34 * @param rxq 35 * Pointer to RX queue structure. 36 * @param pkts 37 * Pointer to array of packets to be stored. 38 * @param pkts_n 39 * Number of packets to be stored. 40 */ 41 static inline void 42 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 43 { 44 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 45 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 46 unsigned int pos; 47 uint16_t p = n & -2; 48 49 for (pos = 0; pos < p; pos += 2) { 50 __m128i mbp; 51 52 mbp = _mm_loadu_si128((__m128i *)&elts[pos]); 53 _mm_storeu_si128((__m128i *)&pkts[pos], mbp); 54 } 55 if (n & 1) 56 pkts[pos] = elts[pos]; 57 } 58 59 /** 60 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 61 * extracted from the title completion descriptor. 62 * 63 * @param rxq 64 * Pointer to RX queue structure. 65 * @param cq 66 * Pointer to completion array having a compressed completion at first. 67 * @param elts 68 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 69 * the title completion descriptor to be copied to the rest of mbufs. 70 * 71 * @return 72 * Number of mini-CQEs successfully decompressed. 73 */ 74 static inline uint16_t 75 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 76 struct rte_mbuf **elts) 77 { 78 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1); 79 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 80 unsigned int pos; 81 unsigned int i; 82 unsigned int inv = 0; 83 /* Mask to shuffle from extracted mini CQE to mbuf. */ 84 const __m128i shuf_mask1 = 85 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */ 86 -1, -1, /* skip vlan_tci */ 87 6, 7, /* data_len, bswap16 */ 88 -1, -1, 6, 7, /* pkt_len, bswap16 */ 89 -1, -1, -1, -1 /* skip packet_type */); 90 const __m128i shuf_mask2 = 91 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */ 92 -1, -1, /* skip vlan_tci */ 93 14, 15, /* data_len, bswap16 */ 94 -1, -1, 14, 15, /* pkt_len, bswap16 */ 95 -1, -1, -1, -1 /* skip packet_type */); 96 /* Restore the compressed count. Must be 16 bits. */ 97 const uint16_t mcqe_n = t_pkt->data_len + 98 (rxq->crc_present * RTE_ETHER_CRC_LEN); 99 const __m128i rearm = 100 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data); 101 const __m128i rxdf = 102 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1); 103 const __m128i crc_adj = 104 _mm_set_epi16(0, 0, 0, 105 rxq->crc_present * RTE_ETHER_CRC_LEN, 106 0, 107 rxq->crc_present * RTE_ETHER_CRC_LEN, 108 0, 0); 109 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 110 #ifdef MLX5_PMD_SOFT_COUNTERS 111 const __m128i zero = _mm_setzero_si128(); 112 const __m128i ones = _mm_cmpeq_epi32(zero, zero); 113 uint32_t rcvd_byte = 0; 114 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 115 const __m128i len_shuf_mask = 116 _mm_set_epi8(-1, -1, -1, -1, 117 -1, -1, -1, -1, 118 14, 15, 6, 7, 119 10, 11, 2, 3); 120 #endif 121 /* 122 * A. load mCQEs into a 128bit register. 123 * B. store rearm data to mbuf. 124 * C. combine data from mCQEs with rx_descriptor_fields1. 125 * D. store rx_descriptor_fields1. 126 * E. store flow tag (rte_flow mark). 127 */ 128 for (pos = 0; pos < mcqe_n; ) { 129 __m128i mcqe1, mcqe2; 130 __m128i rxdf1, rxdf2; 131 #ifdef MLX5_PMD_SOFT_COUNTERS 132 __m128i byte_cnt, invalid_mask; 133 #endif 134 135 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 136 if (likely(pos + i < mcqe_n)) 137 rte_prefetch0((void *)(cq + pos + i)); 138 139 /* A.1 load mCQEs into a 128bit register. */ 140 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]); 141 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]); 142 /* B.1 store rearm data to mbuf. */ 143 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm); 144 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm); 145 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 146 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1); 147 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2); 148 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj); 149 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj); 150 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23); 151 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23); 152 /* D.1 store rx_descriptor_fields1. */ 153 _mm_storeu_si128((__m128i *) 154 &elts[pos]->rx_descriptor_fields1, 155 rxdf1); 156 _mm_storeu_si128((__m128i *) 157 &elts[pos + 1]->rx_descriptor_fields1, 158 rxdf2); 159 /* B.1 store rearm data to mbuf. */ 160 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm); 161 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm); 162 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 163 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1); 164 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2); 165 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj); 166 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj); 167 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23); 168 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23); 169 /* D.1 store rx_descriptor_fields1. */ 170 _mm_storeu_si128((__m128i *) 171 &elts[pos + 2]->rx_descriptor_fields1, 172 rxdf1); 173 _mm_storeu_si128((__m128i *) 174 &elts[pos + 3]->rx_descriptor_fields1, 175 rxdf2); 176 #ifdef MLX5_PMD_SOFT_COUNTERS 177 invalid_mask = _mm_set_epi64x(0, 178 (mcqe_n - pos) * 179 sizeof(uint16_t) * 8); 180 invalid_mask = _mm_sll_epi64(ones, invalid_mask); 181 mcqe1 = _mm_srli_si128(mcqe1, 4); 182 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc); 183 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask); 184 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt); 185 byte_cnt = _mm_hadd_epi16(byte_cnt, zero); 186 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero)); 187 #endif 188 if (rxq->mark) { 189 /* E.1 store flow tag (rte_flow mark). */ 190 elts[pos]->hash.fdir.hi = flow_tag; 191 elts[pos + 1]->hash.fdir.hi = flow_tag; 192 elts[pos + 2]->hash.fdir.hi = flow_tag; 193 elts[pos + 3]->hash.fdir.hi = flow_tag; 194 } 195 if (rxq->dynf_meta) { 196 int32_t offs = rxq->flow_meta_offset; 197 const uint32_t meta = 198 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 199 200 /* Check if title packet has valid metadata. */ 201 if (meta) { 202 MLX5_ASSERT(t_pkt->ol_flags & 203 rxq->flow_meta_mask); 204 *RTE_MBUF_DYNFIELD(elts[pos], offs, 205 uint32_t *) = meta; 206 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 207 uint32_t *) = meta; 208 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 209 uint32_t *) = meta; 210 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 211 uint32_t *) = meta; 212 } 213 } 214 pos += MLX5_VPMD_DESCS_PER_LOOP; 215 /* Move to next CQE and invalidate consumed CQEs. */ 216 if (!(pos & 0x7) && pos < mcqe_n) { 217 mcq = (void *)(cq + pos); 218 for (i = 0; i < 8; ++i) 219 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 220 } 221 } 222 /* Invalidate the rest of CQEs. */ 223 for (; inv < mcqe_n; ++inv) 224 cq[inv].op_own = MLX5_CQE_INVALIDATE; 225 #ifdef MLX5_PMD_SOFT_COUNTERS 226 rxq->stats.ipackets += mcqe_n; 227 rxq->stats.ibytes += rcvd_byte; 228 #endif 229 rxq->cq_ci += mcqe_n; 230 return mcqe_n; 231 } 232 233 /** 234 * Calculate packet type and offload flag for mbuf and store it. 235 * 236 * @param rxq 237 * Pointer to RX queue structure. 238 * @param cqes[4] 239 * Array of four 16bytes completions extracted from the original completion 240 * descriptor. 241 * @param op_err 242 * Opcode vector having responder error status. Each field is 4B. 243 * @param pkts 244 * Pointer to array of packets to be filled. 245 */ 246 static inline void 247 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4], 248 __m128i op_err, struct rte_mbuf **pkts) 249 { 250 __m128i pinfo0, pinfo1; 251 __m128i pinfo, ptype; 252 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH | 253 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 254 __m128i cv_flags; 255 const __m128i zero = _mm_setzero_si128(); 256 const __m128i ptype_mask = 257 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06); 258 const __m128i ptype_ol_mask = 259 _mm_set_epi32(0x106, 0x106, 0x106, 0x106); 260 const __m128i pinfo_mask = 261 _mm_set_epi32(0x3, 0x3, 0x3, 0x3); 262 const __m128i cv_flag_sel = 263 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 264 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | 265 PKT_RX_L4_CKSUM_GOOD) >> 1), 266 0, 267 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 268 0, 269 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 270 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 271 0); 272 const __m128i cv_mask = 273 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 274 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 275 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 276 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 277 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 278 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 279 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 280 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 281 const __m128i mbuf_init = 282 _mm_load_si128((__m128i *)&rxq->mbuf_initializer); 283 __m128i rearm0, rearm1, rearm2, rearm3; 284 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 285 286 /* Extract pkt_info field. */ 287 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]); 288 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]); 289 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1); 290 /* Extract hdr_type_etc field. */ 291 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]); 292 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]); 293 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1); 294 if (rxq->mark) { 295 const __m128i pinfo_ft_mask = 296 _mm_set_epi32(0xffffff00, 0xffffff00, 297 0xffffff00, 0xffffff00); 298 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR); 299 __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID); 300 __m128i flow_tag, invalid_mask; 301 302 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask); 303 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 304 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero); 305 ol_flags = _mm_or_si128(ol_flags, 306 _mm_andnot_si128(invalid_mask, 307 fdir_flags)); 308 /* Mask out invalid entries. */ 309 fdir_id_flags = _mm_andnot_si128(invalid_mask, fdir_id_flags); 310 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 311 ol_flags = _mm_or_si128(ol_flags, 312 _mm_andnot_si128( 313 _mm_cmpeq_epi32(flow_tag, 314 pinfo_ft_mask), 315 fdir_id_flags)); 316 } 317 /* 318 * Merge the two fields to generate the following: 319 * bit[1] = l3_ok 320 * bit[2] = l4_ok 321 * bit[8] = cv 322 * bit[11:10] = l3_hdr_type 323 * bit[14:12] = l4_hdr_type 324 * bit[15] = ip_frag 325 * bit[16] = tunneled 326 * bit[17] = outer_l3_type 327 */ 328 ptype = _mm_and_si128(ptype, ptype_mask); 329 pinfo = _mm_and_si128(pinfo, pinfo_mask); 330 pinfo = _mm_slli_epi32(pinfo, 16); 331 /* Make pinfo has merged fields for ol_flags calculation. */ 332 pinfo = _mm_or_si128(ptype, pinfo); 333 ptype = _mm_srli_epi32(pinfo, 10); 334 ptype = _mm_packs_epi32(ptype, zero); 335 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 336 op_err = _mm_srli_epi16(op_err, 8); 337 ptype = _mm_or_si128(ptype, op_err); 338 pt_idx0 = _mm_extract_epi8(ptype, 0); 339 pt_idx1 = _mm_extract_epi8(ptype, 2); 340 pt_idx2 = _mm_extract_epi8(ptype, 4); 341 pt_idx3 = _mm_extract_epi8(ptype, 6); 342 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 343 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 344 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 345 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 346 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 347 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 348 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 349 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 350 /* Fill flags for checksum and VLAN. */ 351 pinfo = _mm_and_si128(pinfo, ptype_ol_mask); 352 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo); 353 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 354 cv_flags = _mm_slli_epi32(pinfo, 9); 355 cv_flags = _mm_or_si128(pinfo, cv_flags); 356 /* Move back flags to start from byte[0]. */ 357 cv_flags = _mm_srli_epi32(cv_flags, 8); 358 /* Mask out garbage bits. */ 359 cv_flags = _mm_and_si128(cv_flags, cv_mask); 360 /* Merge to ol_flags. */ 361 ol_flags = _mm_or_si128(ol_flags, cv_flags); 362 /* Merge mbuf_init and ol_flags. */ 363 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30); 364 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30); 365 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30); 366 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30); 367 /* Write 8B rearm_data and 8B ol_flags. */ 368 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0); 369 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1); 370 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2); 371 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3); 372 } 373 374 /** 375 * Receive burst of packets. An errored completion also consumes a mbuf, but the 376 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 377 * before returning to application. 378 * 379 * @param rxq 380 * Pointer to RX queue structure. 381 * @param[out] pkts 382 * Array to store received packets. 383 * @param pkts_n 384 * Maximum number of packets in array. 385 * @param[out] err 386 * Pointer to a flag. Set non-zero value if pkts array has at least one error 387 * packet to handle. 388 * @param[out] no_cq 389 * Pointer to a boolean. Set true if no new CQE seen. 390 * 391 * @return 392 * Number of packets received including errors (<= pkts_n). 393 */ 394 static inline uint16_t 395 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 396 uint64_t *err, bool *no_cq) 397 { 398 const uint16_t q_n = 1 << rxq->cqe_n; 399 const uint16_t q_mask = q_n - 1; 400 volatile struct mlx5_cqe *cq; 401 struct rte_mbuf **elts; 402 unsigned int pos; 403 uint64_t n; 404 uint16_t repl_n; 405 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 406 uint16_t nocmp_n = 0; 407 uint16_t rcvd_pkt = 0; 408 unsigned int cq_idx = rxq->cq_ci & q_mask; 409 unsigned int elts_idx; 410 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1)); 411 const __m128i owner_check = 412 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL); 413 const __m128i opcode_check = 414 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL); 415 const __m128i format_check = 416 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL); 417 const __m128i resp_err_check = 418 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL); 419 #ifdef MLX5_PMD_SOFT_COUNTERS 420 uint32_t rcvd_byte = 0; 421 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 422 const __m128i len_shuf_mask = 423 _mm_set_epi8(-1, -1, -1, -1, 424 -1, -1, -1, -1, 425 12, 13, 8, 9, 426 4, 5, 0, 1); 427 #endif 428 /* Mask to shuffle from extracted CQE to mbuf. */ 429 const __m128i shuf_mask = 430 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */ 431 12, 13, 14, 15, /* rss, bswap32 */ 432 10, 11, /* vlan_tci, bswap16 */ 433 4, 5, /* data_len, bswap16 */ 434 -1, -1, /* zero out 2nd half of pkt_len */ 435 4, 5 /* pkt_len, bswap16 */); 436 /* Mask to blend from the last Qword to the first DQword. */ 437 const __m128i blend_mask = 438 _mm_set_epi8(-1, -1, -1, -1, 439 -1, -1, -1, -1, 440 0, 0, 0, 0, 441 0, 0, 0, -1); 442 const __m128i zero = _mm_setzero_si128(); 443 const __m128i ones = _mm_cmpeq_epi32(zero, zero); 444 const __m128i crc_adj = 445 _mm_set_epi16(0, 0, 0, 0, 0, 446 rxq->crc_present * RTE_ETHER_CRC_LEN, 447 0, 448 rxq->crc_present * RTE_ETHER_CRC_LEN); 449 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0); 450 451 MLX5_ASSERT(rxq->sges_n == 0); 452 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n); 453 cq = &(*rxq->cqes)[cq_idx]; 454 rte_prefetch0(cq); 455 rte_prefetch0(cq + 1); 456 rte_prefetch0(cq + 2); 457 rte_prefetch0(cq + 3); 458 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 459 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 460 if (repl_n >= rxq->rq_repl_thresh) 461 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 462 /* See if there're unreturned mbufs from compressed CQE. */ 463 rcvd_pkt = rxq->decompressed; 464 if (rcvd_pkt > 0) { 465 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 466 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 467 rxq->rq_pi += rcvd_pkt; 468 rxq->decompressed -= rcvd_pkt; 469 pkts += rcvd_pkt; 470 } 471 elts_idx = rxq->rq_pi & q_mask; 472 elts = &(*rxq->elts)[elts_idx]; 473 /* Not to overflow pkts array. */ 474 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 475 /* Not to cross queue end. */ 476 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 477 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx); 478 if (!pkts_n) { 479 *no_cq = !rcvd_pkt; 480 return rcvd_pkt; 481 } 482 /* At this point, there shouldn't be any remained packets. */ 483 MLX5_ASSERT(rxq->decompressed == 0); 484 /* 485 * A. load first Qword (8bytes) in one loop. 486 * B. copy 4 mbuf pointers from elts ring to returing pkts. 487 * C. load remained CQE data and extract necessary fields. 488 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 489 * following structure: 490 * struct { 491 * uint8_t pkt_info; 492 * uint8_t flow_tag[3]; 493 * uint16_t byte_cnt; 494 * uint8_t rsvd4; 495 * uint8_t op_own; 496 * uint16_t hdr_type_etc; 497 * uint16_t vlan_info; 498 * uint32_t rx_has_res; 499 * } c; 500 * D. fill in mbuf. 501 * E. get valid CQEs. 502 * F. find compressed CQE. 503 */ 504 for (pos = 0; 505 pos < pkts_n; 506 pos += MLX5_VPMD_DESCS_PER_LOOP) { 507 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP]; 508 __m128i cqe_tmp1, cqe_tmp2; 509 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3; 510 __m128i op_own, op_own_tmp1, op_own_tmp2; 511 __m128i opcode, owner_mask, invalid_mask; 512 __m128i comp_mask; 513 __m128i mask; 514 #ifdef MLX5_PMD_SOFT_COUNTERS 515 __m128i byte_cnt; 516 #endif 517 __m128i mbp1, mbp2; 518 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0); 519 unsigned int p1, p2, p3; 520 521 /* Prefetch next 4 CQEs. */ 522 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 523 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]); 524 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]); 525 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]); 526 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]); 527 } 528 /* A.0 do not cross the end of CQ. */ 529 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8); 530 mask = _mm_sll_epi64(ones, mask); 531 p = _mm_andnot_si128(mask, p); 532 /* A.1 load cqes. */ 533 p3 = _mm_extract_epi16(p, 3); 534 cqes[3] = _mm_loadl_epi64((__m128i *) 535 &cq[pos + p3].sop_drop_qpn); 536 rte_compiler_barrier(); 537 p2 = _mm_extract_epi16(p, 2); 538 cqes[2] = _mm_loadl_epi64((__m128i *) 539 &cq[pos + p2].sop_drop_qpn); 540 rte_compiler_barrier(); 541 /* B.1 load mbuf pointers. */ 542 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]); 543 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]); 544 /* A.1 load a block having op_own. */ 545 p1 = _mm_extract_epi16(p, 1); 546 cqes[1] = _mm_loadl_epi64((__m128i *) 547 &cq[pos + p1].sop_drop_qpn); 548 rte_compiler_barrier(); 549 cqes[0] = _mm_loadl_epi64((__m128i *) 550 &cq[pos].sop_drop_qpn); 551 /* B.2 copy mbuf pointers. */ 552 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1); 553 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2); 554 rte_cio_rmb(); 555 /* C.1 load remained CQE data and extract necessary fields. */ 556 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]); 557 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]); 558 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask); 559 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask); 560 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].csum); 561 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].csum); 562 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30); 563 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30); 564 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd4[2]); 565 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd4[2]); 566 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04); 567 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04); 568 /* C.2 generate final structure for mbuf with swapping bytes. */ 569 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask); 570 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask); 571 /* C.3 adjust CRC length. */ 572 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj); 573 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj); 574 /* C.4 adjust flow mark. */ 575 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj); 576 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj); 577 /* D.1 fill in mbuf - rx_descriptor_fields1. */ 578 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3); 579 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2); 580 /* E.1 extract op_own field. */ 581 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]); 582 /* C.1 load remained CQE data and extract necessary fields. */ 583 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]); 584 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]); 585 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask); 586 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask); 587 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].csum); 588 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].csum); 589 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30); 590 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30); 591 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd4[2]); 592 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd4[2]); 593 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04); 594 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04); 595 /* C.2 generate final structure for mbuf with swapping bytes. */ 596 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask); 597 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask); 598 /* C.3 adjust CRC length. */ 599 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj); 600 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj); 601 /* C.4 adjust flow mark. */ 602 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj); 603 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj); 604 /* E.1 extract op_own byte. */ 605 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]); 606 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2); 607 /* D.1 fill in mbuf - rx_descriptor_fields1. */ 608 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1); 609 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0); 610 /* E.2 flip owner bit to mark CQEs from last round. */ 611 owner_mask = _mm_and_si128(op_own, owner_check); 612 if (ownership) 613 owner_mask = _mm_xor_si128(owner_mask, owner_check); 614 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check); 615 owner_mask = _mm_packs_epi32(owner_mask, zero); 616 /* E.3 get mask for invalidated CQEs. */ 617 opcode = _mm_and_si128(op_own, opcode_check); 618 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode); 619 invalid_mask = _mm_packs_epi32(invalid_mask, zero); 620 /* E.4 mask out beyond boundary. */ 621 invalid_mask = _mm_or_si128(invalid_mask, mask); 622 /* E.5 merge invalid_mask with invalid owner. */ 623 invalid_mask = _mm_or_si128(invalid_mask, owner_mask); 624 /* F.1 find compressed CQE format. */ 625 comp_mask = _mm_and_si128(op_own, format_check); 626 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check); 627 comp_mask = _mm_packs_epi32(comp_mask, zero); 628 /* F.2 mask out invalid entries. */ 629 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask); 630 comp_idx = _mm_cvtsi128_si64(comp_mask); 631 /* F.3 get the first compressed CQE. */ 632 comp_idx = comp_idx ? 633 __builtin_ctzll(comp_idx) / 634 (sizeof(uint16_t) * 8) : 635 MLX5_VPMD_DESCS_PER_LOOP; 636 /* E.6 mask out entries after the compressed CQE. */ 637 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8); 638 mask = _mm_sll_epi64(ones, mask); 639 invalid_mask = _mm_or_si128(invalid_mask, mask); 640 /* E.7 count non-compressed valid CQEs. */ 641 n = _mm_cvtsi128_si64(invalid_mask); 642 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) : 643 MLX5_VPMD_DESCS_PER_LOOP; 644 nocmp_n += n; 645 /* D.2 get the final invalid mask. */ 646 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8); 647 mask = _mm_sll_epi64(ones, mask); 648 invalid_mask = _mm_or_si128(invalid_mask, mask); 649 /* D.3 check error in opcode. */ 650 opcode = _mm_cmpeq_epi32(resp_err_check, opcode); 651 opcode = _mm_packs_epi32(opcode, zero); 652 opcode = _mm_andnot_si128(invalid_mask, opcode); 653 /* D.4 mark if any error is set */ 654 *err |= _mm_cvtsi128_si64(opcode); 655 /* D.5 fill in mbuf - rearm_data and packet_type. */ 656 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); 657 if (rxq->hw_timestamp) { 658 if (rxq->rt_timestamp) { 659 struct mlx5_dev_ctx_shared *sh = rxq->sh; 660 uint64_t ts; 661 662 ts = rte_be_to_cpu_64(cq[pos].timestamp); 663 pkts[pos]->timestamp = 664 mlx5_txpp_convert_rx_ts(sh, ts); 665 ts = rte_be_to_cpu_64(cq[pos + p1].timestamp); 666 pkts[pos + 1]->timestamp = 667 mlx5_txpp_convert_rx_ts(sh, ts); 668 ts = rte_be_to_cpu_64(cq[pos + p2].timestamp); 669 pkts[pos + 2]->timestamp = 670 mlx5_txpp_convert_rx_ts(sh, ts); 671 ts = rte_be_to_cpu_64(cq[pos + p3].timestamp); 672 pkts[pos + 3]->timestamp = 673 mlx5_txpp_convert_rx_ts(sh, ts); 674 } else { 675 pkts[pos]->timestamp = rte_be_to_cpu_64 676 (cq[pos].timestamp); 677 pkts[pos + 1]->timestamp = rte_be_to_cpu_64 678 (cq[pos + p1].timestamp); 679 pkts[pos + 2]->timestamp = rte_be_to_cpu_64 680 (cq[pos + p2].timestamp); 681 pkts[pos + 3]->timestamp = rte_be_to_cpu_64 682 (cq[pos + p3].timestamp); 683 } 684 } 685 if (rxq->dynf_meta) { 686 /* This code is subject for futher optimization. */ 687 int32_t offs = rxq->flow_meta_offset; 688 689 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 690 cq[pos].flow_table_metadata; 691 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 692 cq[pos + p1].flow_table_metadata; 693 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 694 cq[pos + p2].flow_table_metadata; 695 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 696 cq[pos + p3].flow_table_metadata; 697 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 698 pkts[pos]->ol_flags |= rxq->flow_meta_mask; 699 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 700 pkts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 701 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 702 pkts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 703 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 704 pkts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 705 } 706 #ifdef MLX5_PMD_SOFT_COUNTERS 707 /* Add up received bytes count. */ 708 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask); 709 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt); 710 byte_cnt = _mm_hadd_epi16(byte_cnt, zero); 711 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero)); 712 #endif 713 /* 714 * Break the loop unless more valid CQE is expected, or if 715 * there's a compressed CQE. 716 */ 717 if (n != MLX5_VPMD_DESCS_PER_LOOP) 718 break; 719 } 720 /* If no new CQE seen, return without updating cq_db. */ 721 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) { 722 *no_cq = true; 723 return rcvd_pkt; 724 } 725 /* Update the consumer indexes for non-compressed CQEs. */ 726 MLX5_ASSERT(nocmp_n <= pkts_n); 727 rxq->cq_ci += nocmp_n; 728 rxq->rq_pi += nocmp_n; 729 rcvd_pkt += nocmp_n; 730 #ifdef MLX5_PMD_SOFT_COUNTERS 731 rxq->stats.ipackets += nocmp_n; 732 rxq->stats.ibytes += rcvd_byte; 733 #endif 734 /* Decompress the last CQE if compressed. */ 735 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 736 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 737 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n], 738 &elts[nocmp_n]); 739 /* Return more packets if needed. */ 740 if (nocmp_n < pkts_n) { 741 uint16_t n = rxq->decompressed; 742 743 n = RTE_MIN(n, pkts_n - nocmp_n); 744 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 745 rxq->rq_pi += n; 746 rcvd_pkt += n; 747 rxq->decompressed -= n; 748 } 749 } 750 rte_compiler_barrier(); 751 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 752 *no_cq = !rcvd_pkt; 753 return rcvd_pkt; 754 } 755 756 #endif /* RTE_PMD_MLX5_RXTX_VEC_SSE_H_ */ 757