1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_ 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <string.h> 12 #include <stdlib.h> 13 #include <smmintrin.h> 14 15 #include <rte_mbuf.h> 16 #include <rte_mempool.h> 17 #include <rte_prefetch.h> 18 19 #include "mlx5.h" 20 #include "mlx5_utils.h" 21 #include "mlx5_rxtx.h" 22 #include "mlx5_rxtx_vec.h" 23 #include "mlx5_autoconf.h" 24 #include "mlx5_defs.h" 25 #include "mlx5_prm.h" 26 27 #ifndef __INTEL_COMPILER 28 #pragma GCC diagnostic ignored "-Wcast-qual" 29 #endif 30 31 /** 32 * Fill in buffer descriptors in a multi-packet send descriptor. 33 * 34 * @param txq 35 * Pointer to TX queue structure. 36 * @param dseg 37 * Pointer to buffer descriptor to be written. 38 * @param pkts 39 * Pointer to array of packets to be sent. 40 * @param n 41 * Number of packets to be filled. 42 */ 43 static inline void 44 txq_wr_dseg_v(struct mlx5_txq_data *txq, __m128i *dseg, 45 struct rte_mbuf **pkts, unsigned int n) 46 { 47 unsigned int pos; 48 uintptr_t addr; 49 const __m128i shuf_mask_dseg = 50 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */ 51 12, 13, 14, 15, 52 7, 6, 5, 4, /* lkey */ 53 0, 1, 2, 3 /* length, bswap32 */); 54 #ifdef MLX5_PMD_SOFT_COUNTERS 55 uint32_t tx_byte = 0; 56 #endif 57 58 for (pos = 0; pos < n; ++pos, ++dseg) { 59 __m128i desc; 60 struct rte_mbuf *pkt = pkts[pos]; 61 62 addr = rte_pktmbuf_mtod(pkt, uintptr_t); 63 desc = _mm_set_epi32(addr >> 32, 64 addr, 65 mlx5_tx_mb2mr(txq, pkt), 66 DATA_LEN(pkt)); 67 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg); 68 _mm_store_si128(dseg, desc); 69 #ifdef MLX5_PMD_SOFT_COUNTERS 70 tx_byte += DATA_LEN(pkt); 71 #endif 72 } 73 #ifdef MLX5_PMD_SOFT_COUNTERS 74 txq->stats.obytes += tx_byte; 75 #endif 76 } 77 78 /** 79 * Send multi-segmented packets until it encounters a single segment packet in 80 * the pkts list. 81 * 82 * @param txq 83 * Pointer to TX queue structure. 84 * @param pkts 85 * Pointer to array of packets to be sent. 86 * @param pkts_n 87 * Number of packets to be sent. 88 * 89 * @return 90 * Number of packets successfully transmitted (<= pkts_n). 91 */ 92 static uint16_t 93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, 94 uint16_t pkts_n) 95 { 96 uint16_t elts_head = txq->elts_head; 97 const uint16_t elts_n = 1 << txq->elts_n; 98 const uint16_t elts_m = elts_n - 1; 99 const uint16_t wq_n = 1 << txq->wqe_n; 100 const uint16_t wq_mask = wq_n - 1; 101 const unsigned int nb_dword_per_wqebb = 102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 103 const unsigned int nb_dword_in_hdr = 104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 105 unsigned int n; 106 volatile struct mlx5_wqe *wqe = NULL; 107 108 assert(elts_n > pkts_n); 109 mlx5_tx_complete(txq); 110 /* A CQE slot must always be available. */ 111 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); 112 if (unlikely(!pkts_n)) 113 return 0; 114 for (n = 0; n < pkts_n; ++n) { 115 struct rte_mbuf *buf = pkts[n]; 116 unsigned int segs_n = buf->nb_segs; 117 unsigned int ds = nb_dword_in_hdr; 118 unsigned int len = PKT_LEN(buf); 119 uint16_t wqe_ci = txq->wqe_ci; 120 const __m128i shuf_mask_ctrl = 121 _mm_set_epi8(15, 14, 13, 12, 122 8, 9, 10, 11, /* bswap32 */ 123 4, 5, 6, 7, /* bswap32 */ 124 0, 1, 2, 3 /* bswap32 */); 125 uint8_t cs_flags; 126 uint16_t max_elts; 127 uint16_t max_wqe; 128 __m128i *t_wqe, *dseg; 129 __m128i ctrl; 130 131 assert(segs_n); 132 max_elts = elts_n - (elts_head - txq->elts_tail); 133 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi); 134 /* 135 * A MPW session consumes 2 WQEs at most to 136 * include MLX5_MPW_DSEG_MAX pointers. 137 */ 138 if (segs_n == 1 || 139 max_elts < segs_n || max_wqe < 2) 140 break; 141 if (segs_n > MLX5_MPW_DSEG_MAX) { 142 txq->stats.oerrors++; 143 break; 144 } 145 wqe = &((volatile struct mlx5_wqe64 *) 146 txq->wqes)[wqe_ci & wq_mask].hdr; 147 cs_flags = txq_ol_cksum_to_cs(buf); 148 /* Title WQEBB pointer. */ 149 t_wqe = (__m128i *)wqe; 150 dseg = (__m128i *)(wqe + 1); 151 do { 152 if (!(ds++ % nb_dword_per_wqebb)) { 153 dseg = (__m128i *) 154 &((volatile struct mlx5_wqe64 *) 155 txq->wqes)[++wqe_ci & wq_mask]; 156 } 157 txq_wr_dseg_v(txq, dseg++, &buf, 1); 158 (*txq->elts)[elts_head++ & elts_m] = buf; 159 buf = buf->next; 160 } while (--segs_n); 161 ++wqe_ci; 162 /* Fill CTRL in the header. */ 163 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds, 164 MLX5_OPC_MOD_MPW << 24 | 165 txq->wqe_ci << 8 | MLX5_OPCODE_TSO); 166 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl); 167 _mm_store_si128(t_wqe, ctrl); 168 /* Fill ESEG in the header. */ 169 _mm_store_si128(t_wqe + 1, 170 _mm_set_epi16(0, 0, 0, 0, 171 rte_cpu_to_be_16(len), cs_flags, 172 0, 0)); 173 txq->wqe_ci = wqe_ci; 174 } 175 if (!n) 176 return 0; 177 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head); 178 txq->elts_head = elts_head; 179 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) { 180 wqe->ctrl[2] = rte_cpu_to_be_32(8); 181 wqe->ctrl[3] = txq->elts_head; 182 txq->elts_comp = 0; 183 #ifndef NDEBUG 184 ++txq->cq_pi; 185 #endif 186 } 187 #ifdef MLX5_PMD_SOFT_COUNTERS 188 txq->stats.opackets += n; 189 #endif 190 mlx5_tx_dbrec(txq, wqe); 191 return n; 192 } 193 194 /** 195 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet, 196 * it returns to make it processed by txq_scatter_v(). All the packets in 197 * the pkts list should be single segment packets having same offload flags. 198 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload(). 199 * 200 * @param txq 201 * Pointer to TX queue structure. 202 * @param pkts 203 * Pointer to array of packets to be sent. 204 * @param pkts_n 205 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST). 206 * @param cs_flags 207 * Checksum offload flags to be written in the descriptor. 208 * 209 * @return 210 * Number of packets successfully transmitted (<= pkts_n). 211 */ 212 static inline uint16_t 213 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n, 214 uint8_t cs_flags) 215 { 216 struct rte_mbuf **elts; 217 uint16_t elts_head = txq->elts_head; 218 const uint16_t elts_n = 1 << txq->elts_n; 219 const uint16_t elts_m = elts_n - 1; 220 const unsigned int nb_dword_per_wqebb = 221 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 222 const unsigned int nb_dword_in_hdr = 223 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 224 unsigned int n = 0; 225 unsigned int pos; 226 uint16_t max_elts; 227 uint16_t max_wqe; 228 uint32_t comp_req = 0; 229 const uint16_t wq_n = 1 << txq->wqe_n; 230 const uint16_t wq_mask = wq_n - 1; 231 uint16_t wq_idx = txq->wqe_ci & wq_mask; 232 volatile struct mlx5_wqe64 *wq = 233 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx]; 234 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq; 235 const __m128i shuf_mask_ctrl = 236 _mm_set_epi8(15, 14, 13, 12, 237 8, 9, 10, 11, /* bswap32 */ 238 4, 5, 6, 7, /* bswap32 */ 239 0, 1, 2, 3 /* bswap32 */); 240 __m128i *t_wqe, *dseg; 241 __m128i ctrl; 242 243 /* Make sure all packets can fit into a single WQE. */ 244 assert(elts_n > pkts_n); 245 mlx5_tx_complete(txq); 246 max_elts = (elts_n - (elts_head - txq->elts_tail)); 247 /* A CQE slot must always be available. */ 248 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); 249 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 250 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts); 251 assert(pkts_n <= MLX5_DSEG_MAX - nb_dword_in_hdr); 252 if (unlikely(!pkts_n)) 253 return 0; 254 elts = &(*txq->elts)[elts_head & elts_m]; 255 /* Loop for available tailroom first. */ 256 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n); 257 for (pos = 0; pos < (n & -2); pos += 2) 258 _mm_storeu_si128((__m128i *)&elts[pos], 259 _mm_loadu_si128((__m128i *)&pkts[pos])); 260 if (n & 1) 261 elts[pos] = pkts[pos]; 262 /* Check if it crosses the end of the queue. */ 263 if (unlikely(n < pkts_n)) { 264 elts = &(*txq->elts)[0]; 265 for (pos = 0; pos < pkts_n - n; ++pos) 266 elts[pos] = pkts[n + pos]; 267 } 268 txq->elts_head += pkts_n; 269 /* Save title WQEBB pointer. */ 270 t_wqe = (__m128i *)wqe; 271 dseg = (__m128i *)(wqe + 1); 272 /* Calculate the number of entries to the end. */ 273 n = RTE_MIN( 274 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr, 275 pkts_n); 276 /* Fill DSEGs. */ 277 txq_wr_dseg_v(txq, dseg, pkts, n); 278 /* Check if it crosses the end of the queue. */ 279 if (n < pkts_n) { 280 dseg = (__m128i *)txq->wqes; 281 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n); 282 } 283 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) { 284 txq->elts_comp += pkts_n; 285 } else { 286 /* Request a completion. */ 287 txq->elts_comp = 0; 288 #ifndef NDEBUG 289 ++txq->cq_pi; 290 #endif 291 comp_req = 8; 292 } 293 /* Fill CTRL in the header. */ 294 ctrl = _mm_set_epi32(txq->elts_head, comp_req, 295 txq->qp_num_8s | (pkts_n + 2), 296 MLX5_OPC_MOD_ENHANCED_MPSW << 24 | 297 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW); 298 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl); 299 _mm_store_si128(t_wqe, ctrl); 300 /* Fill ESEG in the header. */ 301 _mm_store_si128(t_wqe + 1, 302 _mm_set_epi8(0, 0, 0, 0, 303 0, 0, 0, 0, 304 0, 0, 0, cs_flags, 305 0, 0, 0, 0)); 306 #ifdef MLX5_PMD_SOFT_COUNTERS 307 txq->stats.opackets += pkts_n; 308 #endif 309 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) / 310 nb_dword_per_wqebb; 311 /* Ring QP doorbell. */ 312 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST); 313 return pkts_n; 314 } 315 316 /** 317 * Store free buffers to RX SW ring. 318 * 319 * @param rxq 320 * Pointer to RX queue structure. 321 * @param pkts 322 * Pointer to array of packets to be stored. 323 * @param pkts_n 324 * Number of packets to be stored. 325 */ 326 static inline void 327 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 328 { 329 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 330 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 331 unsigned int pos; 332 uint16_t p = n & -2; 333 334 for (pos = 0; pos < p; pos += 2) { 335 __m128i mbp; 336 337 mbp = _mm_loadu_si128((__m128i *)&elts[pos]); 338 _mm_storeu_si128((__m128i *)&pkts[pos], mbp); 339 } 340 if (n & 1) 341 pkts[pos] = elts[pos]; 342 } 343 344 /** 345 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 346 * extracted from the title completion descriptor. 347 * 348 * @param rxq 349 * Pointer to RX queue structure. 350 * @param cq 351 * Pointer to completion array having a compressed completion at first. 352 * @param elts 353 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 354 * the title completion descriptor to be copied to the rest of mbufs. 355 */ 356 static inline void 357 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 358 struct rte_mbuf **elts) 359 { 360 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1); 361 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 362 unsigned int pos; 363 unsigned int i; 364 unsigned int inv = 0; 365 /* Mask to shuffle from extracted mini CQE to mbuf. */ 366 const __m128i shuf_mask1 = 367 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */ 368 -1, -1, /* skip vlan_tci */ 369 6, 7, /* data_len, bswap16 */ 370 -1, -1, 6, 7, /* pkt_len, bswap16 */ 371 -1, -1, -1, -1 /* skip packet_type */); 372 const __m128i shuf_mask2 = 373 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */ 374 -1, -1, /* skip vlan_tci */ 375 14, 15, /* data_len, bswap16 */ 376 -1, -1, 14, 15, /* pkt_len, bswap16 */ 377 -1, -1, -1, -1 /* skip packet_type */); 378 /* Restore the compressed count. Must be 16 bits. */ 379 const uint16_t mcqe_n = t_pkt->data_len + 380 (rxq->crc_present * ETHER_CRC_LEN); 381 const __m128i rearm = 382 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data); 383 const __m128i rxdf = 384 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1); 385 const __m128i crc_adj = 386 _mm_set_epi16(0, 0, 0, 387 rxq->crc_present * ETHER_CRC_LEN, 388 0, 389 rxq->crc_present * ETHER_CRC_LEN, 390 0, 0); 391 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 392 #ifdef MLX5_PMD_SOFT_COUNTERS 393 const __m128i zero = _mm_setzero_si128(); 394 const __m128i ones = _mm_cmpeq_epi32(zero, zero); 395 uint32_t rcvd_byte = 0; 396 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 397 const __m128i len_shuf_mask = 398 _mm_set_epi8(-1, -1, -1, -1, 399 -1, -1, -1, -1, 400 14, 15, 6, 7, 401 10, 11, 2, 3); 402 #endif 403 404 /* 405 * A. load mCQEs into a 128bit register. 406 * B. store rearm data to mbuf. 407 * C. combine data from mCQEs with rx_descriptor_fields1. 408 * D. store rx_descriptor_fields1. 409 * E. store flow tag (rte_flow mark). 410 */ 411 for (pos = 0; pos < mcqe_n; ) { 412 __m128i mcqe1, mcqe2; 413 __m128i rxdf1, rxdf2; 414 #ifdef MLX5_PMD_SOFT_COUNTERS 415 __m128i byte_cnt, invalid_mask; 416 #endif 417 418 if (!(pos & 0x7) && pos + 8 < mcqe_n) 419 rte_prefetch0((void *)(cq + pos + 8)); 420 /* A.1 load mCQEs into a 128bit register. */ 421 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]); 422 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]); 423 /* B.1 store rearm data to mbuf. */ 424 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm); 425 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm); 426 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 427 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1); 428 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2); 429 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj); 430 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj); 431 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23); 432 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23); 433 /* D.1 store rx_descriptor_fields1. */ 434 _mm_storeu_si128((__m128i *) 435 &elts[pos]->rx_descriptor_fields1, 436 rxdf1); 437 _mm_storeu_si128((__m128i *) 438 &elts[pos + 1]->rx_descriptor_fields1, 439 rxdf2); 440 /* B.1 store rearm data to mbuf. */ 441 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm); 442 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm); 443 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 444 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1); 445 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2); 446 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj); 447 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj); 448 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23); 449 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23); 450 /* D.1 store rx_descriptor_fields1. */ 451 _mm_storeu_si128((__m128i *) 452 &elts[pos + 2]->rx_descriptor_fields1, 453 rxdf1); 454 _mm_storeu_si128((__m128i *) 455 &elts[pos + 3]->rx_descriptor_fields1, 456 rxdf2); 457 #ifdef MLX5_PMD_SOFT_COUNTERS 458 invalid_mask = _mm_set_epi64x(0, 459 (mcqe_n - pos) * 460 sizeof(uint16_t) * 8); 461 invalid_mask = _mm_sll_epi64(ones, invalid_mask); 462 mcqe1 = _mm_srli_si128(mcqe1, 4); 463 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc); 464 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask); 465 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt); 466 byte_cnt = _mm_hadd_epi16(byte_cnt, zero); 467 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero)); 468 #endif 469 if (rxq->mark) { 470 /* E.1 store flow tag (rte_flow mark). */ 471 elts[pos]->hash.fdir.hi = flow_tag; 472 elts[pos + 1]->hash.fdir.hi = flow_tag; 473 elts[pos + 2]->hash.fdir.hi = flow_tag; 474 elts[pos + 3]->hash.fdir.hi = flow_tag; 475 } 476 pos += MLX5_VPMD_DESCS_PER_LOOP; 477 /* Move to next CQE and invalidate consumed CQEs. */ 478 if (!(pos & 0x7) && pos < mcqe_n) { 479 mcq = (void *)(cq + pos); 480 for (i = 0; i < 8; ++i) 481 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 482 } 483 } 484 /* Invalidate the rest of CQEs. */ 485 for (; inv < mcqe_n; ++inv) 486 cq[inv].op_own = MLX5_CQE_INVALIDATE; 487 #ifdef MLX5_PMD_SOFT_COUNTERS 488 rxq->stats.ipackets += mcqe_n; 489 rxq->stats.ibytes += rcvd_byte; 490 #endif 491 rxq->cq_ci += mcqe_n; 492 } 493 494 /** 495 * Calculate packet type and offload flag for mbuf and store it. 496 * 497 * @param rxq 498 * Pointer to RX queue structure. 499 * @param cqes[4] 500 * Array of four 16bytes completions extracted from the original completion 501 * descriptor. 502 * @param op_err 503 * Opcode vector having responder error status. Each field is 4B. 504 * @param pkts 505 * Pointer to array of packets to be filled. 506 */ 507 static inline void 508 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4], 509 __m128i op_err, struct rte_mbuf **pkts) 510 { 511 __m128i pinfo0, pinfo1; 512 __m128i pinfo, ptype; 513 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH | 514 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 515 __m128i cv_flags; 516 const __m128i zero = _mm_setzero_si128(); 517 const __m128i ptype_mask = 518 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06); 519 const __m128i ptype_ol_mask = 520 _mm_set_epi32(0x106, 0x106, 0x106, 0x106); 521 const __m128i pinfo_mask = 522 _mm_set_epi32(0x3, 0x3, 0x3, 0x3); 523 const __m128i cv_flag_sel = 524 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 525 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | 526 PKT_RX_L4_CKSUM_GOOD) >> 1), 527 0, 528 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 529 0, 530 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 531 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 532 0); 533 const __m128i cv_mask = 534 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 535 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 536 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 537 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 538 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 539 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 540 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 541 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 542 const __m128i mbuf_init = 543 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer); 544 __m128i rearm0, rearm1, rearm2, rearm3; 545 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 546 547 /* Extract pkt_info field. */ 548 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]); 549 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]); 550 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1); 551 /* Extract hdr_type_etc field. */ 552 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]); 553 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]); 554 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1); 555 if (rxq->mark) { 556 const __m128i pinfo_ft_mask = 557 _mm_set_epi32(0xffffff00, 0xffffff00, 558 0xffffff00, 0xffffff00); 559 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR); 560 __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID); 561 __m128i flow_tag, invalid_mask; 562 563 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask); 564 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 565 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero); 566 ol_flags = _mm_or_si128(ol_flags, 567 _mm_andnot_si128(invalid_mask, 568 fdir_flags)); 569 /* Mask out invalid entries. */ 570 fdir_id_flags = _mm_andnot_si128(invalid_mask, fdir_id_flags); 571 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 572 ol_flags = _mm_or_si128(ol_flags, 573 _mm_andnot_si128( 574 _mm_cmpeq_epi32(flow_tag, 575 pinfo_ft_mask), 576 fdir_id_flags)); 577 } 578 /* 579 * Merge the two fields to generate the following: 580 * bit[1] = l3_ok 581 * bit[2] = l4_ok 582 * bit[8] = cv 583 * bit[11:10] = l3_hdr_type 584 * bit[14:12] = l4_hdr_type 585 * bit[15] = ip_frag 586 * bit[16] = tunneled 587 * bit[17] = outer_l3_type 588 */ 589 ptype = _mm_and_si128(ptype, ptype_mask); 590 pinfo = _mm_and_si128(pinfo, pinfo_mask); 591 pinfo = _mm_slli_epi32(pinfo, 16); 592 /* Make pinfo has merged fields for ol_flags calculation. */ 593 pinfo = _mm_or_si128(ptype, pinfo); 594 ptype = _mm_srli_epi32(pinfo, 10); 595 ptype = _mm_packs_epi32(ptype, zero); 596 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 597 op_err = _mm_srli_epi16(op_err, 8); 598 ptype = _mm_or_si128(ptype, op_err); 599 pt_idx0 = _mm_extract_epi8(ptype, 0); 600 pt_idx1 = _mm_extract_epi8(ptype, 2); 601 pt_idx2 = _mm_extract_epi8(ptype, 4); 602 pt_idx3 = _mm_extract_epi8(ptype, 6); 603 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 604 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 605 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 606 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 607 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 608 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 609 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 610 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 611 /* Fill flags for checksum and VLAN. */ 612 pinfo = _mm_and_si128(pinfo, ptype_ol_mask); 613 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo); 614 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 615 cv_flags = _mm_slli_epi32(pinfo, 9); 616 cv_flags = _mm_or_si128(pinfo, cv_flags); 617 /* Move back flags to start from byte[0]. */ 618 cv_flags = _mm_srli_epi32(cv_flags, 8); 619 /* Mask out garbage bits. */ 620 cv_flags = _mm_and_si128(cv_flags, cv_mask); 621 /* Merge to ol_flags. */ 622 ol_flags = _mm_or_si128(ol_flags, cv_flags); 623 /* Merge mbuf_init and ol_flags. */ 624 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30); 625 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30); 626 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30); 627 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30); 628 /* Write 8B rearm_data and 8B ol_flags. */ 629 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0); 630 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1); 631 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2); 632 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3); 633 } 634 635 /** 636 * Receive burst of packets. An errored completion also consumes a mbuf, but the 637 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 638 * before returning to application. 639 * 640 * @param rxq 641 * Pointer to RX queue structure. 642 * @param[out] pkts 643 * Array to store received packets. 644 * @param pkts_n 645 * Maximum number of packets in array. 646 * @param[out] err 647 * Pointer to a flag. Set non-zero value if pkts array has at least one error 648 * packet to handle. 649 * 650 * @return 651 * Number of packets received including errors (<= pkts_n). 652 */ 653 static inline uint16_t 654 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 655 uint64_t *err) 656 { 657 const uint16_t q_n = 1 << rxq->cqe_n; 658 const uint16_t q_mask = q_n - 1; 659 volatile struct mlx5_cqe *cq; 660 struct rte_mbuf **elts; 661 unsigned int pos; 662 uint64_t n; 663 uint16_t repl_n; 664 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 665 uint16_t nocmp_n = 0; 666 uint16_t rcvd_pkt = 0; 667 unsigned int cq_idx = rxq->cq_ci & q_mask; 668 unsigned int elts_idx; 669 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1)); 670 const __m128i owner_check = 671 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL); 672 const __m128i opcode_check = 673 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL); 674 const __m128i format_check = 675 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL); 676 const __m128i resp_err_check = 677 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL); 678 #ifdef MLX5_PMD_SOFT_COUNTERS 679 uint32_t rcvd_byte = 0; 680 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 681 const __m128i len_shuf_mask = 682 _mm_set_epi8(-1, -1, -1, -1, 683 -1, -1, -1, -1, 684 12, 13, 8, 9, 685 4, 5, 0, 1); 686 #endif 687 /* Mask to shuffle from extracted CQE to mbuf. */ 688 const __m128i shuf_mask = 689 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */ 690 12, 13, 14, 15, /* rss, bswap32 */ 691 10, 11, /* vlan_tci, bswap16 */ 692 4, 5, /* data_len, bswap16 */ 693 -1, -1, /* zero out 2nd half of pkt_len */ 694 4, 5 /* pkt_len, bswap16 */); 695 /* Mask to blend from the last Qword to the first DQword. */ 696 const __m128i blend_mask = 697 _mm_set_epi8(-1, -1, -1, -1, 698 -1, -1, -1, -1, 699 0, 0, 0, 0, 700 0, 0, 0, -1); 701 const __m128i zero = _mm_setzero_si128(); 702 const __m128i ones = _mm_cmpeq_epi32(zero, zero); 703 const __m128i crc_adj = 704 _mm_set_epi16(0, 0, 0, 0, 0, 705 rxq->crc_present * ETHER_CRC_LEN, 706 0, 707 rxq->crc_present * ETHER_CRC_LEN); 708 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0); 709 710 assert(rxq->sges_n == 0); 711 assert(rxq->cqe_n == rxq->elts_n); 712 cq = &(*rxq->cqes)[cq_idx]; 713 rte_prefetch0(cq); 714 rte_prefetch0(cq + 1); 715 rte_prefetch0(cq + 2); 716 rte_prefetch0(cq + 3); 717 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 718 /* 719 * Order of indexes: 720 * rq_ci >= cq_ci >= rq_pi 721 * Definition of indexes: 722 * rq_ci - cq_ci := # of buffers owned by HW (posted). 723 * cq_ci - rq_pi := # of buffers not returned to app (decompressed). 724 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished). 725 */ 726 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 727 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH) 728 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 729 /* See if there're unreturned mbufs from compressed CQE. */ 730 rcvd_pkt = rxq->cq_ci - rxq->rq_pi; 731 if (rcvd_pkt > 0) { 732 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 733 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 734 rxq->rq_pi += rcvd_pkt; 735 pkts += rcvd_pkt; 736 } 737 elts_idx = rxq->rq_pi & q_mask; 738 elts = &(*rxq->elts)[elts_idx]; 739 /* Not to overflow pkts array. */ 740 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 741 /* Not to cross queue end. */ 742 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 743 if (!pkts_n) 744 return rcvd_pkt; 745 /* At this point, there shouldn't be any remained packets. */ 746 assert(rxq->rq_pi == rxq->cq_ci); 747 /* 748 * A. load first Qword (8bytes) in one loop. 749 * B. copy 4 mbuf pointers from elts ring to returing pkts. 750 * C. load remained CQE data and extract necessary fields. 751 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 752 * following structure: 753 * struct { 754 * uint8_t pkt_info; 755 * uint8_t flow_tag[3]; 756 * uint16_t byte_cnt; 757 * uint8_t rsvd4; 758 * uint8_t op_own; 759 * uint16_t hdr_type_etc; 760 * uint16_t vlan_info; 761 * uint32_t rx_has_res; 762 * } c; 763 * D. fill in mbuf. 764 * E. get valid CQEs. 765 * F. find compressed CQE. 766 */ 767 for (pos = 0; 768 pos < pkts_n; 769 pos += MLX5_VPMD_DESCS_PER_LOOP) { 770 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP]; 771 __m128i cqe_tmp1, cqe_tmp2; 772 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3; 773 __m128i op_own, op_own_tmp1, op_own_tmp2; 774 __m128i opcode, owner_mask, invalid_mask; 775 __m128i comp_mask; 776 __m128i mask; 777 #ifdef MLX5_PMD_SOFT_COUNTERS 778 __m128i byte_cnt; 779 #endif 780 __m128i mbp1, mbp2; 781 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0); 782 unsigned int p1, p2, p3; 783 784 /* Prefetch next 4 CQEs. */ 785 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 786 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]); 787 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]); 788 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]); 789 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]); 790 } 791 /* A.0 do not cross the end of CQ. */ 792 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8); 793 mask = _mm_sll_epi64(ones, mask); 794 p = _mm_andnot_si128(mask, p); 795 /* A.1 load cqes. */ 796 p3 = _mm_extract_epi16(p, 3); 797 cqes[3] = _mm_loadl_epi64((__m128i *) 798 &cq[pos + p3].sop_drop_qpn); 799 rte_compiler_barrier(); 800 p2 = _mm_extract_epi16(p, 2); 801 cqes[2] = _mm_loadl_epi64((__m128i *) 802 &cq[pos + p2].sop_drop_qpn); 803 rte_compiler_barrier(); 804 /* B.1 load mbuf pointers. */ 805 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]); 806 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]); 807 /* A.1 load a block having op_own. */ 808 p1 = _mm_extract_epi16(p, 1); 809 cqes[1] = _mm_loadl_epi64((__m128i *) 810 &cq[pos + p1].sop_drop_qpn); 811 rte_compiler_barrier(); 812 cqes[0] = _mm_loadl_epi64((__m128i *) 813 &cq[pos].sop_drop_qpn); 814 /* B.2 copy mbuf pointers. */ 815 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1); 816 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2); 817 rte_cio_rmb(); 818 /* C.1 load remained CQE data and extract necessary fields. */ 819 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]); 820 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]); 821 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask); 822 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask); 823 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]); 824 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]); 825 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30); 826 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30); 827 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]); 828 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]); 829 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04); 830 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04); 831 /* C.2 generate final structure for mbuf with swapping bytes. */ 832 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask); 833 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask); 834 /* C.3 adjust CRC length. */ 835 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj); 836 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj); 837 /* C.4 adjust flow mark. */ 838 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj); 839 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj); 840 /* D.1 fill in mbuf - rx_descriptor_fields1. */ 841 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3); 842 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2); 843 /* E.1 extract op_own field. */ 844 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]); 845 /* C.1 load remained CQE data and extract necessary fields. */ 846 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]); 847 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]); 848 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask); 849 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask); 850 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]); 851 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]); 852 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30); 853 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30); 854 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]); 855 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]); 856 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04); 857 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04); 858 /* C.2 generate final structure for mbuf with swapping bytes. */ 859 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask); 860 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask); 861 /* C.3 adjust CRC length. */ 862 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj); 863 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj); 864 /* C.4 adjust flow mark. */ 865 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj); 866 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj); 867 /* E.1 extract op_own byte. */ 868 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]); 869 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2); 870 /* D.1 fill in mbuf - rx_descriptor_fields1. */ 871 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1); 872 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0); 873 /* E.2 flip owner bit to mark CQEs from last round. */ 874 owner_mask = _mm_and_si128(op_own, owner_check); 875 if (ownership) 876 owner_mask = _mm_xor_si128(owner_mask, owner_check); 877 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check); 878 owner_mask = _mm_packs_epi32(owner_mask, zero); 879 /* E.3 get mask for invalidated CQEs. */ 880 opcode = _mm_and_si128(op_own, opcode_check); 881 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode); 882 invalid_mask = _mm_packs_epi32(invalid_mask, zero); 883 /* E.4 mask out beyond boundary. */ 884 invalid_mask = _mm_or_si128(invalid_mask, mask); 885 /* E.5 merge invalid_mask with invalid owner. */ 886 invalid_mask = _mm_or_si128(invalid_mask, owner_mask); 887 /* F.1 find compressed CQE format. */ 888 comp_mask = _mm_and_si128(op_own, format_check); 889 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check); 890 comp_mask = _mm_packs_epi32(comp_mask, zero); 891 /* F.2 mask out invalid entries. */ 892 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask); 893 comp_idx = _mm_cvtsi128_si64(comp_mask); 894 /* F.3 get the first compressed CQE. */ 895 comp_idx = comp_idx ? 896 __builtin_ctzll(comp_idx) / 897 (sizeof(uint16_t) * 8) : 898 MLX5_VPMD_DESCS_PER_LOOP; 899 /* E.6 mask out entries after the compressed CQE. */ 900 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8); 901 mask = _mm_sll_epi64(ones, mask); 902 invalid_mask = _mm_or_si128(invalid_mask, mask); 903 /* E.7 count non-compressed valid CQEs. */ 904 n = _mm_cvtsi128_si64(invalid_mask); 905 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) : 906 MLX5_VPMD_DESCS_PER_LOOP; 907 nocmp_n += n; 908 /* D.2 get the final invalid mask. */ 909 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8); 910 mask = _mm_sll_epi64(ones, mask); 911 invalid_mask = _mm_or_si128(invalid_mask, mask); 912 /* D.3 check error in opcode. */ 913 opcode = _mm_cmpeq_epi32(resp_err_check, opcode); 914 opcode = _mm_packs_epi32(opcode, zero); 915 opcode = _mm_andnot_si128(invalid_mask, opcode); 916 /* D.4 mark if any error is set */ 917 *err |= _mm_cvtsi128_si64(opcode); 918 /* D.5 fill in mbuf - rearm_data and packet_type. */ 919 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); 920 if (rxq->hw_timestamp) { 921 pkts[pos]->timestamp = 922 rte_be_to_cpu_64(cq[pos].timestamp); 923 pkts[pos + 1]->timestamp = 924 rte_be_to_cpu_64(cq[pos + p1].timestamp); 925 pkts[pos + 2]->timestamp = 926 rte_be_to_cpu_64(cq[pos + p2].timestamp); 927 pkts[pos + 3]->timestamp = 928 rte_be_to_cpu_64(cq[pos + p3].timestamp); 929 } 930 #ifdef MLX5_PMD_SOFT_COUNTERS 931 /* Add up received bytes count. */ 932 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask); 933 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt); 934 byte_cnt = _mm_hadd_epi16(byte_cnt, zero); 935 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero)); 936 #endif 937 /* 938 * Break the loop unless more valid CQE is expected, or if 939 * there's a compressed CQE. 940 */ 941 if (n != MLX5_VPMD_DESCS_PER_LOOP) 942 break; 943 } 944 /* If no new CQE seen, return without updating cq_db. */ 945 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) 946 return rcvd_pkt; 947 /* Update the consumer indexes for non-compressed CQEs. */ 948 assert(nocmp_n <= pkts_n); 949 rxq->cq_ci += nocmp_n; 950 rxq->rq_pi += nocmp_n; 951 rcvd_pkt += nocmp_n; 952 #ifdef MLX5_PMD_SOFT_COUNTERS 953 rxq->stats.ipackets += nocmp_n; 954 rxq->stats.ibytes += rcvd_byte; 955 #endif 956 /* Decompress the last CQE if compressed. */ 957 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 958 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 959 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]); 960 /* Return more packets if needed. */ 961 if (nocmp_n < pkts_n) { 962 uint16_t n = rxq->cq_ci - rxq->rq_pi; 963 964 n = RTE_MIN(n, pkts_n - nocmp_n); 965 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 966 rxq->rq_pi += n; 967 rcvd_pkt += n; 968 } 969 } 970 rte_compiler_barrier(); 971 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 972 return rcvd_pkt; 973 } 974 975 #endif /* RTE_PMD_MLX5_RXTX_VEC_SSE_H_ */ 976