1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_H_ 7 #define RTE_PMD_MLX5_RXTX_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 /* Verbs header. */ 14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 15 #ifdef PEDANTIC 16 #pragma GCC diagnostic ignored "-Wpedantic" 17 #endif 18 #include <infiniband/verbs.h> 19 #include <infiniband/mlx5dv.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_mbuf.h> 25 #include <rte_mempool.h> 26 #include <rte_common.h> 27 #include <rte_hexdump.h> 28 #include <rte_atomic.h> 29 #include <rte_spinlock.h> 30 #include <rte_io.h> 31 #include <rte_bus_pci.h> 32 33 #include "mlx5_utils.h" 34 #include "mlx5.h" 35 #include "mlx5_mr.h" 36 #include "mlx5_autoconf.h" 37 #include "mlx5_defs.h" 38 #include "mlx5_prm.h" 39 40 /* Support tunnel matching. */ 41 #define MLX5_FLOW_TUNNEL 5 42 43 struct mlx5_rxq_stats { 44 #ifdef MLX5_PMD_SOFT_COUNTERS 45 uint64_t ipackets; /**< Total of successfully received packets. */ 46 uint64_t ibytes; /**< Total of successfully received bytes. */ 47 #endif 48 uint64_t idropped; /**< Total of packets dropped when RX ring full. */ 49 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ 50 }; 51 52 struct mlx5_txq_stats { 53 #ifdef MLX5_PMD_SOFT_COUNTERS 54 uint64_t opackets; /**< Total of successfully sent packets. */ 55 uint64_t obytes; /**< Total of successfully sent bytes. */ 56 #endif 57 uint64_t oerrors; /**< Total number of failed transmitted packets. */ 58 }; 59 60 struct mlx5_priv; 61 62 /* Compressed CQE context. */ 63 struct rxq_zip { 64 uint16_t ai; /* Array index. */ 65 uint16_t ca; /* Current array index. */ 66 uint16_t na; /* Next array index. */ 67 uint16_t cq_ci; /* The next CQE. */ 68 uint32_t cqe_cnt; /* Number of CQEs. */ 69 }; 70 71 /* Multi-Packet RQ buffer header. */ 72 struct mlx5_mprq_buf { 73 struct rte_mempool *mp; 74 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */ 75 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */ 76 } __rte_cache_aligned; 77 78 /* Get pointer to the first stride. */ 79 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1) 80 81 /* RX queue descriptor. */ 82 struct mlx5_rxq_data { 83 unsigned int csum:1; /* Enable checksum offloading. */ 84 unsigned int hw_timestamp:1; /* Enable HW timestamp. */ 85 unsigned int vlan_strip:1; /* Enable VLAN stripping. */ 86 unsigned int crc_present:1; /* CRC must be subtracted. */ 87 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */ 88 unsigned int cqe_n:4; /* Log 2 of CQ elements. */ 89 unsigned int elts_n:4; /* Log 2 of Mbufs. */ 90 unsigned int rss_hash:1; /* RSS hash result is enabled. */ 91 unsigned int mark:1; /* Marked flow available on the queue. */ 92 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */ 93 unsigned int strd_sz_n:4; /* Log 2 of stride size. */ 94 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */ 95 unsigned int :6; /* Remaining bits. */ 96 volatile uint32_t *rq_db; 97 volatile uint32_t *cq_db; 98 uint16_t port_id; 99 uint32_t rq_ci; 100 uint16_t consumed_strd; /* Number of consumed strides in WQE. */ 101 uint32_t rq_pi; 102 uint32_t cq_ci; 103 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */ 104 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 105 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */ 106 volatile void *wqes; 107 volatile struct mlx5_cqe(*cqes)[]; 108 struct rxq_zip zip; /* Compressed context. */ 109 RTE_STD_C11 110 union { 111 struct rte_mbuf *(*elts)[]; 112 struct mlx5_mprq_buf *(*mprq_bufs)[]; 113 }; 114 struct rte_mempool *mp; 115 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 116 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */ 117 uint16_t idx; /* Queue index. */ 118 struct mlx5_rxq_stats stats; 119 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */ 120 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ 121 void *cq_uar; /* CQ user access region. */ 122 uint32_t cqn; /* CQ number. */ 123 uint8_t cq_arm_sn; /* CQ arm seq number. */ 124 #ifndef RTE_ARCH_64 125 rte_spinlock_t *uar_lock_cq; 126 /* CQ (UAR) access lock required for 32bit implementations */ 127 #endif 128 uint32_t tunnel; /* Tunnel information. */ 129 } __rte_cache_aligned; 130 131 /* Verbs Rx queue elements. */ 132 struct mlx5_rxq_ibv { 133 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */ 134 rte_atomic32_t refcnt; /* Reference counter. */ 135 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 136 struct ibv_cq *cq; /* Completion Queue. */ 137 struct ibv_wq *wq; /* Work Queue. */ 138 struct ibv_comp_channel *channel; 139 }; 140 141 /* RX queue control descriptor. */ 142 struct mlx5_rxq_ctrl { 143 struct mlx5_rxq_data rxq; /* Data path structure. */ 144 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ 145 rte_atomic32_t refcnt; /* Reference counter. */ 146 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */ 147 struct mlx5_priv *priv; /* Back pointer to private data. */ 148 unsigned int socket; /* CPU socket ID for allocations. */ 149 unsigned int irq:1; /* Whether IRQ is enabled. */ 150 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ 151 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ 152 }; 153 154 /* Indirection table. */ 155 struct mlx5_ind_table_ibv { 156 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */ 157 rte_atomic32_t refcnt; /* Reference counter. */ 158 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */ 159 uint32_t queues_n; /**< Number of queues in the list. */ 160 uint16_t queues[]; /**< Queue list. */ 161 }; 162 163 /* Hash Rx queue. */ 164 struct mlx5_hrxq { 165 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */ 166 rte_atomic32_t refcnt; /* Reference counter. */ 167 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */ 168 struct ibv_qp *qp; /* Verbs queue pair. */ 169 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 170 void *action; /* DV QP action pointer. */ 171 #endif 172 uint64_t hash_fields; /* Verbs Hash fields. */ 173 uint32_t rss_key_len; /* Hash key length in bytes. */ 174 uint8_t rss_key[]; /* Hash key. */ 175 }; 176 177 /* TX queue descriptor. */ 178 __extension__ 179 struct mlx5_txq_data { 180 uint16_t elts_head; /* Current counter in (*elts)[]. */ 181 uint16_t elts_tail; /* Counter of first element awaiting completion. */ 182 uint16_t elts_comp; /* Counter since last completion request. */ 183 uint16_t mpw_comp; /* WQ index since last completion request. */ 184 uint16_t cq_ci; /* Consumer index for completion queue. */ 185 #ifndef NDEBUG 186 uint16_t cq_pi; /* Producer index for completion queue. */ 187 #endif 188 uint16_t wqe_ci; /* Consumer index for work queue. */ 189 uint16_t wqe_pi; /* Producer index for work queue. */ 190 uint16_t elts_n:4; /* (*elts)[] length (in log2). */ 191 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */ 192 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */ 193 uint16_t tso_en:1; /* When set hardware TSO is enabled. */ 194 uint16_t tunnel_en:1; 195 /* When set TX offload for tunneled packets are supported. */ 196 uint16_t swp_en:1; /* Whether SW parser is enabled. */ 197 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 198 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */ 199 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */ 200 uint32_t qp_num_8s; /* QP number shifted by 8. */ 201 uint64_t offloads; /* Offloads for Tx Queue. */ 202 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 203 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */ 204 volatile void *wqes; /* Work queue (use volatile to write into). */ 205 volatile uint32_t *qp_db; /* Work queue doorbell. */ 206 volatile uint32_t *cq_db; /* Completion queue doorbell. */ 207 struct rte_mbuf *(*elts)[]; /* TX elements. */ 208 uint16_t port_id; /* Port ID of device. */ 209 uint16_t idx; /* Queue index. */ 210 struct mlx5_txq_stats stats; /* TX queue counters. */ 211 #ifndef RTE_ARCH_64 212 rte_spinlock_t *uar_lock; 213 /* UAR access lock required for 32bit implementations */ 214 #endif 215 } __rte_cache_aligned; 216 217 /* Verbs Rx queue elements. */ 218 struct mlx5_txq_ibv { 219 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */ 220 rte_atomic32_t refcnt; /* Reference counter. */ 221 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 222 struct ibv_cq *cq; /* Completion Queue. */ 223 struct ibv_qp *qp; /* Queue Pair. */ 224 }; 225 226 /* TX queue control descriptor. */ 227 struct mlx5_txq_ctrl { 228 struct mlx5_txq_data txq; /* Data path structure. */ 229 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */ 230 rte_atomic32_t refcnt; /* Reference counter. */ 231 unsigned int socket; /* CPU socket ID for allocations. */ 232 unsigned int max_inline_data; /* Max inline data. */ 233 unsigned int max_tso_header; /* Max TSO header size. */ 234 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */ 235 struct mlx5_priv *priv; /* Back pointer to private data. */ 236 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */ 237 void *bf_reg; /* BlueFlame register from Verbs. */ 238 }; 239 240 #define MLX5_TX_BFREG(txq) \ 241 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx]) 242 243 /* mlx5_rxq.c */ 244 245 extern uint8_t rss_hash_default_key[]; 246 247 int mlx5_check_mprq_support(struct rte_eth_dev *dev); 248 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); 249 int mlx5_mprq_enabled(struct rte_eth_dev *dev); 250 int mlx5_mprq_free_mp(struct rte_eth_dev *dev); 251 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); 252 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 253 unsigned int socket, const struct rte_eth_rxconf *conf, 254 struct rte_mempool *mp); 255 void mlx5_rx_queue_release(void *dpdk_rxq); 256 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); 257 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); 258 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 259 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 260 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx); 261 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev); 262 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, 263 uint16_t desc, unsigned int socket, 264 const struct rte_eth_rxconf *conf, 265 struct rte_mempool *mp); 266 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx); 267 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); 268 int mlx5_rxq_verify(struct rte_eth_dev *dev); 269 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); 270 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev); 271 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev, 272 const uint8_t *rss_key, uint32_t rss_key_len, 273 uint64_t hash_fields, 274 const uint16_t *queues, uint32_t queues_n, 275 int tunnel __rte_unused); 276 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev, 277 const uint8_t *rss_key, uint32_t rss_key_len, 278 uint64_t hash_fields, 279 const uint16_t *queues, uint32_t queues_n); 280 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq); 281 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev); 282 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev); 283 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev); 284 uint64_t mlx5_get_rx_port_offloads(void); 285 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); 286 287 /* mlx5_txq.c */ 288 289 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 290 unsigned int socket, const struct rte_eth_txconf *conf); 291 void mlx5_tx_queue_release(void *dpdk_txq); 292 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd); 293 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx); 294 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx); 295 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv); 296 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev); 297 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, 298 uint16_t desc, unsigned int socket, 299 const struct rte_eth_txconf *conf); 300 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx); 301 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx); 302 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx); 303 int mlx5_txq_verify(struct rte_eth_dev *dev); 304 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl); 305 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev); 306 307 /* mlx5_rxtx.c */ 308 309 extern uint32_t mlx5_ptype_table[]; 310 extern uint8_t mlx5_cksum_table[]; 311 extern uint8_t mlx5_swp_types_table[]; 312 313 void mlx5_set_ptype_table(void); 314 void mlx5_set_cksum_table(void); 315 void mlx5_set_swp_types_table(void); 316 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, 317 uint16_t pkts_n); 318 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, 319 uint16_t pkts_n); 320 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts, 321 uint16_t pkts_n); 322 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, 323 uint16_t pkts_n); 324 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); 325 void mlx5_mprq_buf_free_cb(void *addr, void *opaque); 326 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf); 327 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, 328 uint16_t pkts_n); 329 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, 330 uint16_t pkts_n); 331 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, 332 uint16_t pkts_n); 333 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset); 334 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset); 335 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); 336 337 /* Vectorized version of mlx5_rxtx.c */ 338 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev); 339 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev); 340 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); 341 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev); 342 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, 343 uint16_t pkts_n); 344 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, 345 uint16_t pkts_n); 346 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, 347 uint16_t pkts_n); 348 349 /* mlx5_mr.c */ 350 351 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl); 352 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr); 353 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb); 354 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, 355 struct rte_mempool *mp); 356 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova, 357 size_t len); 358 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova, 359 size_t len); 360 361 /** 362 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 363 * 64bit architectures. 364 * 365 * @param val 366 * value to write in CPU endian format. 367 * @param addr 368 * Address to write to. 369 * @param lock 370 * Address of the lock to use for that UAR access. 371 */ 372 static __rte_always_inline void 373 __mlx5_uar_write64_relaxed(uint64_t val, void *addr, 374 rte_spinlock_t *lock __rte_unused) 375 { 376 #ifdef RTE_ARCH_64 377 *(uint64_t *)addr = val; 378 #else /* !RTE_ARCH_64 */ 379 rte_spinlock_lock(lock); 380 *(uint32_t *)addr = val; 381 rte_io_wmb(); 382 *((uint32_t *)addr + 1) = val >> 32; 383 rte_spinlock_unlock(lock); 384 #endif 385 } 386 387 /** 388 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 389 * 64bit architectures while guaranteeing the order of execution with the 390 * code being executed. 391 * 392 * @param val 393 * value to write in CPU endian format. 394 * @param addr 395 * Address to write to. 396 * @param lock 397 * Address of the lock to use for that UAR access. 398 */ 399 static __rte_always_inline void 400 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) 401 { 402 rte_io_wmb(); 403 __mlx5_uar_write64_relaxed(val, addr, lock); 404 } 405 406 /* Assist macros, used instead of directly calling the functions they wrap. */ 407 #ifdef RTE_ARCH_64 408 #define mlx5_uar_write64_relaxed(val, dst, lock) \ 409 __mlx5_uar_write64_relaxed(val, dst, NULL) 410 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL) 411 #else 412 #define mlx5_uar_write64_relaxed(val, dst, lock) \ 413 __mlx5_uar_write64_relaxed(val, dst, lock) 414 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock) 415 #endif 416 417 #ifndef NDEBUG 418 /** 419 * Verify or set magic value in CQE. 420 * 421 * @param cqe 422 * Pointer to CQE. 423 * 424 * @return 425 * 0 the first time. 426 */ 427 static inline int 428 check_cqe_seen(volatile struct mlx5_cqe *cqe) 429 { 430 static const uint8_t magic[] = "seen"; 431 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1; 432 int ret = 1; 433 unsigned int i; 434 435 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i) 436 if (!ret || (*buf)[i] != magic[i]) { 437 ret = 0; 438 (*buf)[i] = magic[i]; 439 } 440 return ret; 441 } 442 #endif /* NDEBUG */ 443 444 /** 445 * Check whether CQE is valid. 446 * 447 * @param cqe 448 * Pointer to CQE. 449 * @param cqes_n 450 * Size of completion queue. 451 * @param ci 452 * Consumer index. 453 * 454 * @return 455 * 0 on success, 1 on failure. 456 */ 457 static __rte_always_inline int 458 check_cqe(volatile struct mlx5_cqe *cqe, 459 unsigned int cqes_n, const uint16_t ci) 460 { 461 uint16_t idx = ci & cqes_n; 462 uint8_t op_own = cqe->op_own; 463 uint8_t op_owner = MLX5_CQE_OWNER(op_own); 464 uint8_t op_code = MLX5_CQE_OPCODE(op_own); 465 466 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 467 return 1; /* No CQE. */ 468 #ifndef NDEBUG 469 if ((op_code == MLX5_CQE_RESP_ERR) || 470 (op_code == MLX5_CQE_REQ_ERR)) { 471 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe; 472 uint8_t syndrome = err_cqe->syndrome; 473 474 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) || 475 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR)) 476 return 0; 477 if (!check_cqe_seen(cqe)) { 478 DRV_LOG(ERR, 479 "unexpected CQE error %u (0x%02x) syndrome" 480 " 0x%02x", 481 op_code, op_code, syndrome); 482 rte_hexdump(stderr, "MLX5 Error CQE:", 483 (const void *)((uintptr_t)err_cqe), 484 sizeof(*cqe)); 485 } 486 return 1; 487 } else if ((op_code != MLX5_CQE_RESP_SEND) && 488 (op_code != MLX5_CQE_REQ)) { 489 if (!check_cqe_seen(cqe)) { 490 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)", 491 op_code, op_code); 492 rte_hexdump(stderr, "MLX5 CQE:", 493 (const void *)((uintptr_t)cqe), 494 sizeof(*cqe)); 495 } 496 return 1; 497 } 498 #endif /* NDEBUG */ 499 return 0; 500 } 501 502 /** 503 * Return the address of the WQE. 504 * 505 * @param txq 506 * Pointer to TX queue structure. 507 * @param wqe_ci 508 * WQE consumer index. 509 * 510 * @return 511 * WQE address. 512 */ 513 static inline uintptr_t * 514 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci) 515 { 516 ci &= ((1 << txq->wqe_n) - 1); 517 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE); 518 } 519 520 /** 521 * Manage TX completions. 522 * 523 * When sending a burst, mlx5_tx_burst() posts several WRs. 524 * 525 * @param txq 526 * Pointer to TX queue structure. 527 */ 528 static __rte_always_inline void 529 mlx5_tx_complete(struct mlx5_txq_data *txq) 530 { 531 const uint16_t elts_n = 1 << txq->elts_n; 532 const uint16_t elts_m = elts_n - 1; 533 const unsigned int cqe_n = 1 << txq->cqe_n; 534 const unsigned int cqe_cnt = cqe_n - 1; 535 uint16_t elts_free = txq->elts_tail; 536 uint16_t elts_tail; 537 uint16_t cq_ci = txq->cq_ci; 538 volatile struct mlx5_cqe *cqe = NULL; 539 volatile struct mlx5_wqe_ctrl *ctrl; 540 struct rte_mbuf *m, *free[elts_n]; 541 struct rte_mempool *pool = NULL; 542 unsigned int blk_n = 0; 543 544 cqe = &(*txq->cqes)[cq_ci & cqe_cnt]; 545 if (unlikely(check_cqe(cqe, cqe_n, cq_ci))) 546 return; 547 #ifndef NDEBUG 548 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) || 549 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) { 550 if (!check_cqe_seen(cqe)) { 551 DRV_LOG(ERR, "unexpected error CQE, Tx stopped"); 552 rte_hexdump(stderr, "MLX5 TXQ:", 553 (const void *)((uintptr_t)txq->wqes), 554 ((1 << txq->wqe_n) * 555 MLX5_WQE_SIZE)); 556 } 557 return; 558 } 559 #endif /* NDEBUG */ 560 ++cq_ci; 561 rte_cio_rmb(); 562 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter); 563 ctrl = (volatile struct mlx5_wqe_ctrl *) 564 tx_mlx5_wqe(txq, txq->wqe_pi); 565 elts_tail = ctrl->ctrl3; 566 assert((elts_tail & elts_m) < (1 << txq->wqe_n)); 567 /* Free buffers. */ 568 while (elts_free != elts_tail) { 569 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]); 570 if (likely(m != NULL)) { 571 if (likely(m->pool == pool)) { 572 free[blk_n++] = m; 573 } else { 574 if (likely(pool != NULL)) 575 rte_mempool_put_bulk(pool, 576 (void *)free, 577 blk_n); 578 free[0] = m; 579 pool = m->pool; 580 blk_n = 1; 581 } 582 } 583 } 584 if (blk_n) 585 rte_mempool_put_bulk(pool, (void *)free, blk_n); 586 #ifndef NDEBUG 587 elts_free = txq->elts_tail; 588 /* Poisoning. */ 589 while (elts_free != elts_tail) { 590 memset(&(*txq->elts)[elts_free & elts_m], 591 0x66, 592 sizeof((*txq->elts)[elts_free & elts_m])); 593 ++elts_free; 594 } 595 #endif 596 txq->cq_ci = cq_ci; 597 txq->elts_tail = elts_tail; 598 /* Update the consumer index. */ 599 rte_compiler_barrier(); 600 *txq->cq_db = rte_cpu_to_be_32(cq_ci); 601 } 602 603 /** 604 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the 605 * cloned mbuf is allocated is returned instead. 606 * 607 * @param buf 608 * Pointer to mbuf. 609 * 610 * @return 611 * Memory pool where data is located for given mbuf. 612 */ 613 static inline struct rte_mempool * 614 mlx5_mb2mp(struct rte_mbuf *buf) 615 { 616 if (unlikely(RTE_MBUF_CLONED(buf))) 617 return rte_mbuf_from_indirect(buf)->pool; 618 return buf->pool; 619 } 620 621 /** 622 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx 623 * as mempool is pre-configured and static. 624 * 625 * @param rxq 626 * Pointer to Rx queue structure. 627 * @param addr 628 * Address to search. 629 * 630 * @return 631 * Searched LKey on success, UINT32_MAX on no match. 632 */ 633 static __rte_always_inline uint32_t 634 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr) 635 { 636 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; 637 uint32_t lkey; 638 639 /* Linear search on MR cache array. */ 640 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru, 641 MLX5_MR_CACHE_N, addr); 642 if (likely(lkey != UINT32_MAX)) 643 return lkey; 644 /* Take slower bottom-half (Binary Search) on miss. */ 645 return mlx5_rx_addr2mr_bh(rxq, addr); 646 } 647 648 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr)) 649 650 /** 651 * Query LKey from a packet buffer for Tx. If not found, add the mempool. 652 * 653 * @param txq 654 * Pointer to Tx queue structure. 655 * @param addr 656 * Address to search. 657 * 658 * @return 659 * Searched LKey on success, UINT32_MAX on no match. 660 */ 661 static __rte_always_inline uint32_t 662 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb) 663 { 664 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl; 665 uintptr_t addr = (uintptr_t)mb->buf_addr; 666 uint32_t lkey; 667 668 /* Check generation bit to see if there's any change on existing MRs. */ 669 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 670 mlx5_mr_flush_local_cache(mr_ctrl); 671 /* Linear search on MR cache array. */ 672 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru, 673 MLX5_MR_CACHE_N, addr); 674 if (likely(lkey != UINT32_MAX)) 675 return lkey; 676 /* Take slower bottom-half on miss. */ 677 return mlx5_tx_mb2mr_bh(txq, mb); 678 } 679 680 /** 681 * Ring TX queue doorbell and flush the update if requested. 682 * 683 * @param txq 684 * Pointer to TX queue structure. 685 * @param wqe 686 * Pointer to the last WQE posted in the NIC. 687 * @param cond 688 * Request for write memory barrier after BlueFlame update. 689 */ 690 static __rte_always_inline void 691 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, 692 int cond) 693 { 694 uint64_t *dst = MLX5_TX_BFREG(txq); 695 volatile uint64_t *src = ((volatile uint64_t *)wqe); 696 697 rte_cio_wmb(); 698 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); 699 /* Ensure ordering between DB record and BF copy. */ 700 rte_wmb(); 701 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock); 702 if (cond) 703 rte_wmb(); 704 } 705 706 /** 707 * Ring TX queue doorbell and flush the update by write memory barrier. 708 * 709 * @param txq 710 * Pointer to TX queue structure. 711 * @param wqe 712 * Pointer to the last WQE posted in the NIC. 713 */ 714 static __rte_always_inline void 715 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe) 716 { 717 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1); 718 } 719 720 /** 721 * Convert mbuf to Verb SWP. 722 * 723 * @param txq_data 724 * Pointer to the Tx queue. 725 * @param buf 726 * Pointer to the mbuf. 727 * @param offsets 728 * Pointer to the SWP header offsets. 729 * @param swp_types 730 * Pointer to the SWP header types. 731 */ 732 static __rte_always_inline void 733 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf, 734 uint8_t *offsets, uint8_t *swp_types) 735 { 736 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT; 737 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK; 738 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG; 739 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK; 740 const uint64_t inner_ip = 741 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6); 742 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 | 743 PKT_TX_OUTER_IPV6; 744 uint16_t idx; 745 uint16_t off; 746 747 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP && 748 tunnel != PKT_TX_TUNNEL_IP))) 749 return; 750 /* 751 * The index should have: 752 * bit[0:1] = PKT_TX_L4_MASK 753 * bit[4] = PKT_TX_IPV6 754 * bit[8] = PKT_TX_OUTER_IPV6 755 * bit[9] = PKT_TX_OUTER_UDP 756 */ 757 idx = (buf->ol_flags & ol_flags_mask) >> 52; 758 if (tunnel == PKT_TX_TUNNEL_UDP) 759 idx |= 1 << 9; 760 *swp_types = mlx5_swp_types_table[idx]; 761 /* 762 * Set offsets for SW parser. Since ConnectX-5, SW parser just 763 * complements HW parser. SW parser starts to engage only if HW parser 764 * can't reach a header. For the older devices, HW parser will not kick 765 * in if any of SWP offsets is set. Therefore, all of the L3 offsets 766 * should be set regardless of HW offload. 767 */ 768 off = buf->outer_l2_len + (vlan ? sizeof(struct rte_vlan_hdr) : 0); 769 offsets[1] = off >> 1; /* Outer L3 offset. */ 770 off += buf->outer_l3_len; 771 if (tunnel == PKT_TX_TUNNEL_UDP) 772 offsets[0] = off >> 1; /* Outer L4 offset. */ 773 if (inner_ip) { 774 off += buf->l2_len; 775 offsets[3] = off >> 1; /* Inner L3 offset. */ 776 if (csum_flags == PKT_TX_TCP_CKSUM || tso || 777 csum_flags == PKT_TX_UDP_CKSUM) { 778 off += buf->l3_len; 779 offsets[2] = off >> 1; /* Inner L4 offset. */ 780 } 781 } 782 } 783 784 /** 785 * Convert the Checksum offloads to Verbs. 786 * 787 * @param buf 788 * Pointer to the mbuf. 789 * 790 * @return 791 * Converted checksum flags. 792 */ 793 static __rte_always_inline uint8_t 794 txq_ol_cksum_to_cs(struct rte_mbuf *buf) 795 { 796 uint32_t idx; 797 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK); 798 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK | 799 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM; 800 801 /* 802 * The index should have: 803 * bit[0] = PKT_TX_TCP_SEG 804 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM 805 * bit[4] = PKT_TX_IP_CKSUM 806 * bit[8] = PKT_TX_OUTER_IP_CKSUM 807 * bit[9] = tunnel 808 */ 809 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9); 810 return mlx5_cksum_table[idx]; 811 } 812 813 /** 814 * Count the number of contiguous single segment packets. 815 * 816 * @param pkts 817 * Pointer to array of packets. 818 * @param pkts_n 819 * Number of packets. 820 * 821 * @return 822 * Number of contiguous single segment packets. 823 */ 824 static __rte_always_inline unsigned int 825 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n) 826 { 827 unsigned int pos; 828 829 if (!pkts_n) 830 return 0; 831 /* Count the number of contiguous single segment packets. */ 832 for (pos = 0; pos < pkts_n; ++pos) 833 if (NB_SEGS(pkts[pos]) > 1) 834 break; 835 return pos; 836 } 837 838 /** 839 * Count the number of contiguous multi-segment packets. 840 * 841 * @param pkts 842 * Pointer to array of packets. 843 * @param pkts_n 844 * Number of packets. 845 * 846 * @return 847 * Number of contiguous multi-segment packets. 848 */ 849 static __rte_always_inline unsigned int 850 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n) 851 { 852 unsigned int pos; 853 854 if (!pkts_n) 855 return 0; 856 /* Count the number of contiguous multi-segment packets. */ 857 for (pos = 0; pos < pkts_n; ++pos) 858 if (NB_SEGS(pkts[pos]) == 1) 859 break; 860 return pos; 861 } 862 863 #endif /* RTE_PMD_MLX5_RXTX_H_ */ 864