1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_H_ 7 #define RTE_PMD_MLX5_RXTX_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 /* Verbs header. */ 14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 15 #ifdef PEDANTIC 16 #pragma GCC diagnostic ignored "-Wpedantic" 17 #endif 18 #include <infiniband/verbs.h> 19 #include <infiniband/mlx5dv.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_mbuf.h> 25 #include <rte_mempool.h> 26 #include <rte_common.h> 27 #include <rte_hexdump.h> 28 #include <rte_atomic.h> 29 #include <rte_spinlock.h> 30 #include <rte_io.h> 31 #include <rte_bus_pci.h> 32 #include <rte_malloc.h> 33 34 #include <mlx5_glue.h> 35 #include <mlx5_prm.h> 36 #include <mlx5_common.h> 37 #include <mlx5_common_mr.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5_utils.h" 41 #include "mlx5.h" 42 #include "mlx5_autoconf.h" 43 44 /* Support tunnel matching. */ 45 #define MLX5_FLOW_TUNNEL 10 46 47 /* Mbuf dynamic flag offset for inline. */ 48 extern uint64_t rte_net_mlx5_dynf_inline_mask; 49 50 struct mlx5_rxq_stats { 51 #ifdef MLX5_PMD_SOFT_COUNTERS 52 uint64_t ipackets; /**< Total of successfully received packets. */ 53 uint64_t ibytes; /**< Total of successfully received bytes. */ 54 #endif 55 uint64_t idropped; /**< Total of packets dropped when RX ring full. */ 56 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ 57 }; 58 59 struct mlx5_txq_stats { 60 #ifdef MLX5_PMD_SOFT_COUNTERS 61 uint64_t opackets; /**< Total of successfully sent packets. */ 62 uint64_t obytes; /**< Total of successfully sent bytes. */ 63 #endif 64 uint64_t oerrors; /**< Total number of failed transmitted packets. */ 65 }; 66 67 struct mlx5_priv; 68 69 /* Compressed CQE context. */ 70 struct rxq_zip { 71 uint16_t ai; /* Array index. */ 72 uint16_t ca; /* Current array index. */ 73 uint16_t na; /* Next array index. */ 74 uint16_t cq_ci; /* The next CQE. */ 75 uint32_t cqe_cnt; /* Number of CQEs. */ 76 }; 77 78 /* Multi-Packet RQ buffer header. */ 79 struct mlx5_mprq_buf { 80 struct rte_mempool *mp; 81 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */ 82 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */ 83 struct rte_mbuf_ext_shared_info shinfos[]; 84 /* 85 * Shared information per stride. 86 * More memory will be allocated for the first stride head-room and for 87 * the strides data. 88 */ 89 } __rte_cache_aligned; 90 91 /* Get pointer to the first stride. */ 92 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \ 93 sizeof(struct mlx5_mprq_buf) + \ 94 (strd_n) * \ 95 sizeof(struct rte_mbuf_ext_shared_info) + \ 96 RTE_PKTMBUF_HEADROOM)) 97 98 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 99 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 100 101 enum mlx5_rxq_err_state { 102 MLX5_RXQ_ERR_STATE_NO_ERROR = 0, 103 MLX5_RXQ_ERR_STATE_NEED_RESET, 104 MLX5_RXQ_ERR_STATE_NEED_READY, 105 }; 106 107 /* RX queue descriptor. */ 108 struct mlx5_rxq_data { 109 unsigned int csum:1; /* Enable checksum offloading. */ 110 unsigned int hw_timestamp:1; /* Enable HW timestamp. */ 111 unsigned int vlan_strip:1; /* Enable VLAN stripping. */ 112 unsigned int crc_present:1; /* CRC must be subtracted. */ 113 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */ 114 unsigned int cqe_n:4; /* Log 2 of CQ elements. */ 115 unsigned int elts_n:4; /* Log 2 of Mbufs. */ 116 unsigned int rss_hash:1; /* RSS hash result is enabled. */ 117 unsigned int mark:1; /* Marked flow available on the queue. */ 118 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */ 119 unsigned int strd_sz_n:4; /* Log 2 of stride size. */ 120 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */ 121 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */ 122 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */ 123 unsigned int lro:1; /* Enable LRO. */ 124 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */ 125 volatile uint32_t *rq_db; 126 volatile uint32_t *cq_db; 127 uint16_t port_id; 128 uint32_t rq_ci; 129 uint16_t consumed_strd; /* Number of consumed strides in WQE. */ 130 uint32_t rq_pi; 131 uint32_t cq_ci; 132 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */ 133 union { 134 struct rxq_zip zip; /* Compressed context. */ 135 uint16_t decompressed; 136 /* Number of ready mbufs decompressed from the CQ. */ 137 }; 138 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 139 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */ 140 volatile void *wqes; 141 volatile struct mlx5_cqe(*cqes)[]; 142 RTE_STD_C11 143 union { 144 struct rte_mbuf *(*elts)[]; 145 struct mlx5_mprq_buf *(*mprq_bufs)[]; 146 }; 147 struct rte_mempool *mp; 148 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 149 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */ 150 uint16_t idx; /* Queue index. */ 151 struct mlx5_rxq_stats stats; 152 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ 153 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ 154 void *cq_uar; /* CQ user access region. */ 155 uint32_t cqn; /* CQ number. */ 156 uint8_t cq_arm_sn; /* CQ arm seq number. */ 157 #ifndef RTE_ARCH_64 158 rte_spinlock_t *uar_lock_cq; 159 /* CQ (UAR) access lock required for 32bit implementations */ 160 #endif 161 uint32_t tunnel; /* Tunnel information. */ 162 uint64_t flow_meta_mask; 163 int32_t flow_meta_offset; 164 } __rte_cache_aligned; 165 166 enum mlx5_rxq_obj_type { 167 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */ 168 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */ 169 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN, 170 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */ 171 }; 172 173 enum mlx5_rxq_type { 174 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */ 175 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ 176 MLX5_RXQ_TYPE_UNDEFINED, 177 }; 178 179 /* Verbs/DevX Rx queue elements. */ 180 struct mlx5_rxq_obj { 181 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 182 rte_atomic32_t refcnt; /* Reference counter. */ 183 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 184 struct ibv_cq *cq; /* Completion Queue. */ 185 enum mlx5_rxq_obj_type type; 186 RTE_STD_C11 187 union { 188 struct ibv_wq *wq; /* Work Queue. */ 189 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */ 190 }; 191 struct ibv_comp_channel *channel; 192 }; 193 194 /* RX queue control descriptor. */ 195 struct mlx5_rxq_ctrl { 196 struct mlx5_rxq_data rxq; /* Data path structure. */ 197 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ 198 rte_atomic32_t refcnt; /* Reference counter. */ 199 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */ 200 struct mlx5_priv *priv; /* Back pointer to private data. */ 201 enum mlx5_rxq_type type; /* Rxq type. */ 202 unsigned int socket; /* CPU socket ID for allocations. */ 203 unsigned int irq:1; /* Whether IRQ is enabled. */ 204 unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */ 205 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ 206 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ 207 uint32_t wqn; /* WQ number. */ 208 uint16_t dump_file_n; /* Number of dump files. */ 209 uint32_t dbr_umem_id; /* Storing door-bell information, */ 210 uint64_t dbr_offset; /* needed when freeing door-bell. */ 211 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */ 212 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ 213 }; 214 215 enum mlx5_ind_tbl_type { 216 MLX5_IND_TBL_TYPE_IBV, 217 MLX5_IND_TBL_TYPE_DEVX, 218 }; 219 220 /* Indirection table. */ 221 struct mlx5_ind_table_obj { 222 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 223 rte_atomic32_t refcnt; /* Reference counter. */ 224 enum mlx5_ind_tbl_type type; 225 RTE_STD_C11 226 union { 227 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */ 228 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 229 }; 230 uint32_t queues_n; /**< Number of queues in the list. */ 231 uint16_t queues[]; /**< Queue list. */ 232 }; 233 234 /* Hash Rx queue. */ 235 struct mlx5_hrxq { 236 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ 237 rte_atomic32_t refcnt; /* Reference counter. */ 238 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 239 RTE_STD_C11 240 union { 241 struct ibv_qp *qp; /* Verbs queue pair. */ 242 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 243 }; 244 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 245 void *action; /* DV QP action pointer. */ 246 #endif 247 uint64_t hash_fields; /* Verbs Hash fields. */ 248 uint32_t rss_key_len; /* Hash key length in bytes. */ 249 uint8_t rss_key[]; /* Hash key. */ 250 }; 251 252 /* TX queue send local data. */ 253 __extension__ 254 struct mlx5_txq_local { 255 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */ 256 struct rte_mbuf *mbuf; /* first mbuf to process. */ 257 uint16_t pkts_copy; /* packets copied to elts. */ 258 uint16_t pkts_sent; /* packets sent. */ 259 uint16_t pkts_loop; /* packets sent on loop entry. */ 260 uint16_t elts_free; /* available elts remain. */ 261 uint16_t wqe_free; /* available wqe remain. */ 262 uint16_t mbuf_off; /* data offset in current mbuf. */ 263 uint16_t mbuf_nseg; /* number of remaining mbuf. */ 264 }; 265 266 /* TX queue descriptor. */ 267 __extension__ 268 struct mlx5_txq_data { 269 uint16_t elts_head; /* Current counter in (*elts)[]. */ 270 uint16_t elts_tail; /* Counter of first element awaiting completion. */ 271 uint16_t elts_comp; /* elts index since last completion request. */ 272 uint16_t elts_s; /* Number of mbuf elements. */ 273 uint16_t elts_m; /* Mask for mbuf elements indices. */ 274 /* Fields related to elts mbuf storage. */ 275 uint16_t wqe_ci; /* Consumer index for work queue. */ 276 uint16_t wqe_pi; /* Producer index for work queue. */ 277 uint16_t wqe_s; /* Number of WQ elements. */ 278 uint16_t wqe_m; /* Mask Number for WQ elements. */ 279 uint16_t wqe_comp; /* WQE index since last completion request. */ 280 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */ 281 /* WQ related fields. */ 282 uint16_t cq_ci; /* Consumer index for completion queue. */ 283 uint16_t cq_pi; /* Production index for completion queue. */ 284 uint16_t cqe_s; /* Number of CQ elements. */ 285 uint16_t cqe_m; /* Mask for CQ indices. */ 286 /* CQ related fields. */ 287 uint16_t elts_n:4; /* elts[] length (in log2). */ 288 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */ 289 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */ 290 uint16_t tso_en:1; /* When set hardware TSO is enabled. */ 291 uint16_t tunnel_en:1; 292 /* When set TX offload for tunneled packets are supported. */ 293 uint16_t swp_en:1; /* Whether SW parser is enabled. */ 294 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */ 295 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */ 296 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */ 297 uint16_t inlen_send; /* Ordinary send data inline size. */ 298 uint16_t inlen_empw; /* eMPW max packet size to inline. */ 299 uint16_t inlen_mode; /* Minimal data length to inline. */ 300 uint32_t qp_num_8s; /* QP number shifted by 8. */ 301 uint64_t offloads; /* Offloads for Tx Queue. */ 302 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 303 struct mlx5_wqe *wqes; /* Work queue. */ 304 struct mlx5_wqe *wqes_end; /* Work queue array limit. */ 305 #ifdef RTE_LIBRTE_MLX5_DEBUG 306 uint32_t *fcqs; /* Free completion queue (debug extended). */ 307 #else 308 uint16_t *fcqs; /* Free completion queue. */ 309 #endif 310 volatile struct mlx5_cqe *cqes; /* Completion queue. */ 311 volatile uint32_t *qp_db; /* Work queue doorbell. */ 312 volatile uint32_t *cq_db; /* Completion queue doorbell. */ 313 uint16_t port_id; /* Port ID of device. */ 314 uint16_t idx; /* Queue index. */ 315 struct mlx5_txq_stats stats; /* TX queue counters. */ 316 #ifndef RTE_ARCH_64 317 rte_spinlock_t *uar_lock; 318 /* UAR access lock required for 32bit implementations */ 319 #endif 320 struct rte_mbuf *elts[0]; 321 /* Storage for queued packets, must be the last field. */ 322 } __rte_cache_aligned; 323 324 enum mlx5_txq_obj_type { 325 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */ 326 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN, 327 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */ 328 }; 329 330 enum mlx5_txq_type { 331 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */ 332 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ 333 }; 334 335 /* Verbs/DevX Tx queue elements. */ 336 struct mlx5_txq_obj { 337 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 338 rte_atomic32_t refcnt; /* Reference counter. */ 339 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 340 enum mlx5_txq_obj_type type; /* The txq object type. */ 341 RTE_STD_C11 342 union { 343 struct { 344 struct ibv_cq *cq; /* Completion Queue. */ 345 struct ibv_qp *qp; /* Queue Pair. */ 346 }; 347 struct { 348 struct mlx5_devx_obj *sq; 349 /* DevX object for Sx queue. */ 350 struct mlx5_devx_obj *tis; /* The TIS object. */ 351 }; 352 }; 353 }; 354 355 /* TX queue control descriptor. */ 356 struct mlx5_txq_ctrl { 357 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */ 358 rte_atomic32_t refcnt; /* Reference counter. */ 359 unsigned int socket; /* CPU socket ID for allocations. */ 360 enum mlx5_txq_type type; /* The txq ctrl type. */ 361 unsigned int max_inline_data; /* Max inline data. */ 362 unsigned int max_tso_header; /* Max TSO header size. */ 363 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */ 364 struct mlx5_priv *priv; /* Back pointer to private data. */ 365 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */ 366 void *bf_reg; /* BlueFlame register from Verbs. */ 367 uint16_t dump_file_n; /* Number of dump files. */ 368 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ 369 struct mlx5_txq_data txq; /* Data path structure. */ 370 /* Must be the last field in the structure, contains elts[]. */ 371 }; 372 373 #define MLX5_TX_BFREG(txq) \ 374 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx]) 375 376 /* mlx5_rxq.c */ 377 378 extern uint8_t rss_hash_default_key[]; 379 380 int mlx5_check_mprq_support(struct rte_eth_dev *dev); 381 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); 382 int mlx5_mprq_enabled(struct rte_eth_dev *dev); 383 int mlx5_mprq_free_mp(struct rte_eth_dev *dev); 384 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); 385 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 386 unsigned int socket, const struct rte_eth_rxconf *conf, 387 struct rte_mempool *mp); 388 int mlx5_rx_hairpin_queue_setup 389 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 390 const struct rte_eth_hairpin_conf *hairpin_conf); 391 void mlx5_rx_queue_release(void *dpdk_rxq); 392 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); 393 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); 394 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 395 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 396 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx, 397 enum mlx5_rxq_obj_type type); 398 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); 399 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, 400 uint16_t desc, unsigned int socket, 401 const struct rte_eth_rxconf *conf, 402 struct rte_mempool *mp); 403 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new 404 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 405 const struct rte_eth_hairpin_conf *hairpin_conf); 406 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx); 407 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); 408 int mlx5_rxq_verify(struct rte_eth_dev *dev); 409 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); 410 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev); 411 uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev, 412 const uint8_t *rss_key, uint32_t rss_key_len, 413 uint64_t hash_fields, 414 const uint16_t *queues, uint32_t queues_n, 415 int tunnel __rte_unused); 416 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, 417 const uint8_t *rss_key, uint32_t rss_key_len, 418 uint64_t hash_fields, 419 const uint16_t *queues, uint32_t queues_n); 420 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); 421 int mlx5_hrxq_verify(struct rte_eth_dev *dev); 422 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx); 423 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev); 424 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev); 425 uint64_t mlx5_get_rx_port_offloads(void); 426 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); 427 428 /* mlx5_txq.c */ 429 430 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 431 unsigned int socket, const struct rte_eth_txconf *conf); 432 int mlx5_tx_hairpin_queue_setup 433 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 434 const struct rte_eth_hairpin_conf *hairpin_conf); 435 void mlx5_tx_queue_release(void *dpdk_txq); 436 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd); 437 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx, 438 enum mlx5_txq_obj_type type); 439 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx); 440 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv); 441 int mlx5_txq_obj_verify(struct rte_eth_dev *dev); 442 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, 443 uint16_t desc, unsigned int socket, 444 const struct rte_eth_txconf *conf); 445 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new 446 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 447 const struct rte_eth_hairpin_conf *hairpin_conf); 448 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx); 449 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx); 450 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx); 451 int mlx5_txq_verify(struct rte_eth_dev *dev); 452 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl); 453 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl); 454 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev); 455 456 /* mlx5_rxtx.c */ 457 458 extern uint32_t mlx5_ptype_table[]; 459 extern uint8_t mlx5_cksum_table[]; 460 extern uint8_t mlx5_swp_types_table[]; 461 462 void mlx5_set_ptype_table(void); 463 void mlx5_set_cksum_table(void); 464 void mlx5_set_swp_types_table(void); 465 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); 466 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq); 467 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec); 468 void mlx5_mprq_buf_free_cb(void *addr, void *opaque); 469 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf); 470 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, 471 uint16_t pkts_n); 472 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, 473 uint16_t pkts_n); 474 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, 475 uint16_t pkts_n); 476 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset); 477 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset); 478 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); 479 void mlx5_dump_debug_information(const char *path, const char *title, 480 const void *buf, unsigned int len); 481 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev, 482 const struct mlx5_mp_arg_queue_state_modify *sm); 483 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 484 struct rte_eth_rxq_info *qinfo); 485 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 486 struct rte_eth_txq_info *qinfo); 487 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 488 struct rte_eth_burst_mode *mode); 489 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 490 struct rte_eth_burst_mode *mode); 491 492 /* Vectorized version of mlx5_rxtx.c */ 493 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); 494 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev); 495 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, 496 uint16_t pkts_n); 497 498 /* mlx5_mr.c */ 499 500 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl); 501 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr); 502 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb); 503 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, 504 struct rte_mempool *mp); 505 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova, 506 size_t len); 507 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova, 508 size_t len); 509 510 /** 511 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 512 * 64bit architectures. 513 * 514 * @param val 515 * value to write in CPU endian format. 516 * @param addr 517 * Address to write to. 518 * @param lock 519 * Address of the lock to use for that UAR access. 520 */ 521 static __rte_always_inline void 522 __mlx5_uar_write64_relaxed(uint64_t val, void *addr, 523 rte_spinlock_t *lock __rte_unused) 524 { 525 #ifdef RTE_ARCH_64 526 *(uint64_t *)addr = val; 527 #else /* !RTE_ARCH_64 */ 528 rte_spinlock_lock(lock); 529 *(uint32_t *)addr = val; 530 rte_io_wmb(); 531 *((uint32_t *)addr + 1) = val >> 32; 532 rte_spinlock_unlock(lock); 533 #endif 534 } 535 536 /** 537 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 538 * 64bit architectures while guaranteeing the order of execution with the 539 * code being executed. 540 * 541 * @param val 542 * value to write in CPU endian format. 543 * @param addr 544 * Address to write to. 545 * @param lock 546 * Address of the lock to use for that UAR access. 547 */ 548 static __rte_always_inline void 549 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) 550 { 551 rte_io_wmb(); 552 __mlx5_uar_write64_relaxed(val, addr, lock); 553 } 554 555 /* Assist macros, used instead of directly calling the functions they wrap. */ 556 #ifdef RTE_ARCH_64 557 #define mlx5_uar_write64_relaxed(val, dst, lock) \ 558 __mlx5_uar_write64_relaxed(val, dst, NULL) 559 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL) 560 #else 561 #define mlx5_uar_write64_relaxed(val, dst, lock) \ 562 __mlx5_uar_write64_relaxed(val, dst, lock) 563 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock) 564 #endif 565 566 /** 567 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the 568 * cloned mbuf is allocated is returned instead. 569 * 570 * @param buf 571 * Pointer to mbuf. 572 * 573 * @return 574 * Memory pool where data is located for given mbuf. 575 */ 576 static inline struct rte_mempool * 577 mlx5_mb2mp(struct rte_mbuf *buf) 578 { 579 if (unlikely(RTE_MBUF_CLONED(buf))) 580 return rte_mbuf_from_indirect(buf)->pool; 581 return buf->pool; 582 } 583 584 /** 585 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx 586 * as mempool is pre-configured and static. 587 * 588 * @param rxq 589 * Pointer to Rx queue structure. 590 * @param addr 591 * Address to search. 592 * 593 * @return 594 * Searched LKey on success, UINT32_MAX on no match. 595 */ 596 static __rte_always_inline uint32_t 597 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr) 598 { 599 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; 600 uint32_t lkey; 601 602 /* Linear search on MR cache array. */ 603 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 604 MLX5_MR_CACHE_N, addr); 605 if (likely(lkey != UINT32_MAX)) 606 return lkey; 607 /* Take slower bottom-half (Binary Search) on miss. */ 608 return mlx5_rx_addr2mr_bh(rxq, addr); 609 } 610 611 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr)) 612 613 /** 614 * Query LKey from a packet buffer for Tx. If not found, add the mempool. 615 * 616 * @param txq 617 * Pointer to Tx queue structure. 618 * @param addr 619 * Address to search. 620 * 621 * @return 622 * Searched LKey on success, UINT32_MAX on no match. 623 */ 624 static __rte_always_inline uint32_t 625 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb) 626 { 627 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl; 628 uintptr_t addr = (uintptr_t)mb->buf_addr; 629 uint32_t lkey; 630 631 /* Check generation bit to see if there's any change on existing MRs. */ 632 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 633 mlx5_mr_flush_local_cache(mr_ctrl); 634 /* Linear search on MR cache array. */ 635 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 636 MLX5_MR_CACHE_N, addr); 637 if (likely(lkey != UINT32_MAX)) 638 return lkey; 639 /* Take slower bottom-half on miss. */ 640 return mlx5_tx_mb2mr_bh(txq, mb); 641 } 642 643 /** 644 * Ring TX queue doorbell and flush the update if requested. 645 * 646 * @param txq 647 * Pointer to TX queue structure. 648 * @param wqe 649 * Pointer to the last WQE posted in the NIC. 650 * @param cond 651 * Request for write memory barrier after BlueFlame update. 652 */ 653 static __rte_always_inline void 654 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, 655 int cond) 656 { 657 uint64_t *dst = MLX5_TX_BFREG(txq); 658 volatile uint64_t *src = ((volatile uint64_t *)wqe); 659 660 rte_cio_wmb(); 661 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); 662 /* Ensure ordering between DB record and BF copy. */ 663 rte_wmb(); 664 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock); 665 if (cond) 666 rte_wmb(); 667 } 668 669 /** 670 * Ring TX queue doorbell and flush the update by write memory barrier. 671 * 672 * @param txq 673 * Pointer to TX queue structure. 674 * @param wqe 675 * Pointer to the last WQE posted in the NIC. 676 */ 677 static __rte_always_inline void 678 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe) 679 { 680 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1); 681 } 682 683 #endif /* RTE_PMD_MLX5_RXTX_H_ */ 684