1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef RTE_PMD_MLX5_RXTX_H_ 35 #define RTE_PMD_MLX5_RXTX_H_ 36 37 #include <stddef.h> 38 #include <stdint.h> 39 40 /* Verbs header. */ 41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 42 #ifdef PEDANTIC 43 #pragma GCC diagnostic ignored "-Wpedantic" 44 #endif 45 #include <infiniband/verbs.h> 46 #include <infiniband/mlx5dv.h> 47 #ifdef PEDANTIC 48 #pragma GCC diagnostic error "-Wpedantic" 49 #endif 50 51 #include <rte_mbuf.h> 52 #include <rte_mempool.h> 53 #include <rte_common.h> 54 #include <rte_hexdump.h> 55 56 #include "mlx5_utils.h" 57 #include "mlx5.h" 58 #include "mlx5_autoconf.h" 59 #include "mlx5_defs.h" 60 #include "mlx5_prm.h" 61 62 struct mlx5_rxq_stats { 63 unsigned int idx; /**< Mapping index. */ 64 #ifdef MLX5_PMD_SOFT_COUNTERS 65 uint64_t ipackets; /**< Total of successfully received packets. */ 66 uint64_t ibytes; /**< Total of successfully received bytes. */ 67 #endif 68 uint64_t idropped; /**< Total of packets dropped when RX ring full. */ 69 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ 70 }; 71 72 struct mlx5_txq_stats { 73 unsigned int idx; /**< Mapping index. */ 74 #ifdef MLX5_PMD_SOFT_COUNTERS 75 uint64_t opackets; /**< Total of successfully sent packets. */ 76 uint64_t obytes; /**< Total of successfully sent bytes. */ 77 #endif 78 uint64_t oerrors; /**< Total number of failed transmitted packets. */ 79 }; 80 81 /* Flow director queue structure. */ 82 struct fdir_queue { 83 struct ibv_qp *qp; /* Associated RX QP. */ 84 struct ibv_rwq_ind_table *ind_table; /* Indirection table. */ 85 struct ibv_wq *wq; /* Work queue. */ 86 struct ibv_cq *cq; /* Completion queue. */ 87 }; 88 89 struct priv; 90 91 /* Compressed CQE context. */ 92 struct rxq_zip { 93 uint16_t ai; /* Array index. */ 94 uint16_t ca; /* Current array index. */ 95 uint16_t na; /* Next array index. */ 96 uint16_t cq_ci; /* The next CQE. */ 97 uint32_t cqe_cnt; /* Number of CQEs. */ 98 }; 99 100 /* RX queue descriptor. */ 101 struct rxq { 102 unsigned int csum:1; /* Enable checksum offloading. */ 103 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */ 104 unsigned int vlan_strip:1; /* Enable VLAN stripping. */ 105 unsigned int crc_present:1; /* CRC must be subtracted. */ 106 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */ 107 unsigned int cqe_n:4; /* Log 2 of CQ elements. */ 108 unsigned int elts_n:4; /* Log 2 of Mbufs. */ 109 unsigned int rss_hash:1; /* RSS hash result is enabled. */ 110 unsigned int mark:1; /* Marked flow available on the queue. */ 111 unsigned int pending_err:1; /* CQE error needs to be handled. */ 112 unsigned int :15; /* Remaining bits. */ 113 volatile uint32_t *rq_db; 114 volatile uint32_t *cq_db; 115 uint16_t port_id; 116 uint16_t rq_ci; 117 uint16_t rq_pi; 118 uint16_t cq_ci; 119 volatile struct mlx5_wqe_data_seg(*wqes)[]; 120 volatile struct mlx5_cqe(*cqes)[]; 121 struct rxq_zip zip; /* Compressed context. */ 122 struct rte_mbuf *(*elts)[]; 123 struct rte_mempool *mp; 124 struct mlx5_rxq_stats stats; 125 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */ 126 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ 127 void *cq_uar; /* CQ user access region. */ 128 uint32_t cqn; /* CQ number. */ 129 uint8_t cq_arm_sn; /* CQ arm seq number. */ 130 } __rte_cache_aligned; 131 132 /* RX queue control descriptor. */ 133 struct rxq_ctrl { 134 struct priv *priv; /* Back pointer to private data. */ 135 struct ibv_cq *cq; /* Completion Queue. */ 136 struct ibv_wq *wq; /* Work Queue. */ 137 struct fdir_queue *fdir_queue; /* Flow director queue. */ 138 struct ibv_mr *mr; /* Memory Region (for mp). */ 139 struct ibv_comp_channel *channel; 140 unsigned int socket; /* CPU socket ID for allocations. */ 141 struct rxq rxq; /* Data path structure. */ 142 }; 143 144 /* Hash RX queue types. */ 145 enum hash_rxq_type { 146 HASH_RXQ_TCPV4, 147 HASH_RXQ_UDPV4, 148 HASH_RXQ_IPV4, 149 HASH_RXQ_TCPV6, 150 HASH_RXQ_UDPV6, 151 HASH_RXQ_IPV6, 152 HASH_RXQ_ETH, 153 }; 154 155 /* Flow structure with Ethernet specification. It is packed to prevent padding 156 * between attr and spec as this layout is expected by libibverbs. */ 157 struct flow_attr_spec_eth { 158 struct ibv_flow_attr attr; 159 struct ibv_flow_spec_eth spec; 160 } __attribute__((packed)); 161 162 /* Define a struct flow_attr_spec_eth object as an array of at least 163 * "size" bytes. Room after the first index is normally used to store 164 * extra flow specifications. */ 165 #define FLOW_ATTR_SPEC_ETH(name, size) \ 166 struct flow_attr_spec_eth name \ 167 [((size) / sizeof(struct flow_attr_spec_eth)) + \ 168 !!((size) % sizeof(struct flow_attr_spec_eth))] 169 170 /* Initialization data for hash RX queue. */ 171 struct hash_rxq_init { 172 uint64_t hash_fields; /* Fields that participate in the hash. */ 173 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */ 174 unsigned int flow_priority; /* Flow priority to use. */ 175 union { 176 struct { 177 enum ibv_flow_spec_type type; 178 uint16_t size; 179 } hdr; 180 struct ibv_flow_spec_tcp_udp tcp_udp; 181 struct ibv_flow_spec_ipv4 ipv4; 182 struct ibv_flow_spec_ipv6 ipv6; 183 struct ibv_flow_spec_eth eth; 184 } flow_spec; /* Flow specification template. */ 185 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */ 186 }; 187 188 /* Initialization data for indirection table. */ 189 struct ind_table_init { 190 unsigned int max_size; /* Maximum number of WQs. */ 191 /* Hash RX queues using this table. */ 192 unsigned int hash_types; 193 unsigned int hash_types_n; 194 }; 195 196 /* Initialization data for special flows. */ 197 struct special_flow_init { 198 uint8_t dst_mac_val[6]; 199 uint8_t dst_mac_mask[6]; 200 unsigned int hash_types; 201 unsigned int per_vlan:1; 202 }; 203 204 enum hash_rxq_flow_type { 205 HASH_RXQ_FLOW_TYPE_PROMISC, 206 HASH_RXQ_FLOW_TYPE_ALLMULTI, 207 HASH_RXQ_FLOW_TYPE_BROADCAST, 208 HASH_RXQ_FLOW_TYPE_IPV6MULTI, 209 HASH_RXQ_FLOW_TYPE_MAC, 210 }; 211 212 #ifndef NDEBUG 213 static inline const char * 214 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type) 215 { 216 switch (flow_type) { 217 case HASH_RXQ_FLOW_TYPE_PROMISC: 218 return "promiscuous"; 219 case HASH_RXQ_FLOW_TYPE_ALLMULTI: 220 return "allmulticast"; 221 case HASH_RXQ_FLOW_TYPE_BROADCAST: 222 return "broadcast"; 223 case HASH_RXQ_FLOW_TYPE_IPV6MULTI: 224 return "IPv6 multicast"; 225 case HASH_RXQ_FLOW_TYPE_MAC: 226 return "MAC"; 227 } 228 return NULL; 229 } 230 #endif /* NDEBUG */ 231 232 struct hash_rxq { 233 struct priv *priv; /* Back pointer to private data. */ 234 struct ibv_qp *qp; /* Hash RX QP. */ 235 enum hash_rxq_type type; /* Hash RX queue type. */ 236 /* MAC flow steering rules, one per VLAN ID. */ 237 struct ibv_flow *mac_flow 238 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS]; 239 struct ibv_flow *special_flow 240 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS]; 241 }; 242 243 /* TX queue descriptor. */ 244 __extension__ 245 struct txq { 246 uint16_t elts_head; /* Current counter in (*elts)[]. */ 247 uint16_t elts_tail; /* Counter of first element awaiting completion. */ 248 uint16_t elts_comp; /* Counter since last completion request. */ 249 uint16_t mpw_comp; /* WQ index since last completion request. */ 250 uint16_t cq_ci; /* Consumer index for completion queue. */ 251 uint16_t cq_pi; /* Producer index for completion queue. */ 252 uint16_t wqe_ci; /* Consumer index for work queue. */ 253 uint16_t wqe_pi; /* Producer index for work queue. */ 254 uint16_t elts_n:4; /* (*elts)[] length (in log2). */ 255 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */ 256 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */ 257 uint16_t inline_en:1; /* When set inline is enabled. */ 258 uint16_t tso_en:1; /* When set hardware TSO is enabled. */ 259 uint16_t tunnel_en:1; 260 /* When set TX offload for tunneled packets are supported. */ 261 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 262 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */ 263 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */ 264 uint32_t qp_num_8s; /* QP number shifted by 8. */ 265 uint32_t flags; /* Flags for Tx Queue. */ 266 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */ 267 volatile void *wqes; /* Work queue (use volatile to write into). */ 268 volatile uint32_t *qp_db; /* Work queue doorbell. */ 269 volatile uint32_t *cq_db; /* Completion queue doorbell. */ 270 volatile void *bf_reg; /* Blueflame register. */ 271 struct { 272 uintptr_t start; /* Start address of MR */ 273 uintptr_t end; /* End address of MR */ 274 struct ibv_mr *mr; /* Memory Region (for mp). */ 275 uint32_t lkey; /* rte_cpu_to_be_32(mr->lkey) */ 276 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */ 277 uint16_t mr_cache_idx; /* Index of last hit entry. */ 278 struct rte_mbuf *(*elts)[]; /* TX elements. */ 279 struct mlx5_txq_stats stats; /* TX queue counters. */ 280 } __rte_cache_aligned; 281 282 /* TX queue control descriptor. */ 283 struct txq_ctrl { 284 struct priv *priv; /* Back pointer to private data. */ 285 struct ibv_cq *cq; /* Completion Queue. */ 286 struct ibv_qp *qp; /* Queue Pair. */ 287 unsigned int socket; /* CPU socket ID for allocations. */ 288 struct txq txq; /* Data path structure. */ 289 }; 290 291 /* mlx5_rxq.c */ 292 293 extern const struct hash_rxq_init hash_rxq_init[]; 294 extern const unsigned int hash_rxq_init_n; 295 296 extern uint8_t rss_hash_default_key[]; 297 extern const size_t rss_hash_default_key_len; 298 299 size_t priv_flow_attr(struct priv *, struct ibv_flow_attr *, 300 size_t, enum hash_rxq_type); 301 int priv_create_hash_rxqs(struct priv *); 302 void priv_destroy_hash_rxqs(struct priv *); 303 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type); 304 int priv_rehash_flows(struct priv *); 305 void rxq_cleanup(struct rxq_ctrl *); 306 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int, 307 const struct rte_eth_rxconf *, struct rte_mempool *); 308 void mlx5_rx_queue_release(void *); 309 int priv_rx_intr_vec_enable(struct priv *priv); 310 void priv_rx_intr_vec_disable(struct priv *priv); 311 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 312 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 313 314 /* mlx5_txq.c */ 315 316 void txq_cleanup(struct txq_ctrl *); 317 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t, 318 unsigned int, const struct rte_eth_txconf *); 319 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int, 320 const struct rte_eth_txconf *); 321 void mlx5_tx_queue_release(void *); 322 323 /* mlx5_rxtx.c */ 324 325 extern uint32_t mlx5_ptype_table[]; 326 327 void mlx5_set_ptype_table(void); 328 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t); 329 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t); 330 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t); 331 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t); 332 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t); 333 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t); 334 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t); 335 int mlx5_rx_descriptor_status(void *, uint16_t); 336 int mlx5_tx_descriptor_status(void *, uint16_t); 337 338 /* Vectorized version of mlx5_rxtx.c */ 339 int priv_check_raw_vec_tx_support(struct priv *); 340 int priv_check_vec_tx_support(struct priv *); 341 int rxq_check_vec_support(struct rxq *); 342 int priv_check_vec_rx_support(struct priv *); 343 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t); 344 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t); 345 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t); 346 347 /* mlx5_mr.c */ 348 349 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *); 350 void txq_mp2mr_iter(struct rte_mempool *, void *); 351 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int); 352 353 #ifndef NDEBUG 354 /** 355 * Verify or set magic value in CQE. 356 * 357 * @param cqe 358 * Pointer to CQE. 359 * 360 * @return 361 * 0 the first time. 362 */ 363 static inline int 364 check_cqe_seen(volatile struct mlx5_cqe *cqe) 365 { 366 static const uint8_t magic[] = "seen"; 367 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0; 368 int ret = 1; 369 unsigned int i; 370 371 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i) 372 if (!ret || (*buf)[i] != magic[i]) { 373 ret = 0; 374 (*buf)[i] = magic[i]; 375 } 376 return ret; 377 } 378 #endif /* NDEBUG */ 379 380 /** 381 * Check whether CQE is valid. 382 * 383 * @param cqe 384 * Pointer to CQE. 385 * @param cqes_n 386 * Size of completion queue. 387 * @param ci 388 * Consumer index. 389 * 390 * @return 391 * 0 on success, 1 on failure. 392 */ 393 static __rte_always_inline int 394 check_cqe(volatile struct mlx5_cqe *cqe, 395 unsigned int cqes_n, const uint16_t ci) 396 { 397 uint16_t idx = ci & cqes_n; 398 uint8_t op_own = cqe->op_own; 399 uint8_t op_owner = MLX5_CQE_OWNER(op_own); 400 uint8_t op_code = MLX5_CQE_OPCODE(op_own); 401 402 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 403 return 1; /* No CQE. */ 404 #ifndef NDEBUG 405 if ((op_code == MLX5_CQE_RESP_ERR) || 406 (op_code == MLX5_CQE_REQ_ERR)) { 407 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe; 408 uint8_t syndrome = err_cqe->syndrome; 409 410 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) || 411 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR)) 412 return 0; 413 if (!check_cqe_seen(cqe)) { 414 ERROR("unexpected CQE error %u (0x%02x)" 415 " syndrome 0x%02x", 416 op_code, op_code, syndrome); 417 rte_hexdump(stderr, "MLX5 Error CQE:", 418 (const void *)((uintptr_t)err_cqe), 419 sizeof(*err_cqe)); 420 } 421 return 1; 422 } else if ((op_code != MLX5_CQE_RESP_SEND) && 423 (op_code != MLX5_CQE_REQ)) { 424 if (!check_cqe_seen(cqe)) { 425 ERROR("unexpected CQE opcode %u (0x%02x)", 426 op_code, op_code); 427 rte_hexdump(stderr, "MLX5 CQE:", 428 (const void *)((uintptr_t)cqe), 429 sizeof(*cqe)); 430 } 431 return 1; 432 } 433 #endif /* NDEBUG */ 434 return 0; 435 } 436 437 /** 438 * Return the address of the WQE. 439 * 440 * @param txq 441 * Pointer to TX queue structure. 442 * @param wqe_ci 443 * WQE consumer index. 444 * 445 * @return 446 * WQE address. 447 */ 448 static inline uintptr_t * 449 tx_mlx5_wqe(struct txq *txq, uint16_t ci) 450 { 451 ci &= ((1 << txq->wqe_n) - 1); 452 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE); 453 } 454 455 /** 456 * Manage TX completions. 457 * 458 * When sending a burst, mlx5_tx_burst() posts several WRs. 459 * 460 * @param txq 461 * Pointer to TX queue structure. 462 */ 463 static __rte_always_inline void 464 mlx5_tx_complete(struct txq *txq) 465 { 466 const uint16_t elts_n = 1 << txq->elts_n; 467 const uint16_t elts_m = elts_n - 1; 468 const unsigned int cqe_n = 1 << txq->cqe_n; 469 const unsigned int cqe_cnt = cqe_n - 1; 470 uint16_t elts_free = txq->elts_tail; 471 uint16_t elts_tail; 472 uint16_t cq_ci = txq->cq_ci; 473 volatile struct mlx5_cqe *cqe = NULL; 474 volatile struct mlx5_wqe_ctrl *ctrl; 475 struct rte_mbuf *m, *free[elts_n]; 476 struct rte_mempool *pool = NULL; 477 unsigned int blk_n = 0; 478 479 cqe = &(*txq->cqes)[cq_ci & cqe_cnt]; 480 if (unlikely(check_cqe(cqe, cqe_n, cq_ci))) 481 return; 482 #ifndef NDEBUG 483 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) || 484 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) { 485 if (!check_cqe_seen(cqe)) { 486 ERROR("unexpected error CQE, TX stopped"); 487 rte_hexdump(stderr, "MLX5 TXQ:", 488 (const void *)((uintptr_t)txq->wqes), 489 ((1 << txq->wqe_n) * 490 MLX5_WQE_SIZE)); 491 } 492 return; 493 } 494 #endif /* NDEBUG */ 495 ++cq_ci; 496 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter); 497 ctrl = (volatile struct mlx5_wqe_ctrl *) 498 tx_mlx5_wqe(txq, txq->wqe_pi); 499 elts_tail = ctrl->ctrl3; 500 assert((elts_tail & elts_m) < (1 << txq->wqe_n)); 501 /* Free buffers. */ 502 while (elts_free != elts_tail) { 503 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]); 504 if (likely(m != NULL)) { 505 if (likely(m->pool == pool)) { 506 free[blk_n++] = m; 507 } else { 508 if (likely(pool != NULL)) 509 rte_mempool_put_bulk(pool, 510 (void *)free, 511 blk_n); 512 free[0] = m; 513 pool = m->pool; 514 blk_n = 1; 515 } 516 } 517 } 518 if (blk_n) 519 rte_mempool_put_bulk(pool, (void *)free, blk_n); 520 #ifndef NDEBUG 521 elts_free = txq->elts_tail; 522 /* Poisoning. */ 523 while (elts_free != elts_tail) { 524 memset(&(*txq->elts)[elts_free & elts_m], 525 0x66, 526 sizeof((*txq->elts)[elts_free & elts_m])); 527 ++elts_free; 528 } 529 #endif 530 txq->cq_ci = cq_ci; 531 txq->elts_tail = elts_tail; 532 /* Update the consumer index. */ 533 rte_wmb(); 534 *txq->cq_db = rte_cpu_to_be_32(cq_ci); 535 } 536 537 /** 538 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which 539 * the cloned mbuf is allocated is returned instead. 540 * 541 * @param buf 542 * Pointer to mbuf. 543 * 544 * @return 545 * Memory pool where data is located for given mbuf. 546 */ 547 static struct rte_mempool * 548 mlx5_tx_mb2mp(struct rte_mbuf *buf) 549 { 550 if (unlikely(RTE_MBUF_INDIRECT(buf))) 551 return rte_mbuf_from_indirect(buf)->pool; 552 return buf->pool; 553 } 554 555 /** 556 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[]. 557 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full, 558 * remove an entry first. 559 * 560 * @param txq 561 * Pointer to TX queue structure. 562 * @param[in] mp 563 * Memory Pool for which a Memory Region lkey must be returned. 564 * 565 * @return 566 * mr->lkey on success, (uint32_t)-1 on failure. 567 */ 568 static __rte_always_inline uint32_t 569 mlx5_tx_mb2mr(struct txq *txq, struct rte_mbuf *mb) 570 { 571 uint16_t i = txq->mr_cache_idx; 572 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t); 573 574 assert(i < RTE_DIM(txq->mp2mr)); 575 if (likely(txq->mp2mr[i].start <= addr && txq->mp2mr[i].end >= addr)) 576 return txq->mp2mr[i].lkey; 577 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) { 578 if (unlikely(txq->mp2mr[i].mr == NULL)) { 579 /* Unknown MP, add a new MR for it. */ 580 break; 581 } 582 if (txq->mp2mr[i].start <= addr && 583 txq->mp2mr[i].end >= addr) { 584 assert(txq->mp2mr[i].lkey != (uint32_t)-1); 585 assert(rte_cpu_to_be_32(txq->mp2mr[i].mr->lkey) == 586 txq->mp2mr[i].lkey); 587 txq->mr_cache_idx = i; 588 return txq->mp2mr[i].lkey; 589 } 590 } 591 txq->mr_cache_idx = 0; 592 return txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i); 593 } 594 595 /** 596 * Ring TX queue doorbell. 597 * 598 * @param txq 599 * Pointer to TX queue structure. 600 * @param wqe 601 * Pointer to the last WQE posted in the NIC. 602 */ 603 static __rte_always_inline void 604 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe) 605 { 606 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg); 607 volatile uint64_t *src = ((volatile uint64_t *)wqe); 608 609 rte_io_wmb(); 610 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); 611 /* Ensure ordering between DB record and BF copy. */ 612 rte_wmb(); 613 *dst = *src; 614 } 615 616 #endif /* RTE_PMD_MLX5_RXTX_H_ */ 617