1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_H_ 7 #define RTE_PMD_MLX5_RXTX_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 #include <rte_mbuf.h> 14 #include <rte_mempool.h> 15 #include <rte_common.h> 16 #include <rte_hexdump.h> 17 #include <rte_atomic.h> 18 #include <rte_spinlock.h> 19 #include <rte_io.h> 20 #include <rte_bus_pci.h> 21 #include <rte_malloc.h> 22 #include <rte_cycles.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_prm.h> 26 #include <mlx5_common.h> 27 #include <mlx5_common_mr.h> 28 29 #include "mlx5_defs.h" 30 #include "mlx5_utils.h" 31 #include "mlx5.h" 32 #include "mlx5_autoconf.h" 33 34 /* Support tunnel matching. */ 35 #define MLX5_FLOW_TUNNEL 10 36 37 /* Mbuf dynamic flag offset for inline. */ 38 extern uint64_t rte_net_mlx5_dynf_inline_mask; 39 40 struct mlx5_rxq_stats { 41 #ifdef MLX5_PMD_SOFT_COUNTERS 42 uint64_t ipackets; /**< Total of successfully received packets. */ 43 uint64_t ibytes; /**< Total of successfully received bytes. */ 44 #endif 45 uint64_t idropped; /**< Total of packets dropped when RX ring full. */ 46 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ 47 }; 48 49 struct mlx5_txq_stats { 50 #ifdef MLX5_PMD_SOFT_COUNTERS 51 uint64_t opackets; /**< Total of successfully sent packets. */ 52 uint64_t obytes; /**< Total of successfully sent bytes. */ 53 #endif 54 uint64_t oerrors; /**< Total number of failed transmitted packets. */ 55 }; 56 57 struct mlx5_priv; 58 59 /* Compressed CQE context. */ 60 struct rxq_zip { 61 uint16_t ai; /* Array index. */ 62 uint16_t ca; /* Current array index. */ 63 uint16_t na; /* Next array index. */ 64 uint16_t cq_ci; /* The next CQE. */ 65 uint32_t cqe_cnt; /* Number of CQEs. */ 66 }; 67 68 /* Multi-Packet RQ buffer header. */ 69 struct mlx5_mprq_buf { 70 struct rte_mempool *mp; 71 uint16_t refcnt; /* Atomically accessed refcnt. */ 72 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */ 73 struct rte_mbuf_ext_shared_info shinfos[]; 74 /* 75 * Shared information per stride. 76 * More memory will be allocated for the first stride head-room and for 77 * the strides data. 78 */ 79 } __rte_cache_aligned; 80 81 /* Get pointer to the first stride. */ 82 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \ 83 sizeof(struct mlx5_mprq_buf) + \ 84 (strd_n) * \ 85 sizeof(struct rte_mbuf_ext_shared_info) + \ 86 RTE_PKTMBUF_HEADROOM)) 87 88 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 89 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 90 91 enum mlx5_rxq_err_state { 92 MLX5_RXQ_ERR_STATE_NO_ERROR = 0, 93 MLX5_RXQ_ERR_STATE_NEED_RESET, 94 MLX5_RXQ_ERR_STATE_NEED_READY, 95 }; 96 97 /* RX queue descriptor. */ 98 struct mlx5_rxq_data { 99 unsigned int csum:1; /* Enable checksum offloading. */ 100 unsigned int hw_timestamp:1; /* Enable HW timestamp. */ 101 unsigned int rt_timestamp:1; /* Realtime timestamp format. */ 102 unsigned int vlan_strip:1; /* Enable VLAN stripping. */ 103 unsigned int crc_present:1; /* CRC must be subtracted. */ 104 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */ 105 unsigned int cqe_n:4; /* Log 2 of CQ elements. */ 106 unsigned int elts_n:4; /* Log 2 of Mbufs. */ 107 unsigned int rss_hash:1; /* RSS hash result is enabled. */ 108 unsigned int mark:1; /* Marked flow available on the queue. */ 109 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */ 110 unsigned int strd_sz_n:4; /* Log 2 of stride size. */ 111 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */ 112 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */ 113 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */ 114 unsigned int lro:1; /* Enable LRO. */ 115 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */ 116 volatile uint32_t *rq_db; 117 volatile uint32_t *cq_db; 118 uint16_t port_id; 119 uint32_t rq_ci; 120 uint16_t consumed_strd; /* Number of consumed strides in WQE. */ 121 uint32_t rq_pi; 122 uint32_t cq_ci; 123 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */ 124 union { 125 struct rxq_zip zip; /* Compressed context. */ 126 uint16_t decompressed; 127 /* Number of ready mbufs decompressed from the CQ. */ 128 }; 129 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 130 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */ 131 volatile void *wqes; 132 volatile struct mlx5_cqe(*cqes)[]; 133 RTE_STD_C11 134 union { 135 struct rte_mbuf *(*elts)[]; 136 struct mlx5_mprq_buf *(*mprq_bufs)[]; 137 }; 138 struct rte_mempool *mp; 139 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 140 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */ 141 struct mlx5_dev_ctx_shared *sh; /* Shared context. */ 142 uint16_t idx; /* Queue index. */ 143 struct mlx5_rxq_stats stats; 144 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ 145 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ 146 void *cq_uar; /* Verbs CQ user access region. */ 147 uint32_t cqn; /* CQ number. */ 148 uint8_t cq_arm_sn; /* CQ arm seq number. */ 149 #ifndef RTE_ARCH_64 150 rte_spinlock_t *uar_lock_cq; 151 /* CQ (UAR) access lock required for 32bit implementations */ 152 #endif 153 uint32_t tunnel; /* Tunnel information. */ 154 int timestamp_offset; /* Dynamic mbuf field for timestamp. */ 155 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */ 156 uint64_t flow_meta_mask; 157 int32_t flow_meta_offset; 158 } __rte_cache_aligned; 159 160 enum mlx5_rxq_type { 161 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */ 162 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ 163 MLX5_RXQ_TYPE_UNDEFINED, 164 }; 165 166 /* RX queue control descriptor. */ 167 struct mlx5_rxq_ctrl { 168 struct mlx5_rxq_data rxq; /* Data path structure. */ 169 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ 170 rte_atomic32_t refcnt; /* Reference counter. */ 171 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */ 172 struct mlx5_priv *priv; /* Back pointer to private data. */ 173 enum mlx5_rxq_type type; /* Rxq type. */ 174 unsigned int socket; /* CPU socket ID for allocations. */ 175 unsigned int irq:1; /* Whether IRQ is enabled. */ 176 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ 177 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ 178 uint32_t wqn; /* WQ number. */ 179 uint16_t dump_file_n; /* Number of dump files. */ 180 struct mlx5_devx_dbr_page *rq_dbrec_page; 181 uint64_t rq_dbr_offset; 182 /* Storing RQ door-bell information, needed when freeing door-bell. */ 183 struct mlx5_devx_dbr_page *cq_dbrec_page; 184 uint64_t cq_dbr_offset; 185 /* Storing CQ door-bell information, needed when freeing door-bell. */ 186 void *wq_umem; /* WQ buffer registration info. */ 187 void *cq_umem; /* CQ buffer registration info. */ 188 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ 189 }; 190 191 /* TX queue send local data. */ 192 __extension__ 193 struct mlx5_txq_local { 194 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */ 195 struct rte_mbuf *mbuf; /* first mbuf to process. */ 196 uint16_t pkts_copy; /* packets copied to elts. */ 197 uint16_t pkts_sent; /* packets sent. */ 198 uint16_t pkts_loop; /* packets sent on loop entry. */ 199 uint16_t elts_free; /* available elts remain. */ 200 uint16_t wqe_free; /* available wqe remain. */ 201 uint16_t mbuf_off; /* data offset in current mbuf. */ 202 uint16_t mbuf_nseg; /* number of remaining mbuf. */ 203 }; 204 205 /* TX queue descriptor. */ 206 __extension__ 207 struct mlx5_txq_data { 208 uint16_t elts_head; /* Current counter in (*elts)[]. */ 209 uint16_t elts_tail; /* Counter of first element awaiting completion. */ 210 uint16_t elts_comp; /* elts index since last completion request. */ 211 uint16_t elts_s; /* Number of mbuf elements. */ 212 uint16_t elts_m; /* Mask for mbuf elements indices. */ 213 /* Fields related to elts mbuf storage. */ 214 uint16_t wqe_ci; /* Consumer index for work queue. */ 215 uint16_t wqe_pi; /* Producer index for work queue. */ 216 uint16_t wqe_s; /* Number of WQ elements. */ 217 uint16_t wqe_m; /* Mask Number for WQ elements. */ 218 uint16_t wqe_comp; /* WQE index since last completion request. */ 219 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */ 220 /* WQ related fields. */ 221 uint16_t cq_ci; /* Consumer index for completion queue. */ 222 uint16_t cq_pi; /* Production index for completion queue. */ 223 uint16_t cqe_s; /* Number of CQ elements. */ 224 uint16_t cqe_m; /* Mask for CQ indices. */ 225 /* CQ related fields. */ 226 uint16_t elts_n:4; /* elts[] length (in log2). */ 227 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */ 228 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */ 229 uint16_t tso_en:1; /* When set hardware TSO is enabled. */ 230 uint16_t tunnel_en:1; 231 /* When set TX offload for tunneled packets are supported. */ 232 uint16_t swp_en:1; /* Whether SW parser is enabled. */ 233 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */ 234 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */ 235 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */ 236 uint16_t inlen_send; /* Ordinary send data inline size. */ 237 uint16_t inlen_empw; /* eMPW max packet size to inline. */ 238 uint16_t inlen_mode; /* Minimal data length to inline. */ 239 uint32_t qp_num_8s; /* QP number shifted by 8. */ 240 uint64_t offloads; /* Offloads for Tx Queue. */ 241 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 242 struct mlx5_wqe *wqes; /* Work queue. */ 243 struct mlx5_wqe *wqes_end; /* Work queue array limit. */ 244 #ifdef RTE_LIBRTE_MLX5_DEBUG 245 uint32_t *fcqs; /* Free completion queue (debug extended). */ 246 #else 247 uint16_t *fcqs; /* Free completion queue. */ 248 #endif 249 volatile struct mlx5_cqe *cqes; /* Completion queue. */ 250 volatile uint32_t *qp_db; /* Work queue doorbell. */ 251 volatile uint32_t *cq_db; /* Completion queue doorbell. */ 252 uint16_t port_id; /* Port ID of device. */ 253 uint16_t idx; /* Queue index. */ 254 uint64_t ts_mask; /* Timestamp flag dynamic mask. */ 255 int32_t ts_offset; /* Timestamp field dynamic offset. */ 256 struct mlx5_dev_ctx_shared *sh; /* Shared context. */ 257 struct mlx5_txq_stats stats; /* TX queue counters. */ 258 #ifndef RTE_ARCH_64 259 rte_spinlock_t *uar_lock; 260 /* UAR access lock required for 32bit implementations */ 261 #endif 262 struct rte_mbuf *elts[0]; 263 /* Storage for queued packets, must be the last field. */ 264 } __rte_cache_aligned; 265 266 enum mlx5_txq_type { 267 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */ 268 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ 269 }; 270 271 /* TX queue control descriptor. */ 272 struct mlx5_txq_ctrl { 273 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */ 274 rte_atomic32_t refcnt; /* Reference counter. */ 275 unsigned int socket; /* CPU socket ID for allocations. */ 276 enum mlx5_txq_type type; /* The txq ctrl type. */ 277 unsigned int max_inline_data; /* Max inline data. */ 278 unsigned int max_tso_header; /* Max TSO header size. */ 279 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */ 280 struct mlx5_priv *priv; /* Back pointer to private data. */ 281 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */ 282 void *bf_reg; /* BlueFlame register from Verbs. */ 283 uint16_t dump_file_n; /* Number of dump files. */ 284 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ 285 struct mlx5_txq_data txq; /* Data path structure. */ 286 /* Must be the last field in the structure, contains elts[]. */ 287 }; 288 289 #define MLX5_TX_BFREG(txq) \ 290 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx]) 291 292 /* mlx5_rxq.c */ 293 294 extern uint8_t rss_hash_default_key[]; 295 296 int mlx5_check_mprq_support(struct rte_eth_dev *dev); 297 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); 298 int mlx5_mprq_enabled(struct rte_eth_dev *dev); 299 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data); 300 int mlx5_mprq_free_mp(struct rte_eth_dev *dev); 301 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); 302 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); 303 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); 304 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); 305 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); 306 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 307 unsigned int socket, const struct rte_eth_rxconf *conf, 308 struct rte_mempool *mp); 309 int mlx5_rx_hairpin_queue_setup 310 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 311 const struct rte_eth_hairpin_conf *hairpin_conf); 312 void mlx5_rx_queue_release(void *dpdk_rxq); 313 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); 314 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); 315 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 316 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 317 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); 318 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, 319 uint16_t desc, unsigned int socket, 320 const struct rte_eth_rxconf *conf, 321 struct rte_mempool *mp); 322 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new 323 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 324 const struct rte_eth_hairpin_conf *hairpin_conf); 325 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx); 326 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); 327 int mlx5_rxq_verify(struct rte_eth_dev *dev); 328 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); 329 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev); 330 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev, 331 const uint16_t *queues, 332 uint32_t queues_n); 333 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev, 334 struct mlx5_ind_table_obj *ind_tbl); 335 uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev, 336 const uint8_t *rss_key, uint32_t rss_key_len, 337 uint64_t hash_fields, 338 const uint16_t *queues, uint32_t queues_n, 339 int tunnel __rte_unused); 340 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, 341 const uint8_t *rss_key, uint32_t rss_key_len, 342 uint64_t hash_fields, 343 const uint16_t *queues, uint32_t queues_n); 344 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); 345 int mlx5_hrxq_verify(struct rte_eth_dev *dev); 346 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx); 347 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev); 348 void mlx5_drop_action_destroy(struct rte_eth_dev *dev); 349 uint64_t mlx5_get_rx_port_offloads(void); 350 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); 351 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); 352 353 354 /* mlx5_txq.c */ 355 356 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); 357 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); 358 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); 359 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); 360 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 361 unsigned int socket, const struct rte_eth_txconf *conf); 362 int mlx5_tx_hairpin_queue_setup 363 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 364 const struct rte_eth_hairpin_conf *hairpin_conf); 365 void mlx5_tx_queue_release(void *dpdk_txq); 366 void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl); 367 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd); 368 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev); 369 int mlx5_txq_obj_verify(struct rte_eth_dev *dev); 370 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, 371 uint16_t desc, unsigned int socket, 372 const struct rte_eth_txconf *conf); 373 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new 374 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 375 const struct rte_eth_hairpin_conf *hairpin_conf); 376 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx); 377 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx); 378 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx); 379 int mlx5_txq_verify(struct rte_eth_dev *dev); 380 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl); 381 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl); 382 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev); 383 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev); 384 385 /* mlx5_rxtx.c */ 386 387 extern uint32_t mlx5_ptype_table[]; 388 extern uint8_t mlx5_cksum_table[]; 389 extern uint8_t mlx5_swp_types_table[]; 390 391 void mlx5_set_ptype_table(void); 392 void mlx5_set_cksum_table(void); 393 void mlx5_set_swp_types_table(void); 394 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); 395 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq); 396 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec); 397 void mlx5_mprq_buf_free_cb(void *addr, void *opaque); 398 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf); 399 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, 400 uint16_t pkts_n); 401 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, 402 uint16_t pkts_n); 403 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, 404 uint16_t pkts_n); 405 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset); 406 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset); 407 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); 408 void mlx5_dump_debug_information(const char *path, const char *title, 409 const void *buf, unsigned int len); 410 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev, 411 const struct mlx5_mp_arg_queue_state_modify *sm); 412 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 413 struct rte_eth_rxq_info *qinfo); 414 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 415 struct rte_eth_txq_info *qinfo); 416 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 417 struct rte_eth_burst_mode *mode); 418 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 419 struct rte_eth_burst_mode *mode); 420 421 /* Vectorized version of mlx5_rxtx.c */ 422 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); 423 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev); 424 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, 425 uint16_t pkts_n); 426 427 /* mlx5_mr.c */ 428 429 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl); 430 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr); 431 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb); 432 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, 433 struct rte_mempool *mp); 434 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova, 435 size_t len); 436 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova, 437 size_t len); 438 439 /** 440 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 441 * 64bit architectures. 442 * 443 * @param val 444 * value to write in CPU endian format. 445 * @param addr 446 * Address to write to. 447 * @param lock 448 * Address of the lock to use for that UAR access. 449 */ 450 static __rte_always_inline void 451 __mlx5_uar_write64_relaxed(uint64_t val, void *addr, 452 rte_spinlock_t *lock __rte_unused) 453 { 454 #ifdef RTE_ARCH_64 455 *(uint64_t *)addr = val; 456 #else /* !RTE_ARCH_64 */ 457 rte_spinlock_lock(lock); 458 *(uint32_t *)addr = val; 459 rte_io_wmb(); 460 *((uint32_t *)addr + 1) = val >> 32; 461 rte_spinlock_unlock(lock); 462 #endif 463 } 464 465 /** 466 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 467 * 64bit architectures while guaranteeing the order of execution with the 468 * code being executed. 469 * 470 * @param val 471 * value to write in CPU endian format. 472 * @param addr 473 * Address to write to. 474 * @param lock 475 * Address of the lock to use for that UAR access. 476 */ 477 static __rte_always_inline void 478 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) 479 { 480 rte_io_wmb(); 481 __mlx5_uar_write64_relaxed(val, addr, lock); 482 } 483 484 /* Assist macros, used instead of directly calling the functions they wrap. */ 485 #ifdef RTE_ARCH_64 486 #define mlx5_uar_write64_relaxed(val, dst, lock) \ 487 __mlx5_uar_write64_relaxed(val, dst, NULL) 488 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL) 489 #else 490 #define mlx5_uar_write64_relaxed(val, dst, lock) \ 491 __mlx5_uar_write64_relaxed(val, dst, lock) 492 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock) 493 #endif 494 495 /** 496 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the 497 * cloned mbuf is allocated is returned instead. 498 * 499 * @param buf 500 * Pointer to mbuf. 501 * 502 * @return 503 * Memory pool where data is located for given mbuf. 504 */ 505 static inline struct rte_mempool * 506 mlx5_mb2mp(struct rte_mbuf *buf) 507 { 508 if (unlikely(RTE_MBUF_CLONED(buf))) 509 return rte_mbuf_from_indirect(buf)->pool; 510 return buf->pool; 511 } 512 513 /** 514 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx 515 * as mempool is pre-configured and static. 516 * 517 * @param rxq 518 * Pointer to Rx queue structure. 519 * @param addr 520 * Address to search. 521 * 522 * @return 523 * Searched LKey on success, UINT32_MAX on no match. 524 */ 525 static __rte_always_inline uint32_t 526 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr) 527 { 528 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; 529 uint32_t lkey; 530 531 /* Linear search on MR cache array. */ 532 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 533 MLX5_MR_CACHE_N, addr); 534 if (likely(lkey != UINT32_MAX)) 535 return lkey; 536 /* Take slower bottom-half (Binary Search) on miss. */ 537 return mlx5_rx_addr2mr_bh(rxq, addr); 538 } 539 540 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr)) 541 542 /** 543 * Query LKey from a packet buffer for Tx. If not found, add the mempool. 544 * 545 * @param txq 546 * Pointer to Tx queue structure. 547 * @param addr 548 * Address to search. 549 * 550 * @return 551 * Searched LKey on success, UINT32_MAX on no match. 552 */ 553 static __rte_always_inline uint32_t 554 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb) 555 { 556 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl; 557 uintptr_t addr = (uintptr_t)mb->buf_addr; 558 uint32_t lkey; 559 560 /* Check generation bit to see if there's any change on existing MRs. */ 561 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 562 mlx5_mr_flush_local_cache(mr_ctrl); 563 /* Linear search on MR cache array. */ 564 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 565 MLX5_MR_CACHE_N, addr); 566 if (likely(lkey != UINT32_MAX)) 567 return lkey; 568 /* Take slower bottom-half on miss. */ 569 return mlx5_tx_mb2mr_bh(txq, mb); 570 } 571 572 /** 573 * Ring TX queue doorbell and flush the update if requested. 574 * 575 * @param txq 576 * Pointer to TX queue structure. 577 * @param wqe 578 * Pointer to the last WQE posted in the NIC. 579 * @param cond 580 * Request for write memory barrier after BlueFlame update. 581 */ 582 static __rte_always_inline void 583 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, 584 int cond) 585 { 586 uint64_t *dst = MLX5_TX_BFREG(txq); 587 volatile uint64_t *src = ((volatile uint64_t *)wqe); 588 589 rte_io_wmb(); 590 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); 591 /* Ensure ordering between DB record and BF copy. */ 592 rte_wmb(); 593 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock); 594 if (cond) 595 rte_wmb(); 596 } 597 598 /** 599 * Ring TX queue doorbell and flush the update by write memory barrier. 600 * 601 * @param txq 602 * Pointer to TX queue structure. 603 * @param wqe 604 * Pointer to the last WQE posted in the NIC. 605 */ 606 static __rte_always_inline void 607 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe) 608 { 609 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1); 610 } 611 612 /** 613 * Convert timestamp from HW format to linear counter 614 * from Packet Pacing Clock Queue CQE timestamp format. 615 * 616 * @param sh 617 * Pointer to the device shared context. Might be needed 618 * to convert according current device configuration. 619 * @param ts 620 * Timestamp from CQE to convert. 621 * @return 622 * UTC in nanoseconds 623 */ 624 static __rte_always_inline uint64_t 625 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts) 626 { 627 RTE_SET_USED(sh); 628 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S; 629 } 630 631 /** 632 * Convert timestamp from mbuf format to linear counter 633 * of Clock Queue completions (24 bits) 634 * 635 * @param sh 636 * Pointer to the device shared context to fetch Tx 637 * packet pacing timestamp and parameters. 638 * @param ts 639 * Timestamp from mbuf to convert. 640 * @return 641 * positive or zero value - completion ID to wait 642 * negative value - conversion error 643 */ 644 static __rte_always_inline int32_t 645 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts) 646 { 647 uint64_t ts, ci; 648 uint32_t tick; 649 650 do { 651 /* 652 * Read atomically two uint64_t fields and compare lsb bits. 653 * It there is no match - the timestamp was updated in 654 * the service thread, data should be re-read. 655 */ 656 rte_compiler_barrier(); 657 ci = rte_atomic64_read(&sh->txpp.ts.ci_ts); 658 ts = rte_atomic64_read(&sh->txpp.ts.ts); 659 rte_compiler_barrier(); 660 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH))) 661 break; 662 } while (true); 663 /* Perform the skew correction, positive value to send earlier. */ 664 mts -= sh->txpp.skew; 665 mts -= ts; 666 if (unlikely(mts >= UINT64_MAX / 2)) { 667 /* We have negative integer, mts is in the past. */ 668 rte_atomic32_inc(&sh->txpp.err_ts_past); 669 return -1; 670 } 671 tick = sh->txpp.tick; 672 MLX5_ASSERT(tick); 673 /* Convert delta to completions, round up. */ 674 mts = (mts + tick - 1) / tick; 675 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) { 676 /* We have mts is too distant future. */ 677 rte_atomic32_inc(&sh->txpp.err_ts_future); 678 return -1; 679 } 680 mts <<= 64 - MLX5_CQ_INDEX_WIDTH; 681 ci += mts; 682 ci >>= 64 - MLX5_CQ_INDEX_WIDTH; 683 return ci; 684 } 685 686 /** 687 * Set timestamp in mbuf dynamic field. 688 * 689 * @param mbuf 690 * Structure to write into. 691 * @param offset 692 * Dynamic field offset in mbuf structure. 693 * @param timestamp 694 * Value to write. 695 */ 696 static __rte_always_inline void 697 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset, 698 rte_mbuf_timestamp_t timestamp) 699 { 700 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp; 701 } 702 703 #endif /* RTE_PMD_MLX5_RXTX_H_ */ 704