1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <assert.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdlib.h> 10 11 /* Verbs header. */ 12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 13 #ifdef PEDANTIC 14 #pragma GCC diagnostic ignored "-Wpedantic" 15 #endif 16 #include <infiniband/verbs.h> 17 #include <infiniband/mlx5dv.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <rte_mbuf.h> 23 #include <rte_mempool.h> 24 #include <rte_prefetch.h> 25 #include <rte_common.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_ether.h> 28 29 #include "mlx5.h" 30 #include "mlx5_utils.h" 31 #include "mlx5_rxtx.h" 32 #include "mlx5_autoconf.h" 33 #include "mlx5_defs.h" 34 #include "mlx5_prm.h" 35 36 static __rte_always_inline uint32_t 37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe); 38 39 static __rte_always_inline int 40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe, 41 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe); 42 43 static __rte_always_inline uint32_t 44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe); 45 46 static __rte_always_inline void 47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, 48 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res); 49 50 static __rte_always_inline void 51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx); 52 53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = { 54 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */ 55 }; 56 57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned; 58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned; 59 60 /** 61 * Build a table to translate Rx completion flags to packet type. 62 * 63 * @note: fix mlx5_dev_supported_ptypes_get() if any change here. 64 */ 65 void 66 mlx5_set_ptype_table(void) 67 { 68 unsigned int i; 69 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table; 70 71 /* Last entry must not be overwritten, reserved for errored packet. */ 72 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i) 73 (*p)[i] = RTE_PTYPE_UNKNOWN; 74 /* 75 * The index to the array should have: 76 * bit[1:0] = l3_hdr_type 77 * bit[4:2] = l4_hdr_type 78 * bit[5] = ip_frag 79 * bit[6] = tunneled 80 * bit[7] = outer_l3_type 81 */ 82 /* L2 */ 83 (*p)[0x00] = RTE_PTYPE_L2_ETHER; 84 /* L3 */ 85 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 86 RTE_PTYPE_L4_NONFRAG; 87 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 88 RTE_PTYPE_L4_NONFRAG; 89 /* Fragmented */ 90 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 91 RTE_PTYPE_L4_FRAG; 92 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 93 RTE_PTYPE_L4_FRAG; 94 /* TCP */ 95 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 96 RTE_PTYPE_L4_TCP; 97 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 98 RTE_PTYPE_L4_TCP; 99 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 100 RTE_PTYPE_L4_TCP; 101 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 102 RTE_PTYPE_L4_TCP; 103 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 104 RTE_PTYPE_L4_TCP; 105 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 106 RTE_PTYPE_L4_TCP; 107 /* UDP */ 108 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 109 RTE_PTYPE_L4_UDP; 110 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 111 RTE_PTYPE_L4_UDP; 112 /* Repeat with outer_l3_type being set. Just in case. */ 113 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 114 RTE_PTYPE_L4_NONFRAG; 115 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 116 RTE_PTYPE_L4_NONFRAG; 117 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 118 RTE_PTYPE_L4_FRAG; 119 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 120 RTE_PTYPE_L4_FRAG; 121 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 122 RTE_PTYPE_L4_TCP; 123 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 124 RTE_PTYPE_L4_TCP; 125 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 126 RTE_PTYPE_L4_TCP; 127 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 128 RTE_PTYPE_L4_TCP; 129 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 130 RTE_PTYPE_L4_TCP; 131 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 132 RTE_PTYPE_L4_TCP; 133 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 134 RTE_PTYPE_L4_UDP; 135 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 136 RTE_PTYPE_L4_UDP; 137 /* Tunneled - L3 */ 138 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 141 RTE_PTYPE_INNER_L4_NONFRAG; 142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 144 RTE_PTYPE_INNER_L4_NONFRAG; 145 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 148 RTE_PTYPE_INNER_L4_NONFRAG; 149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 151 RTE_PTYPE_INNER_L4_NONFRAG; 152 /* Tunneled - Fragmented */ 153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 155 RTE_PTYPE_INNER_L4_FRAG; 156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 158 RTE_PTYPE_INNER_L4_FRAG; 159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 161 RTE_PTYPE_INNER_L4_FRAG; 162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 164 RTE_PTYPE_INNER_L4_FRAG; 165 /* Tunneled - TCP */ 166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 168 RTE_PTYPE_INNER_L4_TCP; 169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 171 RTE_PTYPE_INNER_L4_TCP; 172 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 174 RTE_PTYPE_INNER_L4_TCP; 175 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 177 RTE_PTYPE_INNER_L4_TCP; 178 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 180 RTE_PTYPE_INNER_L4_TCP; 181 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 183 RTE_PTYPE_INNER_L4_TCP; 184 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 186 RTE_PTYPE_INNER_L4_TCP; 187 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 189 RTE_PTYPE_INNER_L4_TCP; 190 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 192 RTE_PTYPE_INNER_L4_TCP; 193 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 194 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 195 RTE_PTYPE_INNER_L4_TCP; 196 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 198 RTE_PTYPE_INNER_L4_TCP; 199 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 201 RTE_PTYPE_INNER_L4_TCP; 202 /* Tunneled - UDP */ 203 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 205 RTE_PTYPE_INNER_L4_UDP; 206 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 208 RTE_PTYPE_INNER_L4_UDP; 209 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 211 RTE_PTYPE_INNER_L4_UDP; 212 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 214 RTE_PTYPE_INNER_L4_UDP; 215 } 216 217 /** 218 * Build a table to translate packet to checksum type of Verbs. 219 */ 220 void 221 mlx5_set_cksum_table(void) 222 { 223 unsigned int i; 224 uint8_t v; 225 226 /* 227 * The index should have: 228 * bit[0] = PKT_TX_TCP_SEG 229 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM 230 * bit[4] = PKT_TX_IP_CKSUM 231 * bit[8] = PKT_TX_OUTER_IP_CKSUM 232 * bit[9] = tunnel 233 */ 234 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) { 235 v = 0; 236 if (i & (1 << 9)) { 237 /* Tunneled packet. */ 238 if (i & (1 << 8)) /* Outer IP. */ 239 v |= MLX5_ETH_WQE_L3_CSUM; 240 if (i & (1 << 4)) /* Inner IP. */ 241 v |= MLX5_ETH_WQE_L3_INNER_CSUM; 242 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */ 243 v |= MLX5_ETH_WQE_L4_INNER_CSUM; 244 } else { 245 /* No tunnel. */ 246 if (i & (1 << 4)) /* IP. */ 247 v |= MLX5_ETH_WQE_L3_CSUM; 248 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */ 249 v |= MLX5_ETH_WQE_L4_CSUM; 250 } 251 mlx5_cksum_table[i] = v; 252 } 253 } 254 255 /** 256 * Build a table to translate packet type of mbuf to SWP type of Verbs. 257 */ 258 void 259 mlx5_set_swp_types_table(void) 260 { 261 unsigned int i; 262 uint8_t v; 263 264 /* 265 * The index should have: 266 * bit[0:1] = PKT_TX_L4_MASK 267 * bit[4] = PKT_TX_IPV6 268 * bit[8] = PKT_TX_OUTER_IPV6 269 * bit[9] = PKT_TX_OUTER_UDP 270 */ 271 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) { 272 v = 0; 273 if (i & (1 << 8)) 274 v |= MLX5_ETH_WQE_L3_OUTER_IPV6; 275 if (i & (1 << 9)) 276 v |= MLX5_ETH_WQE_L4_OUTER_UDP; 277 if (i & (1 << 4)) 278 v |= MLX5_ETH_WQE_L3_INNER_IPV6; 279 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52)) 280 v |= MLX5_ETH_WQE_L4_INNER_UDP; 281 mlx5_swp_types_table[i] = v; 282 } 283 } 284 285 /** 286 * Return the size of tailroom of WQ. 287 * 288 * @param txq 289 * Pointer to TX queue structure. 290 * @param addr 291 * Pointer to tail of WQ. 292 * 293 * @return 294 * Size of tailroom. 295 */ 296 static inline size_t 297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr) 298 { 299 size_t tailroom; 300 tailroom = (uintptr_t)(txq->wqes) + 301 (1 << txq->wqe_n) * MLX5_WQE_SIZE - 302 (uintptr_t)addr; 303 return tailroom; 304 } 305 306 /** 307 * Copy data to tailroom of circular queue. 308 * 309 * @param dst 310 * Pointer to destination. 311 * @param src 312 * Pointer to source. 313 * @param n 314 * Number of bytes to copy. 315 * @param base 316 * Pointer to head of queue. 317 * @param tailroom 318 * Size of tailroom from dst. 319 * 320 * @return 321 * Pointer after copied data. 322 */ 323 static inline void * 324 mlx5_copy_to_wq(void *dst, const void *src, size_t n, 325 void *base, size_t tailroom) 326 { 327 void *ret; 328 329 if (n > tailroom) { 330 rte_memcpy(dst, src, tailroom); 331 rte_memcpy(base, (void *)((uintptr_t)src + tailroom), 332 n - tailroom); 333 ret = (uint8_t *)base + n - tailroom; 334 } else { 335 rte_memcpy(dst, src, n); 336 ret = (n == tailroom) ? base : (uint8_t *)dst + n; 337 } 338 return ret; 339 } 340 341 /** 342 * Inline TSO headers into WQE. 343 * 344 * @return 345 * 0 on success, negative errno value on failure. 346 */ 347 static int 348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf, 349 uint32_t *length, 350 uintptr_t *addr, 351 uint16_t *pkt_inline_sz, 352 uint8_t **raw, 353 uint16_t *max_wqe, 354 uint16_t *tso_segsz, 355 uint16_t *tso_header_sz) 356 { 357 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) + 358 (1 << txq->wqe_n) * MLX5_WQE_SIZE); 359 unsigned int copy_b; 360 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0; 361 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags & 362 PKT_TX_TUNNEL_MASK); 363 uint16_t n_wqe; 364 365 *tso_segsz = buf->tso_segsz; 366 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len; 367 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) { 368 txq->stats.oerrors++; 369 return -EINVAL; 370 } 371 if (tunneled) 372 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len; 373 /* First seg must contain all TSO headers. */ 374 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) || 375 *tso_header_sz > DATA_LEN(buf)) { 376 txq->stats.oerrors++; 377 return -EINVAL; 378 } 379 copy_b = *tso_header_sz - *pkt_inline_sz; 380 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b)) 381 return -EAGAIN; 382 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4; 383 if (unlikely(*max_wqe < n_wqe)) 384 return -EINVAL; 385 *max_wqe -= n_wqe; 386 rte_memcpy((void *)*raw, (void *)*addr, copy_b); 387 *length -= copy_b; 388 *addr += copy_b; 389 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE; 390 *pkt_inline_sz += copy_b; 391 *raw += copy_b; 392 return 0; 393 } 394 395 /** 396 * DPDK callback to check the status of a tx descriptor. 397 * 398 * @param tx_queue 399 * The tx queue. 400 * @param[in] offset 401 * The index of the descriptor in the ring. 402 * 403 * @return 404 * The status of the tx descriptor. 405 */ 406 int 407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset) 408 { 409 struct mlx5_txq_data *txq = tx_queue; 410 uint16_t used; 411 412 mlx5_tx_complete(txq); 413 used = txq->elts_head - txq->elts_tail; 414 if (offset < used) 415 return RTE_ETH_TX_DESC_FULL; 416 return RTE_ETH_TX_DESC_DONE; 417 } 418 419 /** 420 * DPDK callback to check the status of a rx descriptor. 421 * 422 * @param rx_queue 423 * The rx queue. 424 * @param[in] offset 425 * The index of the descriptor in the ring. 426 * 427 * @return 428 * The status of the tx descriptor. 429 */ 430 int 431 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset) 432 { 433 struct mlx5_rxq_data *rxq = rx_queue; 434 struct rxq_zip *zip = &rxq->zip; 435 volatile struct mlx5_cqe *cqe; 436 const unsigned int cqe_n = (1 << rxq->cqe_n); 437 const unsigned int cqe_cnt = cqe_n - 1; 438 unsigned int cq_ci; 439 unsigned int used; 440 441 /* if we are processing a compressed cqe */ 442 if (zip->ai) { 443 used = zip->cqe_cnt - zip->ca; 444 cq_ci = zip->cq_ci; 445 } else { 446 used = 0; 447 cq_ci = rxq->cq_ci; 448 } 449 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt]; 450 while (check_cqe(cqe, cqe_n, cq_ci) == 0) { 451 int8_t op_own; 452 unsigned int n; 453 454 op_own = cqe->op_own; 455 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) 456 n = rte_be_to_cpu_32(cqe->byte_cnt); 457 else 458 n = 1; 459 cq_ci += n; 460 used += n; 461 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt]; 462 } 463 used = RTE_MIN(used, (1U << rxq->elts_n) - 1); 464 if (offset < used) 465 return RTE_ETH_RX_DESC_DONE; 466 return RTE_ETH_RX_DESC_AVAIL; 467 } 468 469 /** 470 * DPDK callback for TX. 471 * 472 * @param dpdk_txq 473 * Generic pointer to TX queue structure. 474 * @param[in] pkts 475 * Packets to transmit. 476 * @param pkts_n 477 * Number of packets in array. 478 * 479 * @return 480 * Number of packets successfully transmitted (<= pkts_n). 481 */ 482 uint16_t 483 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) 484 { 485 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; 486 uint16_t elts_head = txq->elts_head; 487 const uint16_t elts_n = 1 << txq->elts_n; 488 const uint16_t elts_m = elts_n - 1; 489 unsigned int i = 0; 490 unsigned int j = 0; 491 unsigned int k = 0; 492 uint16_t max_elts; 493 uint16_t max_wqe; 494 unsigned int comp; 495 volatile struct mlx5_wqe_ctrl *last_wqe = NULL; 496 unsigned int segs_n = 0; 497 const unsigned int max_inline = txq->max_inline; 498 uint64_t addr_64; 499 500 if (unlikely(!pkts_n)) 501 return 0; 502 /* Prefetch first packet cacheline. */ 503 rte_prefetch0(*pkts); 504 /* Start processing. */ 505 mlx5_tx_complete(txq); 506 max_elts = (elts_n - (elts_head - txq->elts_tail)); 507 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 508 if (unlikely(!max_wqe)) 509 return 0; 510 do { 511 struct rte_mbuf *buf = *pkts; /* First_seg. */ 512 uint8_t *raw; 513 volatile struct mlx5_wqe_v *wqe = NULL; 514 volatile rte_v128u32_t *dseg = NULL; 515 uint32_t length; 516 unsigned int ds = 0; 517 unsigned int sg = 0; /* counter of additional segs attached. */ 518 uintptr_t addr; 519 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2; 520 uint16_t tso_header_sz = 0; 521 uint16_t ehdr; 522 uint8_t cs_flags; 523 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG); 524 uint32_t swp_offsets = 0; 525 uint8_t swp_types = 0; 526 rte_be32_t metadata; 527 uint16_t tso_segsz = 0; 528 #ifdef MLX5_PMD_SOFT_COUNTERS 529 uint32_t total_length = 0; 530 #endif 531 int ret; 532 533 segs_n = buf->nb_segs; 534 /* 535 * Make sure there is enough room to store this packet and 536 * that one ring entry remains unused. 537 */ 538 assert(segs_n); 539 if (max_elts < segs_n) 540 break; 541 max_elts -= segs_n; 542 sg = --segs_n; 543 if (unlikely(--max_wqe == 0)) 544 break; 545 wqe = (volatile struct mlx5_wqe_v *) 546 tx_mlx5_wqe(txq, txq->wqe_ci); 547 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1)); 548 if (pkts_n - i > 1) 549 rte_prefetch0(*(pkts + 1)); 550 addr = rte_pktmbuf_mtod(buf, uintptr_t); 551 length = DATA_LEN(buf); 552 ehdr = (((uint8_t *)addr)[1] << 8) | 553 ((uint8_t *)addr)[0]; 554 #ifdef MLX5_PMD_SOFT_COUNTERS 555 total_length = length; 556 #endif 557 if (length < (MLX5_WQE_DWORD_SIZE + 2)) { 558 txq->stats.oerrors++; 559 break; 560 } 561 /* Update element. */ 562 (*txq->elts)[elts_head & elts_m] = buf; 563 /* Prefetch next buffer data. */ 564 if (pkts_n - i > 1) 565 rte_prefetch0( 566 rte_pktmbuf_mtod(*(pkts + 1), volatile void *)); 567 cs_flags = txq_ol_cksum_to_cs(buf); 568 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types); 569 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE; 570 /* Copy metadata from mbuf if valid */ 571 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata : 572 0; 573 /* Replace the Ethernet type by the VLAN if necessary. */ 574 if (buf->ol_flags & PKT_TX_VLAN_PKT) { 575 uint32_t vlan = rte_cpu_to_be_32(0x81000000 | 576 buf->vlan_tci); 577 unsigned int len = 2 * ETHER_ADDR_LEN - 2; 578 579 addr += 2; 580 length -= 2; 581 /* Copy Destination and source mac address. */ 582 memcpy((uint8_t *)raw, ((uint8_t *)addr), len); 583 /* Copy VLAN. */ 584 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan)); 585 /* Copy missing two bytes to end the DSeg. */ 586 memcpy((uint8_t *)raw + len + sizeof(vlan), 587 ((uint8_t *)addr) + len, 2); 588 addr += len + 2; 589 length -= (len + 2); 590 } else { 591 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 592 MLX5_WQE_DWORD_SIZE); 593 length -= pkt_inline_sz; 594 addr += pkt_inline_sz; 595 } 596 raw += MLX5_WQE_DWORD_SIZE; 597 if (tso) { 598 ret = inline_tso(txq, buf, &length, 599 &addr, &pkt_inline_sz, 600 &raw, &max_wqe, 601 &tso_segsz, &tso_header_sz); 602 if (ret == -EINVAL) { 603 break; 604 } else if (ret == -EAGAIN) { 605 /* NOP WQE. */ 606 wqe->ctrl = (rte_v128u32_t){ 607 rte_cpu_to_be_32(txq->wqe_ci << 8), 608 rte_cpu_to_be_32(txq->qp_num_8s | 1), 609 0, 610 0, 611 }; 612 ds = 1; 613 #ifdef MLX5_PMD_SOFT_COUNTERS 614 total_length = 0; 615 #endif 616 k++; 617 goto next_wqe; 618 } 619 } 620 /* Inline if enough room. */ 621 if (max_inline || tso) { 622 uint32_t inl = 0; 623 uintptr_t end = (uintptr_t) 624 (((uintptr_t)txq->wqes) + 625 (1 << txq->wqe_n) * MLX5_WQE_SIZE); 626 unsigned int inline_room = max_inline * 627 RTE_CACHE_LINE_SIZE - 628 (pkt_inline_sz - 2) - 629 !!tso * sizeof(inl); 630 uintptr_t addr_end; 631 unsigned int copy_b; 632 633 pkt_inline: 634 addr_end = RTE_ALIGN_FLOOR(addr + inline_room, 635 RTE_CACHE_LINE_SIZE); 636 copy_b = (addr_end > addr) ? 637 RTE_MIN((addr_end - addr), length) : 0; 638 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) { 639 /* 640 * One Dseg remains in the current WQE. To 641 * keep the computation positive, it is 642 * removed after the bytes to Dseg conversion. 643 */ 644 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4; 645 646 if (unlikely(max_wqe < n)) 647 break; 648 max_wqe -= n; 649 if (tso) { 650 assert(inl == 0); 651 inl = rte_cpu_to_be_32(copy_b | 652 MLX5_INLINE_SEG); 653 rte_memcpy((void *)raw, 654 (void *)&inl, sizeof(inl)); 655 raw += sizeof(inl); 656 pkt_inline_sz += sizeof(inl); 657 } 658 rte_memcpy((void *)raw, (void *)addr, copy_b); 659 addr += copy_b; 660 length -= copy_b; 661 pkt_inline_sz += copy_b; 662 } 663 /* 664 * 2 DWORDs consumed by the WQE header + ETH segment + 665 * the size of the inline part of the packet. 666 */ 667 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2); 668 if (length > 0) { 669 if (ds % (MLX5_WQE_SIZE / 670 MLX5_WQE_DWORD_SIZE) == 0) { 671 if (unlikely(--max_wqe == 0)) 672 break; 673 dseg = (volatile rte_v128u32_t *) 674 tx_mlx5_wqe(txq, txq->wqe_ci + 675 ds / 4); 676 } else { 677 dseg = (volatile rte_v128u32_t *) 678 ((uintptr_t)wqe + 679 (ds * MLX5_WQE_DWORD_SIZE)); 680 } 681 goto use_dseg; 682 } else if (!segs_n) { 683 goto next_pkt; 684 } else { 685 /* 686 * Further inline the next segment only for 687 * non-TSO packets. 688 */ 689 if (!tso) { 690 raw += copy_b; 691 inline_room -= copy_b; 692 } else { 693 inline_room = 0; 694 } 695 /* Move to the next segment. */ 696 --segs_n; 697 buf = buf->next; 698 assert(buf); 699 addr = rte_pktmbuf_mtod(buf, uintptr_t); 700 length = DATA_LEN(buf); 701 #ifdef MLX5_PMD_SOFT_COUNTERS 702 total_length += length; 703 #endif 704 (*txq->elts)[++elts_head & elts_m] = buf; 705 goto pkt_inline; 706 } 707 } else { 708 /* 709 * No inline has been done in the packet, only the 710 * Ethernet Header as been stored. 711 */ 712 dseg = (volatile rte_v128u32_t *) 713 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE)); 714 ds = 3; 715 use_dseg: 716 /* Add the remaining packet as a simple ds. */ 717 addr_64 = rte_cpu_to_be_64(addr); 718 *dseg = (rte_v128u32_t){ 719 rte_cpu_to_be_32(length), 720 mlx5_tx_mb2mr(txq, buf), 721 addr_64, 722 addr_64 >> 32, 723 }; 724 ++ds; 725 if (!segs_n) 726 goto next_pkt; 727 } 728 next_seg: 729 assert(buf); 730 assert(ds); 731 assert(wqe); 732 /* 733 * Spill on next WQE when the current one does not have 734 * enough room left. Size of WQE must a be a multiple 735 * of data segment size. 736 */ 737 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE)); 738 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) { 739 if (unlikely(--max_wqe == 0)) 740 break; 741 dseg = (volatile rte_v128u32_t *) 742 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4); 743 rte_prefetch0(tx_mlx5_wqe(txq, 744 txq->wqe_ci + ds / 4 + 1)); 745 } else { 746 ++dseg; 747 } 748 ++ds; 749 buf = buf->next; 750 assert(buf); 751 length = DATA_LEN(buf); 752 #ifdef MLX5_PMD_SOFT_COUNTERS 753 total_length += length; 754 #endif 755 /* Store segment information. */ 756 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t)); 757 *dseg = (rte_v128u32_t){ 758 rte_cpu_to_be_32(length), 759 mlx5_tx_mb2mr(txq, buf), 760 addr_64, 761 addr_64 >> 32, 762 }; 763 (*txq->elts)[++elts_head & elts_m] = buf; 764 if (--segs_n) 765 goto next_seg; 766 next_pkt: 767 if (ds > MLX5_DSEG_MAX) { 768 txq->stats.oerrors++; 769 break; 770 } 771 ++elts_head; 772 ++pkts; 773 ++i; 774 j += sg; 775 /* Initialize known and common part of the WQE structure. */ 776 if (tso) { 777 wqe->ctrl = (rte_v128u32_t){ 778 rte_cpu_to_be_32((txq->wqe_ci << 8) | 779 MLX5_OPCODE_TSO), 780 rte_cpu_to_be_32(txq->qp_num_8s | ds), 781 0, 782 0, 783 }; 784 wqe->eseg = (rte_v128u32_t){ 785 swp_offsets, 786 cs_flags | (swp_types << 8) | 787 (rte_cpu_to_be_16(tso_segsz) << 16), 788 metadata, 789 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz), 790 }; 791 } else { 792 wqe->ctrl = (rte_v128u32_t){ 793 rte_cpu_to_be_32((txq->wqe_ci << 8) | 794 MLX5_OPCODE_SEND), 795 rte_cpu_to_be_32(txq->qp_num_8s | ds), 796 0, 797 0, 798 }; 799 wqe->eseg = (rte_v128u32_t){ 800 swp_offsets, 801 cs_flags | (swp_types << 8), 802 metadata, 803 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz), 804 }; 805 } 806 next_wqe: 807 txq->wqe_ci += (ds + 3) / 4; 808 /* Save the last successful WQE for completion request */ 809 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe; 810 #ifdef MLX5_PMD_SOFT_COUNTERS 811 /* Increment sent bytes counter. */ 812 txq->stats.obytes += total_length; 813 #endif 814 } while (i < pkts_n); 815 /* Take a shortcut if nothing must be sent. */ 816 if (unlikely((i + k) == 0)) 817 return 0; 818 txq->elts_head += (i + j); 819 /* Check whether completion threshold has been reached. */ 820 comp = txq->elts_comp + i + j + k; 821 if (comp >= MLX5_TX_COMP_THRESH) { 822 /* A CQE slot must always be available. */ 823 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci)); 824 /* Request completion on last WQE. */ 825 last_wqe->ctrl2 = rte_cpu_to_be_32(8); 826 /* Save elts_head in unused "immediate" field of WQE. */ 827 last_wqe->ctrl3 = txq->elts_head; 828 txq->elts_comp = 0; 829 } else { 830 txq->elts_comp = comp; 831 } 832 #ifdef MLX5_PMD_SOFT_COUNTERS 833 /* Increment sent packets counter. */ 834 txq->stats.opackets += i; 835 #endif 836 /* Ring QP doorbell. */ 837 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe); 838 return i; 839 } 840 841 /** 842 * Open a MPW session. 843 * 844 * @param txq 845 * Pointer to TX queue structure. 846 * @param mpw 847 * Pointer to MPW session structure. 848 * @param length 849 * Packet length. 850 */ 851 static inline void 852 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length) 853 { 854 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1); 855 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] = 856 (volatile struct mlx5_wqe_data_seg (*)[]) 857 tx_mlx5_wqe(txq, idx + 1); 858 859 mpw->state = MLX5_MPW_STATE_OPENED; 860 mpw->pkts_n = 0; 861 mpw->len = length; 862 mpw->total_len = 0; 863 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx); 864 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length); 865 mpw->wqe->eseg.inline_hdr_sz = 0; 866 mpw->wqe->eseg.rsvd0 = 0; 867 mpw->wqe->eseg.rsvd1 = 0; 868 mpw->wqe->eseg.flow_table_metadata = 0; 869 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) | 870 (txq->wqe_ci << 8) | 871 MLX5_OPCODE_TSO); 872 mpw->wqe->ctrl[2] = 0; 873 mpw->wqe->ctrl[3] = 0; 874 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *) 875 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE)); 876 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *) 877 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE)); 878 mpw->data.dseg[2] = &(*dseg)[0]; 879 mpw->data.dseg[3] = &(*dseg)[1]; 880 mpw->data.dseg[4] = &(*dseg)[2]; 881 } 882 883 /** 884 * Close a MPW session. 885 * 886 * @param txq 887 * Pointer to TX queue structure. 888 * @param mpw 889 * Pointer to MPW session structure. 890 */ 891 static inline void 892 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw) 893 { 894 unsigned int num = mpw->pkts_n; 895 896 /* 897 * Store size in multiple of 16 bytes. Control and Ethernet segments 898 * count as 2. 899 */ 900 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num)); 901 mpw->state = MLX5_MPW_STATE_CLOSED; 902 if (num < 3) 903 ++txq->wqe_ci; 904 else 905 txq->wqe_ci += 2; 906 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci)); 907 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1)); 908 } 909 910 /** 911 * DPDK callback for TX with MPW support. 912 * 913 * @param dpdk_txq 914 * Generic pointer to TX queue structure. 915 * @param[in] pkts 916 * Packets to transmit. 917 * @param pkts_n 918 * Number of packets in array. 919 * 920 * @return 921 * Number of packets successfully transmitted (<= pkts_n). 922 */ 923 uint16_t 924 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) 925 { 926 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; 927 uint16_t elts_head = txq->elts_head; 928 const uint16_t elts_n = 1 << txq->elts_n; 929 const uint16_t elts_m = elts_n - 1; 930 unsigned int i = 0; 931 unsigned int j = 0; 932 uint16_t max_elts; 933 uint16_t max_wqe; 934 unsigned int comp; 935 struct mlx5_mpw mpw = { 936 .state = MLX5_MPW_STATE_CLOSED, 937 }; 938 939 if (unlikely(!pkts_n)) 940 return 0; 941 /* Prefetch first packet cacheline. */ 942 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci)); 943 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1)); 944 /* Start processing. */ 945 mlx5_tx_complete(txq); 946 max_elts = (elts_n - (elts_head - txq->elts_tail)); 947 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 948 if (unlikely(!max_wqe)) 949 return 0; 950 do { 951 struct rte_mbuf *buf = *(pkts++); 952 uint32_t length; 953 unsigned int segs_n = buf->nb_segs; 954 uint32_t cs_flags; 955 rte_be32_t metadata; 956 957 /* 958 * Make sure there is enough room to store this packet and 959 * that one ring entry remains unused. 960 */ 961 assert(segs_n); 962 if (max_elts < segs_n) 963 break; 964 /* Do not bother with large packets MPW cannot handle. */ 965 if (segs_n > MLX5_MPW_DSEG_MAX) { 966 txq->stats.oerrors++; 967 break; 968 } 969 max_elts -= segs_n; 970 --pkts_n; 971 cs_flags = txq_ol_cksum_to_cs(buf); 972 /* Copy metadata from mbuf if valid */ 973 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata : 974 0; 975 /* Retrieve packet information. */ 976 length = PKT_LEN(buf); 977 assert(length); 978 /* Start new session if packet differs. */ 979 if ((mpw.state == MLX5_MPW_STATE_OPENED) && 980 ((mpw.len != length) || 981 (segs_n != 1) || 982 (mpw.wqe->eseg.flow_table_metadata != metadata) || 983 (mpw.wqe->eseg.cs_flags != cs_flags))) 984 mlx5_mpw_close(txq, &mpw); 985 if (mpw.state == MLX5_MPW_STATE_CLOSED) { 986 /* 987 * Multi-Packet WQE consumes at most two WQE. 988 * mlx5_mpw_new() expects to be able to use such 989 * resources. 990 */ 991 if (unlikely(max_wqe < 2)) 992 break; 993 max_wqe -= 2; 994 mlx5_mpw_new(txq, &mpw, length); 995 mpw.wqe->eseg.cs_flags = cs_flags; 996 mpw.wqe->eseg.flow_table_metadata = metadata; 997 } 998 /* Multi-segment packets must be alone in their MPW. */ 999 assert((segs_n == 1) || (mpw.pkts_n == 0)); 1000 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG) 1001 length = 0; 1002 #endif 1003 do { 1004 volatile struct mlx5_wqe_data_seg *dseg; 1005 uintptr_t addr; 1006 1007 assert(buf); 1008 (*txq->elts)[elts_head++ & elts_m] = buf; 1009 dseg = mpw.data.dseg[mpw.pkts_n]; 1010 addr = rte_pktmbuf_mtod(buf, uintptr_t); 1011 *dseg = (struct mlx5_wqe_data_seg){ 1012 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)), 1013 .lkey = mlx5_tx_mb2mr(txq, buf), 1014 .addr = rte_cpu_to_be_64(addr), 1015 }; 1016 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG) 1017 length += DATA_LEN(buf); 1018 #endif 1019 buf = buf->next; 1020 ++mpw.pkts_n; 1021 ++j; 1022 } while (--segs_n); 1023 assert(length == mpw.len); 1024 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) 1025 mlx5_mpw_close(txq, &mpw); 1026 #ifdef MLX5_PMD_SOFT_COUNTERS 1027 /* Increment sent bytes counter. */ 1028 txq->stats.obytes += length; 1029 #endif 1030 ++i; 1031 } while (pkts_n); 1032 /* Take a shortcut if nothing must be sent. */ 1033 if (unlikely(i == 0)) 1034 return 0; 1035 /* Check whether completion threshold has been reached. */ 1036 /* "j" includes both packets and segments. */ 1037 comp = txq->elts_comp + j; 1038 if (comp >= MLX5_TX_COMP_THRESH) { 1039 volatile struct mlx5_wqe *wqe = mpw.wqe; 1040 1041 /* A CQE slot must always be available. */ 1042 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci)); 1043 /* Request completion on last WQE. */ 1044 wqe->ctrl[2] = rte_cpu_to_be_32(8); 1045 /* Save elts_head in unused "immediate" field of WQE. */ 1046 wqe->ctrl[3] = elts_head; 1047 txq->elts_comp = 0; 1048 } else { 1049 txq->elts_comp = comp; 1050 } 1051 #ifdef MLX5_PMD_SOFT_COUNTERS 1052 /* Increment sent packets counter. */ 1053 txq->stats.opackets += i; 1054 #endif 1055 /* Ring QP doorbell. */ 1056 if (mpw.state == MLX5_MPW_STATE_OPENED) 1057 mlx5_mpw_close(txq, &mpw); 1058 mlx5_tx_dbrec(txq, mpw.wqe); 1059 txq->elts_head = elts_head; 1060 return i; 1061 } 1062 1063 /** 1064 * Open a MPW inline session. 1065 * 1066 * @param txq 1067 * Pointer to TX queue structure. 1068 * @param mpw 1069 * Pointer to MPW session structure. 1070 * @param length 1071 * Packet length. 1072 */ 1073 static inline void 1074 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, 1075 uint32_t length) 1076 { 1077 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1); 1078 struct mlx5_wqe_inl_small *inl; 1079 1080 mpw->state = MLX5_MPW_INL_STATE_OPENED; 1081 mpw->pkts_n = 0; 1082 mpw->len = length; 1083 mpw->total_len = 0; 1084 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx); 1085 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) | 1086 (txq->wqe_ci << 8) | 1087 MLX5_OPCODE_TSO); 1088 mpw->wqe->ctrl[2] = 0; 1089 mpw->wqe->ctrl[3] = 0; 1090 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length); 1091 mpw->wqe->eseg.inline_hdr_sz = 0; 1092 mpw->wqe->eseg.cs_flags = 0; 1093 mpw->wqe->eseg.rsvd0 = 0; 1094 mpw->wqe->eseg.rsvd1 = 0; 1095 mpw->wqe->eseg.flow_table_metadata = 0; 1096 inl = (struct mlx5_wqe_inl_small *) 1097 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE); 1098 mpw->data.raw = (uint8_t *)&inl->raw; 1099 } 1100 1101 /** 1102 * Close a MPW inline session. 1103 * 1104 * @param txq 1105 * Pointer to TX queue structure. 1106 * @param mpw 1107 * Pointer to MPW session structure. 1108 */ 1109 static inline void 1110 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw) 1111 { 1112 unsigned int size; 1113 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *) 1114 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE)); 1115 1116 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len; 1117 /* 1118 * Store size in multiple of 16 bytes. Control and Ethernet segments 1119 * count as 2. 1120 */ 1121 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | 1122 MLX5_WQE_DS(size)); 1123 mpw->state = MLX5_MPW_STATE_CLOSED; 1124 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG); 1125 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE; 1126 } 1127 1128 /** 1129 * DPDK callback for TX with MPW inline support. 1130 * 1131 * @param dpdk_txq 1132 * Generic pointer to TX queue structure. 1133 * @param[in] pkts 1134 * Packets to transmit. 1135 * @param pkts_n 1136 * Number of packets in array. 1137 * 1138 * @return 1139 * Number of packets successfully transmitted (<= pkts_n). 1140 */ 1141 uint16_t 1142 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts, 1143 uint16_t pkts_n) 1144 { 1145 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; 1146 uint16_t elts_head = txq->elts_head; 1147 const uint16_t elts_n = 1 << txq->elts_n; 1148 const uint16_t elts_m = elts_n - 1; 1149 unsigned int i = 0; 1150 unsigned int j = 0; 1151 uint16_t max_elts; 1152 uint16_t max_wqe; 1153 unsigned int comp; 1154 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE; 1155 struct mlx5_mpw mpw = { 1156 .state = MLX5_MPW_STATE_CLOSED, 1157 }; 1158 /* 1159 * Compute the maximum number of WQE which can be consumed by inline 1160 * code. 1161 * - 2 DSEG for: 1162 * - 1 control segment, 1163 * - 1 Ethernet segment, 1164 * - N Dseg from the inline request. 1165 */ 1166 const unsigned int wqe_inl_n = 1167 ((2 * MLX5_WQE_DWORD_SIZE + 1168 txq->max_inline * RTE_CACHE_LINE_SIZE) + 1169 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE; 1170 1171 if (unlikely(!pkts_n)) 1172 return 0; 1173 /* Prefetch first packet cacheline. */ 1174 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci)); 1175 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1)); 1176 /* Start processing. */ 1177 mlx5_tx_complete(txq); 1178 max_elts = (elts_n - (elts_head - txq->elts_tail)); 1179 do { 1180 struct rte_mbuf *buf = *(pkts++); 1181 uintptr_t addr; 1182 uint32_t length; 1183 unsigned int segs_n = buf->nb_segs; 1184 uint8_t cs_flags; 1185 rte_be32_t metadata; 1186 1187 /* 1188 * Make sure there is enough room to store this packet and 1189 * that one ring entry remains unused. 1190 */ 1191 assert(segs_n); 1192 if (max_elts < segs_n) 1193 break; 1194 /* Do not bother with large packets MPW cannot handle. */ 1195 if (segs_n > MLX5_MPW_DSEG_MAX) { 1196 txq->stats.oerrors++; 1197 break; 1198 } 1199 max_elts -= segs_n; 1200 --pkts_n; 1201 /* 1202 * Compute max_wqe in case less WQE were consumed in previous 1203 * iteration. 1204 */ 1205 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 1206 cs_flags = txq_ol_cksum_to_cs(buf); 1207 /* Copy metadata from mbuf if valid */ 1208 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata : 1209 0; 1210 /* Retrieve packet information. */ 1211 length = PKT_LEN(buf); 1212 /* Start new session if packet differs. */ 1213 if (mpw.state == MLX5_MPW_STATE_OPENED) { 1214 if ((mpw.len != length) || 1215 (segs_n != 1) || 1216 (mpw.wqe->eseg.flow_table_metadata != metadata) || 1217 (mpw.wqe->eseg.cs_flags != cs_flags)) 1218 mlx5_mpw_close(txq, &mpw); 1219 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) { 1220 if ((mpw.len != length) || 1221 (segs_n != 1) || 1222 (length > inline_room) || 1223 (mpw.wqe->eseg.flow_table_metadata != metadata) || 1224 (mpw.wqe->eseg.cs_flags != cs_flags)) { 1225 mlx5_mpw_inline_close(txq, &mpw); 1226 inline_room = 1227 txq->max_inline * RTE_CACHE_LINE_SIZE; 1228 } 1229 } 1230 if (mpw.state == MLX5_MPW_STATE_CLOSED) { 1231 if ((segs_n != 1) || 1232 (length > inline_room)) { 1233 /* 1234 * Multi-Packet WQE consumes at most two WQE. 1235 * mlx5_mpw_new() expects to be able to use 1236 * such resources. 1237 */ 1238 if (unlikely(max_wqe < 2)) 1239 break; 1240 max_wqe -= 2; 1241 mlx5_mpw_new(txq, &mpw, length); 1242 mpw.wqe->eseg.cs_flags = cs_flags; 1243 mpw.wqe->eseg.flow_table_metadata = metadata; 1244 } else { 1245 if (unlikely(max_wqe < wqe_inl_n)) 1246 break; 1247 max_wqe -= wqe_inl_n; 1248 mlx5_mpw_inline_new(txq, &mpw, length); 1249 mpw.wqe->eseg.cs_flags = cs_flags; 1250 mpw.wqe->eseg.flow_table_metadata = metadata; 1251 } 1252 } 1253 /* Multi-segment packets must be alone in their MPW. */ 1254 assert((segs_n == 1) || (mpw.pkts_n == 0)); 1255 if (mpw.state == MLX5_MPW_STATE_OPENED) { 1256 assert(inline_room == 1257 txq->max_inline * RTE_CACHE_LINE_SIZE); 1258 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG) 1259 length = 0; 1260 #endif 1261 do { 1262 volatile struct mlx5_wqe_data_seg *dseg; 1263 1264 assert(buf); 1265 (*txq->elts)[elts_head++ & elts_m] = buf; 1266 dseg = mpw.data.dseg[mpw.pkts_n]; 1267 addr = rte_pktmbuf_mtod(buf, uintptr_t); 1268 *dseg = (struct mlx5_wqe_data_seg){ 1269 .byte_count = 1270 rte_cpu_to_be_32(DATA_LEN(buf)), 1271 .lkey = mlx5_tx_mb2mr(txq, buf), 1272 .addr = rte_cpu_to_be_64(addr), 1273 }; 1274 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG) 1275 length += DATA_LEN(buf); 1276 #endif 1277 buf = buf->next; 1278 ++mpw.pkts_n; 1279 ++j; 1280 } while (--segs_n); 1281 assert(length == mpw.len); 1282 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) 1283 mlx5_mpw_close(txq, &mpw); 1284 } else { 1285 unsigned int max; 1286 1287 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED); 1288 assert(length <= inline_room); 1289 assert(length == DATA_LEN(buf)); 1290 addr = rte_pktmbuf_mtod(buf, uintptr_t); 1291 (*txq->elts)[elts_head++ & elts_m] = buf; 1292 /* Maximum number of bytes before wrapping. */ 1293 max = ((((uintptr_t)(txq->wqes)) + 1294 (1 << txq->wqe_n) * 1295 MLX5_WQE_SIZE) - 1296 (uintptr_t)mpw.data.raw); 1297 if (length > max) { 1298 rte_memcpy((void *)(uintptr_t)mpw.data.raw, 1299 (void *)addr, 1300 max); 1301 mpw.data.raw = (volatile void *)txq->wqes; 1302 rte_memcpy((void *)(uintptr_t)mpw.data.raw, 1303 (void *)(addr + max), 1304 length - max); 1305 mpw.data.raw += length - max; 1306 } else { 1307 rte_memcpy((void *)(uintptr_t)mpw.data.raw, 1308 (void *)addr, 1309 length); 1310 1311 if (length == max) 1312 mpw.data.raw = 1313 (volatile void *)txq->wqes; 1314 else 1315 mpw.data.raw += length; 1316 } 1317 ++mpw.pkts_n; 1318 mpw.total_len += length; 1319 ++j; 1320 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) { 1321 mlx5_mpw_inline_close(txq, &mpw); 1322 inline_room = 1323 txq->max_inline * RTE_CACHE_LINE_SIZE; 1324 } else { 1325 inline_room -= length; 1326 } 1327 } 1328 #ifdef MLX5_PMD_SOFT_COUNTERS 1329 /* Increment sent bytes counter. */ 1330 txq->stats.obytes += length; 1331 #endif 1332 ++i; 1333 } while (pkts_n); 1334 /* Take a shortcut if nothing must be sent. */ 1335 if (unlikely(i == 0)) 1336 return 0; 1337 /* Check whether completion threshold has been reached. */ 1338 /* "j" includes both packets and segments. */ 1339 comp = txq->elts_comp + j; 1340 if (comp >= MLX5_TX_COMP_THRESH) { 1341 volatile struct mlx5_wqe *wqe = mpw.wqe; 1342 1343 /* A CQE slot must always be available. */ 1344 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci)); 1345 /* Request completion on last WQE. */ 1346 wqe->ctrl[2] = rte_cpu_to_be_32(8); 1347 /* Save elts_head in unused "immediate" field of WQE. */ 1348 wqe->ctrl[3] = elts_head; 1349 txq->elts_comp = 0; 1350 } else { 1351 txq->elts_comp = comp; 1352 } 1353 #ifdef MLX5_PMD_SOFT_COUNTERS 1354 /* Increment sent packets counter. */ 1355 txq->stats.opackets += i; 1356 #endif 1357 /* Ring QP doorbell. */ 1358 if (mpw.state == MLX5_MPW_INL_STATE_OPENED) 1359 mlx5_mpw_inline_close(txq, &mpw); 1360 else if (mpw.state == MLX5_MPW_STATE_OPENED) 1361 mlx5_mpw_close(txq, &mpw); 1362 mlx5_tx_dbrec(txq, mpw.wqe); 1363 txq->elts_head = elts_head; 1364 return i; 1365 } 1366 1367 /** 1368 * Open an Enhanced MPW session. 1369 * 1370 * @param txq 1371 * Pointer to TX queue structure. 1372 * @param mpw 1373 * Pointer to MPW session structure. 1374 * @param length 1375 * Packet length. 1376 */ 1377 static inline void 1378 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding) 1379 { 1380 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1); 1381 1382 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED; 1383 mpw->pkts_n = 0; 1384 mpw->total_len = sizeof(struct mlx5_wqe); 1385 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx); 1386 mpw->wqe->ctrl[0] = 1387 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) | 1388 (txq->wqe_ci << 8) | 1389 MLX5_OPCODE_ENHANCED_MPSW); 1390 mpw->wqe->ctrl[2] = 0; 1391 mpw->wqe->ctrl[3] = 0; 1392 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE); 1393 if (unlikely(padding)) { 1394 uintptr_t addr = (uintptr_t)(mpw->wqe + 1); 1395 1396 /* Pad the first 2 DWORDs with zero-length inline header. */ 1397 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG); 1398 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) = 1399 rte_cpu_to_be_32(MLX5_INLINE_SEG); 1400 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE; 1401 /* Start from the next WQEBB. */ 1402 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1)); 1403 } else { 1404 mpw->data.raw = (volatile void *)(mpw->wqe + 1); 1405 } 1406 } 1407 1408 /** 1409 * Close an Enhanced MPW session. 1410 * 1411 * @param txq 1412 * Pointer to TX queue structure. 1413 * @param mpw 1414 * Pointer to MPW session structure. 1415 * 1416 * @return 1417 * Number of consumed WQEs. 1418 */ 1419 static inline uint16_t 1420 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw) 1421 { 1422 uint16_t ret; 1423 1424 /* Store size in multiple of 16 bytes. Control and Ethernet segments 1425 * count as 2. 1426 */ 1427 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | 1428 MLX5_WQE_DS(mpw->total_len)); 1429 mpw->state = MLX5_MPW_STATE_CLOSED; 1430 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE; 1431 txq->wqe_ci += ret; 1432 return ret; 1433 } 1434 1435 /** 1436 * TX with Enhanced MPW support. 1437 * 1438 * @param txq 1439 * Pointer to TX queue structure. 1440 * @param[in] pkts 1441 * Packets to transmit. 1442 * @param pkts_n 1443 * Number of packets in array. 1444 * 1445 * @return 1446 * Number of packets successfully transmitted (<= pkts_n). 1447 */ 1448 static inline uint16_t 1449 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, 1450 uint16_t pkts_n) 1451 { 1452 uint16_t elts_head = txq->elts_head; 1453 const uint16_t elts_n = 1 << txq->elts_n; 1454 const uint16_t elts_m = elts_n - 1; 1455 unsigned int i = 0; 1456 unsigned int j = 0; 1457 uint16_t max_elts; 1458 uint16_t max_wqe; 1459 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE; 1460 unsigned int mpw_room = 0; 1461 unsigned int inl_pad = 0; 1462 uint32_t inl_hdr; 1463 uint64_t addr_64; 1464 struct mlx5_mpw mpw = { 1465 .state = MLX5_MPW_STATE_CLOSED, 1466 }; 1467 1468 if (unlikely(!pkts_n)) 1469 return 0; 1470 /* Start processing. */ 1471 mlx5_tx_complete(txq); 1472 max_elts = (elts_n - (elts_head - txq->elts_tail)); 1473 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 1474 if (unlikely(!max_wqe)) 1475 return 0; 1476 do { 1477 struct rte_mbuf *buf = *(pkts++); 1478 uintptr_t addr; 1479 unsigned int do_inline = 0; /* Whether inline is possible. */ 1480 uint32_t length; 1481 uint8_t cs_flags; 1482 rte_be32_t metadata; 1483 1484 /* Multi-segmented packet is handled in slow-path outside. */ 1485 assert(NB_SEGS(buf) == 1); 1486 /* Make sure there is enough room to store this packet. */ 1487 if (max_elts - j == 0) 1488 break; 1489 cs_flags = txq_ol_cksum_to_cs(buf); 1490 /* Copy metadata from mbuf if valid */ 1491 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata : 1492 0; 1493 /* Retrieve packet information. */ 1494 length = PKT_LEN(buf); 1495 /* Start new session if: 1496 * - multi-segment packet 1497 * - no space left even for a dseg 1498 * - next packet can be inlined with a new WQE 1499 * - cs_flag differs 1500 */ 1501 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) { 1502 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) > 1503 mpw_room) || 1504 (length <= txq->inline_max_packet_sz && 1505 inl_pad + sizeof(inl_hdr) + length > 1506 mpw_room) || 1507 (mpw.wqe->eseg.flow_table_metadata != metadata) || 1508 (mpw.wqe->eseg.cs_flags != cs_flags)) 1509 max_wqe -= mlx5_empw_close(txq, &mpw); 1510 } 1511 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) { 1512 /* In Enhanced MPW, inline as much as the budget is 1513 * allowed. The remaining space is to be filled with 1514 * dsegs. If the title WQEBB isn't padded, it will have 1515 * 2 dsegs there. 1516 */ 1517 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX, 1518 (max_inline ? max_inline : 1519 pkts_n * MLX5_WQE_DWORD_SIZE) + 1520 MLX5_WQE_SIZE); 1521 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room)) 1522 break; 1523 /* Don't pad the title WQEBB to not waste WQ. */ 1524 mlx5_empw_new(txq, &mpw, 0); 1525 mpw_room -= mpw.total_len; 1526 inl_pad = 0; 1527 do_inline = length <= txq->inline_max_packet_sz && 1528 sizeof(inl_hdr) + length <= mpw_room && 1529 !txq->mpw_hdr_dseg; 1530 mpw.wqe->eseg.cs_flags = cs_flags; 1531 mpw.wqe->eseg.flow_table_metadata = metadata; 1532 } else { 1533 /* Evaluate whether the next packet can be inlined. 1534 * Inlininig is possible when: 1535 * - length is less than configured value 1536 * - length fits for remaining space 1537 * - not required to fill the title WQEBB with dsegs 1538 */ 1539 do_inline = 1540 length <= txq->inline_max_packet_sz && 1541 inl_pad + sizeof(inl_hdr) + length <= 1542 mpw_room && 1543 (!txq->mpw_hdr_dseg || 1544 mpw.total_len >= MLX5_WQE_SIZE); 1545 } 1546 if (max_inline && do_inline) { 1547 /* Inline packet into WQE. */ 1548 unsigned int max; 1549 1550 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED); 1551 assert(length == DATA_LEN(buf)); 1552 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG); 1553 addr = rte_pktmbuf_mtod(buf, uintptr_t); 1554 mpw.data.raw = (volatile void *) 1555 ((uintptr_t)mpw.data.raw + inl_pad); 1556 max = tx_mlx5_wq_tailroom(txq, 1557 (void *)(uintptr_t)mpw.data.raw); 1558 /* Copy inline header. */ 1559 mpw.data.raw = (volatile void *) 1560 mlx5_copy_to_wq( 1561 (void *)(uintptr_t)mpw.data.raw, 1562 &inl_hdr, 1563 sizeof(inl_hdr), 1564 (void *)(uintptr_t)txq->wqes, 1565 max); 1566 max = tx_mlx5_wq_tailroom(txq, 1567 (void *)(uintptr_t)mpw.data.raw); 1568 /* Copy packet data. */ 1569 mpw.data.raw = (volatile void *) 1570 mlx5_copy_to_wq( 1571 (void *)(uintptr_t)mpw.data.raw, 1572 (void *)addr, 1573 length, 1574 (void *)(uintptr_t)txq->wqes, 1575 max); 1576 ++mpw.pkts_n; 1577 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length); 1578 /* No need to get completion as the entire packet is 1579 * copied to WQ. Free the buf right away. 1580 */ 1581 rte_pktmbuf_free_seg(buf); 1582 mpw_room -= (inl_pad + sizeof(inl_hdr) + length); 1583 /* Add pad in the next packet if any. */ 1584 inl_pad = (((uintptr_t)mpw.data.raw + 1585 (MLX5_WQE_DWORD_SIZE - 1)) & 1586 ~(MLX5_WQE_DWORD_SIZE - 1)) - 1587 (uintptr_t)mpw.data.raw; 1588 } else { 1589 /* No inline. Load a dseg of packet pointer. */ 1590 volatile rte_v128u32_t *dseg; 1591 1592 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED); 1593 assert((inl_pad + sizeof(*dseg)) <= mpw_room); 1594 assert(length == DATA_LEN(buf)); 1595 if (!tx_mlx5_wq_tailroom(txq, 1596 (void *)((uintptr_t)mpw.data.raw 1597 + inl_pad))) 1598 dseg = (volatile void *)txq->wqes; 1599 else 1600 dseg = (volatile void *) 1601 ((uintptr_t)mpw.data.raw + 1602 inl_pad); 1603 (*txq->elts)[elts_head++ & elts_m] = buf; 1604 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, 1605 uintptr_t)); 1606 *dseg = (rte_v128u32_t) { 1607 rte_cpu_to_be_32(length), 1608 mlx5_tx_mb2mr(txq, buf), 1609 addr_64, 1610 addr_64 >> 32, 1611 }; 1612 mpw.data.raw = (volatile void *)(dseg + 1); 1613 mpw.total_len += (inl_pad + sizeof(*dseg)); 1614 ++j; 1615 ++mpw.pkts_n; 1616 mpw_room -= (inl_pad + sizeof(*dseg)); 1617 inl_pad = 0; 1618 } 1619 #ifdef MLX5_PMD_SOFT_COUNTERS 1620 /* Increment sent bytes counter. */ 1621 txq->stats.obytes += length; 1622 #endif 1623 ++i; 1624 } while (i < pkts_n); 1625 /* Take a shortcut if nothing must be sent. */ 1626 if (unlikely(i == 0)) 1627 return 0; 1628 /* Check whether completion threshold has been reached. */ 1629 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH || 1630 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >= 1631 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) { 1632 volatile struct mlx5_wqe *wqe = mpw.wqe; 1633 1634 /* A CQE slot must always be available. */ 1635 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci)); 1636 /* Request completion on last WQE. */ 1637 wqe->ctrl[2] = rte_cpu_to_be_32(8); 1638 /* Save elts_head in unused "immediate" field of WQE. */ 1639 wqe->ctrl[3] = elts_head; 1640 txq->elts_comp = 0; 1641 txq->mpw_comp = txq->wqe_ci; 1642 } else { 1643 txq->elts_comp += j; 1644 } 1645 #ifdef MLX5_PMD_SOFT_COUNTERS 1646 /* Increment sent packets counter. */ 1647 txq->stats.opackets += i; 1648 #endif 1649 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) 1650 mlx5_empw_close(txq, &mpw); 1651 /* Ring QP doorbell. */ 1652 mlx5_tx_dbrec(txq, mpw.wqe); 1653 txq->elts_head = elts_head; 1654 return i; 1655 } 1656 1657 /** 1658 * DPDK callback for TX with Enhanced MPW support. 1659 * 1660 * @param dpdk_txq 1661 * Generic pointer to TX queue structure. 1662 * @param[in] pkts 1663 * Packets to transmit. 1664 * @param pkts_n 1665 * Number of packets in array. 1666 * 1667 * @return 1668 * Number of packets successfully transmitted (<= pkts_n). 1669 */ 1670 uint16_t 1671 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) 1672 { 1673 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; 1674 uint16_t nb_tx = 0; 1675 1676 while (pkts_n > nb_tx) { 1677 uint16_t n; 1678 uint16_t ret; 1679 1680 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx); 1681 if (n) { 1682 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n); 1683 if (!ret) 1684 break; 1685 nb_tx += ret; 1686 } 1687 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx); 1688 if (n) { 1689 ret = txq_burst_empw(txq, &pkts[nb_tx], n); 1690 if (!ret) 1691 break; 1692 nb_tx += ret; 1693 } 1694 } 1695 return nb_tx; 1696 } 1697 1698 /** 1699 * Translate RX completion flags to packet type. 1700 * 1701 * @param[in] rxq 1702 * Pointer to RX queue structure. 1703 * @param[in] cqe 1704 * Pointer to CQE. 1705 * 1706 * @note: fix mlx5_dev_supported_ptypes_get() if any change here. 1707 * 1708 * @return 1709 * Packet type for struct rte_mbuf. 1710 */ 1711 static inline uint32_t 1712 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe) 1713 { 1714 uint8_t idx; 1715 uint8_t pinfo = cqe->pkt_info; 1716 uint16_t ptype = cqe->hdr_type_etc; 1717 1718 /* 1719 * The index to the array should have: 1720 * bit[1:0] = l3_hdr_type 1721 * bit[4:2] = l4_hdr_type 1722 * bit[5] = ip_frag 1723 * bit[6] = tunneled 1724 * bit[7] = outer_l3_type 1725 */ 1726 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10); 1727 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6)); 1728 } 1729 1730 /** 1731 * Get size of the next packet for a given CQE. For compressed CQEs, the 1732 * consumer index is updated only once all packets of the current one have 1733 * been processed. 1734 * 1735 * @param rxq 1736 * Pointer to RX queue. 1737 * @param cqe 1738 * CQE to process. 1739 * @param[out] mcqe 1740 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not 1741 * written. 1742 * 1743 * @return 1744 * Packet size in bytes (0 if there is none), -1 in case of completion 1745 * with error. 1746 */ 1747 static inline int 1748 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe, 1749 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe) 1750 { 1751 struct rxq_zip *zip = &rxq->zip; 1752 uint16_t cqe_n = cqe_cnt + 1; 1753 int len = 0; 1754 uint16_t idx, end; 1755 1756 /* Process compressed data in the CQE and mini arrays. */ 1757 if (zip->ai) { 1758 volatile struct mlx5_mini_cqe8 (*mc)[8] = 1759 (volatile struct mlx5_mini_cqe8 (*)[8]) 1760 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info); 1761 1762 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt); 1763 *mcqe = &(*mc)[zip->ai & 7]; 1764 if ((++zip->ai & 7) == 0) { 1765 /* Invalidate consumed CQEs */ 1766 idx = zip->ca; 1767 end = zip->na; 1768 while (idx != end) { 1769 (*rxq->cqes)[idx & cqe_cnt].op_own = 1770 MLX5_CQE_INVALIDATE; 1771 ++idx; 1772 } 1773 /* 1774 * Increment consumer index to skip the number of 1775 * CQEs consumed. Hardware leaves holes in the CQ 1776 * ring for software use. 1777 */ 1778 zip->ca = zip->na; 1779 zip->na += 8; 1780 } 1781 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) { 1782 /* Invalidate the rest */ 1783 idx = zip->ca; 1784 end = zip->cq_ci; 1785 1786 while (idx != end) { 1787 (*rxq->cqes)[idx & cqe_cnt].op_own = 1788 MLX5_CQE_INVALIDATE; 1789 ++idx; 1790 } 1791 rxq->cq_ci = zip->cq_ci; 1792 zip->ai = 0; 1793 } 1794 /* No compressed data, get next CQE and verify if it is compressed. */ 1795 } else { 1796 int ret; 1797 int8_t op_own; 1798 1799 ret = check_cqe(cqe, cqe_n, rxq->cq_ci); 1800 if (unlikely(ret == 1)) 1801 return 0; 1802 ++rxq->cq_ci; 1803 op_own = cqe->op_own; 1804 rte_cio_rmb(); 1805 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) { 1806 volatile struct mlx5_mini_cqe8 (*mc)[8] = 1807 (volatile struct mlx5_mini_cqe8 (*)[8]) 1808 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci & 1809 cqe_cnt].pkt_info); 1810 1811 /* Fix endianness. */ 1812 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt); 1813 /* 1814 * Current mini array position is the one returned by 1815 * check_cqe64(). 1816 * 1817 * If completion comprises several mini arrays, as a 1818 * special case the second one is located 7 CQEs after 1819 * the initial CQE instead of 8 for subsequent ones. 1820 */ 1821 zip->ca = rxq->cq_ci; 1822 zip->na = zip->ca + 7; 1823 /* Compute the next non compressed CQE. */ 1824 --rxq->cq_ci; 1825 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt; 1826 /* Get packet size to return. */ 1827 len = rte_be_to_cpu_32((*mc)[0].byte_cnt); 1828 *mcqe = &(*mc)[0]; 1829 zip->ai = 1; 1830 /* Prefetch all the entries to be invalidated */ 1831 idx = zip->ca; 1832 end = zip->cq_ci; 1833 while (idx != end) { 1834 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]); 1835 ++idx; 1836 } 1837 } else { 1838 len = rte_be_to_cpu_32(cqe->byte_cnt); 1839 } 1840 /* Error while receiving packet. */ 1841 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR)) 1842 return -1; 1843 } 1844 return len; 1845 } 1846 1847 /** 1848 * Translate RX completion flags to offload flags. 1849 * 1850 * @param[in] cqe 1851 * Pointer to CQE. 1852 * 1853 * @return 1854 * Offload flags (ol_flags) for struct rte_mbuf. 1855 */ 1856 static inline uint32_t 1857 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe) 1858 { 1859 uint32_t ol_flags = 0; 1860 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc); 1861 1862 ol_flags = 1863 TRANSPOSE(flags, 1864 MLX5_CQE_RX_L3_HDR_VALID, 1865 PKT_RX_IP_CKSUM_GOOD) | 1866 TRANSPOSE(flags, 1867 MLX5_CQE_RX_L4_HDR_VALID, 1868 PKT_RX_L4_CKSUM_GOOD); 1869 return ol_flags; 1870 } 1871 1872 /** 1873 * Fill in mbuf fields from RX completion flags. 1874 * Note that pkt->ol_flags should be initialized outside of this function. 1875 * 1876 * @param rxq 1877 * Pointer to RX queue. 1878 * @param pkt 1879 * mbuf to fill. 1880 * @param cqe 1881 * CQE to process. 1882 * @param rss_hash_res 1883 * Packet RSS Hash result. 1884 */ 1885 static inline void 1886 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, 1887 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res) 1888 { 1889 /* Update packet information. */ 1890 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe); 1891 if (rss_hash_res && rxq->rss_hash) { 1892 pkt->hash.rss = rss_hash_res; 1893 pkt->ol_flags |= PKT_RX_RSS_HASH; 1894 } 1895 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) { 1896 pkt->ol_flags |= PKT_RX_FDIR; 1897 if (cqe->sop_drop_qpn != 1898 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) { 1899 uint32_t mark = cqe->sop_drop_qpn; 1900 1901 pkt->ol_flags |= PKT_RX_FDIR_ID; 1902 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark); 1903 } 1904 } 1905 if (rxq->csum) 1906 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe); 1907 if (rxq->vlan_strip && 1908 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) { 1909 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1910 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info); 1911 } 1912 if (rxq->hw_timestamp) { 1913 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp); 1914 pkt->ol_flags |= PKT_RX_TIMESTAMP; 1915 } 1916 } 1917 1918 /** 1919 * DPDK callback for RX. 1920 * 1921 * @param dpdk_rxq 1922 * Generic pointer to RX queue structure. 1923 * @param[out] pkts 1924 * Array to store received packets. 1925 * @param pkts_n 1926 * Maximum number of packets in array. 1927 * 1928 * @return 1929 * Number of packets successfully received (<= pkts_n). 1930 */ 1931 uint16_t 1932 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n) 1933 { 1934 struct mlx5_rxq_data *rxq = dpdk_rxq; 1935 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1; 1936 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1; 1937 const unsigned int sges_n = rxq->sges_n; 1938 struct rte_mbuf *pkt = NULL; 1939 struct rte_mbuf *seg = NULL; 1940 volatile struct mlx5_cqe *cqe = 1941 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt]; 1942 unsigned int i = 0; 1943 unsigned int rq_ci = rxq->rq_ci << sges_n; 1944 int len = 0; /* keep its value across iterations. */ 1945 1946 while (pkts_n) { 1947 unsigned int idx = rq_ci & wqe_cnt; 1948 volatile struct mlx5_wqe_data_seg *wqe = 1949 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx]; 1950 struct rte_mbuf *rep = (*rxq->elts)[idx]; 1951 volatile struct mlx5_mini_cqe8 *mcqe = NULL; 1952 uint32_t rss_hash_res; 1953 1954 if (pkt) 1955 NEXT(seg) = rep; 1956 seg = rep; 1957 rte_prefetch0(seg); 1958 rte_prefetch0(cqe); 1959 rte_prefetch0(wqe); 1960 rep = rte_mbuf_raw_alloc(rxq->mp); 1961 if (unlikely(rep == NULL)) { 1962 ++rxq->stats.rx_nombuf; 1963 if (!pkt) { 1964 /* 1965 * no buffers before we even started, 1966 * bail out silently. 1967 */ 1968 break; 1969 } 1970 while (pkt != seg) { 1971 assert(pkt != (*rxq->elts)[idx]); 1972 rep = NEXT(pkt); 1973 NEXT(pkt) = NULL; 1974 NB_SEGS(pkt) = 1; 1975 rte_mbuf_raw_free(pkt); 1976 pkt = rep; 1977 } 1978 break; 1979 } 1980 if (!pkt) { 1981 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt]; 1982 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe); 1983 if (!len) { 1984 rte_mbuf_raw_free(rep); 1985 break; 1986 } 1987 if (unlikely(len == -1)) { 1988 /* RX error, packet is likely too large. */ 1989 rte_mbuf_raw_free(rep); 1990 ++rxq->stats.idropped; 1991 goto skip; 1992 } 1993 pkt = seg; 1994 assert(len >= (rxq->crc_present << 2)); 1995 pkt->ol_flags = 0; 1996 /* If compressed, take hash result from mini-CQE. */ 1997 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ? 1998 cqe->rx_hash_res : 1999 mcqe->rx_hash_result); 2000 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res); 2001 if (rxq->crc_present) 2002 len -= ETHER_CRC_LEN; 2003 PKT_LEN(pkt) = len; 2004 } 2005 DATA_LEN(rep) = DATA_LEN(seg); 2006 PKT_LEN(rep) = PKT_LEN(seg); 2007 SET_DATA_OFF(rep, DATA_OFF(seg)); 2008 PORT(rep) = PORT(seg); 2009 (*rxq->elts)[idx] = rep; 2010 /* 2011 * Fill NIC descriptor with the new buffer. The lkey and size 2012 * of the buffers are already known, only the buffer address 2013 * changes. 2014 */ 2015 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t)); 2016 /* If there's only one MR, no need to replace LKey in WQE. */ 2017 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1)) 2018 wqe->lkey = mlx5_rx_mb2mr(rxq, rep); 2019 if (len > DATA_LEN(seg)) { 2020 len -= DATA_LEN(seg); 2021 ++NB_SEGS(pkt); 2022 ++rq_ci; 2023 continue; 2024 } 2025 DATA_LEN(seg) = len; 2026 #ifdef MLX5_PMD_SOFT_COUNTERS 2027 /* Increment bytes counter. */ 2028 rxq->stats.ibytes += PKT_LEN(pkt); 2029 #endif 2030 /* Return packet. */ 2031 *(pkts++) = pkt; 2032 pkt = NULL; 2033 --pkts_n; 2034 ++i; 2035 skip: 2036 /* Align consumer index to the next stride. */ 2037 rq_ci >>= sges_n; 2038 ++rq_ci; 2039 rq_ci <<= sges_n; 2040 } 2041 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci))) 2042 return 0; 2043 /* Update the consumer index. */ 2044 rxq->rq_ci = rq_ci >> sges_n; 2045 rte_cio_wmb(); 2046 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 2047 rte_cio_wmb(); 2048 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci); 2049 #ifdef MLX5_PMD_SOFT_COUNTERS 2050 /* Increment packets counter. */ 2051 rxq->stats.ipackets += i; 2052 #endif 2053 return i; 2054 } 2055 2056 void 2057 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque) 2058 { 2059 struct mlx5_mprq_buf *buf = opaque; 2060 2061 if (rte_atomic16_read(&buf->refcnt) == 1) { 2062 rte_mempool_put(buf->mp, buf); 2063 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) { 2064 rte_atomic16_set(&buf->refcnt, 1); 2065 rte_mempool_put(buf->mp, buf); 2066 } 2067 } 2068 2069 void 2070 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf) 2071 { 2072 mlx5_mprq_buf_free_cb(NULL, buf); 2073 } 2074 2075 static inline void 2076 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx) 2077 { 2078 struct mlx5_mprq_buf *rep = rxq->mprq_repl; 2079 volatile struct mlx5_wqe_data_seg *wqe = 2080 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg; 2081 void *addr; 2082 2083 assert(rep != NULL); 2084 /* Replace MPRQ buf. */ 2085 (*rxq->mprq_bufs)[rq_idx] = rep; 2086 /* Replace WQE. */ 2087 addr = mlx5_mprq_buf_addr(rep); 2088 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr); 2089 /* If there's only one MR, no need to replace LKey in WQE. */ 2090 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1)) 2091 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr); 2092 /* Stash a mbuf for next replacement. */ 2093 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep))) 2094 rxq->mprq_repl = rep; 2095 else 2096 rxq->mprq_repl = NULL; 2097 } 2098 2099 /** 2100 * DPDK callback for RX with Multi-Packet RQ support. 2101 * 2102 * @param dpdk_rxq 2103 * Generic pointer to RX queue structure. 2104 * @param[out] pkts 2105 * Array to store received packets. 2106 * @param pkts_n 2107 * Maximum number of packets in array. 2108 * 2109 * @return 2110 * Number of packets successfully received (<= pkts_n). 2111 */ 2112 uint16_t 2113 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n) 2114 { 2115 struct mlx5_rxq_data *rxq = dpdk_rxq; 2116 const unsigned int strd_n = 1 << rxq->strd_num_n; 2117 const unsigned int strd_sz = 1 << rxq->strd_sz_n; 2118 const unsigned int strd_shift = 2119 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en; 2120 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1; 2121 const unsigned int wq_mask = (1 << rxq->elts_n) - 1; 2122 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask]; 2123 unsigned int i = 0; 2124 uint32_t rq_ci = rxq->rq_ci; 2125 uint16_t consumed_strd = rxq->consumed_strd; 2126 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask]; 2127 2128 while (i < pkts_n) { 2129 struct rte_mbuf *pkt; 2130 void *addr; 2131 int ret; 2132 unsigned int len; 2133 uint16_t strd_cnt; 2134 uint16_t strd_idx; 2135 uint32_t offset; 2136 uint32_t byte_cnt; 2137 volatile struct mlx5_mini_cqe8 *mcqe = NULL; 2138 uint32_t rss_hash_res = 0; 2139 2140 if (consumed_strd == strd_n) { 2141 /* Replace WQE only if the buffer is still in use. */ 2142 if (rte_atomic16_read(&buf->refcnt) > 1) { 2143 mprq_buf_replace(rxq, rq_ci & wq_mask); 2144 /* Release the old buffer. */ 2145 mlx5_mprq_buf_free(buf); 2146 } else if (unlikely(rxq->mprq_repl == NULL)) { 2147 struct mlx5_mprq_buf *rep; 2148 2149 /* 2150 * Currently, the MPRQ mempool is out of buffer 2151 * and doing memcpy regardless of the size of Rx 2152 * packet. Retry allocation to get back to 2153 * normal. 2154 */ 2155 if (!rte_mempool_get(rxq->mprq_mp, 2156 (void **)&rep)) 2157 rxq->mprq_repl = rep; 2158 } 2159 /* Advance to the next WQE. */ 2160 consumed_strd = 0; 2161 ++rq_ci; 2162 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask]; 2163 } 2164 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask]; 2165 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe); 2166 if (!ret) 2167 break; 2168 if (unlikely(ret == -1)) { 2169 /* RX error, packet is likely too large. */ 2170 ++rxq->stats.idropped; 2171 continue; 2172 } 2173 byte_cnt = ret; 2174 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >> 2175 MLX5_MPRQ_STRIDE_NUM_SHIFT; 2176 assert(strd_cnt); 2177 consumed_strd += strd_cnt; 2178 if (byte_cnt & MLX5_MPRQ_FILLER_MASK) 2179 continue; 2180 if (mcqe == NULL) { 2181 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res); 2182 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter); 2183 } else { 2184 /* mini-CQE for MPRQ doesn't have hash result. */ 2185 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx); 2186 } 2187 assert(strd_idx < strd_n); 2188 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask)); 2189 /* 2190 * Currently configured to receive a packet per a stride. But if 2191 * MTU is adjusted through kernel interface, device could 2192 * consume multiple strides without raising an error. In this 2193 * case, the packet should be dropped because it is bigger than 2194 * the max_rx_pkt_len. 2195 */ 2196 if (unlikely(strd_cnt > 1)) { 2197 ++rxq->stats.idropped; 2198 continue; 2199 } 2200 pkt = rte_pktmbuf_alloc(rxq->mp); 2201 if (unlikely(pkt == NULL)) { 2202 ++rxq->stats.rx_nombuf; 2203 break; 2204 } 2205 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT; 2206 assert((int)len >= (rxq->crc_present << 2)); 2207 if (rxq->crc_present) 2208 len -= ETHER_CRC_LEN; 2209 offset = strd_idx * strd_sz + strd_shift; 2210 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset); 2211 /* Initialize the offload flag. */ 2212 pkt->ol_flags = 0; 2213 /* 2214 * Memcpy packets to the target mbuf if: 2215 * - The size of packet is smaller than mprq_max_memcpy_len. 2216 * - Out of buffer in the Mempool for Multi-Packet RQ. 2217 */ 2218 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) { 2219 /* 2220 * When memcpy'ing packet due to out-of-buffer, the 2221 * packet must be smaller than the target mbuf. 2222 */ 2223 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) { 2224 rte_pktmbuf_free_seg(pkt); 2225 ++rxq->stats.idropped; 2226 continue; 2227 } 2228 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len); 2229 } else { 2230 rte_iova_t buf_iova; 2231 struct rte_mbuf_ext_shared_info *shinfo; 2232 uint16_t buf_len = strd_cnt * strd_sz; 2233 2234 /* Increment the refcnt of the whole chunk. */ 2235 rte_atomic16_add_return(&buf->refcnt, 1); 2236 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <= 2237 strd_n + 1); 2238 addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM); 2239 /* 2240 * MLX5 device doesn't use iova but it is necessary in a 2241 * case where the Rx packet is transmitted via a 2242 * different PMD. 2243 */ 2244 buf_iova = rte_mempool_virt2iova(buf) + 2245 RTE_PTR_DIFF(addr, buf); 2246 shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr, 2247 &buf_len, mlx5_mprq_buf_free_cb, buf); 2248 /* 2249 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when 2250 * attaching the stride to mbuf and more offload flags 2251 * will be added below by calling rxq_cq_to_mbuf(). 2252 * Other fields will be overwritten. 2253 */ 2254 rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len, 2255 shinfo); 2256 rte_pktmbuf_reset_headroom(pkt); 2257 assert(pkt->ol_flags == EXT_ATTACHED_MBUF); 2258 /* 2259 * Prevent potential overflow due to MTU change through 2260 * kernel interface. 2261 */ 2262 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) { 2263 rte_pktmbuf_free_seg(pkt); 2264 ++rxq->stats.idropped; 2265 continue; 2266 } 2267 } 2268 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res); 2269 PKT_LEN(pkt) = len; 2270 DATA_LEN(pkt) = len; 2271 PORT(pkt) = rxq->port_id; 2272 #ifdef MLX5_PMD_SOFT_COUNTERS 2273 /* Increment bytes counter. */ 2274 rxq->stats.ibytes += PKT_LEN(pkt); 2275 #endif 2276 /* Return packet. */ 2277 *(pkts++) = pkt; 2278 ++i; 2279 } 2280 /* Update the consumer indexes. */ 2281 rxq->consumed_strd = consumed_strd; 2282 rte_cio_wmb(); 2283 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 2284 if (rq_ci != rxq->rq_ci) { 2285 rxq->rq_ci = rq_ci; 2286 rte_cio_wmb(); 2287 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci); 2288 } 2289 #ifdef MLX5_PMD_SOFT_COUNTERS 2290 /* Increment packets counter. */ 2291 rxq->stats.ipackets += i; 2292 #endif 2293 return i; 2294 } 2295 2296 /** 2297 * Dummy DPDK callback for TX. 2298 * 2299 * This function is used to temporarily replace the real callback during 2300 * unsafe control operations on the queue, or in case of error. 2301 * 2302 * @param dpdk_txq 2303 * Generic pointer to TX queue structure. 2304 * @param[in] pkts 2305 * Packets to transmit. 2306 * @param pkts_n 2307 * Number of packets in array. 2308 * 2309 * @return 2310 * Number of packets successfully transmitted (<= pkts_n). 2311 */ 2312 uint16_t 2313 removed_tx_burst(void *dpdk_txq __rte_unused, 2314 struct rte_mbuf **pkts __rte_unused, 2315 uint16_t pkts_n __rte_unused) 2316 { 2317 return 0; 2318 } 2319 2320 /** 2321 * Dummy DPDK callback for RX. 2322 * 2323 * This function is used to temporarily replace the real callback during 2324 * unsafe control operations on the queue, or in case of error. 2325 * 2326 * @param dpdk_rxq 2327 * Generic pointer to RX queue structure. 2328 * @param[out] pkts 2329 * Array to store received packets. 2330 * @param pkts_n 2331 * Maximum number of packets in array. 2332 * 2333 * @return 2334 * Number of packets successfully received (<= pkts_n). 2335 */ 2336 uint16_t 2337 removed_rx_burst(void *dpdk_txq __rte_unused, 2338 struct rte_mbuf **pkts __rte_unused, 2339 uint16_t pkts_n __rte_unused) 2340 { 2341 return 0; 2342 } 2343 2344 /* 2345 * Vectorized Rx/Tx routines are not compiled in when required vector 2346 * instructions are not supported on a target architecture. The following null 2347 * stubs are needed for linkage when those are not included outside of this file 2348 * (e.g. mlx5_rxtx_vec_sse.c for x86). 2349 */ 2350 2351 __rte_weak uint16_t 2352 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused, 2353 struct rte_mbuf **pkts __rte_unused, 2354 uint16_t pkts_n __rte_unused) 2355 { 2356 return 0; 2357 } 2358 2359 __rte_weak uint16_t 2360 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused, 2361 struct rte_mbuf **pkts __rte_unused, 2362 uint16_t pkts_n __rte_unused) 2363 { 2364 return 0; 2365 } 2366 2367 __rte_weak uint16_t 2368 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused, 2369 struct rte_mbuf **pkts __rte_unused, 2370 uint16_t pkts_n __rte_unused) 2371 { 2372 return 0; 2373 } 2374 2375 __rte_weak int 2376 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused) 2377 { 2378 return -ENOTSUP; 2379 } 2380 2381 __rte_weak int 2382 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused) 2383 { 2384 return -ENOTSUP; 2385 } 2386 2387 __rte_weak int 2388 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused) 2389 { 2390 return -ENOTSUP; 2391 } 2392 2393 __rte_weak int 2394 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused) 2395 { 2396 return -ENOTSUP; 2397 } 2398