1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <errno.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <fcntl.h> 11 #include <sys/queue.h> 12 13 #include <rte_mbuf.h> 14 #include <rte_malloc.h> 15 #include <ethdev_driver.h> 16 #include <rte_common.h> 17 #include <rte_interrupts.h> 18 #include <rte_debug.h> 19 #include <rte_io.h> 20 #include <rte_eal_paging.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_malloc.h> 24 #include <mlx5_common.h> 25 #include <mlx5_common_mr.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_rx.h" 30 #include "mlx5_utils.h" 31 #include "mlx5_autoconf.h" 32 #include "mlx5_devx.h" 33 34 35 /* Default RSS hash key also used for ConnectX-3. */ 36 uint8_t rss_hash_default_key[] = { 37 0x2c, 0xc6, 0x81, 0xd1, 38 0x5b, 0xdb, 0xf4, 0xf7, 39 0xfc, 0xa2, 0x83, 0x19, 40 0xdb, 0x1a, 0x3e, 0x94, 41 0x6b, 0x9e, 0x38, 0xd9, 42 0x2c, 0x9c, 0x03, 0xd1, 43 0xad, 0x99, 0x44, 0xa7, 44 0xd9, 0x56, 0x3d, 0x59, 45 0x06, 0x3c, 0x25, 0xf3, 46 0xfc, 0x1f, 0xdc, 0x2a, 47 }; 48 49 /* Length of the default RSS hash key. */ 50 static_assert(MLX5_RSS_HASH_KEY_LEN == 51 (unsigned int)sizeof(rss_hash_default_key), 52 "wrong RSS default key size."); 53 54 /** 55 * Calculate the number of CQEs in CQ for the Rx queue. 56 * 57 * @param rxq_data 58 * Pointer to receive queue structure. 59 * 60 * @return 61 * Number of CQEs in CQ. 62 */ 63 unsigned int 64 mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data) 65 { 66 unsigned int cqe_n; 67 unsigned int wqe_n = 1 << rxq_data->elts_n; 68 69 if (mlx5_rxq_mprq_enabled(rxq_data)) 70 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1; 71 else 72 cqe_n = wqe_n - 1; 73 return cqe_n; 74 } 75 76 /** 77 * Allocate RX queue elements for Multi-Packet RQ. 78 * 79 * @param rxq_ctrl 80 * Pointer to RX queue structure. 81 * 82 * @return 83 * 0 on success, a negative errno value otherwise and rte_errno is set. 84 */ 85 static int 86 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl) 87 { 88 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq; 89 unsigned int wqe_n = 1 << rxq->elts_n; 90 unsigned int i; 91 int err; 92 93 /* Iterate on segments. */ 94 for (i = 0; i <= wqe_n; ++i) { 95 struct mlx5_mprq_buf *buf; 96 97 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) { 98 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id); 99 rte_errno = ENOMEM; 100 goto error; 101 } 102 if (i < wqe_n) 103 (*rxq->mprq_bufs)[i] = buf; 104 else 105 rxq->mprq_repl = buf; 106 } 107 DRV_LOG(DEBUG, 108 "port %u MPRQ queue %u allocated and configured %u segments", 109 rxq->port_id, rxq->idx, wqe_n); 110 return 0; 111 error: 112 err = rte_errno; /* Save rte_errno before cleanup. */ 113 wqe_n = i; 114 for (i = 0; (i != wqe_n); ++i) { 115 if ((*rxq->mprq_bufs)[i] != NULL) 116 rte_mempool_put(rxq->mprq_mp, 117 (*rxq->mprq_bufs)[i]); 118 (*rxq->mprq_bufs)[i] = NULL; 119 } 120 DRV_LOG(DEBUG, "port %u MPRQ queue %u failed, freed everything", 121 rxq->port_id, rxq->idx); 122 rte_errno = err; /* Restore rte_errno. */ 123 return -rte_errno; 124 } 125 126 /** 127 * Allocate RX queue elements for Single-Packet RQ. 128 * 129 * @param rxq_ctrl 130 * Pointer to RX queue structure. 131 * 132 * @return 133 * 0 on success, negative errno value on failure. 134 */ 135 static int 136 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl) 137 { 138 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n; 139 unsigned int elts_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ? 140 (1 << rxq_ctrl->rxq.elts_n) * (1 << rxq_ctrl->rxq.strd_num_n) : 141 (1 << rxq_ctrl->rxq.elts_n); 142 unsigned int i; 143 int err; 144 145 /* Iterate on segments. */ 146 for (i = 0; (i != elts_n); ++i) { 147 struct mlx5_eth_rxseg *seg = &rxq_ctrl->rxq.rxseg[i % sges_n]; 148 struct rte_mbuf *buf; 149 150 buf = rte_pktmbuf_alloc(seg->mp); 151 if (buf == NULL) { 152 if (rxq_ctrl->share_group == 0) 153 DRV_LOG(ERR, "port %u queue %u empty mbuf pool", 154 RXQ_PORT_ID(rxq_ctrl), 155 rxq_ctrl->rxq.idx); 156 else 157 DRV_LOG(ERR, "share group %u queue %u empty mbuf pool", 158 rxq_ctrl->share_group, 159 rxq_ctrl->share_qid); 160 rte_errno = ENOMEM; 161 goto error; 162 } 163 /* Headroom is reserved by rte_pktmbuf_alloc(). */ 164 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM); 165 /* Buffer is supposed to be empty. */ 166 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0); 167 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0); 168 MLX5_ASSERT(!buf->next); 169 SET_DATA_OFF(buf, seg->offset); 170 PORT(buf) = rxq_ctrl->rxq.port_id; 171 DATA_LEN(buf) = seg->length; 172 PKT_LEN(buf) = seg->length; 173 NB_SEGS(buf) = 1; 174 (*rxq_ctrl->rxq.elts)[i] = buf; 175 } 176 /* If Rx vector is activated. */ 177 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) { 178 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq; 179 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf; 180 struct rte_pktmbuf_pool_private *priv = 181 (struct rte_pktmbuf_pool_private *) 182 rte_mempool_get_priv(rxq_ctrl->rxq.mp); 183 int j; 184 185 /* Initialize default rearm_data for vPMD. */ 186 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM; 187 rte_mbuf_refcnt_set(mbuf_init, 1); 188 mbuf_init->nb_segs = 1; 189 /* For shared queues port is provided in CQE */ 190 mbuf_init->port = rxq->shared ? 0 : rxq->port_id; 191 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) 192 mbuf_init->ol_flags = RTE_MBUF_F_EXTERNAL; 193 /* 194 * prevent compiler reordering: 195 * rearm_data covers previous fields. 196 */ 197 rte_compiler_barrier(); 198 rxq->mbuf_initializer = 199 *(rte_xmm_t *)&mbuf_init->rearm_data; 200 /* Padding with a fake mbuf for vectorized Rx. */ 201 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j) 202 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf; 203 } 204 if (rxq_ctrl->share_group == 0) 205 DRV_LOG(DEBUG, 206 "port %u SPRQ queue %u allocated and configured %u segments (max %u packets)", 207 RXQ_PORT_ID(rxq_ctrl), rxq_ctrl->rxq.idx, elts_n, 208 elts_n / (1 << rxq_ctrl->rxq.sges_n)); 209 else 210 DRV_LOG(DEBUG, 211 "share group %u SPRQ queue %u allocated and configured %u segments (max %u packets)", 212 rxq_ctrl->share_group, rxq_ctrl->share_qid, elts_n, 213 elts_n / (1 << rxq_ctrl->rxq.sges_n)); 214 return 0; 215 error: 216 err = rte_errno; /* Save rte_errno before cleanup. */ 217 elts_n = i; 218 for (i = 0; (i != elts_n); ++i) { 219 if ((*rxq_ctrl->rxq.elts)[i] != NULL) 220 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]); 221 (*rxq_ctrl->rxq.elts)[i] = NULL; 222 } 223 if (rxq_ctrl->share_group == 0) 224 DRV_LOG(DEBUG, "port %u SPRQ queue %u failed, freed everything", 225 RXQ_PORT_ID(rxq_ctrl), rxq_ctrl->rxq.idx); 226 else 227 DRV_LOG(DEBUG, "share group %u SPRQ queue %u failed, freed everything", 228 rxq_ctrl->share_group, rxq_ctrl->share_qid); 229 rte_errno = err; /* Restore rte_errno. */ 230 return -rte_errno; 231 } 232 233 /** 234 * Allocate RX queue elements. 235 * 236 * @param rxq_ctrl 237 * Pointer to RX queue structure. 238 * 239 * @return 240 * 0 on success, negative errno value on failure. 241 */ 242 int 243 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl) 244 { 245 int ret = 0; 246 247 /** 248 * For MPRQ we need to allocate both MPRQ buffers 249 * for WQEs and simple mbufs for vector processing. 250 */ 251 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) 252 ret = rxq_alloc_elts_mprq(rxq_ctrl); 253 if (ret == 0) 254 ret = rxq_alloc_elts_sprq(rxq_ctrl); 255 return ret; 256 } 257 258 /** 259 * Free RX queue elements for Multi-Packet RQ. 260 * 261 * @param rxq_ctrl 262 * Pointer to RX queue structure. 263 */ 264 static void 265 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl) 266 { 267 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq; 268 uint16_t i; 269 270 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing %d WRs", 271 rxq->port_id, rxq->idx, (1u << rxq->elts_n)); 272 if (rxq->mprq_bufs == NULL) 273 return; 274 for (i = 0; (i != (1u << rxq->elts_n)); ++i) { 275 if ((*rxq->mprq_bufs)[i] != NULL) 276 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]); 277 (*rxq->mprq_bufs)[i] = NULL; 278 } 279 if (rxq->mprq_repl != NULL) { 280 mlx5_mprq_buf_free(rxq->mprq_repl); 281 rxq->mprq_repl = NULL; 282 } 283 } 284 285 /** 286 * Free RX queue elements for Single-Packet RQ. 287 * 288 * @param rxq_ctrl 289 * Pointer to RX queue structure. 290 */ 291 static void 292 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl) 293 { 294 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq; 295 const uint16_t q_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ? 296 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) : 297 (1 << rxq->elts_n); 298 const uint16_t q_mask = q_n - 1; 299 uint16_t elts_ci = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ? 300 rxq->elts_ci : rxq->rq_ci; 301 uint16_t used = q_n - (elts_ci - rxq->rq_pi); 302 uint16_t i; 303 304 if (rxq_ctrl->share_group == 0) 305 DRV_LOG(DEBUG, "port %u Rx queue %u freeing %d WRs", 306 RXQ_PORT_ID(rxq_ctrl), rxq->idx, q_n); 307 else 308 DRV_LOG(DEBUG, "share group %u Rx queue %u freeing %d WRs", 309 rxq_ctrl->share_group, rxq_ctrl->share_qid, q_n); 310 if (rxq->elts == NULL) 311 return; 312 /** 313 * Some mbuf in the Ring belongs to the application. 314 * They cannot be freed. 315 */ 316 if (mlx5_rxq_check_vec_support(rxq) > 0) { 317 for (i = 0; i < used; ++i) 318 (*rxq->elts)[(elts_ci + i) & q_mask] = NULL; 319 rxq->rq_pi = elts_ci; 320 } 321 for (i = 0; i != q_n; ++i) { 322 if ((*rxq->elts)[i] != NULL) 323 rte_pktmbuf_free_seg((*rxq->elts)[i]); 324 (*rxq->elts)[i] = NULL; 325 } 326 } 327 328 /** 329 * Free RX queue elements. 330 * 331 * @param rxq_ctrl 332 * Pointer to RX queue structure. 333 */ 334 static void 335 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl) 336 { 337 /* 338 * For MPRQ we need to allocate both MPRQ buffers 339 * for WQEs and simple mbufs for vector processing. 340 */ 341 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) 342 rxq_free_elts_mprq(rxq_ctrl); 343 rxq_free_elts_sprq(rxq_ctrl); 344 } 345 346 /** 347 * Returns the per-queue supported offloads. 348 * 349 * @param dev 350 * Pointer to Ethernet device. 351 * 352 * @return 353 * Supported Rx offloads. 354 */ 355 uint64_t 356 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev) 357 { 358 struct mlx5_priv *priv = dev->data->dev_private; 359 struct mlx5_dev_config *config = &priv->config; 360 uint64_t offloads = (RTE_ETH_RX_OFFLOAD_SCATTER | 361 RTE_ETH_RX_OFFLOAD_TIMESTAMP | 362 RTE_ETH_RX_OFFLOAD_RSS_HASH); 363 364 if (!config->mprq.enabled) 365 offloads |= RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT; 366 if (config->hw_fcs_strip) 367 offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC; 368 if (config->hw_csum) 369 offloads |= (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 370 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 371 RTE_ETH_RX_OFFLOAD_TCP_CKSUM); 372 if (config->hw_vlan_strip) 373 offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 374 if (MLX5_LRO_SUPPORTED(dev)) 375 offloads |= RTE_ETH_RX_OFFLOAD_TCP_LRO; 376 return offloads; 377 } 378 379 380 /** 381 * Returns the per-port supported offloads. 382 * 383 * @return 384 * Supported Rx offloads. 385 */ 386 uint64_t 387 mlx5_get_rx_port_offloads(void) 388 { 389 uint64_t offloads = RTE_ETH_RX_OFFLOAD_VLAN_FILTER; 390 391 return offloads; 392 } 393 394 /** 395 * Verify if the queue can be released. 396 * 397 * @param dev 398 * Pointer to Ethernet device. 399 * @param idx 400 * RX queue index. 401 * 402 * @return 403 * 1 if the queue can be released 404 * 0 if the queue can not be released, there are references to it. 405 * Negative errno and rte_errno is set if queue doesn't exist. 406 */ 407 static int 408 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx) 409 { 410 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 411 412 if (rxq == NULL) { 413 rte_errno = EINVAL; 414 return -rte_errno; 415 } 416 return (__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED) == 1); 417 } 418 419 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */ 420 static void 421 rxq_sync_cq(struct mlx5_rxq_data *rxq) 422 { 423 const uint16_t cqe_n = 1 << rxq->cqe_n; 424 const uint16_t cqe_mask = cqe_n - 1; 425 volatile struct mlx5_cqe *cqe; 426 int ret, i; 427 428 i = cqe_n; 429 do { 430 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask]; 431 ret = check_cqe(cqe, cqe_n, rxq->cq_ci); 432 if (ret == MLX5_CQE_STATUS_HW_OWN) 433 break; 434 if (ret == MLX5_CQE_STATUS_ERR) { 435 rxq->cq_ci++; 436 continue; 437 } 438 MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN); 439 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) { 440 rxq->cq_ci++; 441 continue; 442 } 443 /* Compute the next non compressed CQE. */ 444 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt); 445 446 } while (--i); 447 /* Move all CQEs to HW ownership, including possible MiniCQEs. */ 448 for (i = 0; i < cqe_n; i++) { 449 cqe = &(*rxq->cqes)[i]; 450 cqe->op_own = MLX5_CQE_INVALIDATE; 451 } 452 /* Resync CQE and WQE (WQ in RESET state). */ 453 rte_io_wmb(); 454 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 455 rte_io_wmb(); 456 *rxq->rq_db = rte_cpu_to_be_32(0); 457 rte_io_wmb(); 458 } 459 460 /** 461 * Rx queue stop. Device queue goes to the RESET state, 462 * all involved mbufs are freed from WQ. 463 * 464 * @param dev 465 * Pointer to Ethernet device structure. 466 * @param idx 467 * RX queue index. 468 * 469 * @return 470 * 0 on success, a negative errno value otherwise and rte_errno is set. 471 */ 472 int 473 mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx) 474 { 475 struct mlx5_priv *priv = dev->data->dev_private; 476 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 477 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl; 478 int ret; 479 480 MLX5_ASSERT(rxq != NULL && rxq_ctrl != NULL); 481 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 482 ret = priv->obj_ops.rxq_obj_modify(rxq, MLX5_RXQ_MOD_RDY2RST); 483 if (ret) { 484 DRV_LOG(ERR, "Cannot change Rx WQ state to RESET: %s", 485 strerror(errno)); 486 rte_errno = errno; 487 return ret; 488 } 489 /* Remove all processes CQEs. */ 490 rxq_sync_cq(&rxq_ctrl->rxq); 491 /* Free all involved mbufs. */ 492 rxq_free_elts(rxq_ctrl); 493 /* Set the actual queue state. */ 494 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED; 495 return 0; 496 } 497 498 /** 499 * Rx queue stop. Device queue goes to the RESET state, 500 * all involved mbufs are freed from WQ. 501 * 502 * @param dev 503 * Pointer to Ethernet device structure. 504 * @param idx 505 * RX queue index. 506 * 507 * @return 508 * 0 on success, a negative errno value otherwise and rte_errno is set. 509 */ 510 int 511 mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx) 512 { 513 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 514 int ret; 515 516 if (rte_eth_dev_is_rx_hairpin_queue(dev, idx)) { 517 DRV_LOG(ERR, "Hairpin queue can't be stopped"); 518 rte_errno = EINVAL; 519 return -EINVAL; 520 } 521 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED) 522 return 0; 523 /* 524 * Vectorized Rx burst requires the CQ and RQ indices 525 * synchronized, that might be broken on RQ restart 526 * and cause Rx malfunction, so queue stopping is 527 * not supported if vectorized Rx burst is engaged. 528 * The routine pointer depends on the process 529 * type, should perform check there. 530 */ 531 if (pkt_burst == mlx5_rx_burst_vec) { 532 DRV_LOG(ERR, "Rx queue stop is not supported " 533 "for vectorized Rx"); 534 rte_errno = EINVAL; 535 return -EINVAL; 536 } 537 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 538 ret = mlx5_mp_os_req_queue_control(dev, idx, 539 MLX5_MP_REQ_QUEUE_RX_STOP); 540 } else { 541 ret = mlx5_rx_queue_stop_primary(dev, idx); 542 } 543 return ret; 544 } 545 546 /** 547 * Rx queue start. Device queue goes to the ready state, 548 * all required mbufs are allocated and WQ is replenished. 549 * 550 * @param dev 551 * Pointer to Ethernet device structure. 552 * @param idx 553 * RX queue index. 554 * 555 * @return 556 * 0 on success, a negative errno value otherwise and rte_errno is set. 557 */ 558 int 559 mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx) 560 { 561 struct mlx5_priv *priv = dev->data->dev_private; 562 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 563 struct mlx5_rxq_data *rxq_data = &rxq->ctrl->rxq; 564 int ret; 565 566 MLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL); 567 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 568 /* Allocate needed buffers. */ 569 ret = rxq_alloc_elts(rxq->ctrl); 570 if (ret) { 571 DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ"); 572 rte_errno = errno; 573 return ret; 574 } 575 rte_io_wmb(); 576 *rxq_data->cq_db = rte_cpu_to_be_32(rxq_data->cq_ci); 577 rte_io_wmb(); 578 /* Reset RQ consumer before moving queue to READY state. */ 579 *rxq_data->rq_db = rte_cpu_to_be_32(0); 580 rte_io_wmb(); 581 ret = priv->obj_ops.rxq_obj_modify(rxq, MLX5_RXQ_MOD_RST2RDY); 582 if (ret) { 583 DRV_LOG(ERR, "Cannot change Rx WQ state to READY: %s", 584 strerror(errno)); 585 rte_errno = errno; 586 return ret; 587 } 588 /* Reinitialize RQ - set WQEs. */ 589 mlx5_rxq_initialize(rxq_data); 590 rxq_data->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR; 591 /* Set actual queue state. */ 592 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED; 593 return 0; 594 } 595 596 /** 597 * Rx queue start. Device queue goes to the ready state, 598 * all required mbufs are allocated and WQ is replenished. 599 * 600 * @param dev 601 * Pointer to Ethernet device structure. 602 * @param idx 603 * RX queue index. 604 * 605 * @return 606 * 0 on success, a negative errno value otherwise and rte_errno is set. 607 */ 608 int 609 mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx) 610 { 611 int ret; 612 613 if (rte_eth_dev_is_rx_hairpin_queue(dev, idx)) { 614 DRV_LOG(ERR, "Hairpin queue can't be started"); 615 rte_errno = EINVAL; 616 return -EINVAL; 617 } 618 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED) 619 return 0; 620 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 621 ret = mlx5_mp_os_req_queue_control(dev, idx, 622 MLX5_MP_REQ_QUEUE_RX_START); 623 } else { 624 ret = mlx5_rx_queue_start_primary(dev, idx); 625 } 626 return ret; 627 } 628 629 /** 630 * Rx queue presetup checks. 631 * 632 * @param dev 633 * Pointer to Ethernet device structure. 634 * @param idx 635 * RX queue index. 636 * @param desc 637 * Number of descriptors to configure in queue. 638 * @param[out] rxq_ctrl 639 * Address of pointer to shared Rx queue control. 640 * 641 * @return 642 * 0 on success, a negative errno value otherwise and rte_errno is set. 643 */ 644 static int 645 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc, 646 struct mlx5_rxq_ctrl **rxq_ctrl) 647 { 648 struct mlx5_priv *priv = dev->data->dev_private; 649 struct mlx5_rxq_priv *rxq; 650 bool empty; 651 652 if (!rte_is_power_of_2(*desc)) { 653 *desc = 1 << log2above(*desc); 654 DRV_LOG(WARNING, 655 "port %u increased number of descriptors in Rx queue %u" 656 " to the next power of two (%d)", 657 dev->data->port_id, idx, *desc); 658 } 659 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors", 660 dev->data->port_id, idx, *desc); 661 if (idx >= priv->rxqs_n) { 662 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)", 663 dev->data->port_id, idx, priv->rxqs_n); 664 rte_errno = EOVERFLOW; 665 return -rte_errno; 666 } 667 if (rxq_ctrl == NULL || *rxq_ctrl == NULL) 668 return 0; 669 if (!(*rxq_ctrl)->rxq.shared) { 670 if (!mlx5_rxq_releasable(dev, idx)) { 671 DRV_LOG(ERR, "port %u unable to release queue index %u", 672 dev->data->port_id, idx); 673 rte_errno = EBUSY; 674 return -rte_errno; 675 } 676 mlx5_rxq_release(dev, idx); 677 } else { 678 if ((*rxq_ctrl)->obj != NULL) 679 /* Some port using shared Rx queue has been started. */ 680 return 0; 681 /* Release all owner RxQ to reconfigure Shared RxQ. */ 682 do { 683 rxq = LIST_FIRST(&(*rxq_ctrl)->owners); 684 LIST_REMOVE(rxq, owner_entry); 685 empty = LIST_EMPTY(&(*rxq_ctrl)->owners); 686 mlx5_rxq_release(ETH_DEV(rxq->priv), rxq->idx); 687 } while (!empty); 688 *rxq_ctrl = NULL; 689 } 690 return 0; 691 } 692 693 /** 694 * Get the shared Rx queue object that matches group and queue index. 695 * 696 * @param dev 697 * Pointer to Ethernet device structure. 698 * @param group 699 * Shared RXQ group. 700 * @param share_qid 701 * Shared RX queue index. 702 * 703 * @return 704 * Shared RXQ object that matching, or NULL if not found. 705 */ 706 static struct mlx5_rxq_ctrl * 707 mlx5_shared_rxq_get(struct rte_eth_dev *dev, uint32_t group, uint16_t share_qid) 708 { 709 struct mlx5_rxq_ctrl *rxq_ctrl; 710 struct mlx5_priv *priv = dev->data->dev_private; 711 712 LIST_FOREACH(rxq_ctrl, &priv->sh->shared_rxqs, share_entry) { 713 if (rxq_ctrl->share_group == group && 714 rxq_ctrl->share_qid == share_qid) 715 return rxq_ctrl; 716 } 717 return NULL; 718 } 719 720 /** 721 * Check whether requested Rx queue configuration matches shared RXQ. 722 * 723 * @param rxq_ctrl 724 * Pointer to shared RXQ. 725 * @param dev 726 * Pointer to Ethernet device structure. 727 * @param idx 728 * Queue index. 729 * @param desc 730 * Number of descriptors to configure in queue. 731 * @param socket 732 * NUMA socket on which memory must be allocated. 733 * @param[in] conf 734 * Thresholds parameters. 735 * @param mp 736 * Memory pool for buffer allocations. 737 * 738 * @return 739 * 0 on success, a negative errno value otherwise and rte_errno is set. 740 */ 741 static bool 742 mlx5_shared_rxq_match(struct mlx5_rxq_ctrl *rxq_ctrl, struct rte_eth_dev *dev, 743 uint16_t idx, uint16_t desc, unsigned int socket, 744 const struct rte_eth_rxconf *conf, 745 struct rte_mempool *mp) 746 { 747 struct mlx5_priv *spriv = LIST_FIRST(&rxq_ctrl->owners)->priv; 748 struct mlx5_priv *priv = dev->data->dev_private; 749 unsigned int i; 750 751 RTE_SET_USED(conf); 752 if (rxq_ctrl->socket != socket) { 753 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: socket mismatch", 754 dev->data->port_id, idx); 755 return false; 756 } 757 if (rxq_ctrl->rxq.elts_n != log2above(desc)) { 758 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: descriptor number mismatch", 759 dev->data->port_id, idx); 760 return false; 761 } 762 if (priv->mtu != spriv->mtu) { 763 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: mtu mismatch", 764 dev->data->port_id, idx); 765 return false; 766 } 767 if (priv->dev_data->dev_conf.intr_conf.rxq != 768 spriv->dev_data->dev_conf.intr_conf.rxq) { 769 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: interrupt mismatch", 770 dev->data->port_id, idx); 771 return false; 772 } 773 if (mp != NULL && rxq_ctrl->rxq.mp != mp) { 774 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: mempool mismatch", 775 dev->data->port_id, idx); 776 return false; 777 } else if (mp == NULL) { 778 for (i = 0; i < conf->rx_nseg; i++) { 779 if (conf->rx_seg[i].split.mp != 780 rxq_ctrl->rxq.rxseg[i].mp || 781 conf->rx_seg[i].split.length != 782 rxq_ctrl->rxq.rxseg[i].length) { 783 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: segment %u configuration mismatch", 784 dev->data->port_id, idx, i); 785 return false; 786 } 787 } 788 } 789 if (priv->config.hw_padding != spriv->config.hw_padding) { 790 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: padding mismatch", 791 dev->data->port_id, idx); 792 return false; 793 } 794 if (priv->config.cqe_comp != spriv->config.cqe_comp || 795 (priv->config.cqe_comp && 796 priv->config.cqe_comp_fmt != spriv->config.cqe_comp_fmt)) { 797 DRV_LOG(ERR, "port %u queue index %u failed to join shared group: CQE compression mismatch", 798 dev->data->port_id, idx); 799 return false; 800 } 801 return true; 802 } 803 804 /** 805 * 806 * @param dev 807 * Pointer to Ethernet device structure. 808 * @param idx 809 * RX queue index. 810 * @param desc 811 * Number of descriptors to configure in queue. 812 * @param socket 813 * NUMA socket on which memory must be allocated. 814 * @param[in] conf 815 * Thresholds parameters. 816 * @param mp 817 * Memory pool for buffer allocations. 818 * 819 * @return 820 * 0 on success, a negative errno value otherwise and rte_errno is set. 821 */ 822 int 823 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 824 unsigned int socket, const struct rte_eth_rxconf *conf, 825 struct rte_mempool *mp) 826 { 827 struct mlx5_priv *priv = dev->data->dev_private; 828 struct mlx5_rxq_priv *rxq; 829 struct mlx5_rxq_ctrl *rxq_ctrl = NULL; 830 struct rte_eth_rxseg_split *rx_seg = 831 (struct rte_eth_rxseg_split *)conf->rx_seg; 832 struct rte_eth_rxseg_split rx_single = {.mp = mp}; 833 uint16_t n_seg = conf->rx_nseg; 834 int res; 835 uint64_t offloads = conf->offloads | 836 dev->data->dev_conf.rxmode.offloads; 837 838 if (mp) { 839 /* 840 * The parameters should be checked on rte_eth_dev layer. 841 * If mp is specified it means the compatible configuration 842 * without buffer split feature tuning. 843 */ 844 rx_seg = &rx_single; 845 n_seg = 1; 846 } 847 if (n_seg > 1) { 848 /* The offloads should be checked on rte_eth_dev layer. */ 849 MLX5_ASSERT(offloads & RTE_ETH_RX_OFFLOAD_SCATTER); 850 if (!(offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT)) { 851 DRV_LOG(ERR, "port %u queue index %u split " 852 "offload not configured", 853 dev->data->port_id, idx); 854 rte_errno = ENOSPC; 855 return -rte_errno; 856 } 857 MLX5_ASSERT(n_seg < MLX5_MAX_RXQ_NSEG); 858 } 859 if (conf->share_group > 0) { 860 if (!priv->config.hca_attr.mem_rq_rmp) { 861 DRV_LOG(ERR, "port %u queue index %u shared Rx queue not supported by fw", 862 dev->data->port_id, idx); 863 rte_errno = EINVAL; 864 return -rte_errno; 865 } 866 if (priv->obj_ops.rxq_obj_new != devx_obj_ops.rxq_obj_new) { 867 DRV_LOG(ERR, "port %u queue index %u shared Rx queue needs DevX api", 868 dev->data->port_id, idx); 869 rte_errno = EINVAL; 870 return -rte_errno; 871 } 872 if (conf->share_qid >= priv->rxqs_n) { 873 DRV_LOG(ERR, "port %u shared Rx queue index %u > number of Rx queues %u", 874 dev->data->port_id, conf->share_qid, 875 priv->rxqs_n); 876 rte_errno = EINVAL; 877 return -rte_errno; 878 } 879 if (priv->config.mprq.enabled) { 880 DRV_LOG(ERR, "port %u shared Rx queue index %u: not supported when MPRQ enabled", 881 dev->data->port_id, conf->share_qid); 882 rte_errno = EINVAL; 883 return -rte_errno; 884 } 885 /* Try to reuse shared RXQ. */ 886 rxq_ctrl = mlx5_shared_rxq_get(dev, conf->share_group, 887 conf->share_qid); 888 if (rxq_ctrl != NULL && 889 !mlx5_shared_rxq_match(rxq_ctrl, dev, idx, desc, socket, 890 conf, mp)) { 891 rte_errno = EINVAL; 892 return -rte_errno; 893 } 894 } 895 res = mlx5_rx_queue_pre_setup(dev, idx, &desc, &rxq_ctrl); 896 if (res) 897 return res; 898 /* Allocate RXQ. */ 899 rxq = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*rxq), 0, 900 SOCKET_ID_ANY); 901 if (!rxq) { 902 DRV_LOG(ERR, "port %u unable to allocate rx queue index %u private data", 903 dev->data->port_id, idx); 904 rte_errno = ENOMEM; 905 return -rte_errno; 906 } 907 rxq->priv = priv; 908 rxq->idx = idx; 909 (*priv->rxq_privs)[idx] = rxq; 910 if (rxq_ctrl != NULL) { 911 /* Join owner list. */ 912 LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry); 913 rxq->ctrl = rxq_ctrl; 914 } else { 915 rxq_ctrl = mlx5_rxq_new(dev, rxq, desc, socket, conf, rx_seg, 916 n_seg); 917 if (rxq_ctrl == NULL) { 918 DRV_LOG(ERR, "port %u unable to allocate rx queue index %u", 919 dev->data->port_id, idx); 920 mlx5_free(rxq); 921 (*priv->rxq_privs)[idx] = NULL; 922 rte_errno = ENOMEM; 923 return -rte_errno; 924 } 925 } 926 mlx5_rxq_ref(dev, idx); 927 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list", 928 dev->data->port_id, idx); 929 dev->data->rx_queues[idx] = &rxq_ctrl->rxq; 930 return 0; 931 } 932 933 /** 934 * 935 * @param dev 936 * Pointer to Ethernet device structure. 937 * @param idx 938 * RX queue index. 939 * @param desc 940 * Number of descriptors to configure in queue. 941 * @param hairpin_conf 942 * Hairpin configuration parameters. 943 * 944 * @return 945 * 0 on success, a negative errno value otherwise and rte_errno is set. 946 */ 947 int 948 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx, 949 uint16_t desc, 950 const struct rte_eth_hairpin_conf *hairpin_conf) 951 { 952 struct mlx5_priv *priv = dev->data->dev_private; 953 struct mlx5_rxq_priv *rxq; 954 struct mlx5_rxq_ctrl *rxq_ctrl; 955 int res; 956 957 res = mlx5_rx_queue_pre_setup(dev, idx, &desc, NULL); 958 if (res) 959 return res; 960 if (hairpin_conf->peer_count != 1) { 961 rte_errno = EINVAL; 962 DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue index %u" 963 " peer count is %u", dev->data->port_id, 964 idx, hairpin_conf->peer_count); 965 return -rte_errno; 966 } 967 if (hairpin_conf->peers[0].port == dev->data->port_id) { 968 if (hairpin_conf->peers[0].queue >= priv->txqs_n) { 969 rte_errno = EINVAL; 970 DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue" 971 " index %u, Tx %u is larger than %u", 972 dev->data->port_id, idx, 973 hairpin_conf->peers[0].queue, priv->txqs_n); 974 return -rte_errno; 975 } 976 } else { 977 if (hairpin_conf->manual_bind == 0 || 978 hairpin_conf->tx_explicit == 0) { 979 rte_errno = EINVAL; 980 DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue" 981 " index %u peer port %u with attributes %u %u", 982 dev->data->port_id, idx, 983 hairpin_conf->peers[0].port, 984 hairpin_conf->manual_bind, 985 hairpin_conf->tx_explicit); 986 return -rte_errno; 987 } 988 } 989 rxq = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*rxq), 0, 990 SOCKET_ID_ANY); 991 if (!rxq) { 992 DRV_LOG(ERR, "port %u unable to allocate hairpin rx queue index %u private data", 993 dev->data->port_id, idx); 994 rte_errno = ENOMEM; 995 return -rte_errno; 996 } 997 rxq->priv = priv; 998 rxq->idx = idx; 999 (*priv->rxq_privs)[idx] = rxq; 1000 rxq_ctrl = mlx5_rxq_hairpin_new(dev, rxq, desc, hairpin_conf); 1001 if (!rxq_ctrl) { 1002 DRV_LOG(ERR, "port %u unable to allocate hairpin queue index %u", 1003 dev->data->port_id, idx); 1004 mlx5_free(rxq); 1005 (*priv->rxq_privs)[idx] = NULL; 1006 rte_errno = ENOMEM; 1007 return -rte_errno; 1008 } 1009 DRV_LOG(DEBUG, "port %u adding hairpin Rx queue %u to list", 1010 dev->data->port_id, idx); 1011 dev->data->rx_queues[idx] = &rxq_ctrl->rxq; 1012 return 0; 1013 } 1014 1015 /** 1016 * DPDK callback to release a RX queue. 1017 * 1018 * @param dev 1019 * Pointer to Ethernet device structure. 1020 * @param qid 1021 * Receive queue index. 1022 */ 1023 void 1024 mlx5_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 1025 { 1026 struct mlx5_rxq_data *rxq = dev->data->rx_queues[qid]; 1027 1028 if (rxq == NULL) 1029 return; 1030 if (!mlx5_rxq_releasable(dev, qid)) 1031 rte_panic("port %u Rx queue %u is still used by a flow and" 1032 " cannot be removed\n", dev->data->port_id, qid); 1033 mlx5_rxq_release(dev, qid); 1034 } 1035 1036 /** 1037 * Allocate queue vector and fill epoll fd list for Rx interrupts. 1038 * 1039 * @param dev 1040 * Pointer to Ethernet device. 1041 * 1042 * @return 1043 * 0 on success, a negative errno value otherwise and rte_errno is set. 1044 */ 1045 int 1046 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev) 1047 { 1048 struct mlx5_priv *priv = dev->data->dev_private; 1049 unsigned int i; 1050 unsigned int rxqs_n = priv->rxqs_n; 1051 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID); 1052 unsigned int count = 0; 1053 struct rte_intr_handle *intr_handle = dev->intr_handle; 1054 1055 if (!dev->data->dev_conf.intr_conf.rxq) 1056 return 0; 1057 mlx5_rx_intr_vec_disable(dev); 1058 if (rte_intr_vec_list_alloc(intr_handle, NULL, n)) { 1059 DRV_LOG(ERR, 1060 "port %u failed to allocate memory for interrupt" 1061 " vector, Rx interrupts will not be supported", 1062 dev->data->port_id); 1063 rte_errno = ENOMEM; 1064 return -rte_errno; 1065 } 1066 1067 if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_EXT)) 1068 return -rte_errno; 1069 1070 for (i = 0; i != n; ++i) { 1071 /* This rxq obj must not be released in this function. */ 1072 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1073 struct mlx5_rxq_obj *rxq_obj = rxq ? rxq->ctrl->obj : NULL; 1074 int rc; 1075 1076 /* Skip queues that cannot request interrupts. */ 1077 if (!rxq_obj || (!rxq_obj->ibv_channel && 1078 !rxq_obj->devx_channel)) { 1079 /* Use invalid intr_vec[] index to disable entry. */ 1080 if (rte_intr_vec_list_index_set(intr_handle, i, 1081 RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID)) 1082 return -rte_errno; 1083 continue; 1084 } 1085 mlx5_rxq_ref(dev, i); 1086 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) { 1087 DRV_LOG(ERR, 1088 "port %u too many Rx queues for interrupt" 1089 " vector size (%d), Rx interrupts cannot be" 1090 " enabled", 1091 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID); 1092 mlx5_rx_intr_vec_disable(dev); 1093 rte_errno = ENOMEM; 1094 return -rte_errno; 1095 } 1096 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd); 1097 if (rc < 0) { 1098 rte_errno = errno; 1099 DRV_LOG(ERR, 1100 "port %u failed to make Rx interrupt file" 1101 " descriptor %d non-blocking for queue index" 1102 " %d", 1103 dev->data->port_id, rxq_obj->fd, i); 1104 mlx5_rx_intr_vec_disable(dev); 1105 return -rte_errno; 1106 } 1107 1108 if (rte_intr_vec_list_index_set(intr_handle, i, 1109 RTE_INTR_VEC_RXTX_OFFSET + count)) 1110 return -rte_errno; 1111 if (rte_intr_efds_index_set(intr_handle, count, 1112 rxq_obj->fd)) 1113 return -rte_errno; 1114 count++; 1115 } 1116 if (!count) 1117 mlx5_rx_intr_vec_disable(dev); 1118 else if (rte_intr_nb_efd_set(intr_handle, count)) 1119 return -rte_errno; 1120 return 0; 1121 } 1122 1123 /** 1124 * Clean up Rx interrupts handler. 1125 * 1126 * @param dev 1127 * Pointer to Ethernet device. 1128 */ 1129 void 1130 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev) 1131 { 1132 struct mlx5_priv *priv = dev->data->dev_private; 1133 struct rte_intr_handle *intr_handle = dev->intr_handle; 1134 unsigned int i; 1135 unsigned int rxqs_n = priv->rxqs_n; 1136 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID); 1137 1138 if (!dev->data->dev_conf.intr_conf.rxq) 1139 return; 1140 if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) 1141 goto free; 1142 for (i = 0; i != n; ++i) { 1143 if (rte_intr_vec_list_index_get(intr_handle, i) == 1144 RTE_INTR_VEC_RXTX_OFFSET + RTE_MAX_RXTX_INTR_VEC_ID) 1145 continue; 1146 /** 1147 * Need to access directly the queue to release the reference 1148 * kept in mlx5_rx_intr_vec_enable(). 1149 */ 1150 mlx5_rxq_deref(dev, i); 1151 } 1152 free: 1153 rte_intr_free_epoll_fd(intr_handle); 1154 1155 rte_intr_vec_list_free(intr_handle); 1156 1157 rte_intr_nb_efd_set(intr_handle, 0); 1158 } 1159 1160 /** 1161 * MLX5 CQ notification . 1162 * 1163 * @param rxq 1164 * Pointer to receive queue structure. 1165 * @param sq_n_rxq 1166 * Sequence number per receive queue . 1167 */ 1168 static inline void 1169 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq) 1170 { 1171 int sq_n = 0; 1172 uint32_t doorbell_hi; 1173 uint64_t doorbell; 1174 1175 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK; 1176 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK); 1177 doorbell = (uint64_t)doorbell_hi << 32; 1178 doorbell |= rxq->cqn; 1179 mlx5_doorbell_ring(&rxq->uar_data, rte_cpu_to_be_64(doorbell), 1180 doorbell_hi, &rxq->cq_db[MLX5_CQ_ARM_DB], 0); 1181 } 1182 1183 /** 1184 * DPDK callback for Rx queue interrupt enable. 1185 * 1186 * @param dev 1187 * Pointer to Ethernet device structure. 1188 * @param rx_queue_id 1189 * Rx queue number. 1190 * 1191 * @return 1192 * 0 on success, a negative errno value otherwise and rte_errno is set. 1193 */ 1194 int 1195 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1196 { 1197 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id); 1198 if (!rxq) 1199 goto error; 1200 if (rxq->ctrl->irq) { 1201 if (!rxq->ctrl->obj) 1202 goto error; 1203 mlx5_arm_cq(&rxq->ctrl->rxq, rxq->ctrl->rxq.cq_arm_sn); 1204 } 1205 return 0; 1206 error: 1207 rte_errno = EINVAL; 1208 return -rte_errno; 1209 } 1210 1211 /** 1212 * DPDK callback for Rx queue interrupt disable. 1213 * 1214 * @param dev 1215 * Pointer to Ethernet device structure. 1216 * @param rx_queue_id 1217 * Rx queue number. 1218 * 1219 * @return 1220 * 0 on success, a negative errno value otherwise and rte_errno is set. 1221 */ 1222 int 1223 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1224 { 1225 struct mlx5_priv *priv = dev->data->dev_private; 1226 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id); 1227 int ret = 0; 1228 1229 if (!rxq) { 1230 rte_errno = EINVAL; 1231 return -rte_errno; 1232 } 1233 if (!rxq->ctrl->obj) 1234 goto error; 1235 if (rxq->ctrl->irq) { 1236 ret = priv->obj_ops.rxq_event_get(rxq->ctrl->obj); 1237 if (ret < 0) 1238 goto error; 1239 rxq->ctrl->rxq.cq_arm_sn++; 1240 } 1241 return 0; 1242 error: 1243 /** 1244 * The ret variable may be EAGAIN which means the get_event function was 1245 * called before receiving one. 1246 */ 1247 if (ret < 0) 1248 rte_errno = errno; 1249 else 1250 rte_errno = EINVAL; 1251 if (rte_errno != EAGAIN) 1252 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d", 1253 dev->data->port_id, rx_queue_id); 1254 return -rte_errno; 1255 } 1256 1257 /** 1258 * Verify the Rx queue objects list is empty 1259 * 1260 * @param dev 1261 * Pointer to Ethernet device. 1262 * 1263 * @return 1264 * The number of objects not released. 1265 */ 1266 int 1267 mlx5_rxq_obj_verify(struct rte_eth_dev *dev) 1268 { 1269 struct mlx5_priv *priv = dev->data->dev_private; 1270 int ret = 0; 1271 struct mlx5_rxq_obj *rxq_obj; 1272 1273 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) { 1274 if (rxq_obj->rxq_ctrl->rxq.shared && 1275 !LIST_EMPTY(&rxq_obj->rxq_ctrl->owners)) 1276 continue; 1277 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced", 1278 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx); 1279 ++ret; 1280 } 1281 return ret; 1282 } 1283 1284 /** 1285 * Callback function to initialize mbufs for Multi-Packet RQ. 1286 */ 1287 static inline void 1288 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg, 1289 void *_m, unsigned int i __rte_unused) 1290 { 1291 struct mlx5_mprq_buf *buf = _m; 1292 struct rte_mbuf_ext_shared_info *shinfo; 1293 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg; 1294 unsigned int j; 1295 1296 memset(_m, 0, sizeof(*buf)); 1297 buf->mp = mp; 1298 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED); 1299 for (j = 0; j != strd_n; ++j) { 1300 shinfo = &buf->shinfos[j]; 1301 shinfo->free_cb = mlx5_mprq_buf_free_cb; 1302 shinfo->fcb_opaque = buf; 1303 } 1304 } 1305 1306 /** 1307 * Free mempool of Multi-Packet RQ. 1308 * 1309 * @param dev 1310 * Pointer to Ethernet device. 1311 * 1312 * @return 1313 * 0 on success, negative errno value on failure. 1314 */ 1315 int 1316 mlx5_mprq_free_mp(struct rte_eth_dev *dev) 1317 { 1318 struct mlx5_priv *priv = dev->data->dev_private; 1319 struct rte_mempool *mp = priv->mprq_mp; 1320 unsigned int i; 1321 1322 if (mp == NULL) 1323 return 0; 1324 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ", 1325 dev->data->port_id, mp->name); 1326 /* 1327 * If a buffer in the pool has been externally attached to a mbuf and it 1328 * is still in use by application, destroying the Rx queue can spoil 1329 * the packet. It is unlikely to happen but if application dynamically 1330 * creates and destroys with holding Rx packets, this can happen. 1331 * 1332 * TODO: It is unavoidable for now because the mempool for Multi-Packet 1333 * RQ isn't provided by application but managed by PMD. 1334 */ 1335 if (!rte_mempool_full(mp)) { 1336 DRV_LOG(ERR, 1337 "port %u mempool for Multi-Packet RQ is still in use", 1338 dev->data->port_id); 1339 rte_errno = EBUSY; 1340 return -rte_errno; 1341 } 1342 rte_mempool_free(mp); 1343 /* Unset mempool for each Rx queue. */ 1344 for (i = 0; i != priv->rxqs_n; ++i) { 1345 struct mlx5_rxq_data *rxq = mlx5_rxq_data_get(dev, i); 1346 1347 if (rxq == NULL) 1348 continue; 1349 rxq->mprq_mp = NULL; 1350 } 1351 priv->mprq_mp = NULL; 1352 return 0; 1353 } 1354 1355 /** 1356 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the 1357 * mempool. If already allocated, reuse it if there're enough elements. 1358 * Otherwise, resize it. 1359 * 1360 * @param dev 1361 * Pointer to Ethernet device. 1362 * 1363 * @return 1364 * 0 on success, negative errno value on failure. 1365 */ 1366 int 1367 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev) 1368 { 1369 struct mlx5_priv *priv = dev->data->dev_private; 1370 struct rte_mempool *mp = priv->mprq_mp; 1371 char name[RTE_MEMPOOL_NAMESIZE]; 1372 unsigned int desc = 0; 1373 unsigned int buf_len; 1374 unsigned int obj_num; 1375 unsigned int obj_size; 1376 unsigned int strd_num_n = 0; 1377 unsigned int strd_sz_n = 0; 1378 unsigned int i; 1379 unsigned int n_ibv = 0; 1380 int ret; 1381 1382 if (!mlx5_mprq_enabled(dev)) 1383 return 0; 1384 /* Count the total number of descriptors configured. */ 1385 for (i = 0; i != priv->rxqs_n; ++i) { 1386 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 1387 struct mlx5_rxq_data *rxq; 1388 1389 if (rxq_ctrl == NULL || 1390 rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD) 1391 continue; 1392 rxq = &rxq_ctrl->rxq; 1393 n_ibv++; 1394 desc += 1 << rxq->elts_n; 1395 /* Get the max number of strides. */ 1396 if (strd_num_n < rxq->strd_num_n) 1397 strd_num_n = rxq->strd_num_n; 1398 /* Get the max size of a stride. */ 1399 if (strd_sz_n < rxq->strd_sz_n) 1400 strd_sz_n = rxq->strd_sz_n; 1401 } 1402 MLX5_ASSERT(strd_num_n && strd_sz_n); 1403 buf_len = (1 << strd_num_n) * (1 << strd_sz_n); 1404 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) * 1405 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM; 1406 /* 1407 * Received packets can be either memcpy'd or externally referenced. In 1408 * case that the packet is attached to an mbuf as an external buffer, as 1409 * it isn't possible to predict how the buffers will be queued by 1410 * application, there's no option to exactly pre-allocate needed buffers 1411 * in advance but to speculatively prepares enough buffers. 1412 * 1413 * In the data path, if this Mempool is depleted, PMD will try to memcpy 1414 * received packets to buffers provided by application (rxq->mp) until 1415 * this Mempool gets available again. 1416 */ 1417 desc *= 4; 1418 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv; 1419 /* 1420 * rte_mempool_create_empty() has sanity check to refuse large cache 1421 * size compared to the number of elements. 1422 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a 1423 * constant number 2 instead. 1424 */ 1425 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2); 1426 /* Check a mempool is already allocated and if it can be resued. */ 1427 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) { 1428 DRV_LOG(DEBUG, "port %u mempool %s is being reused", 1429 dev->data->port_id, mp->name); 1430 /* Reuse. */ 1431 goto exit; 1432 } else if (mp != NULL) { 1433 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it", 1434 dev->data->port_id, mp->name); 1435 /* 1436 * If failed to free, which means it may be still in use, no way 1437 * but to keep using the existing one. On buffer underrun, 1438 * packets will be memcpy'd instead of external buffer 1439 * attachment. 1440 */ 1441 if (mlx5_mprq_free_mp(dev)) { 1442 if (mp->elt_size >= obj_size) 1443 goto exit; 1444 else 1445 return -rte_errno; 1446 } 1447 } 1448 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id); 1449 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ, 1450 0, NULL, NULL, mlx5_mprq_buf_init, 1451 (void *)((uintptr_t)1 << strd_num_n), 1452 dev->device->numa_node, 0); 1453 if (mp == NULL) { 1454 DRV_LOG(ERR, 1455 "port %u failed to allocate a mempool for" 1456 " Multi-Packet RQ, count=%u, size=%u", 1457 dev->data->port_id, obj_num, obj_size); 1458 rte_errno = ENOMEM; 1459 return -rte_errno; 1460 } 1461 ret = mlx5_mr_mempool_register(priv->sh->cdev, mp); 1462 if (ret < 0 && rte_errno != EEXIST) { 1463 ret = rte_errno; 1464 DRV_LOG(ERR, "port %u failed to register a mempool for Multi-Packet RQ", 1465 dev->data->port_id); 1466 rte_mempool_free(mp); 1467 rte_errno = ret; 1468 return -rte_errno; 1469 } 1470 priv->mprq_mp = mp; 1471 exit: 1472 /* Set mempool for each Rx queue. */ 1473 for (i = 0; i != priv->rxqs_n; ++i) { 1474 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 1475 1476 if (rxq_ctrl == NULL || 1477 rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD) 1478 continue; 1479 rxq_ctrl->rxq.mprq_mp = mp; 1480 } 1481 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured", 1482 dev->data->port_id); 1483 return 0; 1484 } 1485 1486 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \ 1487 sizeof(struct rte_vlan_hdr) * 2 + \ 1488 sizeof(struct rte_ipv6_hdr))) 1489 #define MAX_TCP_OPTION_SIZE 40u 1490 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \ 1491 sizeof(struct rte_tcp_hdr) + \ 1492 MAX_TCP_OPTION_SIZE)) 1493 1494 /** 1495 * Adjust the maximum LRO massage size. 1496 * 1497 * @param dev 1498 * Pointer to Ethernet device. 1499 * @param idx 1500 * RX queue index. 1501 * @param max_lro_size 1502 * The maximum size for LRO packet. 1503 */ 1504 static void 1505 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx, 1506 uint32_t max_lro_size) 1507 { 1508 struct mlx5_priv *priv = dev->data->dev_private; 1509 1510 if (priv->config.hca_attr.lro_max_msg_sz_mode == 1511 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size > 1512 MLX5_MAX_TCP_HDR_OFFSET) 1513 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET; 1514 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE); 1515 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE); 1516 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE; 1517 if (priv->max_lro_msg_size) 1518 priv->max_lro_msg_size = 1519 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size); 1520 else 1521 priv->max_lro_msg_size = max_lro_size; 1522 DRV_LOG(DEBUG, 1523 "port %u Rx Queue %u max LRO message size adjusted to %u bytes", 1524 dev->data->port_id, idx, 1525 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE); 1526 } 1527 1528 /** 1529 * Create a DPDK Rx queue. 1530 * 1531 * @param dev 1532 * Pointer to Ethernet device. 1533 * @param rxq 1534 * RX queue private data. 1535 * @param desc 1536 * Number of descriptors to configure in queue. 1537 * @param socket 1538 * NUMA socket on which memory must be allocated. 1539 * 1540 * @return 1541 * A DPDK queue object on success, NULL otherwise and rte_errno is set. 1542 */ 1543 struct mlx5_rxq_ctrl * 1544 mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, 1545 uint16_t desc, 1546 unsigned int socket, const struct rte_eth_rxconf *conf, 1547 const struct rte_eth_rxseg_split *rx_seg, uint16_t n_seg) 1548 { 1549 uint16_t idx = rxq->idx; 1550 struct mlx5_priv *priv = dev->data->dev_private; 1551 struct mlx5_rxq_ctrl *tmpl; 1552 unsigned int mb_len = rte_pktmbuf_data_room_size(rx_seg[0].mp); 1553 struct mlx5_dev_config *config = &priv->config; 1554 uint64_t offloads = conf->offloads | 1555 dev->data->dev_conf.rxmode.offloads; 1556 unsigned int lro_on_queue = !!(offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO); 1557 unsigned int max_rx_pktlen = lro_on_queue ? 1558 dev->data->dev_conf.rxmode.max_lro_pkt_size : 1559 dev->data->mtu + (unsigned int)RTE_ETHER_HDR_LEN + 1560 RTE_ETHER_CRC_LEN; 1561 unsigned int non_scatter_min_mbuf_size = max_rx_pktlen + 1562 RTE_PKTMBUF_HEADROOM; 1563 unsigned int max_lro_size = 0; 1564 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM; 1565 const int mprq_en = mlx5_check_mprq_support(dev) > 0 && n_seg == 1 && 1566 !rx_seg[0].offset && !rx_seg[0].length; 1567 unsigned int mprq_stride_nums = config->mprq.stride_num_n ? 1568 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N; 1569 unsigned int mprq_stride_size = non_scatter_min_mbuf_size <= 1570 (1U << config->mprq.max_stride_size_n) ? 1571 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N; 1572 unsigned int mprq_stride_cap = (config->mprq.stride_num_n ? 1573 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) * 1574 (config->mprq.stride_size_n ? 1575 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size)); 1576 /* 1577 * Always allocate extra slots, even if eventually 1578 * the vector Rx will not be used. 1579 */ 1580 uint16_t desc_n = desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP; 1581 const struct rte_eth_rxseg_split *qs_seg = rx_seg; 1582 unsigned int tail_len; 1583 1584 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, 1585 sizeof(*tmpl) + desc_n * sizeof(struct rte_mbuf *) + 1586 (!!mprq_en) * 1587 (desc >> mprq_stride_nums) * sizeof(struct mlx5_mprq_buf *), 1588 0, socket); 1589 if (!tmpl) { 1590 rte_errno = ENOMEM; 1591 return NULL; 1592 } 1593 LIST_INIT(&tmpl->owners); 1594 if (conf->share_group > 0) { 1595 tmpl->rxq.shared = 1; 1596 tmpl->share_group = conf->share_group; 1597 tmpl->share_qid = conf->share_qid; 1598 LIST_INSERT_HEAD(&priv->sh->shared_rxqs, tmpl, share_entry); 1599 } 1600 rxq->ctrl = tmpl; 1601 LIST_INSERT_HEAD(&tmpl->owners, rxq, owner_entry); 1602 MLX5_ASSERT(n_seg && n_seg <= MLX5_MAX_RXQ_NSEG); 1603 /* 1604 * Build the array of actual buffer offsets and lengths. 1605 * Pad with the buffers from the last memory pool if 1606 * needed to handle max size packets, replace zero length 1607 * with the buffer length from the pool. 1608 */ 1609 tail_len = max_rx_pktlen; 1610 do { 1611 struct mlx5_eth_rxseg *hw_seg = 1612 &tmpl->rxq.rxseg[tmpl->rxq.rxseg_n]; 1613 uint32_t buf_len, offset, seg_len; 1614 1615 /* 1616 * For the buffers beyond descriptions offset is zero, 1617 * the first buffer contains head room. 1618 */ 1619 buf_len = rte_pktmbuf_data_room_size(qs_seg->mp); 1620 offset = (tmpl->rxq.rxseg_n >= n_seg ? 0 : qs_seg->offset) + 1621 (tmpl->rxq.rxseg_n ? 0 : RTE_PKTMBUF_HEADROOM); 1622 /* 1623 * For the buffers beyond descriptions the length is 1624 * pool buffer length, zero lengths are replaced with 1625 * pool buffer length either. 1626 */ 1627 seg_len = tmpl->rxq.rxseg_n >= n_seg ? buf_len : 1628 qs_seg->length ? 1629 qs_seg->length : 1630 (buf_len - offset); 1631 /* Check is done in long int, now overflows. */ 1632 if (buf_len < seg_len + offset) { 1633 DRV_LOG(ERR, "port %u Rx queue %u: Split offset/length " 1634 "%u/%u can't be satisfied", 1635 dev->data->port_id, idx, 1636 qs_seg->length, qs_seg->offset); 1637 rte_errno = EINVAL; 1638 goto error; 1639 } 1640 if (seg_len > tail_len) 1641 seg_len = buf_len - offset; 1642 if (++tmpl->rxq.rxseg_n > MLX5_MAX_RXQ_NSEG) { 1643 DRV_LOG(ERR, 1644 "port %u too many SGEs (%u) needed to handle" 1645 " requested maximum packet size %u, the maximum" 1646 " supported are %u", dev->data->port_id, 1647 tmpl->rxq.rxseg_n, max_rx_pktlen, 1648 MLX5_MAX_RXQ_NSEG); 1649 rte_errno = ENOTSUP; 1650 goto error; 1651 } 1652 /* Build the actual scattering element in the queue object. */ 1653 hw_seg->mp = qs_seg->mp; 1654 MLX5_ASSERT(offset <= UINT16_MAX); 1655 MLX5_ASSERT(seg_len <= UINT16_MAX); 1656 hw_seg->offset = (uint16_t)offset; 1657 hw_seg->length = (uint16_t)seg_len; 1658 /* 1659 * Advance the segment descriptor, the padding is the based 1660 * on the attributes of the last descriptor. 1661 */ 1662 if (tmpl->rxq.rxseg_n < n_seg) 1663 qs_seg++; 1664 tail_len -= RTE_MIN(tail_len, seg_len); 1665 } while (tail_len || !rte_is_power_of_2(tmpl->rxq.rxseg_n)); 1666 MLX5_ASSERT(tmpl->rxq.rxseg_n && 1667 tmpl->rxq.rxseg_n <= MLX5_MAX_RXQ_NSEG); 1668 if (tmpl->rxq.rxseg_n > 1 && !(offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) { 1669 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not" 1670 " configured and no enough mbuf space(%u) to contain " 1671 "the maximum RX packet length(%u) with head-room(%u)", 1672 dev->data->port_id, idx, mb_len, max_rx_pktlen, 1673 RTE_PKTMBUF_HEADROOM); 1674 rte_errno = ENOSPC; 1675 goto error; 1676 } 1677 tmpl->type = MLX5_RXQ_TYPE_STANDARD; 1678 if (mlx5_mr_ctrl_init(&tmpl->rxq.mr_ctrl, 1679 &priv->sh->cdev->mr_scache.dev_gen, socket)) { 1680 /* rte_errno is already set. */ 1681 goto error; 1682 } 1683 tmpl->socket = socket; 1684 if (dev->data->dev_conf.intr_conf.rxq) 1685 tmpl->irq = 1; 1686 /* 1687 * This Rx queue can be configured as a Multi-Packet RQ if all of the 1688 * following conditions are met: 1689 * - MPRQ is enabled. 1690 * - The number of descs is more than the number of strides. 1691 * - max_rx_pktlen plus overhead is less than the max size 1692 * of a stride or mprq_stride_size is specified by a user. 1693 * Need to make sure that there are enough strides to encap 1694 * the maximum packet size in case mprq_stride_size is set. 1695 * Otherwise, enable Rx scatter if necessary. 1696 */ 1697 if (mprq_en && desc > (1U << mprq_stride_nums) && 1698 (non_scatter_min_mbuf_size <= 1699 (1U << config->mprq.max_stride_size_n) || 1700 (config->mprq.stride_size_n && 1701 non_scatter_min_mbuf_size <= mprq_stride_cap))) { 1702 /* TODO: Rx scatter isn't supported yet. */ 1703 tmpl->rxq.sges_n = 0; 1704 /* Trim the number of descs needed. */ 1705 desc >>= mprq_stride_nums; 1706 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ? 1707 config->mprq.stride_num_n : mprq_stride_nums; 1708 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ? 1709 config->mprq.stride_size_n : mprq_stride_size; 1710 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT; 1711 tmpl->rxq.strd_scatter_en = 1712 !!(offloads & RTE_ETH_RX_OFFLOAD_SCATTER); 1713 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size, 1714 config->mprq.max_memcpy_len); 1715 max_lro_size = RTE_MIN(max_rx_pktlen, 1716 (1u << tmpl->rxq.strd_num_n) * 1717 (1u << tmpl->rxq.strd_sz_n)); 1718 DRV_LOG(DEBUG, 1719 "port %u Rx queue %u: Multi-Packet RQ is enabled" 1720 " strd_num_n = %u, strd_sz_n = %u", 1721 dev->data->port_id, idx, 1722 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n); 1723 } else if (tmpl->rxq.rxseg_n == 1) { 1724 MLX5_ASSERT(max_rx_pktlen <= first_mb_free_size); 1725 tmpl->rxq.sges_n = 0; 1726 max_lro_size = max_rx_pktlen; 1727 } else if (offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 1728 unsigned int sges_n; 1729 1730 if (lro_on_queue && first_mb_free_size < 1731 MLX5_MAX_LRO_HEADER_FIX) { 1732 DRV_LOG(ERR, "Not enough space in the first segment(%u)" 1733 " to include the max header size(%u) for LRO", 1734 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX); 1735 rte_errno = ENOTSUP; 1736 goto error; 1737 } 1738 /* 1739 * Determine the number of SGEs needed for a full packet 1740 * and round it to the next power of two. 1741 */ 1742 sges_n = log2above(tmpl->rxq.rxseg_n); 1743 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) { 1744 DRV_LOG(ERR, 1745 "port %u too many SGEs (%u) needed to handle" 1746 " requested maximum packet size %u, the maximum" 1747 " supported are %u", dev->data->port_id, 1748 1 << sges_n, max_rx_pktlen, 1749 1u << MLX5_MAX_LOG_RQ_SEGS); 1750 rte_errno = ENOTSUP; 1751 goto error; 1752 } 1753 tmpl->rxq.sges_n = sges_n; 1754 max_lro_size = max_rx_pktlen; 1755 } 1756 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq)) 1757 DRV_LOG(WARNING, 1758 "port %u MPRQ is requested but cannot be enabled\n" 1759 " (requested: pkt_sz = %u, desc_num = %u," 1760 " rxq_num = %u, stride_sz = %u, stride_num = %u\n" 1761 " supported: min_rxqs_num = %u," 1762 " min_stride_sz = %u, max_stride_sz = %u).", 1763 dev->data->port_id, non_scatter_min_mbuf_size, 1764 desc, priv->rxqs_n, 1765 config->mprq.stride_size_n ? 1766 (1U << config->mprq.stride_size_n) : 1767 (1U << mprq_stride_size), 1768 config->mprq.stride_num_n ? 1769 (1U << config->mprq.stride_num_n) : 1770 (1U << mprq_stride_nums), 1771 config->mprq.min_rxqs_num, 1772 (1U << config->mprq.min_stride_size_n), 1773 (1U << config->mprq.max_stride_size_n)); 1774 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u", 1775 dev->data->port_id, 1 << tmpl->rxq.sges_n); 1776 if (desc % (1 << tmpl->rxq.sges_n)) { 1777 DRV_LOG(ERR, 1778 "port %u number of Rx queue descriptors (%u) is not a" 1779 " multiple of SGEs per packet (%u)", 1780 dev->data->port_id, 1781 desc, 1782 1 << tmpl->rxq.sges_n); 1783 rte_errno = EINVAL; 1784 goto error; 1785 } 1786 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size); 1787 /* Toggle RX checksum offload if hardware supports it. */ 1788 tmpl->rxq.csum = !!(offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM); 1789 /* Configure Rx timestamp. */ 1790 tmpl->rxq.hw_timestamp = !!(offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP); 1791 tmpl->rxq.timestamp_rx_flag = 0; 1792 if (tmpl->rxq.hw_timestamp && rte_mbuf_dyn_rx_timestamp_register( 1793 &tmpl->rxq.timestamp_offset, 1794 &tmpl->rxq.timestamp_rx_flag) != 0) { 1795 DRV_LOG(ERR, "Cannot register Rx timestamp field/flag"); 1796 goto error; 1797 } 1798 /* Configure VLAN stripping. */ 1799 tmpl->rxq.vlan_strip = !!(offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); 1800 /* By default, FCS (CRC) is stripped by hardware. */ 1801 tmpl->rxq.crc_present = 0; 1802 tmpl->rxq.lro = lro_on_queue; 1803 if (offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { 1804 if (config->hw_fcs_strip) { 1805 /* 1806 * RQs used for LRO-enabled TIRs should not be 1807 * configured to scatter the FCS. 1808 */ 1809 if (lro_on_queue) 1810 DRV_LOG(WARNING, 1811 "port %u CRC stripping has been " 1812 "disabled but will still be performed " 1813 "by hardware, because LRO is enabled", 1814 dev->data->port_id); 1815 else 1816 tmpl->rxq.crc_present = 1; 1817 } else { 1818 DRV_LOG(WARNING, 1819 "port %u CRC stripping has been disabled but will" 1820 " still be performed by hardware, make sure MLNX_OFED" 1821 " and firmware are up to date", 1822 dev->data->port_id); 1823 } 1824 } 1825 DRV_LOG(DEBUG, 1826 "port %u CRC stripping is %s, %u bytes will be subtracted from" 1827 " incoming frames to hide it", 1828 dev->data->port_id, 1829 tmpl->rxq.crc_present ? "disabled" : "enabled", 1830 tmpl->rxq.crc_present << 2); 1831 /* Save port ID. */ 1832 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf && 1833 (!!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS)); 1834 tmpl->rxq.port_id = dev->data->port_id; 1835 tmpl->sh = priv->sh; 1836 tmpl->rxq.mp = rx_seg[0].mp; 1837 tmpl->rxq.elts_n = log2above(desc); 1838 tmpl->rxq.rq_repl_thresh = 1839 MLX5_VPMD_RXQ_RPLNSH_THRESH(desc_n); 1840 tmpl->rxq.elts = 1841 (struct rte_mbuf *(*)[desc_n])(tmpl + 1); 1842 tmpl->rxq.mprq_bufs = 1843 (struct mlx5_mprq_buf *(*)[desc])(*tmpl->rxq.elts + desc_n); 1844 tmpl->rxq.idx = idx; 1845 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); 1846 return tmpl; 1847 error: 1848 mlx5_mr_btree_free(&tmpl->rxq.mr_ctrl.cache_bh); 1849 mlx5_free(tmpl); 1850 return NULL; 1851 } 1852 1853 /** 1854 * Create a DPDK Rx hairpin queue. 1855 * 1856 * @param dev 1857 * Pointer to Ethernet device. 1858 * @param rxq 1859 * RX queue. 1860 * @param desc 1861 * Number of descriptors to configure in queue. 1862 * @param hairpin_conf 1863 * The hairpin binding configuration. 1864 * 1865 * @return 1866 * A DPDK queue object on success, NULL otherwise and rte_errno is set. 1867 */ 1868 struct mlx5_rxq_ctrl * 1869 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, 1870 uint16_t desc, 1871 const struct rte_eth_hairpin_conf *hairpin_conf) 1872 { 1873 uint16_t idx = rxq->idx; 1874 struct mlx5_priv *priv = dev->data->dev_private; 1875 struct mlx5_rxq_ctrl *tmpl; 1876 1877 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0, 1878 SOCKET_ID_ANY); 1879 if (!tmpl) { 1880 rte_errno = ENOMEM; 1881 return NULL; 1882 } 1883 LIST_INIT(&tmpl->owners); 1884 rxq->ctrl = tmpl; 1885 LIST_INSERT_HEAD(&tmpl->owners, rxq, owner_entry); 1886 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN; 1887 tmpl->socket = SOCKET_ID_ANY; 1888 tmpl->rxq.rss_hash = 0; 1889 tmpl->rxq.port_id = dev->data->port_id; 1890 tmpl->sh = priv->sh; 1891 tmpl->rxq.mp = NULL; 1892 tmpl->rxq.elts_n = log2above(desc); 1893 tmpl->rxq.elts = NULL; 1894 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 }; 1895 tmpl->rxq.idx = idx; 1896 rxq->hairpin_conf = *hairpin_conf; 1897 mlx5_rxq_ref(dev, idx); 1898 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); 1899 return tmpl; 1900 } 1901 1902 /** 1903 * Increase Rx queue reference count. 1904 * 1905 * @param dev 1906 * Pointer to Ethernet device. 1907 * @param idx 1908 * RX queue index. 1909 * 1910 * @return 1911 * A pointer to the queue if it exists, NULL otherwise. 1912 */ 1913 struct mlx5_rxq_priv * 1914 mlx5_rxq_ref(struct rte_eth_dev *dev, uint16_t idx) 1915 { 1916 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 1917 1918 if (rxq != NULL) 1919 __atomic_fetch_add(&rxq->refcnt, 1, __ATOMIC_RELAXED); 1920 return rxq; 1921 } 1922 1923 /** 1924 * Dereference a Rx queue. 1925 * 1926 * @param dev 1927 * Pointer to Ethernet device. 1928 * @param idx 1929 * RX queue index. 1930 * 1931 * @return 1932 * Updated reference count. 1933 */ 1934 uint32_t 1935 mlx5_rxq_deref(struct rte_eth_dev *dev, uint16_t idx) 1936 { 1937 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 1938 1939 if (rxq == NULL) 1940 return 0; 1941 return __atomic_sub_fetch(&rxq->refcnt, 1, __ATOMIC_RELAXED); 1942 } 1943 1944 /** 1945 * Get a Rx queue. 1946 * 1947 * @param dev 1948 * Pointer to Ethernet device. 1949 * @param idx 1950 * RX queue index. 1951 * 1952 * @return 1953 * A pointer to the queue if it exists, NULL otherwise. 1954 */ 1955 struct mlx5_rxq_priv * 1956 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx) 1957 { 1958 struct mlx5_priv *priv = dev->data->dev_private; 1959 1960 MLX5_ASSERT(priv->rxq_privs != NULL); 1961 return (*priv->rxq_privs)[idx]; 1962 } 1963 1964 /** 1965 * Get Rx queue shareable control. 1966 * 1967 * @param dev 1968 * Pointer to Ethernet device. 1969 * @param idx 1970 * RX queue index. 1971 * 1972 * @return 1973 * A pointer to the queue control if it exists, NULL otherwise. 1974 */ 1975 struct mlx5_rxq_ctrl * 1976 mlx5_rxq_ctrl_get(struct rte_eth_dev *dev, uint16_t idx) 1977 { 1978 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 1979 1980 return rxq == NULL ? NULL : rxq->ctrl; 1981 } 1982 1983 /** 1984 * Get Rx queue shareable data. 1985 * 1986 * @param dev 1987 * Pointer to Ethernet device. 1988 * @param idx 1989 * RX queue index. 1990 * 1991 * @return 1992 * A pointer to the queue data if it exists, NULL otherwise. 1993 */ 1994 struct mlx5_rxq_data * 1995 mlx5_rxq_data_get(struct rte_eth_dev *dev, uint16_t idx) 1996 { 1997 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 1998 1999 return rxq == NULL ? NULL : &rxq->ctrl->rxq; 2000 } 2001 2002 /** 2003 * Release a Rx queue. 2004 * 2005 * @param dev 2006 * Pointer to Ethernet device. 2007 * @param idx 2008 * RX queue index. 2009 * 2010 * @return 2011 * 1 while a reference on it exists, 0 when freed. 2012 */ 2013 int 2014 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) 2015 { 2016 struct mlx5_priv *priv = dev->data->dev_private; 2017 struct mlx5_rxq_priv *rxq; 2018 struct mlx5_rxq_ctrl *rxq_ctrl; 2019 uint32_t refcnt; 2020 2021 if (priv->rxq_privs == NULL) 2022 return 0; 2023 rxq = mlx5_rxq_get(dev, idx); 2024 if (rxq == NULL || rxq->refcnt == 0) 2025 return 0; 2026 rxq_ctrl = rxq->ctrl; 2027 refcnt = mlx5_rxq_deref(dev, idx); 2028 if (refcnt > 1) { 2029 return 1; 2030 } else if (refcnt == 1) { /* RxQ stopped. */ 2031 priv->obj_ops.rxq_obj_release(rxq); 2032 if (!rxq_ctrl->started && rxq_ctrl->obj != NULL) { 2033 LIST_REMOVE(rxq_ctrl->obj, next); 2034 mlx5_free(rxq_ctrl->obj); 2035 rxq_ctrl->obj = NULL; 2036 } 2037 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) { 2038 if (!rxq_ctrl->started) 2039 rxq_free_elts(rxq_ctrl); 2040 dev->data->rx_queue_state[idx] = 2041 RTE_ETH_QUEUE_STATE_STOPPED; 2042 } 2043 } else { /* Refcnt zero, closing device. */ 2044 LIST_REMOVE(rxq, owner_entry); 2045 if (LIST_EMPTY(&rxq_ctrl->owners)) { 2046 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) 2047 mlx5_mr_btree_free 2048 (&rxq_ctrl->rxq.mr_ctrl.cache_bh); 2049 if (rxq_ctrl->rxq.shared) 2050 LIST_REMOVE(rxq_ctrl, share_entry); 2051 LIST_REMOVE(rxq_ctrl, next); 2052 mlx5_free(rxq_ctrl); 2053 } 2054 dev->data->rx_queues[idx] = NULL; 2055 mlx5_free(rxq); 2056 (*priv->rxq_privs)[idx] = NULL; 2057 } 2058 return 0; 2059 } 2060 2061 /** 2062 * Verify the Rx Queue list is empty 2063 * 2064 * @param dev 2065 * Pointer to Ethernet device. 2066 * 2067 * @return 2068 * The number of object not released. 2069 */ 2070 int 2071 mlx5_rxq_verify(struct rte_eth_dev *dev) 2072 { 2073 struct mlx5_priv *priv = dev->data->dev_private; 2074 struct mlx5_rxq_ctrl *rxq_ctrl; 2075 int ret = 0; 2076 2077 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 2078 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced", 2079 dev->data->port_id, rxq_ctrl->rxq.idx); 2080 ++ret; 2081 } 2082 return ret; 2083 } 2084 2085 /** 2086 * Get a Rx queue type. 2087 * 2088 * @param dev 2089 * Pointer to Ethernet device. 2090 * @param idx 2091 * Rx queue index. 2092 * 2093 * @return 2094 * The Rx queue type. 2095 */ 2096 enum mlx5_rxq_type 2097 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx) 2098 { 2099 struct mlx5_priv *priv = dev->data->dev_private; 2100 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 2101 2102 if (idx < priv->rxqs_n && rxq_ctrl != NULL) 2103 return rxq_ctrl->type; 2104 return MLX5_RXQ_TYPE_UNDEFINED; 2105 } 2106 2107 /* 2108 * Get a Rx hairpin queue configuration. 2109 * 2110 * @param dev 2111 * Pointer to Ethernet device. 2112 * @param idx 2113 * Rx queue index. 2114 * 2115 * @return 2116 * Pointer to the configuration if a hairpin RX queue, otherwise NULL. 2117 */ 2118 const struct rte_eth_hairpin_conf * 2119 mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) 2120 { 2121 struct mlx5_priv *priv = dev->data->dev_private; 2122 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); 2123 2124 if (idx < priv->rxqs_n && rxq != NULL) { 2125 if (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) 2126 return &rxq->hairpin_conf; 2127 } 2128 return NULL; 2129 } 2130 2131 /** 2132 * Match queues listed in arguments to queues contained in indirection table 2133 * object. 2134 * 2135 * @param ind_tbl 2136 * Pointer to indirection table to match. 2137 * @param queues 2138 * Queues to match to ques in indirection table. 2139 * @param queues_n 2140 * Number of queues in the array. 2141 * 2142 * @return 2143 * 1 if all queues in indirection table match 0 othrwise. 2144 */ 2145 static int 2146 mlx5_ind_table_obj_match_queues(const struct mlx5_ind_table_obj *ind_tbl, 2147 const uint16_t *queues, uint32_t queues_n) 2148 { 2149 return (ind_tbl->queues_n == queues_n) && 2150 (!memcmp(ind_tbl->queues, queues, 2151 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))); 2152 } 2153 2154 /** 2155 * Get an indirection table. 2156 * 2157 * @param dev 2158 * Pointer to Ethernet device. 2159 * @param queues 2160 * Queues entering in the indirection table. 2161 * @param queues_n 2162 * Number of queues in the array. 2163 * 2164 * @return 2165 * An indirection table if found. 2166 */ 2167 struct mlx5_ind_table_obj * 2168 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues, 2169 uint32_t queues_n) 2170 { 2171 struct mlx5_priv *priv = dev->data->dev_private; 2172 struct mlx5_ind_table_obj *ind_tbl; 2173 2174 rte_rwlock_read_lock(&priv->ind_tbls_lock); 2175 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) { 2176 if ((ind_tbl->queues_n == queues_n) && 2177 (memcmp(ind_tbl->queues, queues, 2178 ind_tbl->queues_n * sizeof(ind_tbl->queues[0])) 2179 == 0)) { 2180 __atomic_fetch_add(&ind_tbl->refcnt, 1, 2181 __ATOMIC_RELAXED); 2182 break; 2183 } 2184 } 2185 rte_rwlock_read_unlock(&priv->ind_tbls_lock); 2186 return ind_tbl; 2187 } 2188 2189 /** 2190 * Release an indirection table. 2191 * 2192 * @param dev 2193 * Pointer to Ethernet device. 2194 * @param ind_table 2195 * Indirection table to release. 2196 * @param standalone 2197 * Indirection table for Standalone queue. 2198 * 2199 * @return 2200 * 1 while a reference on it exists, 0 when freed. 2201 */ 2202 int 2203 mlx5_ind_table_obj_release(struct rte_eth_dev *dev, 2204 struct mlx5_ind_table_obj *ind_tbl, 2205 bool standalone) 2206 { 2207 struct mlx5_priv *priv = dev->data->dev_private; 2208 unsigned int i, ret; 2209 2210 rte_rwlock_write_lock(&priv->ind_tbls_lock); 2211 ret = __atomic_sub_fetch(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED); 2212 if (!ret && !standalone) 2213 LIST_REMOVE(ind_tbl, next); 2214 rte_rwlock_write_unlock(&priv->ind_tbls_lock); 2215 if (ret) 2216 return 1; 2217 priv->obj_ops.ind_table_destroy(ind_tbl); 2218 for (i = 0; i != ind_tbl->queues_n; ++i) 2219 claim_nonzero(mlx5_rxq_deref(dev, ind_tbl->queues[i])); 2220 mlx5_free(ind_tbl); 2221 return 0; 2222 } 2223 2224 /** 2225 * Verify the Rx Queue list is empty 2226 * 2227 * @param dev 2228 * Pointer to Ethernet device. 2229 * 2230 * @return 2231 * The number of object not released. 2232 */ 2233 int 2234 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev) 2235 { 2236 struct mlx5_priv *priv = dev->data->dev_private; 2237 struct mlx5_ind_table_obj *ind_tbl; 2238 int ret = 0; 2239 2240 rte_rwlock_read_lock(&priv->ind_tbls_lock); 2241 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) { 2242 DRV_LOG(DEBUG, 2243 "port %u indirection table obj %p still referenced", 2244 dev->data->port_id, (void *)ind_tbl); 2245 ++ret; 2246 } 2247 rte_rwlock_read_unlock(&priv->ind_tbls_lock); 2248 return ret; 2249 } 2250 2251 /** 2252 * Setup an indirection table structure fields. 2253 * 2254 * @param dev 2255 * Pointer to Ethernet device. 2256 * @param ind_table 2257 * Indirection table to modify. 2258 * 2259 * @return 2260 * 0 on success, a negative errno value otherwise and rte_errno is set. 2261 */ 2262 int 2263 mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, 2264 struct mlx5_ind_table_obj *ind_tbl) 2265 { 2266 struct mlx5_priv *priv = dev->data->dev_private; 2267 uint32_t queues_n = ind_tbl->queues_n; 2268 uint16_t *queues = ind_tbl->queues; 2269 unsigned int i, j; 2270 int ret = 0, err; 2271 const unsigned int n = rte_is_power_of_2(queues_n) ? 2272 log2above(queues_n) : 2273 log2above(priv->config.ind_table_max_size); 2274 2275 for (i = 0; i != queues_n; ++i) { 2276 if (mlx5_rxq_ref(dev, queues[i]) == NULL) { 2277 ret = -rte_errno; 2278 goto error; 2279 } 2280 } 2281 ret = priv->obj_ops.ind_table_new(dev, n, ind_tbl); 2282 if (ret) 2283 goto error; 2284 __atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED); 2285 return 0; 2286 error: 2287 err = rte_errno; 2288 for (j = 0; j < i; j++) 2289 mlx5_rxq_deref(dev, ind_tbl->queues[j]); 2290 rte_errno = err; 2291 DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", 2292 dev->data->port_id); 2293 return ret; 2294 } 2295 2296 /** 2297 * Create an indirection table. 2298 * 2299 * @param dev 2300 * Pointer to Ethernet device. 2301 * @param queues 2302 * Queues entering in the indirection table. 2303 * @param queues_n 2304 * Number of queues in the array. 2305 * @param standalone 2306 * Indirection table for Standalone queue. 2307 * 2308 * @return 2309 * The Verbs/DevX object initialized, NULL otherwise and rte_errno is set. 2310 */ 2311 static struct mlx5_ind_table_obj * 2312 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues, 2313 uint32_t queues_n, bool standalone) 2314 { 2315 struct mlx5_priv *priv = dev->data->dev_private; 2316 struct mlx5_ind_table_obj *ind_tbl; 2317 int ret; 2318 2319 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) + 2320 queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY); 2321 if (!ind_tbl) { 2322 rte_errno = ENOMEM; 2323 return NULL; 2324 } 2325 ind_tbl->queues_n = queues_n; 2326 ind_tbl->queues = (uint16_t *)(ind_tbl + 1); 2327 memcpy(ind_tbl->queues, queues, queues_n * sizeof(*queues)); 2328 ret = mlx5_ind_table_obj_setup(dev, ind_tbl); 2329 if (ret < 0) { 2330 mlx5_free(ind_tbl); 2331 return NULL; 2332 } 2333 if (!standalone) { 2334 rte_rwlock_write_lock(&priv->ind_tbls_lock); 2335 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next); 2336 rte_rwlock_write_unlock(&priv->ind_tbls_lock); 2337 } 2338 return ind_tbl; 2339 } 2340 2341 static int 2342 mlx5_ind_table_obj_check_standalone(struct rte_eth_dev *dev __rte_unused, 2343 struct mlx5_ind_table_obj *ind_tbl) 2344 { 2345 uint32_t refcnt; 2346 2347 refcnt = __atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED); 2348 if (refcnt <= 1) 2349 return 0; 2350 /* 2351 * Modification of indirection tables having more than 1 2352 * reference is unsupported. 2353 */ 2354 DRV_LOG(DEBUG, 2355 "Port %u cannot modify indirection table %p (refcnt %u > 1).", 2356 dev->data->port_id, (void *)ind_tbl, refcnt); 2357 rte_errno = EINVAL; 2358 return -rte_errno; 2359 } 2360 2361 /** 2362 * Modify an indirection table. 2363 * 2364 * @param dev 2365 * Pointer to Ethernet device. 2366 * @param ind_table 2367 * Indirection table to modify. 2368 * @param queues 2369 * Queues replacement for the indirection table. 2370 * @param queues_n 2371 * Number of queues in the array. 2372 * @param standalone 2373 * Indirection table for Standalone queue. 2374 * 2375 * @return 2376 * 0 on success, a negative errno value otherwise and rte_errno is set. 2377 */ 2378 int 2379 mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, 2380 struct mlx5_ind_table_obj *ind_tbl, 2381 uint16_t *queues, const uint32_t queues_n, 2382 bool standalone) 2383 { 2384 struct mlx5_priv *priv = dev->data->dev_private; 2385 unsigned int i; 2386 int ret = 0, err; 2387 const unsigned int n = rte_is_power_of_2(queues_n) ? 2388 log2above(queues_n) : 2389 log2above(priv->config.ind_table_max_size); 2390 2391 MLX5_ASSERT(standalone); 2392 RTE_SET_USED(standalone); 2393 if (mlx5_ind_table_obj_check_standalone(dev, ind_tbl) < 0) 2394 return -rte_errno; 2395 for (i = 0; i != queues_n; ++i) { 2396 if (!mlx5_rxq_get(dev, queues[i])) { 2397 ret = -rte_errno; 2398 goto error; 2399 } 2400 } 2401 MLX5_ASSERT(priv->obj_ops.ind_table_modify); 2402 ret = priv->obj_ops.ind_table_modify(dev, n, queues, queues_n, ind_tbl); 2403 if (ret) 2404 goto error; 2405 ind_tbl->queues_n = queues_n; 2406 ind_tbl->queues = queues; 2407 return 0; 2408 error: 2409 err = rte_errno; 2410 rte_errno = err; 2411 DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", 2412 dev->data->port_id); 2413 return ret; 2414 } 2415 2416 /** 2417 * Attach an indirection table to its queues. 2418 * 2419 * @param dev 2420 * Pointer to Ethernet device. 2421 * @param ind_table 2422 * Indirection table to attach. 2423 * 2424 * @return 2425 * 0 on success, a negative errno value otherwise and rte_errno is set. 2426 */ 2427 int 2428 mlx5_ind_table_obj_attach(struct rte_eth_dev *dev, 2429 struct mlx5_ind_table_obj *ind_tbl) 2430 { 2431 unsigned int i; 2432 int ret; 2433 2434 ret = mlx5_ind_table_obj_modify(dev, ind_tbl, ind_tbl->queues, 2435 ind_tbl->queues_n, true); 2436 if (ret != 0) { 2437 DRV_LOG(ERR, "Port %u could not modify indirect table obj %p", 2438 dev->data->port_id, (void *)ind_tbl); 2439 return ret; 2440 } 2441 for (i = 0; i < ind_tbl->queues_n; i++) 2442 mlx5_rxq_ref(dev, ind_tbl->queues[i]); 2443 return 0; 2444 } 2445 2446 /** 2447 * Detach an indirection table from its queues. 2448 * 2449 * @param dev 2450 * Pointer to Ethernet device. 2451 * @param ind_table 2452 * Indirection table to detach. 2453 * 2454 * @return 2455 * 0 on success, a negative errno value otherwise and rte_errno is set. 2456 */ 2457 int 2458 mlx5_ind_table_obj_detach(struct rte_eth_dev *dev, 2459 struct mlx5_ind_table_obj *ind_tbl) 2460 { 2461 struct mlx5_priv *priv = dev->data->dev_private; 2462 const unsigned int n = rte_is_power_of_2(ind_tbl->queues_n) ? 2463 log2above(ind_tbl->queues_n) : 2464 log2above(priv->config.ind_table_max_size); 2465 unsigned int i; 2466 int ret; 2467 2468 ret = mlx5_ind_table_obj_check_standalone(dev, ind_tbl); 2469 if (ret != 0) 2470 return ret; 2471 MLX5_ASSERT(priv->obj_ops.ind_table_modify); 2472 ret = priv->obj_ops.ind_table_modify(dev, n, NULL, 0, ind_tbl); 2473 if (ret != 0) { 2474 DRV_LOG(ERR, "Port %u could not modify indirect table obj %p", 2475 dev->data->port_id, (void *)ind_tbl); 2476 return ret; 2477 } 2478 for (i = 0; i < ind_tbl->queues_n; i++) 2479 mlx5_rxq_release(dev, ind_tbl->queues[i]); 2480 return ret; 2481 } 2482 2483 int 2484 mlx5_hrxq_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry, 2485 void *cb_ctx) 2486 { 2487 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 2488 struct mlx5_flow_rss_desc *rss_desc = ctx->data; 2489 struct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry); 2490 2491 return (hrxq->rss_key_len != rss_desc->key_len || 2492 memcmp(hrxq->rss_key, rss_desc->key, rss_desc->key_len) || 2493 hrxq->hash_fields != rss_desc->hash_fields || 2494 hrxq->ind_table->queues_n != rss_desc->queue_num || 2495 memcmp(hrxq->ind_table->queues, rss_desc->queue, 2496 rss_desc->queue_num * sizeof(rss_desc->queue[0]))); 2497 } 2498 2499 /** 2500 * Modify an Rx Hash queue configuration. 2501 * 2502 * @param dev 2503 * Pointer to Ethernet device. 2504 * @param hrxq 2505 * Index to Hash Rx queue to modify. 2506 * @param rss_key 2507 * RSS key for the Rx hash queue. 2508 * @param rss_key_len 2509 * RSS key length. 2510 * @param hash_fields 2511 * Verbs protocol hash field to make the RSS on. 2512 * @param queues 2513 * Queues entering in hash queue. In case of empty hash_fields only the 2514 * first queue index will be taken for the indirection table. 2515 * @param queues_n 2516 * Number of queues. 2517 * 2518 * @return 2519 * 0 on success, a negative errno value otherwise and rte_errno is set. 2520 */ 2521 int 2522 mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx, 2523 const uint8_t *rss_key, uint32_t rss_key_len, 2524 uint64_t hash_fields, 2525 const uint16_t *queues, uint32_t queues_n) 2526 { 2527 int err; 2528 struct mlx5_ind_table_obj *ind_tbl = NULL; 2529 struct mlx5_priv *priv = dev->data->dev_private; 2530 struct mlx5_hrxq *hrxq = 2531 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx); 2532 int ret; 2533 2534 if (!hrxq) { 2535 rte_errno = EINVAL; 2536 return -rte_errno; 2537 } 2538 /* validations */ 2539 if (hrxq->rss_key_len != rss_key_len) { 2540 /* rss_key_len is fixed size 40 byte & not supposed to change */ 2541 rte_errno = EINVAL; 2542 return -rte_errno; 2543 } 2544 queues_n = hash_fields ? queues_n : 1; 2545 if (mlx5_ind_table_obj_match_queues(hrxq->ind_table, 2546 queues, queues_n)) { 2547 ind_tbl = hrxq->ind_table; 2548 } else { 2549 if (hrxq->standalone) { 2550 /* 2551 * Replacement of indirection table unsupported for 2552 * stanalone hrxq objects (used by shared RSS). 2553 */ 2554 rte_errno = ENOTSUP; 2555 return -rte_errno; 2556 } 2557 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n); 2558 if (!ind_tbl) 2559 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, 2560 hrxq->standalone); 2561 } 2562 if (!ind_tbl) { 2563 rte_errno = ENOMEM; 2564 return -rte_errno; 2565 } 2566 MLX5_ASSERT(priv->obj_ops.hrxq_modify); 2567 ret = priv->obj_ops.hrxq_modify(dev, hrxq, rss_key, 2568 hash_fields, ind_tbl); 2569 if (ret) { 2570 rte_errno = errno; 2571 goto error; 2572 } 2573 if (ind_tbl != hrxq->ind_table) { 2574 MLX5_ASSERT(!hrxq->standalone); 2575 mlx5_ind_table_obj_release(dev, hrxq->ind_table, 2576 hrxq->standalone); 2577 hrxq->ind_table = ind_tbl; 2578 } 2579 hrxq->hash_fields = hash_fields; 2580 memcpy(hrxq->rss_key, rss_key, rss_key_len); 2581 return 0; 2582 error: 2583 err = rte_errno; 2584 if (ind_tbl != hrxq->ind_table) { 2585 MLX5_ASSERT(!hrxq->standalone); 2586 mlx5_ind_table_obj_release(dev, ind_tbl, hrxq->standalone); 2587 } 2588 rte_errno = err; 2589 return -rte_errno; 2590 } 2591 2592 static void 2593 __mlx5_hrxq_remove(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq) 2594 { 2595 struct mlx5_priv *priv = dev->data->dev_private; 2596 2597 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2598 mlx5_glue->destroy_flow_action(hrxq->action); 2599 #endif 2600 priv->obj_ops.hrxq_destroy(hrxq); 2601 if (!hrxq->standalone) { 2602 mlx5_ind_table_obj_release(dev, hrxq->ind_table, 2603 hrxq->standalone); 2604 } 2605 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq->idx); 2606 } 2607 2608 /** 2609 * Release the hash Rx queue. 2610 * 2611 * @param dev 2612 * Pointer to Ethernet device. 2613 * @param hrxq 2614 * Index to Hash Rx queue to release. 2615 * 2616 * @param list 2617 * mlx5 list pointer. 2618 * @param entry 2619 * Hash queue entry pointer. 2620 */ 2621 void 2622 mlx5_hrxq_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 2623 { 2624 struct rte_eth_dev *dev = tool_ctx; 2625 struct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry); 2626 2627 __mlx5_hrxq_remove(dev, hrxq); 2628 } 2629 2630 static struct mlx5_hrxq * 2631 __mlx5_hrxq_create(struct rte_eth_dev *dev, 2632 struct mlx5_flow_rss_desc *rss_desc) 2633 { 2634 struct mlx5_priv *priv = dev->data->dev_private; 2635 const uint8_t *rss_key = rss_desc->key; 2636 uint32_t rss_key_len = rss_desc->key_len; 2637 bool standalone = !!rss_desc->shared_rss; 2638 const uint16_t *queues = 2639 standalone ? rss_desc->const_q : rss_desc->queue; 2640 uint32_t queues_n = rss_desc->queue_num; 2641 struct mlx5_hrxq *hrxq = NULL; 2642 uint32_t hrxq_idx = 0; 2643 struct mlx5_ind_table_obj *ind_tbl = rss_desc->ind_tbl; 2644 int ret; 2645 2646 queues_n = rss_desc->hash_fields ? queues_n : 1; 2647 if (!ind_tbl) 2648 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n); 2649 if (!ind_tbl) 2650 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, 2651 standalone); 2652 if (!ind_tbl) 2653 return NULL; 2654 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx); 2655 if (!hrxq) 2656 goto error; 2657 hrxq->standalone = standalone; 2658 hrxq->idx = hrxq_idx; 2659 hrxq->ind_table = ind_tbl; 2660 hrxq->rss_key_len = rss_key_len; 2661 hrxq->hash_fields = rss_desc->hash_fields; 2662 memcpy(hrxq->rss_key, rss_key, rss_key_len); 2663 ret = priv->obj_ops.hrxq_new(dev, hrxq, rss_desc->tunnel); 2664 if (ret < 0) 2665 goto error; 2666 return hrxq; 2667 error: 2668 if (!rss_desc->ind_tbl) 2669 mlx5_ind_table_obj_release(dev, ind_tbl, standalone); 2670 if (hrxq) 2671 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx); 2672 return NULL; 2673 } 2674 2675 struct mlx5_list_entry * 2676 mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx) 2677 { 2678 struct rte_eth_dev *dev = tool_ctx; 2679 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 2680 struct mlx5_flow_rss_desc *rss_desc = ctx->data; 2681 struct mlx5_hrxq *hrxq; 2682 2683 hrxq = __mlx5_hrxq_create(dev, rss_desc); 2684 return hrxq ? &hrxq->entry : NULL; 2685 } 2686 2687 struct mlx5_list_entry * 2688 mlx5_hrxq_clone_cb(void *tool_ctx, struct mlx5_list_entry *entry, 2689 void *cb_ctx __rte_unused) 2690 { 2691 struct rte_eth_dev *dev = tool_ctx; 2692 struct mlx5_priv *priv = dev->data->dev_private; 2693 struct mlx5_hrxq *hrxq; 2694 uint32_t hrxq_idx = 0; 2695 2696 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx); 2697 if (!hrxq) 2698 return NULL; 2699 memcpy(hrxq, entry, sizeof(*hrxq) + MLX5_RSS_HASH_KEY_LEN); 2700 hrxq->idx = hrxq_idx; 2701 return &hrxq->entry; 2702 } 2703 2704 void 2705 mlx5_hrxq_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 2706 { 2707 struct rte_eth_dev *dev = tool_ctx; 2708 struct mlx5_priv *priv = dev->data->dev_private; 2709 struct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry); 2710 2711 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq->idx); 2712 } 2713 2714 /** 2715 * Get an Rx Hash queue. 2716 * 2717 * @param dev 2718 * Pointer to Ethernet device. 2719 * @param rss_desc 2720 * RSS configuration for the Rx hash queue. 2721 * 2722 * @return 2723 * An hash Rx queue index on success. 2724 */ 2725 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, 2726 struct mlx5_flow_rss_desc *rss_desc) 2727 { 2728 struct mlx5_priv *priv = dev->data->dev_private; 2729 struct mlx5_hrxq *hrxq; 2730 struct mlx5_list_entry *entry; 2731 struct mlx5_flow_cb_ctx ctx = { 2732 .data = rss_desc, 2733 }; 2734 2735 if (rss_desc->shared_rss) { 2736 hrxq = __mlx5_hrxq_create(dev, rss_desc); 2737 } else { 2738 entry = mlx5_list_register(priv->hrxqs, &ctx); 2739 if (!entry) 2740 return 0; 2741 hrxq = container_of(entry, typeof(*hrxq), entry); 2742 } 2743 if (hrxq) 2744 return hrxq->idx; 2745 return 0; 2746 } 2747 2748 /** 2749 * Release the hash Rx queue. 2750 * 2751 * @param dev 2752 * Pointer to Ethernet device. 2753 * @param hrxq_idx 2754 * Index to Hash Rx queue to release. 2755 * 2756 * @return 2757 * 1 while a reference on it exists, 0 when freed. 2758 */ 2759 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx) 2760 { 2761 struct mlx5_priv *priv = dev->data->dev_private; 2762 struct mlx5_hrxq *hrxq; 2763 2764 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx); 2765 if (!hrxq) 2766 return 0; 2767 if (!hrxq->standalone) 2768 return mlx5_list_unregister(priv->hrxqs, &hrxq->entry); 2769 __mlx5_hrxq_remove(dev, hrxq); 2770 return 0; 2771 } 2772 2773 /** 2774 * Create a drop Rx Hash queue. 2775 * 2776 * @param dev 2777 * Pointer to Ethernet device. 2778 * 2779 * @return 2780 * The Verbs/DevX object initialized, NULL otherwise and rte_errno is set. 2781 */ 2782 struct mlx5_hrxq * 2783 mlx5_drop_action_create(struct rte_eth_dev *dev) 2784 { 2785 struct mlx5_priv *priv = dev->data->dev_private; 2786 struct mlx5_hrxq *hrxq = NULL; 2787 int ret; 2788 2789 if (priv->drop_queue.hrxq) 2790 return priv->drop_queue.hrxq; 2791 hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY); 2792 if (!hrxq) { 2793 DRV_LOG(WARNING, 2794 "Port %u cannot allocate memory for drop queue.", 2795 dev->data->port_id); 2796 rte_errno = ENOMEM; 2797 goto error; 2798 } 2799 priv->drop_queue.hrxq = hrxq; 2800 hrxq->ind_table = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq->ind_table), 2801 0, SOCKET_ID_ANY); 2802 if (!hrxq->ind_table) { 2803 rte_errno = ENOMEM; 2804 goto error; 2805 } 2806 ret = priv->obj_ops.drop_action_create(dev); 2807 if (ret < 0) 2808 goto error; 2809 return hrxq; 2810 error: 2811 if (hrxq) { 2812 if (hrxq->ind_table) 2813 mlx5_free(hrxq->ind_table); 2814 priv->drop_queue.hrxq = NULL; 2815 mlx5_free(hrxq); 2816 } 2817 return NULL; 2818 } 2819 2820 /** 2821 * Release a drop hash Rx queue. 2822 * 2823 * @param dev 2824 * Pointer to Ethernet device. 2825 */ 2826 void 2827 mlx5_drop_action_destroy(struct rte_eth_dev *dev) 2828 { 2829 struct mlx5_priv *priv = dev->data->dev_private; 2830 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq; 2831 2832 if (!priv->drop_queue.hrxq) 2833 return; 2834 priv->obj_ops.drop_action_destroy(dev); 2835 mlx5_free(priv->drop_queue.rxq); 2836 mlx5_free(hrxq->ind_table); 2837 mlx5_free(hrxq); 2838 priv->drop_queue.rxq = NULL; 2839 priv->drop_queue.hrxq = NULL; 2840 } 2841 2842 /** 2843 * Verify the Rx Queue list is empty 2844 * 2845 * @param dev 2846 * Pointer to Ethernet device. 2847 * 2848 * @return 2849 * The number of object not released. 2850 */ 2851 uint32_t 2852 mlx5_hrxq_verify(struct rte_eth_dev *dev) 2853 { 2854 struct mlx5_priv *priv = dev->data->dev_private; 2855 2856 return mlx5_list_get_entry_num(priv->hrxqs); 2857 } 2858 2859 /** 2860 * Set the Rx queue timestamp conversion parameters 2861 * 2862 * @param[in] dev 2863 * Pointer to the Ethernet device structure. 2864 */ 2865 void 2866 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev) 2867 { 2868 struct mlx5_priv *priv = dev->data->dev_private; 2869 struct mlx5_dev_ctx_shared *sh = priv->sh; 2870 unsigned int i; 2871 2872 for (i = 0; i != priv->rxqs_n; ++i) { 2873 struct mlx5_rxq_data *data = mlx5_rxq_data_get(dev, i); 2874 2875 if (data == NULL) 2876 continue; 2877 data->sh = sh; 2878 data->rt_timestamp = priv->config.rt_timestamp; 2879 } 2880 } 2881