1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 6WIND S.A. 3 * Copyright 2021 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RX_H_ 7 #define RTE_PMD_MLX5_RX_H_ 8 9 #include <stdint.h> 10 #include <sys/queue.h> 11 12 #include <rte_mbuf.h> 13 #include <rte_mempool.h> 14 #include <rte_common.h> 15 #include <rte_spinlock.h> 16 17 #include <mlx5_common_mr.h> 18 19 #include "mlx5.h" 20 #include "mlx5_autoconf.h" 21 #include "mlx5_mr.h" 22 23 /* Support tunnel matching. */ 24 #define MLX5_FLOW_TUNNEL 10 25 26 struct mlx5_rxq_stats { 27 #ifdef MLX5_PMD_SOFT_COUNTERS 28 uint64_t ipackets; /**< Total of successfully received packets. */ 29 uint64_t ibytes; /**< Total of successfully received bytes. */ 30 #endif 31 uint64_t idropped; /**< Total of packets dropped when RX ring full. */ 32 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ 33 }; 34 35 /* Compressed CQE context. */ 36 struct rxq_zip { 37 uint16_t ai; /* Array index. */ 38 uint16_t ca; /* Current array index. */ 39 uint16_t na; /* Next array index. */ 40 uint16_t cq_ci; /* The next CQE. */ 41 uint32_t cqe_cnt; /* Number of CQEs. */ 42 }; 43 44 /* Multi-Packet RQ buffer header. */ 45 struct mlx5_mprq_buf { 46 struct rte_mempool *mp; 47 uint16_t refcnt; /* Atomically accessed refcnt. */ 48 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */ 49 struct rte_mbuf_ext_shared_info shinfos[]; 50 /* 51 * Shared information per stride. 52 * More memory will be allocated for the first stride head-room and for 53 * the strides data. 54 */ 55 } __rte_cache_aligned; 56 57 /* Get pointer to the first stride. */ 58 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \ 59 sizeof(struct mlx5_mprq_buf) + \ 60 (strd_n) * \ 61 sizeof(struct rte_mbuf_ext_shared_info) + \ 62 RTE_PKTMBUF_HEADROOM)) 63 64 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 65 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 66 67 enum mlx5_rxq_err_state { 68 MLX5_RXQ_ERR_STATE_NO_ERROR = 0, 69 MLX5_RXQ_ERR_STATE_NEED_RESET, 70 MLX5_RXQ_ERR_STATE_NEED_READY, 71 }; 72 73 enum mlx5_rqx_code { 74 MLX5_RXQ_CODE_EXIT = 0, 75 MLX5_RXQ_CODE_NOMBUF, 76 MLX5_RXQ_CODE_DROPPED, 77 }; 78 79 struct mlx5_eth_rxseg { 80 struct rte_mempool *mp; /**< Memory pool to allocate segment from. */ 81 uint16_t length; /**< Segment data length, configures split point. */ 82 uint16_t offset; /**< Data offset from beginning of mbuf data buffer. */ 83 uint32_t reserved; /**< Reserved field. */ 84 }; 85 86 /* RX queue descriptor. */ 87 struct mlx5_rxq_data { 88 unsigned int csum:1; /* Enable checksum offloading. */ 89 unsigned int hw_timestamp:1; /* Enable HW timestamp. */ 90 unsigned int rt_timestamp:1; /* Realtime timestamp format. */ 91 unsigned int vlan_strip:1; /* Enable VLAN stripping. */ 92 unsigned int crc_present:1; /* CRC must be subtracted. */ 93 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */ 94 unsigned int cqe_n:4; /* Log 2 of CQ elements. */ 95 unsigned int elts_n:4; /* Log 2 of Mbufs. */ 96 unsigned int rss_hash:1; /* RSS hash result is enabled. */ 97 unsigned int mark:1; /* Marked flow available on the queue. */ 98 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */ 99 unsigned int strd_sz_n:4; /* Log 2 of stride size. */ 100 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */ 101 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */ 102 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */ 103 unsigned int lro:1; /* Enable LRO. */ 104 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */ 105 unsigned int mcqe_format:3; /* CQE compression format. */ 106 volatile uint32_t *rq_db; 107 volatile uint32_t *cq_db; 108 uint16_t port_id; 109 uint32_t elts_ci; 110 uint32_t rq_ci; 111 uint16_t consumed_strd; /* Number of consumed strides in WQE. */ 112 uint32_t rq_pi; 113 uint32_t cq_ci; 114 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */ 115 uint32_t byte_mask; 116 union { 117 struct rxq_zip zip; /* Compressed context. */ 118 uint16_t decompressed; 119 /* Number of ready mbufs decompressed from the CQ. */ 120 }; 121 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 122 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */ 123 volatile void *wqes; 124 volatile struct mlx5_cqe(*cqes)[]; 125 struct rte_mbuf *(*elts)[]; 126 struct mlx5_mprq_buf *(*mprq_bufs)[]; 127 struct rte_mempool *mp; 128 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 129 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */ 130 struct mlx5_dev_ctx_shared *sh; /* Shared context. */ 131 uint16_t idx; /* Queue index. */ 132 struct mlx5_rxq_stats stats; 133 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ 134 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ 135 void *cq_uar; /* Verbs CQ user access region. */ 136 uint32_t cqn; /* CQ number. */ 137 uint8_t cq_arm_sn; /* CQ arm seq number. */ 138 #ifndef RTE_ARCH_64 139 rte_spinlock_t *uar_lock_cq; 140 /* CQ (UAR) access lock required for 32bit implementations */ 141 #endif 142 uint32_t tunnel; /* Tunnel information. */ 143 int timestamp_offset; /* Dynamic mbuf field for timestamp. */ 144 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */ 145 uint64_t flow_meta_mask; 146 int32_t flow_meta_offset; 147 uint32_t flow_meta_port_mask; 148 uint32_t rxseg_n; /* Number of split segment descriptions. */ 149 struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG]; 150 /* Buffer split segment descriptions - sizes, offsets, pools. */ 151 } __rte_cache_aligned; 152 153 enum mlx5_rxq_type { 154 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */ 155 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ 156 MLX5_RXQ_TYPE_UNDEFINED, 157 }; 158 159 /* RX queue control descriptor. */ 160 struct mlx5_rxq_ctrl { 161 struct mlx5_rxq_data rxq; /* Data path structure. */ 162 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ 163 uint32_t refcnt; /* Reference counter. */ 164 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */ 165 struct mlx5_priv *priv; /* Back pointer to private data. */ 166 enum mlx5_rxq_type type; /* Rxq type. */ 167 unsigned int socket; /* CPU socket ID for allocations. */ 168 unsigned int irq:1; /* Whether IRQ is enabled. */ 169 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ 170 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ 171 uint32_t wqn; /* WQ number. */ 172 uint16_t dump_file_n; /* Number of dump files. */ 173 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ 174 uint32_t hairpin_status; /* Hairpin binding status. */ 175 }; 176 177 /* mlx5_rxq.c */ 178 179 extern uint8_t rss_hash_default_key[]; 180 181 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data); 182 int mlx5_mprq_free_mp(struct rte_eth_dev *dev); 183 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); 184 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); 185 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); 186 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); 187 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); 188 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 189 unsigned int socket, const struct rte_eth_rxconf *conf, 190 struct rte_mempool *mp); 191 int mlx5_rx_hairpin_queue_setup 192 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 193 const struct rte_eth_hairpin_conf *hairpin_conf); 194 void mlx5_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 195 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); 196 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); 197 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 198 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 199 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); 200 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, 201 uint16_t desc, unsigned int socket, 202 const struct rte_eth_rxconf *conf, 203 const struct rte_eth_rxseg_split *rx_seg, 204 uint16_t n_seg); 205 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new 206 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 207 const struct rte_eth_hairpin_conf *hairpin_conf); 208 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx); 209 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); 210 int mlx5_rxq_verify(struct rte_eth_dev *dev); 211 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); 212 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev); 213 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev, 214 const uint16_t *queues, 215 uint32_t queues_n); 216 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev, 217 struct mlx5_ind_table_obj *ind_tbl, 218 bool standalone); 219 int mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, 220 struct mlx5_ind_table_obj *ind_tbl); 221 int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, 222 struct mlx5_ind_table_obj *ind_tbl, 223 uint16_t *queues, const uint32_t queues_n, 224 bool standalone); 225 struct mlx5_list_entry *mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx); 226 int mlx5_hrxq_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 227 void *cb_ctx); 228 void mlx5_hrxq_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 229 struct mlx5_list_entry *mlx5_hrxq_clone_cb(void *tool_ctx, 230 struct mlx5_list_entry *entry, 231 void *cb_ctx __rte_unused); 232 void mlx5_hrxq_clone_free_cb(void *tool_ctx __rte_unused, 233 struct mlx5_list_entry *entry); 234 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, 235 struct mlx5_flow_rss_desc *rss_desc); 236 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); 237 uint32_t mlx5_hrxq_verify(struct rte_eth_dev *dev); 238 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx); 239 const struct rte_eth_hairpin_conf *mlx5_rxq_get_hairpin_conf 240 (struct rte_eth_dev *dev, uint16_t idx); 241 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev); 242 void mlx5_drop_action_destroy(struct rte_eth_dev *dev); 243 uint64_t mlx5_get_rx_port_offloads(void); 244 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); 245 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); 246 int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx, 247 const uint8_t *rss_key, uint32_t rss_key_len, 248 uint64_t hash_fields, 249 const uint16_t *queues, uint32_t queues_n); 250 251 /* mlx5_rx.c */ 252 253 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); 254 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq); 255 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec); 256 void mlx5_mprq_buf_free_cb(void *addr, void *opaque); 257 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf); 258 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, 259 uint16_t pkts_n); 260 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, 261 uint16_t pkts_n); 262 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset); 263 uint32_t mlx5_rx_queue_count(void *rx_queue); 264 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 265 struct rte_eth_rxq_info *qinfo); 266 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 267 struct rte_eth_burst_mode *mode); 268 int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); 269 270 /* Vectorized version of mlx5_rx.c */ 271 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); 272 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev); 273 uint16_t mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, 274 uint16_t pkts_n); 275 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts, 276 uint16_t pkts_n); 277 278 static int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); 279 280 /** 281 * Query LKey from a packet buffer for Rx. No need to flush local caches 282 * as the Rx mempool database entries are valid for the lifetime of the queue. 283 * 284 * @param rxq 285 * Pointer to Rx queue structure. 286 * @param addr 287 * Address to search. 288 * 289 * @return 290 * Searched LKey on success, UINT32_MAX on no match. 291 * This function always succeeds on valid input. 292 */ 293 static __rte_always_inline uint32_t 294 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr) 295 { 296 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; 297 struct mlx5_rxq_ctrl *rxq_ctrl; 298 struct rte_mempool *mp; 299 uint32_t lkey; 300 301 /* Linear search on MR cache array. */ 302 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 303 MLX5_MR_CACHE_N, addr); 304 if (likely(lkey != UINT32_MAX)) 305 return lkey; 306 /* 307 * Slower search in the mempool database on miss. 308 * During queue creation rxq->sh is not yet set, so we use rxq_ctrl. 309 */ 310 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq); 311 mp = mlx5_rxq_mprq_enabled(rxq) ? rxq->mprq_mp : rxq->mp; 312 return mlx5_mr_mempool2mr_bh(&rxq_ctrl->priv->sh->share_cache, 313 mr_ctrl, mp, addr); 314 } 315 316 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr)) 317 318 /** 319 * Convert timestamp from HW format to linear counter 320 * from Packet Pacing Clock Queue CQE timestamp format. 321 * 322 * @param sh 323 * Pointer to the device shared context. Might be needed 324 * to convert according current device configuration. 325 * @param ts 326 * Timestamp from CQE to convert. 327 * @return 328 * UTC in nanoseconds 329 */ 330 static __rte_always_inline uint64_t 331 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts) 332 { 333 RTE_SET_USED(sh); 334 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S; 335 } 336 337 /** 338 * Set timestamp in mbuf dynamic field. 339 * 340 * @param mbuf 341 * Structure to write into. 342 * @param offset 343 * Dynamic field offset in mbuf structure. 344 * @param timestamp 345 * Value to write. 346 */ 347 static __rte_always_inline void 348 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset, 349 rte_mbuf_timestamp_t timestamp) 350 { 351 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp; 352 } 353 354 /** 355 * Replace MPRQ buffer. 356 * 357 * @param rxq 358 * Pointer to Rx queue structure. 359 * @param rq_idx 360 * RQ index to replace. 361 */ 362 static __rte_always_inline void 363 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx) 364 { 365 const uint32_t strd_n = 1 << rxq->strd_num_n; 366 struct mlx5_mprq_buf *rep = rxq->mprq_repl; 367 volatile struct mlx5_wqe_data_seg *wqe = 368 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg; 369 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx]; 370 void *addr; 371 372 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) { 373 MLX5_ASSERT(rep != NULL); 374 /* Replace MPRQ buf. */ 375 (*rxq->mprq_bufs)[rq_idx] = rep; 376 /* Replace WQE. */ 377 addr = mlx5_mprq_buf_addr(rep, strd_n); 378 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr); 379 /* If there's only one MR, no need to replace LKey in WQE. */ 380 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1)) 381 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr); 382 /* Stash a mbuf for next replacement. */ 383 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep))) 384 rxq->mprq_repl = rep; 385 else 386 rxq->mprq_repl = NULL; 387 /* Release the old buffer. */ 388 mlx5_mprq_buf_free(buf); 389 } else if (unlikely(rxq->mprq_repl == NULL)) { 390 struct mlx5_mprq_buf *rep; 391 392 /* 393 * Currently, the MPRQ mempool is out of buffer 394 * and doing memcpy regardless of the size of Rx 395 * packet. Retry allocation to get back to 396 * normal. 397 */ 398 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep)) 399 rxq->mprq_repl = rep; 400 } 401 } 402 403 /** 404 * Attach or copy MPRQ buffer content to a packet. 405 * 406 * @param rxq 407 * Pointer to Rx queue structure. 408 * @param pkt 409 * Pointer to a packet to fill. 410 * @param len 411 * Packet length. 412 * @param buf 413 * Pointer to a MPRQ buffer to take the data from. 414 * @param strd_idx 415 * Stride index to start from. 416 * @param strd_cnt 417 * Number of strides to consume. 418 */ 419 static __rte_always_inline enum mlx5_rqx_code 420 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len, 421 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt) 422 { 423 const uint32_t strd_n = 1 << rxq->strd_num_n; 424 const uint16_t strd_sz = 1 << rxq->strd_sz_n; 425 const uint16_t strd_shift = 426 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en; 427 const int32_t hdrm_overlap = 428 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz; 429 const uint32_t offset = strd_idx * strd_sz + strd_shift; 430 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset); 431 432 /* 433 * Memcpy packets to the target mbuf if: 434 * - The size of packet is smaller than mprq_max_memcpy_len. 435 * - Out of buffer in the Mempool for Multi-Packet RQ. 436 * - The packet's stride overlaps a headroom and scatter is off. 437 */ 438 if (len <= rxq->mprq_max_memcpy_len || 439 rxq->mprq_repl == NULL || 440 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) { 441 if (likely(len <= 442 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) { 443 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), 444 addr, len); 445 DATA_LEN(pkt) = len; 446 } else if (rxq->strd_scatter_en) { 447 struct rte_mbuf *prev = pkt; 448 uint32_t seg_len = RTE_MIN(len, (uint32_t) 449 (pkt->buf_len - RTE_PKTMBUF_HEADROOM)); 450 uint32_t rem_len = len - seg_len; 451 452 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), 453 addr, seg_len); 454 DATA_LEN(pkt) = seg_len; 455 while (rem_len) { 456 struct rte_mbuf *next = 457 rte_pktmbuf_alloc(rxq->mp); 458 459 if (unlikely(next == NULL)) 460 return MLX5_RXQ_CODE_NOMBUF; 461 NEXT(prev) = next; 462 SET_DATA_OFF(next, 0); 463 addr = RTE_PTR_ADD(addr, seg_len); 464 seg_len = RTE_MIN(rem_len, (uint32_t) 465 (next->buf_len - RTE_PKTMBUF_HEADROOM)); 466 rte_memcpy 467 (rte_pktmbuf_mtod(next, void *), 468 addr, seg_len); 469 DATA_LEN(next) = seg_len; 470 rem_len -= seg_len; 471 prev = next; 472 ++NB_SEGS(pkt); 473 } 474 } else { 475 return MLX5_RXQ_CODE_DROPPED; 476 } 477 } else { 478 rte_iova_t buf_iova; 479 struct rte_mbuf_ext_shared_info *shinfo; 480 uint16_t buf_len = strd_cnt * strd_sz; 481 void *buf_addr; 482 483 /* Increment the refcnt of the whole chunk. */ 484 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED); 485 MLX5_ASSERT(__atomic_load_n(&buf->refcnt, 486 __ATOMIC_RELAXED) <= strd_n + 1); 487 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM); 488 /* 489 * MLX5 device doesn't use iova but it is necessary in a 490 * case where the Rx packet is transmitted via a 491 * different PMD. 492 */ 493 buf_iova = rte_mempool_virt2iova(buf) + 494 RTE_PTR_DIFF(buf_addr, buf); 495 shinfo = &buf->shinfos[strd_idx]; 496 rte_mbuf_ext_refcnt_set(shinfo, 1); 497 /* 498 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when 499 * attaching the stride to mbuf and more offload flags 500 * will be added below by calling rxq_cq_to_mbuf(). 501 * Other fields will be overwritten. 502 */ 503 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova, 504 buf_len, shinfo); 505 /* Set mbuf head-room. */ 506 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM); 507 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF); 508 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >= 509 len - (hdrm_overlap > 0 ? hdrm_overlap : 0)); 510 DATA_LEN(pkt) = len; 511 /* 512 * Copy the last fragment of a packet (up to headroom 513 * size bytes) in case there is a stride overlap with 514 * a next packet's headroom. Allocate a separate mbuf 515 * to store this fragment and link it. Scatter is on. 516 */ 517 if (hdrm_overlap > 0) { 518 MLX5_ASSERT(rxq->strd_scatter_en); 519 struct rte_mbuf *seg = 520 rte_pktmbuf_alloc(rxq->mp); 521 522 if (unlikely(seg == NULL)) 523 return MLX5_RXQ_CODE_NOMBUF; 524 SET_DATA_OFF(seg, 0); 525 rte_memcpy(rte_pktmbuf_mtod(seg, void *), 526 RTE_PTR_ADD(addr, len - hdrm_overlap), 527 hdrm_overlap); 528 DATA_LEN(seg) = hdrm_overlap; 529 DATA_LEN(pkt) = len - hdrm_overlap; 530 NEXT(pkt) = seg; 531 NB_SEGS(pkt) = 2; 532 } 533 } 534 return MLX5_RXQ_CODE_EXIT; 535 } 536 537 /** 538 * Check whether Multi-Packet RQ can be enabled for the device. 539 * 540 * @param dev 541 * Pointer to Ethernet device. 542 * 543 * @return 544 * 1 if supported, negative errno value if not. 545 */ 546 static __rte_always_inline int 547 mlx5_check_mprq_support(struct rte_eth_dev *dev) 548 { 549 struct mlx5_priv *priv = dev->data->dev_private; 550 551 if (priv->config.mprq.enabled && 552 priv->rxqs_n >= priv->config.mprq.min_rxqs_num) 553 return 1; 554 return -ENOTSUP; 555 } 556 557 /** 558 * Check whether Multi-Packet RQ is enabled for the Rx queue. 559 * 560 * @param rxq 561 * Pointer to receive queue structure. 562 * 563 * @return 564 * 0 if disabled, otherwise enabled. 565 */ 566 static __rte_always_inline int 567 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq) 568 { 569 return rxq->strd_num_n > 0; 570 } 571 572 /** 573 * Check whether Multi-Packet RQ is enabled for the device. 574 * 575 * @param dev 576 * Pointer to Ethernet device. 577 * 578 * @return 579 * 0 if disabled, otherwise enabled. 580 */ 581 static __rte_always_inline int 582 mlx5_mprq_enabled(struct rte_eth_dev *dev) 583 { 584 struct mlx5_priv *priv = dev->data->dev_private; 585 uint32_t i; 586 uint16_t n = 0; 587 uint16_t n_ibv = 0; 588 589 if (mlx5_check_mprq_support(dev) < 0) 590 return 0; 591 /* All the configured queues should be enabled. */ 592 for (i = 0; i < priv->rxqs_n; ++i) { 593 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i]; 594 struct mlx5_rxq_ctrl *rxq_ctrl = container_of 595 (rxq, struct mlx5_rxq_ctrl, rxq); 596 597 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD) 598 continue; 599 n_ibv++; 600 if (mlx5_rxq_mprq_enabled(rxq)) 601 ++n; 602 } 603 /* Multi-Packet RQ can't be partially configured. */ 604 MLX5_ASSERT(n == 0 || n == n_ibv); 605 return n == n_ibv; 606 } 607 608 #endif /* RTE_PMD_MLX5_RX_H_ */ 609