1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_atomic.h> 25 #include <rte_alarm.h> 26 #include <rte_mtr.h> 27 28 #include "mlx5.h" 29 #include "mlx5_prm.h" 30 31 /* Private rte flow items. */ 32 enum mlx5_rte_flow_item_type { 33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 36 }; 37 38 /* Private (internal) rte flow actions. */ 39 enum mlx5_rte_flow_action_type { 40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 41 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 42 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 44 }; 45 46 /* Matches on selected register. */ 47 struct mlx5_rte_flow_item_tag { 48 enum modify_reg id; 49 uint32_t data; 50 }; 51 52 /* Modify selected register. */ 53 struct mlx5_rte_flow_action_set_tag { 54 enum modify_reg id; 55 uint32_t data; 56 }; 57 58 struct mlx5_flow_action_copy_mreg { 59 enum modify_reg dst; 60 enum modify_reg src; 61 }; 62 63 /* Matches on source queue. */ 64 struct mlx5_rte_flow_item_tx_queue { 65 uint32_t queue; 66 }; 67 68 /* Feature name to allocate metadata register. */ 69 enum mlx5_feature_name { 70 MLX5_HAIRPIN_RX, 71 MLX5_HAIRPIN_TX, 72 MLX5_METADATA_RX, 73 MLX5_METADATA_TX, 74 MLX5_METADATA_FDB, 75 MLX5_FLOW_MARK, 76 MLX5_APP_TAG, 77 MLX5_COPY_MARK, 78 MLX5_MTR_COLOR, 79 MLX5_MTR_SFX, 80 }; 81 82 /* Pattern outer Layer bits. */ 83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 89 90 /* Pattern inner Layer bits. */ 91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 97 98 /* Pattern tunnel Layer bits. */ 99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 101 #define MLX5_FLOW_LAYER_GRE (1u << 14) 102 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 103 /* List of tunnel Layer bits continued below. */ 104 105 /* General pattern items bits. */ 106 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 108 #define MLX5_FLOW_ITEM_TAG (1u << 18) 109 #define MLX5_FLOW_ITEM_MARK (1u << 19) 110 111 /* Pattern MISC bits. */ 112 #define MLX5_FLOW_LAYER_ICMP (1u << 19) 113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20) 114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21) 115 116 /* Pattern tunnel Layer bits (continued). */ 117 #define MLX5_FLOW_LAYER_IPIP (1u << 21) 118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22) 119 #define MLX5_FLOW_LAYER_NVGRE (1u << 23) 120 #define MLX5_FLOW_LAYER_GENEVE (1u << 24) 121 122 /* Queue items. */ 123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25) 124 125 /* Outer Masks. */ 126 #define MLX5_FLOW_LAYER_OUTER_L3 \ 127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 128 #define MLX5_FLOW_LAYER_OUTER_L4 \ 129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 130 #define MLX5_FLOW_LAYER_OUTER \ 131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 132 MLX5_FLOW_LAYER_OUTER_L4) 133 134 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */ 135 #define MLX5_FLOW_LAYER_IPV4_LRO \ 136 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP) 137 #define MLX5_FLOW_LAYER_IPV6_LRO \ 138 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP) 139 140 /* Tunnel Masks. */ 141 #define MLX5_FLOW_LAYER_TUNNEL \ 142 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 143 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 144 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 145 MLX5_FLOW_LAYER_GENEVE) 146 147 /* Inner Masks. */ 148 #define MLX5_FLOW_LAYER_INNER_L3 \ 149 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 150 #define MLX5_FLOW_LAYER_INNER_L4 \ 151 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 152 #define MLX5_FLOW_LAYER_INNER \ 153 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 154 MLX5_FLOW_LAYER_INNER_L4) 155 156 /* Layer Masks. */ 157 #define MLX5_FLOW_LAYER_L2 \ 158 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 159 #define MLX5_FLOW_LAYER_L3_IPV4 \ 160 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 161 #define MLX5_FLOW_LAYER_L3_IPV6 \ 162 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 163 #define MLX5_FLOW_LAYER_L3 \ 164 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 165 #define MLX5_FLOW_LAYER_L4 \ 166 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 167 168 /* Actions */ 169 #define MLX5_FLOW_ACTION_DROP (1u << 0) 170 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 171 #define MLX5_FLOW_ACTION_RSS (1u << 2) 172 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 173 #define MLX5_FLOW_ACTION_MARK (1u << 4) 174 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 175 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 176 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 177 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 179 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 180 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 181 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 182 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 183 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 184 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 185 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 186 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 187 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 188 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 189 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 190 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 191 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 192 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 193 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 194 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 195 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 196 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 197 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28) 198 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29) 199 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30) 200 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31) 201 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32) 202 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33) 203 #define MLX5_FLOW_ACTION_SET_META (1ull << 34) 204 #define MLX5_FLOW_ACTION_METER (1ull << 35) 205 206 #define MLX5_FLOW_FATE_ACTIONS \ 207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 208 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) 209 210 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 211 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 212 MLX5_FLOW_ACTION_JUMP) 213 214 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 215 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 216 MLX5_FLOW_ACTION_RAW_ENCAP | \ 217 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 218 219 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 220 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 221 MLX5_FLOW_ACTION_RAW_DECAP | \ 222 MLX5_FLOW_ACTION_OF_POP_VLAN) 223 224 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 225 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 226 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 227 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 228 MLX5_FLOW_ACTION_SET_TP_SRC | \ 229 MLX5_FLOW_ACTION_SET_TP_DST | \ 230 MLX5_FLOW_ACTION_SET_TTL | \ 231 MLX5_FLOW_ACTION_DEC_TTL | \ 232 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 233 MLX5_FLOW_ACTION_SET_MAC_DST | \ 234 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 235 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 236 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 237 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 238 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 239 MLX5_FLOW_ACTION_SET_TAG | \ 240 MLX5_FLOW_ACTION_MARK_EXT | \ 241 MLX5_FLOW_ACTION_SET_META) 242 243 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 244 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 245 #ifndef IPPROTO_MPLS 246 #define IPPROTO_MPLS 137 247 #endif 248 249 /* UDP port number for MPLS */ 250 #define MLX5_UDP_PORT_MPLS 6635 251 252 /* UDP port numbers for VxLAN. */ 253 #define MLX5_UDP_PORT_VXLAN 4789 254 #define MLX5_UDP_PORT_VXLAN_GPE 4790 255 256 /* UDP port numbers for GENEVE. */ 257 #define MLX5_UDP_PORT_GENEVE 6081 258 259 /* Priority reserved for default flows. */ 260 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 261 262 /* 263 * Number of sub priorities. 264 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 265 * matching on the NIC (firmware dependent) L4 most have the higher priority 266 * followed by L3 and ending with L2. 267 */ 268 #define MLX5_PRIORITY_MAP_L2 2 269 #define MLX5_PRIORITY_MAP_L3 1 270 #define MLX5_PRIORITY_MAP_L4 0 271 #define MLX5_PRIORITY_MAP_MAX 3 272 273 /* Valid layer type for IPV4 RSS. */ 274 #define MLX5_IPV4_LAYER_TYPES \ 275 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 276 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 277 ETH_RSS_NONFRAG_IPV4_OTHER) 278 279 /* IBV hash source bits for IPV4. */ 280 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 281 282 /* Valid layer type for IPV6 RSS. */ 283 #define MLX5_IPV6_LAYER_TYPES \ 284 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 285 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 286 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 287 288 /* IBV hash source bits for IPV6. */ 289 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 290 291 292 /* Geneve header first 16Bit */ 293 #define MLX5_GENEVE_VER_MASK 0x3 294 #define MLX5_GENEVE_VER_SHIFT 14 295 #define MLX5_GENEVE_VER_VAL(a) \ 296 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 297 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 298 #define MLX5_GENEVE_OPTLEN_SHIFT 7 299 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 300 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 301 #define MLX5_GENEVE_OAMF_MASK 0x1 302 #define MLX5_GENEVE_OAMF_SHIFT 7 303 #define MLX5_GENEVE_OAMF_VAL(a) \ 304 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 305 #define MLX5_GENEVE_CRITO_MASK 0x1 306 #define MLX5_GENEVE_CRITO_SHIFT 6 307 #define MLX5_GENEVE_CRITO_VAL(a) \ 308 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 309 #define MLX5_GENEVE_RSVD_MASK 0x3F 310 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 311 /* 312 * The length of the Geneve options fields, expressed in four byte multiples, 313 * not including the eight byte fixed tunnel. 314 */ 315 #define MLX5_GENEVE_OPT_LEN_0 14 316 #define MLX5_GENEVE_OPT_LEN_1 63 317 318 enum mlx5_flow_drv_type { 319 MLX5_FLOW_TYPE_MIN, 320 MLX5_FLOW_TYPE_DV, 321 MLX5_FLOW_TYPE_VERBS, 322 MLX5_FLOW_TYPE_MAX, 323 }; 324 325 /* Matcher PRM representation */ 326 struct mlx5_flow_dv_match_params { 327 size_t size; 328 /**< Size of match value. Do NOT split size and key! */ 329 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 330 /**< Matcher value. This value is used as the mask or as a key. */ 331 }; 332 333 /* Matcher structure. */ 334 struct mlx5_flow_dv_matcher { 335 LIST_ENTRY(mlx5_flow_dv_matcher) next; 336 /**< Pointer to the next element. */ 337 struct mlx5_flow_tbl_resource *tbl; 338 /**< Pointer to the table(group) the matcher associated with. */ 339 rte_atomic32_t refcnt; /**< Reference counter. */ 340 void *matcher_object; /**< Pointer to DV matcher */ 341 uint16_t crc; /**< CRC of key. */ 342 uint16_t priority; /**< Priority of matcher. */ 343 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 344 }; 345 346 #define MLX5_ENCAP_MAX_LEN 132 347 348 /* Encap/decap resource structure. */ 349 struct mlx5_flow_dv_encap_decap_resource { 350 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 351 /* Pointer to next element. */ 352 rte_atomic32_t refcnt; /**< Reference counter. */ 353 void *verbs_action; 354 /**< Verbs encap/decap action object. */ 355 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 356 size_t size; 357 uint8_t reformat_type; 358 uint8_t ft_type; 359 uint64_t flags; /**< Flags for RDMA API. */ 360 }; 361 362 /* Tag resource structure. */ 363 struct mlx5_flow_dv_tag_resource { 364 struct mlx5_hlist_entry entry; 365 /**< hash list entry for tag resource, tag value as the key. */ 366 void *action; 367 /**< Verbs tag action object. */ 368 rte_atomic32_t refcnt; /**< Reference counter. */ 369 }; 370 371 /* 372 * Number of modification commands. 373 * If extensive metadata registers are supported 374 * the maximal actions amount is 16 and 8 otherwise. 375 */ 376 #define MLX5_MODIFY_NUM 16 377 #define MLX5_MODIFY_NUM_NO_MREG 8 378 379 /* Modify resource structure */ 380 struct mlx5_flow_dv_modify_hdr_resource { 381 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 382 /* Pointer to next element. */ 383 rte_atomic32_t refcnt; /**< Reference counter. */ 384 struct ibv_flow_action *verbs_action; 385 /**< Verbs modify header action object. */ 386 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 387 uint32_t actions_num; /**< Number of modification actions. */ 388 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM]; 389 /**< Modification actions. */ 390 uint64_t flags; /**< Flags for RDMA API. */ 391 }; 392 393 /* Jump action resource structure. */ 394 struct mlx5_flow_dv_jump_tbl_resource { 395 rte_atomic32_t refcnt; /**< Reference counter. */ 396 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 397 void *action; /**< Pointer to the rdma core action. */ 398 }; 399 400 /* Port ID resource structure. */ 401 struct mlx5_flow_dv_port_id_action_resource { 402 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next; 403 /* Pointer to next element. */ 404 rte_atomic32_t refcnt; /**< Reference counter. */ 405 void *action; 406 /**< Verbs tag action object. */ 407 uint32_t port_id; /**< Port ID value. */ 408 }; 409 410 /* Push VLAN action resource structure */ 411 struct mlx5_flow_dv_push_vlan_action_resource { 412 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next; 413 /* Pointer to next element. */ 414 rte_atomic32_t refcnt; /**< Reference counter. */ 415 void *action; /**< Direct verbs action object. */ 416 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 417 rte_be32_t vlan_tag; /**< VLAN tag value. */ 418 }; 419 420 /* Metadata register copy table entry. */ 421 struct mlx5_flow_mreg_copy_resource { 422 /* 423 * Hash list entry for copy table. 424 * - Key is 32/64-bit MARK action ID. 425 * - MUST be the first entry. 426 */ 427 struct mlx5_hlist_entry hlist_ent; 428 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 429 /* List entry for device flows. */ 430 uint32_t refcnt; /* Reference counter. */ 431 uint32_t appcnt; /* Apply/Remove counter. */ 432 struct rte_flow *flow; /* Built flow for copy. */ 433 }; 434 435 /* Table data structure of the hash organization. */ 436 struct mlx5_flow_tbl_data_entry { 437 struct mlx5_hlist_entry entry; 438 /**< hash list entry, 64-bits key inside. */ 439 struct mlx5_flow_tbl_resource tbl; 440 /**< flow table resource. */ 441 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 442 /**< matchers' header associated with the flow table. */ 443 struct mlx5_flow_dv_jump_tbl_resource jump; 444 /**< jump resource, at most one for each table created. */ 445 }; 446 447 /* 448 * Max number of actions per DV flow. 449 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 450 * In rdma-core file providers/mlx5/verbs.c 451 */ 452 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 453 454 /* DV flows structure. */ 455 struct mlx5_flow_dv { 456 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 457 /* Flow DV api: */ 458 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 459 struct mlx5_flow_dv_match_params value; 460 /**< Holds the value that the packet is compared to. */ 461 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 462 /**< Pointer to encap/decap resource in cache. */ 463 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 464 /**< Pointer to modify header resource in cache. */ 465 struct ibv_flow *flow; /**< Installed flow. */ 466 struct mlx5_flow_dv_jump_tbl_resource *jump; 467 /**< Pointer to the jump action resource. */ 468 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 469 /**< Pointer to port ID action resource. */ 470 struct mlx5_vf_vlan vf_vlan; 471 /**< Structure for VF VLAN workaround. */ 472 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 473 /**< Pointer to push VLAN action resource in cache. */ 474 struct mlx5_flow_dv_tag_resource *tag_resource; 475 /**< pointer to the tag action. */ 476 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 477 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 478 /**< Action list. */ 479 #endif 480 int actions_n; /**< number of actions. */ 481 }; 482 483 /* Verbs specification header. */ 484 struct ibv_spec_header { 485 enum ibv_flow_spec_type type; 486 uint16_t size; 487 }; 488 489 /** Handles information leading to a drop fate. */ 490 struct mlx5_flow_verbs { 491 LIST_ENTRY(mlx5_flow_verbs) next; 492 unsigned int size; /**< Size of the attribute. */ 493 struct { 494 struct ibv_flow_attr *attr; 495 /**< Pointer to the Specification buffer. */ 496 uint8_t *specs; /**< Pointer to the specifications. */ 497 }; 498 struct ibv_flow *flow; /**< Verbs flow pointer. */ 499 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 500 struct mlx5_vf_vlan vf_vlan; 501 /**< Structure for VF VLAN workaround. */ 502 }; 503 504 struct mlx5_flow_rss { 505 uint32_t level; 506 uint32_t queue_num; /**< Number of entries in @p queue. */ 507 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 508 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 509 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 510 }; 511 512 /** Device flow structure. */ 513 struct mlx5_flow { 514 LIST_ENTRY(mlx5_flow) next; 515 struct rte_flow *flow; /**< Pointer to the main flow. */ 516 uint64_t layers; 517 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 518 uint64_t actions; 519 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 520 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 521 uint8_t ingress; /**< 1 if the flow is ingress. */ 522 uint32_t group; /**< The group index. */ 523 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 524 union { 525 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 526 struct mlx5_flow_dv dv; 527 #endif 528 struct mlx5_flow_verbs verbs; 529 }; 530 union { 531 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */ 532 uint32_t mtr_flow_id; /**< Unique meter match flow id. */ 533 }; 534 bool external; /**< true if the flow is created external to PMD. */ 535 }; 536 537 /* Flow meter state. */ 538 #define MLX5_FLOW_METER_DISABLE 0 539 #define MLX5_FLOW_METER_ENABLE 1 540 541 #define MLX5_MAN_WIDTH 8 542 /* Modify this value if enum rte_mtr_color changes. */ 543 #define RTE_MTR_DROPPED RTE_COLORS 544 545 /* Meter policer statistics */ 546 struct mlx5_flow_policer_stats { 547 struct mlx5_flow_counter *cnt[RTE_COLORS + 1]; 548 /**< Color counter, extra for drop. */ 549 uint64_t stats_mask; 550 /**< Statistics mask for the colors. */ 551 }; 552 553 /* Meter table structure. */ 554 struct mlx5_meter_domain_info { 555 struct mlx5_flow_tbl_resource *tbl; 556 /**< Meter table. */ 557 void *any_matcher; 558 /**< Meter color not match default criteria. */ 559 void *color_matcher; 560 /**< Meter color match criteria. */ 561 void *jump_actn; 562 /**< Meter match action. */ 563 void *policer_rules[RTE_MTR_DROPPED + 1]; 564 /**< Meter policer for the match. */ 565 }; 566 567 /* Meter table set for TX RX FDB. */ 568 struct mlx5_meter_domains_infos { 569 uint32_t ref_cnt; 570 /**< Table user count. */ 571 struct mlx5_meter_domain_info egress; 572 /**< TX meter table. */ 573 struct mlx5_meter_domain_info ingress; 574 /**< RX meter table. */ 575 struct mlx5_meter_domain_info transfer; 576 /**< FDB meter table. */ 577 void *drop_actn; 578 /**< Drop action as not matched. */ 579 void *count_actns[RTE_MTR_DROPPED + 1]; 580 /**< Counters for match and unmatched statistics. */ 581 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 582 /**< Flow meter parameter. */ 583 size_t fmp_size; 584 /**< Flow meter parameter size. */ 585 void *meter_action; 586 /**< Flow meter action. */ 587 }; 588 589 /* Meter parameter structure. */ 590 struct mlx5_flow_meter { 591 TAILQ_ENTRY(mlx5_flow_meter) next; 592 /**< Pointer to the next flow meter structure. */ 593 uint32_t meter_id; 594 /**< Meter id. */ 595 struct rte_mtr_params params; 596 /**< Meter rule parameters. */ 597 struct mlx5_flow_meter_profile *profile; 598 /**< Meter profile parameters. */ 599 struct rte_flow_attr attr; 600 /**< Flow attributes. */ 601 struct mlx5_meter_domains_infos *mfts; 602 /**< Flow table created for this meter. */ 603 struct mlx5_flow_policer_stats policer_stats; 604 /**< Meter policer statistics. */ 605 uint32_t ref_cnt; 606 /**< Use count. */ 607 uint32_t active_state:1; 608 /**< Meter state. */ 609 uint32_t shared:1; 610 /**< Meter shared or not. */ 611 }; 612 613 /* RFC2697 parameter structure. */ 614 struct mlx5_flow_meter_srtcm_rfc2697_prm { 615 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 616 uint32_t cbs_exponent:5; 617 uint32_t cbs_mantissa:8; 618 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 619 uint32_t cir_exponent:5; 620 uint32_t cir_mantissa:8; 621 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 622 uint32_t ebs_exponent:5; 623 uint32_t ebs_mantissa:8; 624 }; 625 626 /* Flow meter profile structure. */ 627 struct mlx5_flow_meter_profile { 628 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 629 /**< Pointer to the next flow meter structure. */ 630 uint32_t meter_profile_id; /**< Profile id. */ 631 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 632 union { 633 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 634 /**< srtcm_rfc2697 struct. */ 635 }; 636 uint32_t ref_cnt; /**< Use count. */ 637 }; 638 639 /* Flow structure. */ 640 struct rte_flow { 641 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 642 enum mlx5_flow_drv_type drv_type; /**< Driver type. */ 643 struct mlx5_flow_rss rss; /**< RSS context. */ 644 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 645 struct mlx5_flow_mreg_copy_resource *mreg_copy; 646 /**< pointer to metadata register copy table resource. */ 647 struct mlx5_flow_meter *meter; /**< Holds flow meter. */ 648 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 649 /**< Device flows that are part of the flow. */ 650 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 651 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */ 652 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */ 653 }; 654 655 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 656 const struct rte_flow_attr *attr, 657 const struct rte_flow_item items[], 658 const struct rte_flow_action actions[], 659 bool external, 660 struct rte_flow_error *error); 661 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 662 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 663 const struct rte_flow_action actions[], struct rte_flow_error *error); 664 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 665 struct mlx5_flow *dev_flow, 666 const struct rte_flow_attr *attr, 667 const struct rte_flow_item items[], 668 const struct rte_flow_action actions[], 669 struct rte_flow_error *error); 670 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 671 struct rte_flow_error *error); 672 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 673 struct rte_flow *flow); 674 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 675 struct rte_flow *flow); 676 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 677 struct rte_flow *flow, 678 const struct rte_flow_action *actions, 679 void *data, 680 struct rte_flow_error *error); 681 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 682 (struct rte_eth_dev *dev, 683 const struct mlx5_flow_meter *fm); 684 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 685 struct mlx5_meter_domains_infos *tbls); 686 typedef int (*mlx5_flow_create_policer_rules_t) 687 (struct rte_eth_dev *dev, 688 struct mlx5_flow_meter *fm, 689 const struct rte_flow_attr *attr); 690 typedef int (*mlx5_flow_destroy_policer_rules_t) 691 (struct rte_eth_dev *dev, 692 const struct mlx5_flow_meter *fm, 693 const struct rte_flow_attr *attr); 694 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t) 695 (struct rte_eth_dev *dev); 696 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 697 struct mlx5_flow_counter *cnt); 698 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 699 struct mlx5_flow_counter *cnt, 700 bool clear, uint64_t *pkts, 701 uint64_t *bytes); 702 struct mlx5_flow_driver_ops { 703 mlx5_flow_validate_t validate; 704 mlx5_flow_prepare_t prepare; 705 mlx5_flow_translate_t translate; 706 mlx5_flow_apply_t apply; 707 mlx5_flow_remove_t remove; 708 mlx5_flow_destroy_t destroy; 709 mlx5_flow_query_t query; 710 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 711 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 712 mlx5_flow_create_policer_rules_t create_policer_rules; 713 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 714 mlx5_flow_counter_alloc_t counter_alloc; 715 mlx5_flow_counter_free_t counter_free; 716 mlx5_flow_counter_query_t counter_query; 717 }; 718 719 720 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \ 721 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) 722 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \ 723 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) 724 725 /* mlx5_flow.c */ 726 727 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void); 728 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool); 729 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id); 730 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, 731 uint32_t id); 732 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, 733 bool external, uint32_t group, uint32_t *table, 734 struct rte_flow_error *error); 735 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 736 uint64_t layer_types, 737 uint64_t hash_fields); 738 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 739 uint32_t subpriority); 740 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 741 enum mlx5_feature_name feature, 742 uint32_t id, 743 struct rte_flow_error *error); 744 const struct rte_flow_action *mlx5_flow_find_action 745 (const struct rte_flow_action *actions, 746 enum rte_flow_action_type action); 747 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 748 const struct rte_flow_attr *attr, 749 struct rte_flow_error *error); 750 int mlx5_flow_validate_action_drop(uint64_t action_flags, 751 const struct rte_flow_attr *attr, 752 struct rte_flow_error *error); 753 int mlx5_flow_validate_action_flag(uint64_t action_flags, 754 const struct rte_flow_attr *attr, 755 struct rte_flow_error *error); 756 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 757 uint64_t action_flags, 758 const struct rte_flow_attr *attr, 759 struct rte_flow_error *error); 760 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 761 uint64_t action_flags, 762 struct rte_eth_dev *dev, 763 const struct rte_flow_attr *attr, 764 struct rte_flow_error *error); 765 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 766 uint64_t action_flags, 767 struct rte_eth_dev *dev, 768 const struct rte_flow_attr *attr, 769 uint64_t item_flags, 770 struct rte_flow_error *error); 771 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 772 const struct rte_flow_attr *attributes, 773 struct rte_flow_error *error); 774 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 775 const uint8_t *mask, 776 const uint8_t *nic_mask, 777 unsigned int size, 778 struct rte_flow_error *error); 779 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 780 uint64_t item_flags, 781 struct rte_flow_error *error); 782 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 783 uint64_t item_flags, 784 uint8_t target_protocol, 785 struct rte_flow_error *error); 786 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 787 uint64_t item_flags, 788 const struct rte_flow_item *gre_item, 789 struct rte_flow_error *error); 790 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 791 uint64_t item_flags, 792 uint64_t last_item, 793 uint16_t ether_type, 794 const struct rte_flow_item_ipv4 *acc_mask, 795 struct rte_flow_error *error); 796 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 797 uint64_t item_flags, 798 uint64_t last_item, 799 uint16_t ether_type, 800 const struct rte_flow_item_ipv6 *acc_mask, 801 struct rte_flow_error *error); 802 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 803 const struct rte_flow_item *item, 804 uint64_t item_flags, 805 uint64_t prev_layer, 806 struct rte_flow_error *error); 807 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 808 uint64_t item_flags, 809 uint8_t target_protocol, 810 const struct rte_flow_item_tcp *flow_mask, 811 struct rte_flow_error *error); 812 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 813 uint64_t item_flags, 814 uint8_t target_protocol, 815 struct rte_flow_error *error); 816 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 817 uint64_t item_flags, 818 struct rte_eth_dev *dev, 819 struct rte_flow_error *error); 820 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 821 uint64_t item_flags, 822 struct rte_flow_error *error); 823 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 824 uint64_t item_flags, 825 struct rte_eth_dev *dev, 826 struct rte_flow_error *error); 827 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 828 uint64_t item_flags, 829 uint8_t target_protocol, 830 struct rte_flow_error *error); 831 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 832 uint64_t item_flags, 833 uint8_t target_protocol, 834 struct rte_flow_error *error); 835 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 836 uint64_t item_flags, 837 uint8_t target_protocol, 838 struct rte_flow_error *error); 839 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 840 uint64_t item_flags, 841 struct rte_eth_dev *dev, 842 struct rte_flow_error *error); 843 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 844 (struct rte_eth_dev *dev, 845 const struct mlx5_flow_meter *fm); 846 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 847 struct mlx5_meter_domains_infos *tbl); 848 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 849 struct mlx5_flow_meter *fm, 850 const struct rte_flow_attr *attr); 851 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 852 struct mlx5_flow_meter *fm, 853 const struct rte_flow_attr *attr); 854 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 855 struct rte_mtr_error *error); 856 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 857