1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_atomic.h> 25 #include <rte_alarm.h> 26 #include <rte_mtr.h> 27 28 #include "mlx5.h" 29 #include "mlx5_prm.h" 30 31 /* Private rte flow items. */ 32 enum mlx5_rte_flow_item_type { 33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 36 }; 37 38 /* Private (internal) rte flow actions. */ 39 enum mlx5_rte_flow_action_type { 40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 41 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 42 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 44 }; 45 46 /* Matches on selected register. */ 47 struct mlx5_rte_flow_item_tag { 48 enum modify_reg id; 49 uint32_t data; 50 }; 51 52 /* Modify selected register. */ 53 struct mlx5_rte_flow_action_set_tag { 54 enum modify_reg id; 55 uint32_t data; 56 }; 57 58 struct mlx5_flow_action_copy_mreg { 59 enum modify_reg dst; 60 enum modify_reg src; 61 }; 62 63 /* Matches on source queue. */ 64 struct mlx5_rte_flow_item_tx_queue { 65 uint32_t queue; 66 }; 67 68 /* Feature name to allocate metadata register. */ 69 enum mlx5_feature_name { 70 MLX5_HAIRPIN_RX, 71 MLX5_HAIRPIN_TX, 72 MLX5_METADATA_RX, 73 MLX5_METADATA_TX, 74 MLX5_METADATA_FDB, 75 MLX5_FLOW_MARK, 76 MLX5_APP_TAG, 77 MLX5_COPY_MARK, 78 MLX5_MTR_COLOR, 79 MLX5_MTR_SFX, 80 }; 81 82 /* Pattern outer Layer bits. */ 83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 89 90 /* Pattern inner Layer bits. */ 91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 97 98 /* Pattern tunnel Layer bits. */ 99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 101 #define MLX5_FLOW_LAYER_GRE (1u << 14) 102 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 103 /* List of tunnel Layer bits continued below. */ 104 105 /* General pattern items bits. */ 106 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 108 #define MLX5_FLOW_ITEM_TAG (1u << 18) 109 #define MLX5_FLOW_ITEM_MARK (1u << 19) 110 111 /* Pattern MISC bits. */ 112 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 115 116 /* Pattern tunnel Layer bits (continued). */ 117 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 119 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 120 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 121 122 /* Queue items. */ 123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 124 125 /* Outer Masks. */ 126 #define MLX5_FLOW_LAYER_OUTER_L3 \ 127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 128 #define MLX5_FLOW_LAYER_OUTER_L4 \ 129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 130 #define MLX5_FLOW_LAYER_OUTER \ 131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 132 MLX5_FLOW_LAYER_OUTER_L4) 133 134 /* Tunnel Masks. */ 135 #define MLX5_FLOW_LAYER_TUNNEL \ 136 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 137 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 138 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 139 MLX5_FLOW_LAYER_GENEVE) 140 141 /* Inner Masks. */ 142 #define MLX5_FLOW_LAYER_INNER_L3 \ 143 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 144 #define MLX5_FLOW_LAYER_INNER_L4 \ 145 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 146 #define MLX5_FLOW_LAYER_INNER \ 147 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 148 MLX5_FLOW_LAYER_INNER_L4) 149 150 /* Layer Masks. */ 151 #define MLX5_FLOW_LAYER_L2 \ 152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 153 #define MLX5_FLOW_LAYER_L3_IPV4 \ 154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 155 #define MLX5_FLOW_LAYER_L3_IPV6 \ 156 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 157 #define MLX5_FLOW_LAYER_L3 \ 158 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 159 #define MLX5_FLOW_LAYER_L4 \ 160 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 161 162 /* Actions */ 163 #define MLX5_FLOW_ACTION_DROP (1u << 0) 164 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 165 #define MLX5_FLOW_ACTION_RSS (1u << 2) 166 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 167 #define MLX5_FLOW_ACTION_MARK (1u << 4) 168 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 169 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 170 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 171 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 172 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 174 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 175 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 176 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 177 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 178 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 179 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 180 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 181 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 182 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 183 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 184 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 185 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 186 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 187 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 188 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 189 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 190 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 191 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28) 192 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29) 193 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30) 194 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31) 195 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32) 196 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33) 197 #define MLX5_FLOW_ACTION_SET_META (1ull << 34) 198 #define MLX5_FLOW_ACTION_METER (1ull << 35) 199 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 36) 200 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 37) 201 202 #define MLX5_FLOW_FATE_ACTIONS \ 203 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 204 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) 205 206 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 208 MLX5_FLOW_ACTION_JUMP) 209 210 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 211 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 212 MLX5_FLOW_ACTION_RAW_ENCAP | \ 213 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 214 215 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 216 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 217 MLX5_FLOW_ACTION_RAW_DECAP | \ 218 MLX5_FLOW_ACTION_OF_POP_VLAN) 219 220 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 221 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 222 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 223 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 224 MLX5_FLOW_ACTION_SET_TP_SRC | \ 225 MLX5_FLOW_ACTION_SET_TP_DST | \ 226 MLX5_FLOW_ACTION_SET_TTL | \ 227 MLX5_FLOW_ACTION_DEC_TTL | \ 228 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 229 MLX5_FLOW_ACTION_SET_MAC_DST | \ 230 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 231 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 232 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 233 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 234 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 235 MLX5_FLOW_ACTION_SET_TAG | \ 236 MLX5_FLOW_ACTION_MARK_EXT | \ 237 MLX5_FLOW_ACTION_SET_META | \ 238 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 239 MLX5_FLOW_ACTION_SET_IPV6_DSCP) 240 241 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 242 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 243 #ifndef IPPROTO_MPLS 244 #define IPPROTO_MPLS 137 245 #endif 246 247 /* UDP port number for MPLS */ 248 #define MLX5_UDP_PORT_MPLS 6635 249 250 /* UDP port numbers for VxLAN. */ 251 #define MLX5_UDP_PORT_VXLAN 4789 252 #define MLX5_UDP_PORT_VXLAN_GPE 4790 253 254 /* UDP port numbers for GENEVE. */ 255 #define MLX5_UDP_PORT_GENEVE 6081 256 257 /* Priority reserved for default flows. */ 258 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 259 260 /* 261 * Number of sub priorities. 262 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 263 * matching on the NIC (firmware dependent) L4 most have the higher priority 264 * followed by L3 and ending with L2. 265 */ 266 #define MLX5_PRIORITY_MAP_L2 2 267 #define MLX5_PRIORITY_MAP_L3 1 268 #define MLX5_PRIORITY_MAP_L4 0 269 #define MLX5_PRIORITY_MAP_MAX 3 270 271 /* Valid layer type for IPV4 RSS. */ 272 #define MLX5_IPV4_LAYER_TYPES \ 273 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 274 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 275 ETH_RSS_NONFRAG_IPV4_OTHER) 276 277 /* IBV hash source bits for IPV4. */ 278 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 279 280 /* Valid layer type for IPV6 RSS. */ 281 #define MLX5_IPV6_LAYER_TYPES \ 282 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 283 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 284 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 285 286 /* IBV hash source bits for IPV6. */ 287 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 288 289 /* IBV hash bits for L3 SRC. */ 290 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 291 292 /* IBV hash bits for L3 DST. */ 293 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 294 295 /* IBV hash bits for TCP. */ 296 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 297 IBV_RX_HASH_DST_PORT_TCP) 298 299 /* IBV hash bits for UDP. */ 300 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 301 IBV_RX_HASH_DST_PORT_UDP) 302 303 /* IBV hash bits for L4 SRC. */ 304 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 305 IBV_RX_HASH_SRC_PORT_UDP) 306 307 /* IBV hash bits for L4 DST. */ 308 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 309 IBV_RX_HASH_DST_PORT_UDP) 310 311 /* Geneve header first 16Bit */ 312 #define MLX5_GENEVE_VER_MASK 0x3 313 #define MLX5_GENEVE_VER_SHIFT 14 314 #define MLX5_GENEVE_VER_VAL(a) \ 315 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 316 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 317 #define MLX5_GENEVE_OPTLEN_SHIFT 7 318 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 319 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 320 #define MLX5_GENEVE_OAMF_MASK 0x1 321 #define MLX5_GENEVE_OAMF_SHIFT 7 322 #define MLX5_GENEVE_OAMF_VAL(a) \ 323 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 324 #define MLX5_GENEVE_CRITO_MASK 0x1 325 #define MLX5_GENEVE_CRITO_SHIFT 6 326 #define MLX5_GENEVE_CRITO_VAL(a) \ 327 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 328 #define MLX5_GENEVE_RSVD_MASK 0x3F 329 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 330 /* 331 * The length of the Geneve options fields, expressed in four byte multiples, 332 * not including the eight byte fixed tunnel. 333 */ 334 #define MLX5_GENEVE_OPT_LEN_0 14 335 #define MLX5_GENEVE_OPT_LEN_1 63 336 337 enum mlx5_flow_drv_type { 338 MLX5_FLOW_TYPE_MIN, 339 MLX5_FLOW_TYPE_DV, 340 MLX5_FLOW_TYPE_VERBS, 341 MLX5_FLOW_TYPE_MAX, 342 }; 343 344 /* Matcher PRM representation */ 345 struct mlx5_flow_dv_match_params { 346 size_t size; 347 /**< Size of match value. Do NOT split size and key! */ 348 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 349 /**< Matcher value. This value is used as the mask or as a key. */ 350 }; 351 352 /* Matcher structure. */ 353 struct mlx5_flow_dv_matcher { 354 LIST_ENTRY(mlx5_flow_dv_matcher) next; 355 /**< Pointer to the next element. */ 356 struct mlx5_flow_tbl_resource *tbl; 357 /**< Pointer to the table(group) the matcher associated with. */ 358 rte_atomic32_t refcnt; /**< Reference counter. */ 359 void *matcher_object; /**< Pointer to DV matcher */ 360 uint16_t crc; /**< CRC of key. */ 361 uint16_t priority; /**< Priority of matcher. */ 362 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 363 }; 364 365 #define MLX5_ENCAP_MAX_LEN 132 366 367 /* Encap/decap resource structure. */ 368 struct mlx5_flow_dv_encap_decap_resource { 369 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 370 /* Pointer to next element. */ 371 rte_atomic32_t refcnt; /**< Reference counter. */ 372 void *verbs_action; 373 /**< Verbs encap/decap action object. */ 374 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 375 size_t size; 376 uint8_t reformat_type; 377 uint8_t ft_type; 378 uint64_t flags; /**< Flags for RDMA API. */ 379 }; 380 381 /* Tag resource structure. */ 382 struct mlx5_flow_dv_tag_resource { 383 struct mlx5_hlist_entry entry; 384 /**< hash list entry for tag resource, tag value as the key. */ 385 void *action; 386 /**< Verbs tag action object. */ 387 rte_atomic32_t refcnt; /**< Reference counter. */ 388 }; 389 390 /* 391 * Number of modification commands. 392 * If extensive metadata registers are supported 393 * the maximal actions amount is 16 and 8 otherwise. 394 */ 395 #define MLX5_MODIFY_NUM 16 396 #define MLX5_MODIFY_NUM_NO_MREG 8 397 398 /* Modify resource structure */ 399 struct mlx5_flow_dv_modify_hdr_resource { 400 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 401 /* Pointer to next element. */ 402 rte_atomic32_t refcnt; /**< Reference counter. */ 403 struct ibv_flow_action *verbs_action; 404 /**< Verbs modify header action object. */ 405 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 406 uint32_t actions_num; /**< Number of modification actions. */ 407 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM]; 408 /**< Modification actions. */ 409 uint64_t flags; /**< Flags for RDMA API. */ 410 }; 411 412 /* Jump action resource structure. */ 413 struct mlx5_flow_dv_jump_tbl_resource { 414 rte_atomic32_t refcnt; /**< Reference counter. */ 415 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 416 void *action; /**< Pointer to the rdma core action. */ 417 }; 418 419 /* Port ID resource structure. */ 420 struct mlx5_flow_dv_port_id_action_resource { 421 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next; 422 /* Pointer to next element. */ 423 rte_atomic32_t refcnt; /**< Reference counter. */ 424 void *action; 425 /**< Verbs tag action object. */ 426 uint32_t port_id; /**< Port ID value. */ 427 }; 428 429 /* Push VLAN action resource structure */ 430 struct mlx5_flow_dv_push_vlan_action_resource { 431 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next; 432 /* Pointer to next element. */ 433 rte_atomic32_t refcnt; /**< Reference counter. */ 434 void *action; /**< Direct verbs action object. */ 435 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 436 rte_be32_t vlan_tag; /**< VLAN tag value. */ 437 }; 438 439 /* Metadata register copy table entry. */ 440 struct mlx5_flow_mreg_copy_resource { 441 /* 442 * Hash list entry for copy table. 443 * - Key is 32/64-bit MARK action ID. 444 * - MUST be the first entry. 445 */ 446 struct mlx5_hlist_entry hlist_ent; 447 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 448 /* List entry for device flows. */ 449 uint32_t refcnt; /* Reference counter. */ 450 uint32_t appcnt; /* Apply/Remove counter. */ 451 struct rte_flow *flow; /* Built flow for copy. */ 452 }; 453 454 /* Table data structure of the hash organization. */ 455 struct mlx5_flow_tbl_data_entry { 456 struct mlx5_hlist_entry entry; 457 /**< hash list entry, 64-bits key inside. */ 458 struct mlx5_flow_tbl_resource tbl; 459 /**< flow table resource. */ 460 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 461 /**< matchers' header associated with the flow table. */ 462 struct mlx5_flow_dv_jump_tbl_resource jump; 463 /**< jump resource, at most one for each table created. */ 464 }; 465 466 /* 467 * Max number of actions per DV flow. 468 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 469 * In rdma-core file providers/mlx5/verbs.c 470 */ 471 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 472 473 /* DV flows structure. */ 474 struct mlx5_flow_dv { 475 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 476 /* Flow DV api: */ 477 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 478 struct mlx5_flow_dv_match_params value; 479 /**< Holds the value that the packet is compared to. */ 480 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 481 /**< Pointer to encap/decap resource in cache. */ 482 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 483 /**< Pointer to modify header resource in cache. */ 484 struct ibv_flow *flow; /**< Installed flow. */ 485 struct mlx5_flow_dv_jump_tbl_resource *jump; 486 /**< Pointer to the jump action resource. */ 487 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 488 /**< Pointer to port ID action resource. */ 489 struct mlx5_vf_vlan vf_vlan; 490 /**< Structure for VF VLAN workaround. */ 491 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 492 /**< Pointer to push VLAN action resource in cache. */ 493 struct mlx5_flow_dv_tag_resource *tag_resource; 494 /**< pointer to the tag action. */ 495 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 496 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 497 /**< Action list. */ 498 #endif 499 int actions_n; /**< number of actions. */ 500 }; 501 502 /* Verbs specification header. */ 503 struct ibv_spec_header { 504 enum ibv_flow_spec_type type; 505 uint16_t size; 506 }; 507 508 /** Handles information leading to a drop fate. */ 509 struct mlx5_flow_verbs { 510 LIST_ENTRY(mlx5_flow_verbs) next; 511 unsigned int size; /**< Size of the attribute. */ 512 struct { 513 struct ibv_flow_attr *attr; 514 /**< Pointer to the Specification buffer. */ 515 uint8_t *specs; /**< Pointer to the specifications. */ 516 }; 517 struct ibv_flow *flow; /**< Verbs flow pointer. */ 518 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 519 struct mlx5_vf_vlan vf_vlan; 520 /**< Structure for VF VLAN workaround. */ 521 }; 522 523 struct mlx5_flow_rss { 524 uint32_t level; 525 uint32_t queue_num; /**< Number of entries in @p queue. */ 526 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 527 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 528 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 529 }; 530 531 /** Device flow structure. */ 532 struct mlx5_flow { 533 LIST_ENTRY(mlx5_flow) next; 534 struct rte_flow *flow; /**< Pointer to the main flow. */ 535 uint64_t layers; 536 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 537 uint64_t actions; 538 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 539 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 540 uint8_t ingress; /**< 1 if the flow is ingress. */ 541 uint32_t group; /**< The group index. */ 542 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 543 union { 544 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 545 struct mlx5_flow_dv dv; 546 #endif 547 struct mlx5_flow_verbs verbs; 548 }; 549 union { 550 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */ 551 uint32_t mtr_flow_id; /**< Unique meter match flow id. */ 552 }; 553 bool external; /**< true if the flow is created external to PMD. */ 554 }; 555 556 /* Flow meter state. */ 557 #define MLX5_FLOW_METER_DISABLE 0 558 #define MLX5_FLOW_METER_ENABLE 1 559 560 #define MLX5_MAN_WIDTH 8 561 /* Modify this value if enum rte_mtr_color changes. */ 562 #define RTE_MTR_DROPPED RTE_COLORS 563 564 /* Meter policer statistics */ 565 struct mlx5_flow_policer_stats { 566 struct mlx5_flow_counter *cnt[RTE_COLORS + 1]; 567 /**< Color counter, extra for drop. */ 568 uint64_t stats_mask; 569 /**< Statistics mask for the colors. */ 570 }; 571 572 /* Meter table structure. */ 573 struct mlx5_meter_domain_info { 574 struct mlx5_flow_tbl_resource *tbl; 575 /**< Meter table. */ 576 void *any_matcher; 577 /**< Meter color not match default criteria. */ 578 void *color_matcher; 579 /**< Meter color match criteria. */ 580 void *jump_actn; 581 /**< Meter match action. */ 582 void *policer_rules[RTE_MTR_DROPPED + 1]; 583 /**< Meter policer for the match. */ 584 }; 585 586 /* Meter table set for TX RX FDB. */ 587 struct mlx5_meter_domains_infos { 588 uint32_t ref_cnt; 589 /**< Table user count. */ 590 struct mlx5_meter_domain_info egress; 591 /**< TX meter table. */ 592 struct mlx5_meter_domain_info ingress; 593 /**< RX meter table. */ 594 struct mlx5_meter_domain_info transfer; 595 /**< FDB meter table. */ 596 void *drop_actn; 597 /**< Drop action as not matched. */ 598 void *count_actns[RTE_MTR_DROPPED + 1]; 599 /**< Counters for match and unmatched statistics. */ 600 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 601 /**< Flow meter parameter. */ 602 size_t fmp_size; 603 /**< Flow meter parameter size. */ 604 void *meter_action; 605 /**< Flow meter action. */ 606 }; 607 608 /* Meter parameter structure. */ 609 struct mlx5_flow_meter { 610 TAILQ_ENTRY(mlx5_flow_meter) next; 611 /**< Pointer to the next flow meter structure. */ 612 uint32_t meter_id; 613 /**< Meter id. */ 614 struct rte_mtr_params params; 615 /**< Meter rule parameters. */ 616 struct mlx5_flow_meter_profile *profile; 617 /**< Meter profile parameters. */ 618 struct rte_flow_attr attr; 619 /**< Flow attributes. */ 620 struct mlx5_meter_domains_infos *mfts; 621 /**< Flow table created for this meter. */ 622 struct mlx5_flow_policer_stats policer_stats; 623 /**< Meter policer statistics. */ 624 uint32_t ref_cnt; 625 /**< Use count. */ 626 uint32_t active_state:1; 627 /**< Meter state. */ 628 uint32_t shared:1; 629 /**< Meter shared or not. */ 630 }; 631 632 /* RFC2697 parameter structure. */ 633 struct mlx5_flow_meter_srtcm_rfc2697_prm { 634 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 635 uint32_t cbs_exponent:5; 636 uint32_t cbs_mantissa:8; 637 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 638 uint32_t cir_exponent:5; 639 uint32_t cir_mantissa:8; 640 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 641 uint32_t ebs_exponent:5; 642 uint32_t ebs_mantissa:8; 643 }; 644 645 /* Flow meter profile structure. */ 646 struct mlx5_flow_meter_profile { 647 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 648 /**< Pointer to the next flow meter structure. */ 649 uint32_t meter_profile_id; /**< Profile id. */ 650 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 651 union { 652 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 653 /**< srtcm_rfc2697 struct. */ 654 }; 655 uint32_t ref_cnt; /**< Use count. */ 656 }; 657 658 /* Flow structure. */ 659 struct rte_flow { 660 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 661 enum mlx5_flow_drv_type drv_type; /**< Driver type. */ 662 struct mlx5_flow_rss rss; /**< RSS context. */ 663 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 664 struct mlx5_flow_mreg_copy_resource *mreg_copy; 665 /**< pointer to metadata register copy table resource. */ 666 struct mlx5_flow_meter *meter; /**< Holds flow meter. */ 667 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 668 /**< Device flows that are part of the flow. */ 669 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 670 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */ 671 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */ 672 }; 673 674 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 675 const struct rte_flow_attr *attr, 676 const struct rte_flow_item items[], 677 const struct rte_flow_action actions[], 678 bool external, 679 struct rte_flow_error *error); 680 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 681 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 682 const struct rte_flow_action actions[], struct rte_flow_error *error); 683 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 684 struct mlx5_flow *dev_flow, 685 const struct rte_flow_attr *attr, 686 const struct rte_flow_item items[], 687 const struct rte_flow_action actions[], 688 struct rte_flow_error *error); 689 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 690 struct rte_flow_error *error); 691 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 692 struct rte_flow *flow); 693 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 694 struct rte_flow *flow); 695 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 696 struct rte_flow *flow, 697 const struct rte_flow_action *actions, 698 void *data, 699 struct rte_flow_error *error); 700 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 701 (struct rte_eth_dev *dev, 702 const struct mlx5_flow_meter *fm); 703 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 704 struct mlx5_meter_domains_infos *tbls); 705 typedef int (*mlx5_flow_create_policer_rules_t) 706 (struct rte_eth_dev *dev, 707 struct mlx5_flow_meter *fm, 708 const struct rte_flow_attr *attr); 709 typedef int (*mlx5_flow_destroy_policer_rules_t) 710 (struct rte_eth_dev *dev, 711 const struct mlx5_flow_meter *fm, 712 const struct rte_flow_attr *attr); 713 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t) 714 (struct rte_eth_dev *dev); 715 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 716 struct mlx5_flow_counter *cnt); 717 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 718 struct mlx5_flow_counter *cnt, 719 bool clear, uint64_t *pkts, 720 uint64_t *bytes); 721 struct mlx5_flow_driver_ops { 722 mlx5_flow_validate_t validate; 723 mlx5_flow_prepare_t prepare; 724 mlx5_flow_translate_t translate; 725 mlx5_flow_apply_t apply; 726 mlx5_flow_remove_t remove; 727 mlx5_flow_destroy_t destroy; 728 mlx5_flow_query_t query; 729 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 730 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 731 mlx5_flow_create_policer_rules_t create_policer_rules; 732 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 733 mlx5_flow_counter_alloc_t counter_alloc; 734 mlx5_flow_counter_free_t counter_free; 735 mlx5_flow_counter_query_t counter_query; 736 }; 737 738 739 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \ 740 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) 741 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \ 742 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) 743 744 /* mlx5_flow.c */ 745 746 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void); 747 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool); 748 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id); 749 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, 750 uint32_t id); 751 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, 752 bool external, uint32_t group, uint32_t *table, 753 struct rte_flow_error *error); 754 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 755 uint64_t layer_types, 756 uint64_t hash_fields); 757 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 758 uint32_t subpriority); 759 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 760 enum mlx5_feature_name feature, 761 uint32_t id, 762 struct rte_flow_error *error); 763 const struct rte_flow_action *mlx5_flow_find_action 764 (const struct rte_flow_action *actions, 765 enum rte_flow_action_type action); 766 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 767 const struct rte_flow_attr *attr, 768 struct rte_flow_error *error); 769 int mlx5_flow_validate_action_drop(uint64_t action_flags, 770 const struct rte_flow_attr *attr, 771 struct rte_flow_error *error); 772 int mlx5_flow_validate_action_flag(uint64_t action_flags, 773 const struct rte_flow_attr *attr, 774 struct rte_flow_error *error); 775 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 776 uint64_t action_flags, 777 const struct rte_flow_attr *attr, 778 struct rte_flow_error *error); 779 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 780 uint64_t action_flags, 781 struct rte_eth_dev *dev, 782 const struct rte_flow_attr *attr, 783 struct rte_flow_error *error); 784 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 785 uint64_t action_flags, 786 struct rte_eth_dev *dev, 787 const struct rte_flow_attr *attr, 788 uint64_t item_flags, 789 struct rte_flow_error *error); 790 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 791 const struct rte_flow_attr *attributes, 792 struct rte_flow_error *error); 793 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 794 const uint8_t *mask, 795 const uint8_t *nic_mask, 796 unsigned int size, 797 struct rte_flow_error *error); 798 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 799 uint64_t item_flags, 800 struct rte_flow_error *error); 801 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 802 uint64_t item_flags, 803 uint8_t target_protocol, 804 struct rte_flow_error *error); 805 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 806 uint64_t item_flags, 807 const struct rte_flow_item *gre_item, 808 struct rte_flow_error *error); 809 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 810 uint64_t item_flags, 811 uint64_t last_item, 812 uint16_t ether_type, 813 const struct rte_flow_item_ipv4 *acc_mask, 814 struct rte_flow_error *error); 815 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 816 uint64_t item_flags, 817 uint64_t last_item, 818 uint16_t ether_type, 819 const struct rte_flow_item_ipv6 *acc_mask, 820 struct rte_flow_error *error); 821 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 822 const struct rte_flow_item *item, 823 uint64_t item_flags, 824 uint64_t prev_layer, 825 struct rte_flow_error *error); 826 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 827 uint64_t item_flags, 828 uint8_t target_protocol, 829 const struct rte_flow_item_tcp *flow_mask, 830 struct rte_flow_error *error); 831 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 832 uint64_t item_flags, 833 uint8_t target_protocol, 834 struct rte_flow_error *error); 835 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 836 uint64_t item_flags, 837 struct rte_eth_dev *dev, 838 struct rte_flow_error *error); 839 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 840 uint64_t item_flags, 841 struct rte_flow_error *error); 842 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 843 uint64_t item_flags, 844 struct rte_eth_dev *dev, 845 struct rte_flow_error *error); 846 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 847 uint64_t item_flags, 848 uint8_t target_protocol, 849 struct rte_flow_error *error); 850 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 851 uint64_t item_flags, 852 uint8_t target_protocol, 853 struct rte_flow_error *error); 854 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 855 uint64_t item_flags, 856 uint8_t target_protocol, 857 struct rte_flow_error *error); 858 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 859 uint64_t item_flags, 860 struct rte_eth_dev *dev, 861 struct rte_flow_error *error); 862 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 863 (struct rte_eth_dev *dev, 864 const struct mlx5_flow_meter *fm); 865 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 866 struct mlx5_meter_domains_infos *tbl); 867 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 868 struct mlx5_flow_meter *fm, 869 const struct rte_flow_attr *attr); 870 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 871 struct mlx5_flow_meter *fm, 872 const struct rte_flow_attr *attr); 873 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 874 struct rte_mtr_error *error); 875 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 876