1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_atomic.h> 25 #include <rte_alarm.h> 26 #include <rte_mtr.h> 27 28 #include <mlx5_prm.h> 29 30 #include "mlx5.h" 31 32 /* Private rte flow items. */ 33 enum mlx5_rte_flow_item_type { 34 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 35 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 36 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 37 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 38 }; 39 40 /* Private (internal) rte flow actions. */ 41 enum mlx5_rte_flow_action_type { 42 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 43 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 44 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 45 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 46 }; 47 48 /* Matches on selected register. */ 49 struct mlx5_rte_flow_item_tag { 50 enum modify_reg id; 51 uint32_t data; 52 }; 53 54 /* Modify selected register. */ 55 struct mlx5_rte_flow_action_set_tag { 56 enum modify_reg id; 57 uint32_t data; 58 }; 59 60 struct mlx5_flow_action_copy_mreg { 61 enum modify_reg dst; 62 enum modify_reg src; 63 }; 64 65 /* Matches on source queue. */ 66 struct mlx5_rte_flow_item_tx_queue { 67 uint32_t queue; 68 }; 69 70 /* Feature name to allocate metadata register. */ 71 enum mlx5_feature_name { 72 MLX5_HAIRPIN_RX, 73 MLX5_HAIRPIN_TX, 74 MLX5_METADATA_RX, 75 MLX5_METADATA_TX, 76 MLX5_METADATA_FDB, 77 MLX5_FLOW_MARK, 78 MLX5_APP_TAG, 79 MLX5_COPY_MARK, 80 MLX5_MTR_COLOR, 81 MLX5_MTR_SFX, 82 }; 83 84 /* Pattern outer Layer bits. */ 85 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 86 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 87 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 88 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 89 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 90 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 91 92 /* Pattern inner Layer bits. */ 93 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 94 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 95 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 96 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 97 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 98 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 99 100 /* Pattern tunnel Layer bits. */ 101 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 102 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 103 #define MLX5_FLOW_LAYER_GRE (1u << 14) 104 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 105 /* List of tunnel Layer bits continued below. */ 106 107 /* General pattern items bits. */ 108 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 109 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 110 #define MLX5_FLOW_ITEM_TAG (1u << 18) 111 #define MLX5_FLOW_ITEM_MARK (1u << 19) 112 113 /* Pattern MISC bits. */ 114 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 115 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 116 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 117 118 /* Pattern tunnel Layer bits (continued). */ 119 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 120 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 121 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 122 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 123 124 /* Queue items. */ 125 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 126 127 /* Pattern tunnel Layer bits (continued). */ 128 #define MLX5_FLOW_LAYER_GTP (1u << 28) 129 130 /* Outer Masks. */ 131 #define MLX5_FLOW_LAYER_OUTER_L3 \ 132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 133 #define MLX5_FLOW_LAYER_OUTER_L4 \ 134 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 135 #define MLX5_FLOW_LAYER_OUTER \ 136 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 137 MLX5_FLOW_LAYER_OUTER_L4) 138 139 /* Tunnel Masks. */ 140 #define MLX5_FLOW_LAYER_TUNNEL \ 141 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 142 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 143 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 144 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 145 146 /* Inner Masks. */ 147 #define MLX5_FLOW_LAYER_INNER_L3 \ 148 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 149 #define MLX5_FLOW_LAYER_INNER_L4 \ 150 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 151 #define MLX5_FLOW_LAYER_INNER \ 152 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 153 MLX5_FLOW_LAYER_INNER_L4) 154 155 /* Layer Masks. */ 156 #define MLX5_FLOW_LAYER_L2 \ 157 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 158 #define MLX5_FLOW_LAYER_L3_IPV4 \ 159 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 160 #define MLX5_FLOW_LAYER_L3_IPV6 \ 161 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 162 #define MLX5_FLOW_LAYER_L3 \ 163 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 164 #define MLX5_FLOW_LAYER_L4 \ 165 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 166 167 /* Actions */ 168 #define MLX5_FLOW_ACTION_DROP (1u << 0) 169 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 170 #define MLX5_FLOW_ACTION_RSS (1u << 2) 171 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 172 #define MLX5_FLOW_ACTION_MARK (1u << 4) 173 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 174 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 175 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 176 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 179 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 180 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 181 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 182 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 183 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 184 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 185 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 186 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 187 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 188 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 189 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 190 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 191 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 192 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 193 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 194 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 195 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 196 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 197 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 198 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 199 #define MLX5_FLOW_ACTION_METER (1ull << 31) 200 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 201 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 202 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 203 204 #define MLX5_FLOW_FATE_ACTIONS \ 205 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 206 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) 207 208 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 209 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 210 MLX5_FLOW_ACTION_JUMP) 211 212 213 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 214 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 215 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 216 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 217 MLX5_FLOW_ACTION_SET_TP_SRC | \ 218 MLX5_FLOW_ACTION_SET_TP_DST | \ 219 MLX5_FLOW_ACTION_SET_TTL | \ 220 MLX5_FLOW_ACTION_DEC_TTL | \ 221 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 222 MLX5_FLOW_ACTION_SET_MAC_DST | \ 223 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 224 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 225 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 226 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 227 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 228 MLX5_FLOW_ACTION_SET_TAG | \ 229 MLX5_FLOW_ACTION_MARK_EXT | \ 230 MLX5_FLOW_ACTION_SET_META | \ 231 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 232 MLX5_FLOW_ACTION_SET_IPV6_DSCP) 233 234 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 235 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 236 237 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 238 239 #ifndef IPPROTO_MPLS 240 #define IPPROTO_MPLS 137 241 #endif 242 243 /* UDP port number for MPLS */ 244 #define MLX5_UDP_PORT_MPLS 6635 245 246 /* UDP port numbers for VxLAN. */ 247 #define MLX5_UDP_PORT_VXLAN 4789 248 #define MLX5_UDP_PORT_VXLAN_GPE 4790 249 250 /* UDP port numbers for GENEVE. */ 251 #define MLX5_UDP_PORT_GENEVE 6081 252 253 /* Priority reserved for default flows. */ 254 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 255 256 /* 257 * Number of sub priorities. 258 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 259 * matching on the NIC (firmware dependent) L4 most have the higher priority 260 * followed by L3 and ending with L2. 261 */ 262 #define MLX5_PRIORITY_MAP_L2 2 263 #define MLX5_PRIORITY_MAP_L3 1 264 #define MLX5_PRIORITY_MAP_L4 0 265 #define MLX5_PRIORITY_MAP_MAX 3 266 267 /* Valid layer type for IPV4 RSS. */ 268 #define MLX5_IPV4_LAYER_TYPES \ 269 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 270 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 271 ETH_RSS_NONFRAG_IPV4_OTHER) 272 273 /* IBV hash source bits for IPV4. */ 274 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 275 276 /* Valid layer type for IPV6 RSS. */ 277 #define MLX5_IPV6_LAYER_TYPES \ 278 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 279 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 280 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 281 282 /* IBV hash source bits for IPV6. */ 283 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 284 285 /* IBV hash bits for L3 SRC. */ 286 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 287 288 /* IBV hash bits for L3 DST. */ 289 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 290 291 /* IBV hash bits for TCP. */ 292 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 293 IBV_RX_HASH_DST_PORT_TCP) 294 295 /* IBV hash bits for UDP. */ 296 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 297 IBV_RX_HASH_DST_PORT_UDP) 298 299 /* IBV hash bits for L4 SRC. */ 300 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 301 IBV_RX_HASH_SRC_PORT_UDP) 302 303 /* IBV hash bits for L4 DST. */ 304 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 305 IBV_RX_HASH_DST_PORT_UDP) 306 307 /* Geneve header first 16Bit */ 308 #define MLX5_GENEVE_VER_MASK 0x3 309 #define MLX5_GENEVE_VER_SHIFT 14 310 #define MLX5_GENEVE_VER_VAL(a) \ 311 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 312 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 313 #define MLX5_GENEVE_OPTLEN_SHIFT 7 314 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 315 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 316 #define MLX5_GENEVE_OAMF_MASK 0x1 317 #define MLX5_GENEVE_OAMF_SHIFT 7 318 #define MLX5_GENEVE_OAMF_VAL(a) \ 319 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 320 #define MLX5_GENEVE_CRITO_MASK 0x1 321 #define MLX5_GENEVE_CRITO_SHIFT 6 322 #define MLX5_GENEVE_CRITO_VAL(a) \ 323 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 324 #define MLX5_GENEVE_RSVD_MASK 0x3F 325 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 326 /* 327 * The length of the Geneve options fields, expressed in four byte multiples, 328 * not including the eight byte fixed tunnel. 329 */ 330 #define MLX5_GENEVE_OPT_LEN_0 14 331 #define MLX5_GENEVE_OPT_LEN_1 63 332 333 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \ 334 sizeof(struct rte_flow_item_ipv4)) 335 336 /* Software header modify action numbers of a flow. */ 337 #define MLX5_ACT_NUM_MDF_IPV4 1 338 #define MLX5_ACT_NUM_MDF_IPV6 4 339 #define MLX5_ACT_NUM_MDF_MAC 2 340 #define MLX5_ACT_NUM_MDF_VID 1 341 #define MLX5_ACT_NUM_MDF_PORT 2 342 #define MLX5_ACT_NUM_MDF_TTL 1 343 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 344 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 345 #define MLX5_ACT_NUM_MDF_TCPACK 1 346 #define MLX5_ACT_NUM_SET_REG 1 347 #define MLX5_ACT_NUM_SET_TAG 1 348 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 349 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 350 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 351 #define MLX5_ACT_NUM_SET_DSCP 1 352 353 enum mlx5_flow_drv_type { 354 MLX5_FLOW_TYPE_MIN, 355 MLX5_FLOW_TYPE_DV, 356 MLX5_FLOW_TYPE_VERBS, 357 MLX5_FLOW_TYPE_MAX, 358 }; 359 360 /* Fate action type. */ 361 enum mlx5_flow_fate_type { 362 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 363 MLX5_FLOW_FATE_QUEUE, 364 MLX5_FLOW_FATE_JUMP, 365 MLX5_FLOW_FATE_PORT_ID, 366 MLX5_FLOW_FATE_DROP, 367 MLX5_FLOW_FATE_MAX, 368 }; 369 370 /* Matcher PRM representation */ 371 struct mlx5_flow_dv_match_params { 372 size_t size; 373 /**< Size of match value. Do NOT split size and key! */ 374 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 375 /**< Matcher value. This value is used as the mask or as a key. */ 376 }; 377 378 /* Matcher structure. */ 379 struct mlx5_flow_dv_matcher { 380 LIST_ENTRY(mlx5_flow_dv_matcher) next; 381 /**< Pointer to the next element. */ 382 struct mlx5_flow_tbl_resource *tbl; 383 /**< Pointer to the table(group) the matcher associated with. */ 384 rte_atomic32_t refcnt; /**< Reference counter. */ 385 void *matcher_object; /**< Pointer to DV matcher */ 386 uint16_t crc; /**< CRC of key. */ 387 uint16_t priority; /**< Priority of matcher. */ 388 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 389 }; 390 391 #define MLX5_ENCAP_MAX_LEN 132 392 393 /* Encap/decap resource structure. */ 394 struct mlx5_flow_dv_encap_decap_resource { 395 ILIST_ENTRY(uint32_t)next; 396 /* Pointer to next element. */ 397 rte_atomic32_t refcnt; /**< Reference counter. */ 398 void *verbs_action; 399 /**< Verbs encap/decap action object. */ 400 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 401 size_t size; 402 uint8_t reformat_type; 403 uint8_t ft_type; 404 uint64_t flags; /**< Flags for RDMA API. */ 405 }; 406 407 /* Tag resource structure. */ 408 struct mlx5_flow_dv_tag_resource { 409 struct mlx5_hlist_entry entry; 410 /**< hash list entry for tag resource, tag value as the key. */ 411 void *action; 412 /**< Verbs tag action object. */ 413 rte_atomic32_t refcnt; /**< Reference counter. */ 414 uint32_t idx; /**< Index for the index memory pool. */ 415 }; 416 417 /* 418 * Number of modification commands. 419 * The maximal actions amount in FW is some constant, and it is 16 in the 420 * latest releases. In some old releases, it will be limited to 8. 421 * Since there is no interface to query the capacity, the maximal value should 422 * be used to allow PMD to create the flow. The validation will be done in the 423 * lower driver layer or FW. A failure will be returned if exceeds the maximal 424 * supported actions number on the root table. 425 * On non-root tables, there is no limitation, but 32 is enough right now. 426 */ 427 #define MLX5_MAX_MODIFY_NUM 32 428 #define MLX5_ROOT_TBL_MODIFY_NUM 16 429 430 /* Modify resource structure */ 431 struct mlx5_flow_dv_modify_hdr_resource { 432 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 433 /* Pointer to next element. */ 434 rte_atomic32_t refcnt; /**< Reference counter. */ 435 struct ibv_flow_action *verbs_action; 436 /**< Verbs modify header action object. */ 437 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 438 uint32_t actions_num; /**< Number of modification actions. */ 439 uint64_t flags; /**< Flags for RDMA API. */ 440 struct mlx5_modification_cmd actions[]; 441 /**< Modification actions. */ 442 }; 443 444 /* Jump action resource structure. */ 445 struct mlx5_flow_dv_jump_tbl_resource { 446 rte_atomic32_t refcnt; /**< Reference counter. */ 447 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 448 void *action; /**< Pointer to the rdma core action. */ 449 }; 450 451 /* Port ID resource structure. */ 452 struct mlx5_flow_dv_port_id_action_resource { 453 ILIST_ENTRY(uint32_t)next; 454 /* Pointer to next element. */ 455 rte_atomic32_t refcnt; /**< Reference counter. */ 456 void *action; 457 /**< Verbs tag action object. */ 458 uint32_t port_id; /**< Port ID value. */ 459 }; 460 461 /* Push VLAN action resource structure */ 462 struct mlx5_flow_dv_push_vlan_action_resource { 463 ILIST_ENTRY(uint32_t)next; 464 /* Pointer to next element. */ 465 rte_atomic32_t refcnt; /**< Reference counter. */ 466 void *action; /**< Direct verbs action object. */ 467 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 468 rte_be32_t vlan_tag; /**< VLAN tag value. */ 469 }; 470 471 /* Metadata register copy table entry. */ 472 struct mlx5_flow_mreg_copy_resource { 473 /* 474 * Hash list entry for copy table. 475 * - Key is 32/64-bit MARK action ID. 476 * - MUST be the first entry. 477 */ 478 struct mlx5_hlist_entry hlist_ent; 479 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 480 /* List entry for device flows. */ 481 uint32_t refcnt; /* Reference counter. */ 482 uint32_t appcnt; /* Apply/Remove counter. */ 483 uint32_t idx; 484 uint32_t rix_flow; /* Built flow for copy. */ 485 }; 486 487 /* Table data structure of the hash organization. */ 488 struct mlx5_flow_tbl_data_entry { 489 struct mlx5_hlist_entry entry; 490 /**< hash list entry, 64-bits key inside. */ 491 struct mlx5_flow_tbl_resource tbl; 492 /**< flow table resource. */ 493 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 494 /**< matchers' header associated with the flow table. */ 495 struct mlx5_flow_dv_jump_tbl_resource jump; 496 /**< jump resource, at most one for each table created. */ 497 uint32_t idx; /**< index for the indexed mempool. */ 498 }; 499 500 /* Verbs specification header. */ 501 struct ibv_spec_header { 502 enum ibv_flow_spec_type type; 503 uint16_t size; 504 }; 505 506 /* RSS description. */ 507 struct mlx5_flow_rss_desc { 508 uint32_t level; 509 uint32_t queue_num; /**< Number of entries in @p queue. */ 510 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 511 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 512 uint16_t queue[]; /**< Destination queues to redirect traffic to. */ 513 }; 514 515 516 /** Device flow handle structure for DV mode only. */ 517 struct mlx5_flow_handle_dv { 518 /* Flow DV api: */ 519 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 520 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 521 /**< Pointer to modify header resource in cache. */ 522 uint32_t rix_encap_decap; 523 /**< Index to encap/decap resource in cache. */ 524 uint32_t rix_push_vlan; 525 /**< Index to push VLAN action resource in cache. */ 526 uint32_t rix_tag; 527 /**< Index to the tag action. */ 528 } __rte_packed; 529 530 /** Device flow handle structure: used both for creating & destroying. */ 531 struct mlx5_flow_handle { 532 SILIST_ENTRY(uint32_t)next; 533 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 534 /**< Index to next device flow handle. */ 535 uint64_t layers; 536 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 537 void *ib_flow; /**< Verbs flow pointer. */ 538 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 539 uint32_t mark:1; /**< Metadate rxq mark flag. */ 540 uint32_t fate_action:3; /**< Fate action type. */ 541 union { 542 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 543 uint32_t rix_jump; /**< Index to the jump action resource. */ 544 uint32_t rix_port_id_action; 545 /**< Index to port ID action resource. */ 546 uint32_t rix_fate; 547 /**< Generic value indicates the fate action. */ 548 }; 549 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 550 struct mlx5_flow_handle_dv dvh; 551 #endif 552 } __rte_packed; 553 554 /* 555 * Size for Verbs device flow handle structure only. Do not use the DV only 556 * structure in Verbs. No DV flows attributes will be accessed. 557 * Macro offsetof() could also be used here. 558 */ 559 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 560 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 561 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 562 #else 563 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 564 #endif 565 566 /* 567 * Max number of actions per DV flow. 568 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 569 * in rdma-core file providers/mlx5/verbs.c. 570 */ 571 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 572 573 /** Device flow structure only for DV flow creation. */ 574 struct mlx5_flow_dv_workspace { 575 uint32_t group; /**< The group index. */ 576 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 577 int actions_n; /**< number of actions. */ 578 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 579 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 580 /**< Pointer to encap/decap resource in cache. */ 581 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 582 /**< Pointer to push VLAN action resource in cache. */ 583 struct mlx5_flow_dv_tag_resource *tag_resource; 584 /**< pointer to the tag action. */ 585 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 586 /**< Pointer to port ID action resource. */ 587 struct mlx5_flow_dv_jump_tbl_resource *jump; 588 /**< Pointer to the jump action resource. */ 589 struct mlx5_flow_dv_match_params value; 590 /**< Holds the value that the packet is compared to. */ 591 }; 592 593 /* 594 * Maximal Verbs flow specifications & actions size. 595 * Some elements are mutually exclusive, but enough space should be allocated. 596 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 597 * 2. One tunnel header (exception: GRE + MPLS), 598 * SPEC length: GRE == tunnel. 599 * Actions: 1. 1 Mark OR Flag. 600 * 2. 1 Drop (if any). 601 * 3. No limitation for counters, but it makes no sense to support too 602 * many counters in a single device flow. 603 */ 604 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 605 #define MLX5_VERBS_MAX_SPEC_SIZE \ 606 ( \ 607 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 608 sizeof(struct ibv_flow_spec_ipv6) + \ 609 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 610 sizeof(struct ibv_flow_spec_gre) + \ 611 sizeof(struct ibv_flow_spec_mpls)) \ 612 ) 613 #else 614 #define MLX5_VERBS_MAX_SPEC_SIZE \ 615 ( \ 616 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 617 sizeof(struct ibv_flow_spec_ipv6) + \ 618 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 619 sizeof(struct ibv_flow_spec_tunnel)) \ 620 ) 621 #endif 622 623 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 624 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 625 #define MLX5_VERBS_MAX_ACT_SIZE \ 626 ( \ 627 sizeof(struct ibv_flow_spec_action_tag) + \ 628 sizeof(struct ibv_flow_spec_action_drop) + \ 629 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 630 ) 631 #else 632 #define MLX5_VERBS_MAX_ACT_SIZE \ 633 ( \ 634 sizeof(struct ibv_flow_spec_action_tag) + \ 635 sizeof(struct ibv_flow_spec_action_drop) \ 636 ) 637 #endif 638 639 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 640 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 641 642 /** Device flow structure only for Verbs flow creation. */ 643 struct mlx5_flow_verbs_workspace { 644 unsigned int size; /**< Size of the attribute. */ 645 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 646 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 647 /**< Specifications & actions buffer of verbs flow. */ 648 }; 649 650 /** Maximal number of device sub-flows supported. */ 651 #define MLX5_NUM_MAX_DEV_FLOWS 32 652 653 /** Device flow structure. */ 654 struct mlx5_flow { 655 struct rte_flow *flow; /**< Pointer to the main flow. */ 656 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 657 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 658 uint64_t act_flags; 659 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 660 bool external; /**< true if the flow is created external to PMD. */ 661 uint8_t ingress; /**< 1 if the flow is ingress. */ 662 union { 663 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 664 struct mlx5_flow_dv_workspace dv; 665 #endif 666 struct mlx5_flow_verbs_workspace verbs; 667 }; 668 struct mlx5_flow_handle *handle; 669 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 670 }; 671 672 /* Flow meter state. */ 673 #define MLX5_FLOW_METER_DISABLE 0 674 #define MLX5_FLOW_METER_ENABLE 1 675 676 #define MLX5_MAN_WIDTH 8 677 /* Modify this value if enum rte_mtr_color changes. */ 678 #define RTE_MTR_DROPPED RTE_COLORS 679 680 /* Meter policer statistics */ 681 struct mlx5_flow_policer_stats { 682 uint32_t cnt[RTE_COLORS + 1]; 683 /**< Color counter, extra for drop. */ 684 uint64_t stats_mask; 685 /**< Statistics mask for the colors. */ 686 }; 687 688 /* Meter table structure. */ 689 struct mlx5_meter_domain_info { 690 struct mlx5_flow_tbl_resource *tbl; 691 /**< Meter table. */ 692 struct mlx5_flow_tbl_resource *sfx_tbl; 693 /**< Meter suffix table. */ 694 void *any_matcher; 695 /**< Meter color not match default criteria. */ 696 void *color_matcher; 697 /**< Meter color match criteria. */ 698 void *jump_actn; 699 /**< Meter match action. */ 700 void *policer_rules[RTE_MTR_DROPPED + 1]; 701 /**< Meter policer for the match. */ 702 }; 703 704 /* Meter table set for TX RX FDB. */ 705 struct mlx5_meter_domains_infos { 706 uint32_t ref_cnt; 707 /**< Table user count. */ 708 struct mlx5_meter_domain_info egress; 709 /**< TX meter table. */ 710 struct mlx5_meter_domain_info ingress; 711 /**< RX meter table. */ 712 struct mlx5_meter_domain_info transfer; 713 /**< FDB meter table. */ 714 void *drop_actn; 715 /**< Drop action as not matched. */ 716 void *count_actns[RTE_MTR_DROPPED + 1]; 717 /**< Counters for match and unmatched statistics. */ 718 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 719 /**< Flow meter parameter. */ 720 size_t fmp_size; 721 /**< Flow meter parameter size. */ 722 void *meter_action; 723 /**< Flow meter action. */ 724 }; 725 726 /* Meter parameter structure. */ 727 struct mlx5_flow_meter { 728 TAILQ_ENTRY(mlx5_flow_meter) next; 729 /**< Pointer to the next flow meter structure. */ 730 uint32_t idx; /* Index to meter object. */ 731 uint32_t meter_id; 732 /**< Meter id. */ 733 struct mlx5_flow_meter_profile *profile; 734 /**< Meter profile parameters. */ 735 736 /** Policer actions (per meter output color). */ 737 enum rte_mtr_policer_action action[RTE_COLORS]; 738 739 /** Set of stats counters to be enabled. 740 * @see enum rte_mtr_stats_type 741 */ 742 uint64_t stats_mask; 743 744 /**< Rule applies to ingress traffic. */ 745 uint32_t ingress:1; 746 747 /**< Rule applies to egress traffic. */ 748 uint32_t egress:1; 749 /** 750 * Instead of simply matching the properties of traffic as it would 751 * appear on a given DPDK port ID, enabling this attribute transfers 752 * a flow rule to the lowest possible level of any device endpoints 753 * found in the pattern. 754 * 755 * When supported, this effectively enables an application to 756 * re-route traffic not necessarily intended for it (e.g. coming 757 * from or addressed to different physical ports, VFs or 758 * applications) at the device level. 759 * 760 * It complements the behavior of some pattern items such as 761 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 762 * 763 * When transferring flow rules, ingress and egress attributes keep 764 * their original meaning, as if processing traffic emitted or 765 * received by the application. 766 */ 767 uint32_t transfer:1; 768 struct mlx5_meter_domains_infos *mfts; 769 /**< Flow table created for this meter. */ 770 struct mlx5_flow_policer_stats policer_stats; 771 /**< Meter policer statistics. */ 772 uint32_t ref_cnt; 773 /**< Use count. */ 774 uint32_t active_state:1; 775 /**< Meter state. */ 776 uint32_t shared:1; 777 /**< Meter shared or not. */ 778 }; 779 780 /* RFC2697 parameter structure. */ 781 struct mlx5_flow_meter_srtcm_rfc2697_prm { 782 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 783 uint32_t cbs_exponent:5; 784 uint32_t cbs_mantissa:8; 785 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 786 uint32_t cir_exponent:5; 787 uint32_t cir_mantissa:8; 788 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 789 uint32_t ebs_exponent:5; 790 uint32_t ebs_mantissa:8; 791 }; 792 793 /* Flow meter profile structure. */ 794 struct mlx5_flow_meter_profile { 795 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 796 /**< Pointer to the next flow meter structure. */ 797 uint32_t meter_profile_id; /**< Profile id. */ 798 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 799 union { 800 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 801 /**< srtcm_rfc2697 struct. */ 802 }; 803 uint32_t ref_cnt; /**< Use count. */ 804 }; 805 806 /* Fdir flow structure */ 807 struct mlx5_fdir_flow { 808 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */ 809 struct mlx5_fdir *fdir; /* Pointer to fdir. */ 810 uint32_t rix_flow; /* Index to flow. */ 811 }; 812 813 #define HAIRPIN_FLOW_ID_BITS 28 814 815 /* Flow structure. */ 816 struct rte_flow { 817 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 818 uint32_t dev_handles; 819 /**< Device flow handles that are part of the flow. */ 820 uint32_t drv_type:2; /**< Driver type. */ 821 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */ 822 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS; 823 /**< The flow id used for hairpin. */ 824 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */ 825 uint32_t rix_mreg_copy; 826 /**< Index to metadata register copy table resource. */ 827 uint32_t counter; /**< Holds flow counter. */ 828 uint16_t meter; /**< Holds flow meter id. */ 829 } __rte_packed; 830 831 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 832 const struct rte_flow_attr *attr, 833 const struct rte_flow_item items[], 834 const struct rte_flow_action actions[], 835 bool external, 836 int hairpin, 837 struct rte_flow_error *error); 838 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 839 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 840 const struct rte_flow_item items[], 841 const struct rte_flow_action actions[], struct rte_flow_error *error); 842 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 843 struct mlx5_flow *dev_flow, 844 const struct rte_flow_attr *attr, 845 const struct rte_flow_item items[], 846 const struct rte_flow_action actions[], 847 struct rte_flow_error *error); 848 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 849 struct rte_flow_error *error); 850 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 851 struct rte_flow *flow); 852 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 853 struct rte_flow *flow); 854 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 855 struct rte_flow *flow, 856 const struct rte_flow_action *actions, 857 void *data, 858 struct rte_flow_error *error); 859 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 860 (struct rte_eth_dev *dev, 861 const struct mlx5_flow_meter *fm); 862 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 863 struct mlx5_meter_domains_infos *tbls); 864 typedef int (*mlx5_flow_create_policer_rules_t) 865 (struct rte_eth_dev *dev, 866 struct mlx5_flow_meter *fm, 867 const struct rte_flow_attr *attr); 868 typedef int (*mlx5_flow_destroy_policer_rules_t) 869 (struct rte_eth_dev *dev, 870 const struct mlx5_flow_meter *fm, 871 const struct rte_flow_attr *attr); 872 typedef uint32_t (*mlx5_flow_counter_alloc_t) 873 (struct rte_eth_dev *dev); 874 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 875 uint32_t cnt); 876 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 877 uint32_t cnt, 878 bool clear, uint64_t *pkts, 879 uint64_t *bytes); 880 typedef int (*mlx5_flow_get_aged_flows_t) 881 (struct rte_eth_dev *dev, 882 void **context, 883 uint32_t nb_contexts, 884 struct rte_flow_error *error); 885 struct mlx5_flow_driver_ops { 886 mlx5_flow_validate_t validate; 887 mlx5_flow_prepare_t prepare; 888 mlx5_flow_translate_t translate; 889 mlx5_flow_apply_t apply; 890 mlx5_flow_remove_t remove; 891 mlx5_flow_destroy_t destroy; 892 mlx5_flow_query_t query; 893 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 894 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 895 mlx5_flow_create_policer_rules_t create_policer_rules; 896 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 897 mlx5_flow_counter_alloc_t counter_alloc; 898 mlx5_flow_counter_free_t counter_free; 899 mlx5_flow_counter_query_t counter_query; 900 mlx5_flow_get_aged_flows_t get_aged_flows; 901 }; 902 903 904 #define MLX5_CNT_CONTAINER(sh, batch, thread, age) (&(sh)->cmng.ccont \ 905 [(((sh)->cmng.mhi[batch][age] >> (thread)) & 0x1) * 2 + (batch)][age]) 906 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread, age) (&(sh)->cmng.ccont \ 907 [(~((sh)->cmng.mhi[batch][age] >> (thread)) & 0x1) * 2 + (batch)][age]) 908 909 /* mlx5_flow.c */ 910 911 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id); 912 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool); 913 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id); 914 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, 915 uint32_t id); 916 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, 917 bool external, uint32_t group, bool fdb_def_rule, 918 uint32_t *table, struct rte_flow_error *error); 919 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 920 int tunnel, uint64_t layer_types, 921 uint64_t hash_fields); 922 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 923 uint32_t subpriority); 924 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 925 enum mlx5_feature_name feature, 926 uint32_t id, 927 struct rte_flow_error *error); 928 const struct rte_flow_action *mlx5_flow_find_action 929 (const struct rte_flow_action *actions, 930 enum rte_flow_action_type action); 931 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 932 const struct rte_flow_attr *attr, 933 struct rte_flow_error *error); 934 int mlx5_flow_validate_action_drop(uint64_t action_flags, 935 const struct rte_flow_attr *attr, 936 struct rte_flow_error *error); 937 int mlx5_flow_validate_action_flag(uint64_t action_flags, 938 const struct rte_flow_attr *attr, 939 struct rte_flow_error *error); 940 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 941 uint64_t action_flags, 942 const struct rte_flow_attr *attr, 943 struct rte_flow_error *error); 944 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 945 uint64_t action_flags, 946 struct rte_eth_dev *dev, 947 const struct rte_flow_attr *attr, 948 struct rte_flow_error *error); 949 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 950 uint64_t action_flags, 951 struct rte_eth_dev *dev, 952 const struct rte_flow_attr *attr, 953 uint64_t item_flags, 954 struct rte_flow_error *error); 955 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 956 const struct rte_flow_attr *attributes, 957 struct rte_flow_error *error); 958 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 959 const uint8_t *mask, 960 const uint8_t *nic_mask, 961 unsigned int size, 962 struct rte_flow_error *error); 963 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 964 uint64_t item_flags, 965 struct rte_flow_error *error); 966 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 967 uint64_t item_flags, 968 uint8_t target_protocol, 969 struct rte_flow_error *error); 970 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 971 uint64_t item_flags, 972 const struct rte_flow_item *gre_item, 973 struct rte_flow_error *error); 974 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 975 uint64_t item_flags, 976 uint64_t last_item, 977 uint16_t ether_type, 978 const struct rte_flow_item_ipv4 *acc_mask, 979 struct rte_flow_error *error); 980 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 981 uint64_t item_flags, 982 uint64_t last_item, 983 uint16_t ether_type, 984 const struct rte_flow_item_ipv6 *acc_mask, 985 struct rte_flow_error *error); 986 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 987 const struct rte_flow_item *item, 988 uint64_t item_flags, 989 uint64_t prev_layer, 990 struct rte_flow_error *error); 991 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 992 uint64_t item_flags, 993 uint8_t target_protocol, 994 const struct rte_flow_item_tcp *flow_mask, 995 struct rte_flow_error *error); 996 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 997 uint64_t item_flags, 998 uint8_t target_protocol, 999 struct rte_flow_error *error); 1000 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1001 uint64_t item_flags, 1002 struct rte_eth_dev *dev, 1003 struct rte_flow_error *error); 1004 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1005 uint64_t item_flags, 1006 struct rte_flow_error *error); 1007 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1008 uint64_t item_flags, 1009 struct rte_eth_dev *dev, 1010 struct rte_flow_error *error); 1011 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1012 uint64_t item_flags, 1013 uint8_t target_protocol, 1014 struct rte_flow_error *error); 1015 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1016 uint64_t item_flags, 1017 uint8_t target_protocol, 1018 struct rte_flow_error *error); 1019 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1020 uint64_t item_flags, 1021 uint8_t target_protocol, 1022 struct rte_flow_error *error); 1023 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1024 uint64_t item_flags, 1025 struct rte_eth_dev *dev, 1026 struct rte_flow_error *error); 1027 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1028 (struct rte_eth_dev *dev, 1029 const struct mlx5_flow_meter *fm); 1030 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1031 struct mlx5_meter_domains_infos *tbl); 1032 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1033 struct mlx5_flow_meter *fm, 1034 const struct rte_flow_attr *attr); 1035 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1036 struct mlx5_flow_meter *fm, 1037 const struct rte_flow_attr *attr); 1038 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1039 struct rte_mtr_error *error); 1040 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1041