1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* Private rte flow items. */ 22 enum mlx5_rte_flow_item_type { 23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 24 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 28 }; 29 30 /* Private (internal) rte flow actions. */ 31 enum mlx5_rte_flow_action_type { 32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 33 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 34 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 38 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT, 40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP, 41 }; 42 43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 44 45 enum { 46 MLX5_INDIRECT_ACTION_TYPE_RSS, 47 MLX5_INDIRECT_ACTION_TYPE_AGE, 48 MLX5_INDIRECT_ACTION_TYPE_COUNT, 49 MLX5_INDIRECT_ACTION_TYPE_CT, 50 }; 51 52 /* Now, the maximal ports will be supported is 256, action number is 4M. */ 53 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100 54 55 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22 56 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1) 57 58 /* 30-31: type, 22-29: owner port, 0-21: index. */ 59 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \ 60 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \ 61 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \ 62 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index)) 63 64 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \ 65 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \ 66 MLX5_INDIRECT_ACT_CT_OWNER_MASK) 67 68 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \ 69 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1)) 70 71 /* Matches on selected register. */ 72 struct mlx5_rte_flow_item_tag { 73 enum modify_reg id; 74 uint32_t data; 75 }; 76 77 /* Modify selected register. */ 78 struct mlx5_rte_flow_action_set_tag { 79 enum modify_reg id; 80 uint8_t offset; 81 uint8_t length; 82 uint32_t data; 83 }; 84 85 struct mlx5_flow_action_copy_mreg { 86 enum modify_reg dst; 87 enum modify_reg src; 88 }; 89 90 /* Matches on source queue. */ 91 struct mlx5_rte_flow_item_tx_queue { 92 uint32_t queue; 93 }; 94 95 /* Feature name to allocate metadata register. */ 96 enum mlx5_feature_name { 97 MLX5_HAIRPIN_RX, 98 MLX5_HAIRPIN_TX, 99 MLX5_METADATA_RX, 100 MLX5_METADATA_TX, 101 MLX5_METADATA_FDB, 102 MLX5_FLOW_MARK, 103 MLX5_APP_TAG, 104 MLX5_COPY_MARK, 105 MLX5_MTR_COLOR, 106 MLX5_MTR_ID, 107 MLX5_ASO_FLOW_HIT, 108 MLX5_ASO_CONNTRACK, 109 }; 110 111 /* Default queue number. */ 112 #define MLX5_RSSQ_DEFAULT_NUM 16 113 114 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 115 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 116 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 117 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 118 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 119 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 120 121 /* Pattern inner Layer bits. */ 122 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 123 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 124 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 125 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 126 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 127 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 128 129 /* Pattern tunnel Layer bits. */ 130 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 131 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 132 #define MLX5_FLOW_LAYER_GRE (1u << 14) 133 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 134 /* List of tunnel Layer bits continued below. */ 135 136 /* General pattern items bits. */ 137 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 138 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 139 #define MLX5_FLOW_ITEM_TAG (1u << 18) 140 #define MLX5_FLOW_ITEM_MARK (1u << 19) 141 142 /* Pattern MISC bits. */ 143 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 144 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 145 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 146 147 /* Pattern tunnel Layer bits (continued). */ 148 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 149 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 150 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 151 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 152 153 /* Queue items. */ 154 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 155 156 /* Pattern tunnel Layer bits (continued). */ 157 #define MLX5_FLOW_LAYER_GTP (1u << 28) 158 159 /* Pattern eCPRI Layer bit. */ 160 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 161 162 /* IPv6 Fragment Extension Header bit. */ 163 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 164 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 165 166 /* Pattern tunnel Layer bits (continued). */ 167 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 168 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 169 170 /* INTEGRITY item bit */ 171 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34) 172 173 /* Conntrack item. */ 174 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35) 175 176 /* Outer Masks. */ 177 #define MLX5_FLOW_LAYER_OUTER_L3 \ 178 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 179 #define MLX5_FLOW_LAYER_OUTER_L4 \ 180 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 181 #define MLX5_FLOW_LAYER_OUTER \ 182 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 183 MLX5_FLOW_LAYER_OUTER_L4) 184 185 /* Tunnel Masks. */ 186 #define MLX5_FLOW_LAYER_TUNNEL \ 187 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 188 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 189 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 190 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 191 192 /* Inner Masks. */ 193 #define MLX5_FLOW_LAYER_INNER_L3 \ 194 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 195 #define MLX5_FLOW_LAYER_INNER_L4 \ 196 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 197 #define MLX5_FLOW_LAYER_INNER \ 198 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 199 MLX5_FLOW_LAYER_INNER_L4) 200 201 /* Layer Masks. */ 202 #define MLX5_FLOW_LAYER_L2 \ 203 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 204 #define MLX5_FLOW_LAYER_L3_IPV4 \ 205 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 206 #define MLX5_FLOW_LAYER_L3_IPV6 \ 207 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 208 #define MLX5_FLOW_LAYER_L3 \ 209 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 210 #define MLX5_FLOW_LAYER_L4 \ 211 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 212 213 /* Actions */ 214 #define MLX5_FLOW_ACTION_DROP (1u << 0) 215 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 216 #define MLX5_FLOW_ACTION_RSS (1u << 2) 217 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 218 #define MLX5_FLOW_ACTION_MARK (1u << 4) 219 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 220 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 221 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 222 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 223 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 224 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 225 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 226 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 227 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 228 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 229 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 230 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 231 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 232 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 233 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 234 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 235 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 236 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 237 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 238 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 239 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 240 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 241 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 242 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 243 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 244 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 245 #define MLX5_FLOW_ACTION_METER (1ull << 31) 246 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 247 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 248 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 249 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 250 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 251 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 252 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 253 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 254 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40) 255 #define MLX5_FLOW_ACTION_CT (1ull << 41) 256 257 #define MLX5_FLOW_FATE_ACTIONS \ 258 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 259 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 260 MLX5_FLOW_ACTION_DEFAULT_MISS | \ 261 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 262 263 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 264 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 265 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 266 267 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 268 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 269 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 270 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 271 MLX5_FLOW_ACTION_SET_TP_SRC | \ 272 MLX5_FLOW_ACTION_SET_TP_DST | \ 273 MLX5_FLOW_ACTION_SET_TTL | \ 274 MLX5_FLOW_ACTION_DEC_TTL | \ 275 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 276 MLX5_FLOW_ACTION_SET_MAC_DST | \ 277 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 278 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 279 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 280 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 281 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 282 MLX5_FLOW_ACTION_SET_TAG | \ 283 MLX5_FLOW_ACTION_MARK_EXT | \ 284 MLX5_FLOW_ACTION_SET_META | \ 285 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 286 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 287 MLX5_FLOW_ACTION_MODIFY_FIELD) 288 289 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 290 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 291 292 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 293 294 #ifndef IPPROTO_MPLS 295 #define IPPROTO_MPLS 137 296 #endif 297 298 /* UDP port number for MPLS */ 299 #define MLX5_UDP_PORT_MPLS 6635 300 301 /* UDP port numbers for VxLAN. */ 302 #define MLX5_UDP_PORT_VXLAN 4789 303 #define MLX5_UDP_PORT_VXLAN_GPE 4790 304 305 /* UDP port numbers for GENEVE. */ 306 #define MLX5_UDP_PORT_GENEVE 6081 307 308 /* Lowest priority indicator. */ 309 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 310 311 /* 312 * Max priority for ingress\egress flow groups 313 * greater than 0 and for any transfer flow group. 314 * From user configation: 0 - 21843. 315 */ 316 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 317 318 /* 319 * Number of sub priorities. 320 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 321 * matching on the NIC (firmware dependent) L4 most have the higher priority 322 * followed by L3 and ending with L2. 323 */ 324 #define MLX5_PRIORITY_MAP_L2 2 325 #define MLX5_PRIORITY_MAP_L3 1 326 #define MLX5_PRIORITY_MAP_L4 0 327 #define MLX5_PRIORITY_MAP_MAX 3 328 329 /* Valid layer type for IPV4 RSS. */ 330 #define MLX5_IPV4_LAYER_TYPES \ 331 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 332 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 333 ETH_RSS_NONFRAG_IPV4_OTHER) 334 335 /* IBV hash source bits for IPV4. */ 336 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 337 338 /* Valid layer type for IPV6 RSS. */ 339 #define MLX5_IPV6_LAYER_TYPES \ 340 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 341 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 342 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 343 344 /* IBV hash source bits for IPV6. */ 345 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 346 347 /* IBV hash bits for L3 SRC. */ 348 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 349 350 /* IBV hash bits for L3 DST. */ 351 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 352 353 /* IBV hash bits for TCP. */ 354 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 355 IBV_RX_HASH_DST_PORT_TCP) 356 357 /* IBV hash bits for UDP. */ 358 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 359 IBV_RX_HASH_DST_PORT_UDP) 360 361 /* IBV hash bits for L4 SRC. */ 362 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 363 IBV_RX_HASH_SRC_PORT_UDP) 364 365 /* IBV hash bits for L4 DST. */ 366 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 367 IBV_RX_HASH_DST_PORT_UDP) 368 369 /* Geneve header first 16Bit */ 370 #define MLX5_GENEVE_VER_MASK 0x3 371 #define MLX5_GENEVE_VER_SHIFT 14 372 #define MLX5_GENEVE_VER_VAL(a) \ 373 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 374 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 375 #define MLX5_GENEVE_OPTLEN_SHIFT 8 376 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 377 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 378 #define MLX5_GENEVE_OAMF_MASK 0x1 379 #define MLX5_GENEVE_OAMF_SHIFT 7 380 #define MLX5_GENEVE_OAMF_VAL(a) \ 381 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 382 #define MLX5_GENEVE_CRITO_MASK 0x1 383 #define MLX5_GENEVE_CRITO_SHIFT 6 384 #define MLX5_GENEVE_CRITO_VAL(a) \ 385 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 386 #define MLX5_GENEVE_RSVD_MASK 0x3F 387 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 388 /* 389 * The length of the Geneve options fields, expressed in four byte multiples, 390 * not including the eight byte fixed tunnel. 391 */ 392 #define MLX5_GENEVE_OPT_LEN_0 14 393 #define MLX5_GENEVE_OPT_LEN_1 63 394 395 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 396 sizeof(struct rte_ipv4_hdr)) 397 /* GTP extension header flag. */ 398 #define MLX5_GTP_EXT_HEADER_FLAG 4 399 400 /* GTP extension header max PDU type value. */ 401 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 402 403 /* GTP extension header PDU type shift. */ 404 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 405 406 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 407 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 408 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 409 410 /* Specific item's fields can accept a range of values (using spec and last). */ 411 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 412 #define MLX5_ITEM_RANGE_ACCEPTED true 413 414 /* Software header modify action numbers of a flow. */ 415 #define MLX5_ACT_NUM_MDF_IPV4 1 416 #define MLX5_ACT_NUM_MDF_IPV6 4 417 #define MLX5_ACT_NUM_MDF_MAC 2 418 #define MLX5_ACT_NUM_MDF_VID 1 419 #define MLX5_ACT_NUM_MDF_PORT 2 420 #define MLX5_ACT_NUM_MDF_TTL 1 421 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 422 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 423 #define MLX5_ACT_NUM_MDF_TCPACK 1 424 #define MLX5_ACT_NUM_SET_REG 1 425 #define MLX5_ACT_NUM_SET_TAG 1 426 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 427 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 428 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 429 #define MLX5_ACT_NUM_SET_DSCP 1 430 431 /* Maximum number of fields to modify in MODIFY_FIELD */ 432 #define MLX5_ACT_MAX_MOD_FIELDS 5 433 434 /* Syndrome bits definition for connection tracking. */ 435 #define MLX5_CT_SYNDROME_VALID (0x0 << 6) 436 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6) 437 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6) 438 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1) 439 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0) 440 441 enum mlx5_flow_drv_type { 442 MLX5_FLOW_TYPE_MIN, 443 MLX5_FLOW_TYPE_DV, 444 MLX5_FLOW_TYPE_VERBS, 445 MLX5_FLOW_TYPE_MAX, 446 }; 447 448 /* Fate action type. */ 449 enum mlx5_flow_fate_type { 450 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 451 MLX5_FLOW_FATE_QUEUE, 452 MLX5_FLOW_FATE_JUMP, 453 MLX5_FLOW_FATE_PORT_ID, 454 MLX5_FLOW_FATE_DROP, 455 MLX5_FLOW_FATE_DEFAULT_MISS, 456 MLX5_FLOW_FATE_SHARED_RSS, 457 MLX5_FLOW_FATE_MTR, 458 MLX5_FLOW_FATE_MAX, 459 }; 460 461 /* Matcher PRM representation */ 462 struct mlx5_flow_dv_match_params { 463 size_t size; 464 /**< Size of match value. Do NOT split size and key! */ 465 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 466 /**< Matcher value. This value is used as the mask or as a key. */ 467 }; 468 469 /* Matcher structure. */ 470 struct mlx5_flow_dv_matcher { 471 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 472 struct mlx5_flow_tbl_resource *tbl; 473 /**< Pointer to the table(group) the matcher associated with. */ 474 void *matcher_object; /**< Pointer to DV matcher */ 475 uint16_t crc; /**< CRC of key. */ 476 uint16_t priority; /**< Priority of matcher. */ 477 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 478 }; 479 480 #define MLX5_ENCAP_MAX_LEN 132 481 482 /* Encap/decap resource structure. */ 483 struct mlx5_flow_dv_encap_decap_resource { 484 struct mlx5_hlist_entry entry; 485 /* Pointer to next element. */ 486 uint32_t refcnt; /**< Reference counter. */ 487 void *action; 488 /**< Encap/decap action object. */ 489 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 490 size_t size; 491 uint8_t reformat_type; 492 uint8_t ft_type; 493 uint64_t flags; /**< Flags for RDMA API. */ 494 uint32_t idx; /**< Index for the index memory pool. */ 495 }; 496 497 /* Tag resource structure. */ 498 struct mlx5_flow_dv_tag_resource { 499 struct mlx5_hlist_entry entry; 500 /**< hash list entry for tag resource, tag value as the key. */ 501 void *action; 502 /**< Tag action object. */ 503 uint32_t refcnt; /**< Reference counter. */ 504 uint32_t idx; /**< Index for the index memory pool. */ 505 uint32_t tag_id; /**< Tag ID. */ 506 }; 507 508 /* 509 * Number of modification commands. 510 * The maximal actions amount in FW is some constant, and it is 16 in the 511 * latest releases. In some old releases, it will be limited to 8. 512 * Since there is no interface to query the capacity, the maximal value should 513 * be used to allow PMD to create the flow. The validation will be done in the 514 * lower driver layer or FW. A failure will be returned if exceeds the maximal 515 * supported actions number on the root table. 516 * On non-root tables, there is no limitation, but 32 is enough right now. 517 */ 518 #define MLX5_MAX_MODIFY_NUM 32 519 #define MLX5_ROOT_TBL_MODIFY_NUM 16 520 521 /* Modify resource structure */ 522 struct mlx5_flow_dv_modify_hdr_resource { 523 struct mlx5_hlist_entry entry; 524 void *action; /**< Modify header action object. */ 525 /* Key area for hash list matching: */ 526 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 527 uint32_t actions_num; /**< Number of modification actions. */ 528 uint64_t flags; /**< Flags for RDMA API. */ 529 struct mlx5_modification_cmd actions[]; 530 /**< Modification actions. */ 531 }; 532 533 /* Modify resource key of the hash organization. */ 534 union mlx5_flow_modify_hdr_key { 535 struct { 536 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 537 uint32_t actions_num:5; /**< Number of modification actions. */ 538 uint32_t group:19; /**< Flow group id. */ 539 uint32_t cksum; /**< Actions check sum. */ 540 }; 541 uint64_t v64; /**< full 64bits value of key */ 542 }; 543 544 /* Jump action resource structure. */ 545 struct mlx5_flow_dv_jump_tbl_resource { 546 void *action; /**< Pointer to the rdma core action. */ 547 }; 548 549 /* Port ID resource structure. */ 550 struct mlx5_flow_dv_port_id_action_resource { 551 struct mlx5_cache_entry entry; 552 void *action; /**< Action object. */ 553 uint32_t port_id; /**< Port ID value. */ 554 uint32_t idx; /**< Indexed pool memory index. */ 555 }; 556 557 /* Push VLAN action resource structure */ 558 struct mlx5_flow_dv_push_vlan_action_resource { 559 struct mlx5_cache_entry entry; /* Cache entry. */ 560 void *action; /**< Action object. */ 561 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 562 rte_be32_t vlan_tag; /**< VLAN tag value. */ 563 uint32_t idx; /**< Indexed pool memory index. */ 564 }; 565 566 /* Metadata register copy table entry. */ 567 struct mlx5_flow_mreg_copy_resource { 568 /* 569 * Hash list entry for copy table. 570 * - Key is 32/64-bit MARK action ID. 571 * - MUST be the first entry. 572 */ 573 struct mlx5_hlist_entry hlist_ent; 574 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 575 /* List entry for device flows. */ 576 uint32_t idx; 577 uint32_t rix_flow; /* Built flow for copy. */ 578 uint32_t mark_id; 579 }; 580 581 /* Table tunnel parameter. */ 582 struct mlx5_flow_tbl_tunnel_prm { 583 const struct mlx5_flow_tunnel *tunnel; 584 uint32_t group_id; 585 bool external; 586 }; 587 588 /* Table data structure of the hash organization. */ 589 struct mlx5_flow_tbl_data_entry { 590 struct mlx5_hlist_entry entry; 591 /**< hash list entry, 64-bits key inside. */ 592 struct mlx5_flow_tbl_resource tbl; 593 /**< flow table resource. */ 594 struct mlx5_cache_list matchers; 595 /**< matchers' header associated with the flow table. */ 596 struct mlx5_flow_dv_jump_tbl_resource jump; 597 /**< jump resource, at most one for each table created. */ 598 uint32_t idx; /**< index for the indexed mempool. */ 599 /**< tunnel offload */ 600 const struct mlx5_flow_tunnel *tunnel; 601 uint32_t group_id; 602 uint32_t external:1; 603 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 604 uint32_t is_egress:1; /**< Egress table. */ 605 uint32_t is_transfer:1; /**< Transfer table. */ 606 uint32_t dummy:1; /**< DR table. */ 607 uint32_t id:22; /**< Table ID. */ 608 uint32_t reserve:5; /**< Reserved to future using. */ 609 uint32_t level; /**< Table level. */ 610 }; 611 612 /* Sub rdma-core actions list. */ 613 struct mlx5_flow_sub_actions_list { 614 uint32_t actions_num; /**< Number of sample actions. */ 615 uint64_t action_flags; 616 void *dr_queue_action; 617 void *dr_tag_action; 618 void *dr_cnt_action; 619 void *dr_port_id_action; 620 void *dr_encap_action; 621 void *dr_jump_action; 622 }; 623 624 /* Sample sub-actions resource list. */ 625 struct mlx5_flow_sub_actions_idx { 626 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 627 uint32_t rix_tag; /**< Index to the tag action. */ 628 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 629 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 630 uint32_t rix_jump; /**< Index to the jump action resource. */ 631 }; 632 633 /* Sample action resource structure. */ 634 struct mlx5_flow_dv_sample_resource { 635 struct mlx5_cache_entry entry; /**< Cache entry. */ 636 union { 637 void *verbs_action; /**< Verbs sample action object. */ 638 void **sub_actions; /**< Sample sub-action array. */ 639 }; 640 struct rte_eth_dev *dev; /**< Device registers the action. */ 641 uint32_t idx; /** Sample object index. */ 642 uint8_t ft_type; /** Flow Table Type */ 643 uint32_t ft_id; /** Flow Table Level */ 644 uint32_t ratio; /** Sample Ratio */ 645 uint64_t set_action; /** Restore reg_c0 value */ 646 void *normal_path_tbl; /** Flow Table pointer */ 647 struct mlx5_flow_sub_actions_idx sample_idx; 648 /**< Action index resources. */ 649 struct mlx5_flow_sub_actions_list sample_act; 650 /**< Action resources. */ 651 }; 652 653 #define MLX5_MAX_DEST_NUM 2 654 655 /* Destination array action resource structure. */ 656 struct mlx5_flow_dv_dest_array_resource { 657 struct mlx5_cache_entry entry; /**< Cache entry. */ 658 uint32_t idx; /** Destination array action object index. */ 659 uint8_t ft_type; /** Flow Table Type */ 660 uint8_t num_of_dest; /**< Number of destination actions. */ 661 struct rte_eth_dev *dev; /**< Device registers the action. */ 662 void *action; /**< Pointer to the rdma core action. */ 663 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 664 /**< Action index resources. */ 665 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 666 /**< Action resources. */ 667 }; 668 669 /* PMD flow priority for tunnel */ 670 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 671 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 672 673 674 /** Device flow handle structure for DV mode only. */ 675 struct mlx5_flow_handle_dv { 676 /* Flow DV api: */ 677 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 678 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 679 /**< Pointer to modify header resource in cache. */ 680 uint32_t rix_encap_decap; 681 /**< Index to encap/decap resource in cache. */ 682 uint32_t rix_push_vlan; 683 /**< Index to push VLAN action resource in cache. */ 684 uint32_t rix_tag; 685 /**< Index to the tag action. */ 686 uint32_t rix_sample; 687 /**< Index to sample action resource in cache. */ 688 uint32_t rix_dest_array; 689 /**< Index to destination array resource in cache. */ 690 } __rte_packed; 691 692 /** Device flow handle structure: used both for creating & destroying. */ 693 struct mlx5_flow_handle { 694 SILIST_ENTRY(uint32_t)next; 695 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 696 /**< Index to next device flow handle. */ 697 uint64_t layers; 698 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 699 void *drv_flow; /**< pointer to driver flow object. */ 700 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */ 701 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */ 702 uint32_t mark:1; /**< Metadate rxq mark flag. */ 703 uint32_t fate_action:3; /**< Fate action type. */ 704 union { 705 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 706 uint32_t rix_jump; /**< Index to the jump action resource. */ 707 uint32_t rix_port_id_action; 708 /**< Index to port ID action resource. */ 709 uint32_t rix_fate; 710 /**< Generic value indicates the fate action. */ 711 uint32_t rix_default_fate; 712 /**< Indicates default miss fate action. */ 713 uint32_t rix_srss; 714 /**< Indicates shared RSS fate action. */ 715 }; 716 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 717 struct mlx5_flow_handle_dv dvh; 718 #endif 719 } __rte_packed; 720 721 /* 722 * Size for Verbs device flow handle structure only. Do not use the DV only 723 * structure in Verbs. No DV flows attributes will be accessed. 724 * Macro offsetof() could also be used here. 725 */ 726 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 727 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 728 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 729 #else 730 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 731 #endif 732 733 /** Device flow structure only for DV flow creation. */ 734 struct mlx5_flow_dv_workspace { 735 uint32_t group; /**< The group index. */ 736 uint32_t table_id; /**< Flow table identifier. */ 737 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 738 int actions_n; /**< number of actions. */ 739 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 740 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 741 /**< Pointer to encap/decap resource in cache. */ 742 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 743 /**< Pointer to push VLAN action resource in cache. */ 744 struct mlx5_flow_dv_tag_resource *tag_resource; 745 /**< pointer to the tag action. */ 746 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 747 /**< Pointer to port ID action resource. */ 748 struct mlx5_flow_dv_jump_tbl_resource *jump; 749 /**< Pointer to the jump action resource. */ 750 struct mlx5_flow_dv_match_params value; 751 /**< Holds the value that the packet is compared to. */ 752 struct mlx5_flow_dv_sample_resource *sample_res; 753 /**< Pointer to the sample action resource. */ 754 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 755 /**< Pointer to the destination array resource. */ 756 }; 757 758 #ifdef HAVE_INFINIBAND_VERBS_H 759 /* 760 * Maximal Verbs flow specifications & actions size. 761 * Some elements are mutually exclusive, but enough space should be allocated. 762 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 763 * 2. One tunnel header (exception: GRE + MPLS), 764 * SPEC length: GRE == tunnel. 765 * Actions: 1. 1 Mark OR Flag. 766 * 2. 1 Drop (if any). 767 * 3. No limitation for counters, but it makes no sense to support too 768 * many counters in a single device flow. 769 */ 770 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 771 #define MLX5_VERBS_MAX_SPEC_SIZE \ 772 ( \ 773 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 774 sizeof(struct ibv_flow_spec_ipv6) + \ 775 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 776 sizeof(struct ibv_flow_spec_gre) + \ 777 sizeof(struct ibv_flow_spec_mpls)) \ 778 ) 779 #else 780 #define MLX5_VERBS_MAX_SPEC_SIZE \ 781 ( \ 782 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 783 sizeof(struct ibv_flow_spec_ipv6) + \ 784 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 785 sizeof(struct ibv_flow_spec_tunnel)) \ 786 ) 787 #endif 788 789 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 790 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 791 #define MLX5_VERBS_MAX_ACT_SIZE \ 792 ( \ 793 sizeof(struct ibv_flow_spec_action_tag) + \ 794 sizeof(struct ibv_flow_spec_action_drop) + \ 795 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 796 ) 797 #else 798 #define MLX5_VERBS_MAX_ACT_SIZE \ 799 ( \ 800 sizeof(struct ibv_flow_spec_action_tag) + \ 801 sizeof(struct ibv_flow_spec_action_drop) \ 802 ) 803 #endif 804 805 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 806 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 807 808 /** Device flow structure only for Verbs flow creation. */ 809 struct mlx5_flow_verbs_workspace { 810 unsigned int size; /**< Size of the attribute. */ 811 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 812 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 813 /**< Specifications & actions buffer of verbs flow. */ 814 }; 815 #endif /* HAVE_INFINIBAND_VERBS_H */ 816 817 #define MLX5_SCALE_FLOW_GROUP_BIT 0 818 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 819 820 /** Maximal number of device sub-flows supported. */ 821 #define MLX5_NUM_MAX_DEV_FLOWS 32 822 823 /** 824 * tunnel offload rules type 825 */ 826 enum mlx5_tof_rule_type { 827 MLX5_TUNNEL_OFFLOAD_NONE = 0, 828 MLX5_TUNNEL_OFFLOAD_SET_RULE, 829 MLX5_TUNNEL_OFFLOAD_MATCH_RULE, 830 MLX5_TUNNEL_OFFLOAD_MISS_RULE, 831 }; 832 833 /** Device flow structure. */ 834 __extension__ 835 struct mlx5_flow { 836 struct rte_flow *flow; /**< Pointer to the main flow. */ 837 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 838 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 839 uint64_t act_flags; 840 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 841 bool external; /**< true if the flow is created external to PMD. */ 842 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 843 uint8_t skip_scale:2; 844 /** 845 * Each Bit be set to 1 if Skip the scale the flow group with factor. 846 * If bit0 be set to 1, then skip the scale the original flow group; 847 * If bit1 be set to 1, then skip the scale the jump flow group if 848 * having jump action. 849 * 00: Enable scale in a flow, default value. 850 * 01: Skip scale the flow group with factor, enable scale the group 851 * of jump action. 852 * 10: Enable scale the group with factor, skip scale the group of 853 * jump action. 854 * 11: Skip scale the table with factor both for flow group and jump 855 * group. 856 */ 857 union { 858 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 859 struct mlx5_flow_dv_workspace dv; 860 #endif 861 #ifdef HAVE_INFINIBAND_VERBS_H 862 struct mlx5_flow_verbs_workspace verbs; 863 #endif 864 }; 865 struct mlx5_flow_handle *handle; 866 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 867 const struct mlx5_flow_tunnel *tunnel; 868 enum mlx5_tof_rule_type tof_type; 869 }; 870 871 /* Flow meter state. */ 872 #define MLX5_FLOW_METER_DISABLE 0 873 #define MLX5_FLOW_METER_ENABLE 1 874 875 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u 876 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u 877 878 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES 879 880 #define MLX5_MAN_WIDTH 8 881 /* Legacy Meter parameter structure. */ 882 struct mlx5_legacy_flow_meter { 883 struct mlx5_flow_meter_info fm; 884 /* Must be the first in struct. */ 885 TAILQ_ENTRY(mlx5_legacy_flow_meter) next; 886 /**< Pointer to the next flow meter structure. */ 887 uint32_t idx; 888 /* Index to meter object. */ 889 }; 890 891 #define MLX5_MAX_TUNNELS 256 892 #define MLX5_TNL_MISS_RULE_PRIORITY 3 893 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 894 895 /* 896 * When tunnel offload is active, all JUMP group ids are converted 897 * using the same method. That conversion is applied both to tunnel and 898 * regular rule types. 899 * Group ids used in tunnel rules are relative to it's tunnel (!). 900 * Application can create number of steer rules, using the same 901 * tunnel, with different group id in each rule. 902 * Each tunnel stores its groups internally in PMD tunnel object. 903 * Groups used in regular rules do not belong to any tunnel and are stored 904 * in tunnel hub. 905 */ 906 907 struct mlx5_flow_tunnel { 908 LIST_ENTRY(mlx5_flow_tunnel) chain; 909 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 910 uint32_t tunnel_id; /** unique tunnel ID */ 911 uint32_t refctn; 912 struct rte_flow_action action; 913 struct rte_flow_item item; 914 struct mlx5_hlist *groups; /** tunnel groups */ 915 }; 916 917 /** PMD tunnel related context */ 918 struct mlx5_flow_tunnel_hub { 919 /* Tunnels list 920 * Access to the list MUST be MT protected 921 */ 922 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 923 /* protect access to the tunnels list */ 924 rte_spinlock_t sl; 925 struct mlx5_hlist *groups; /** non tunnel groups */ 926 }; 927 928 /* convert jump group to flow table ID in tunnel rules */ 929 struct tunnel_tbl_entry { 930 struct mlx5_hlist_entry hash; 931 uint32_t flow_table; 932 uint32_t tunnel_id; 933 uint32_t group; 934 }; 935 936 static inline uint32_t 937 tunnel_id_to_flow_tbl(uint32_t id) 938 { 939 return id | (1u << 16); 940 } 941 942 static inline uint32_t 943 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 944 { 945 return flow_tbl & ~(1u << 16); 946 } 947 948 union tunnel_tbl_key { 949 uint64_t val; 950 struct { 951 uint32_t tunnel_id; 952 uint32_t group; 953 }; 954 }; 955 956 static inline struct mlx5_flow_tunnel_hub * 957 mlx5_tunnel_hub(struct rte_eth_dev *dev) 958 { 959 struct mlx5_priv *priv = dev->data->dev_private; 960 return priv->sh->tunnel_hub; 961 } 962 963 static inline bool 964 is_tunnel_offload_active(const struct rte_eth_dev *dev) 965 { 966 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 967 const struct mlx5_priv *priv = dev->data->dev_private; 968 return !!priv->config.dv_miss_info; 969 #else 970 RTE_SET_USED(dev); 971 return false; 972 #endif 973 } 974 975 static inline bool 976 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type) 977 { 978 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 979 } 980 981 static inline bool 982 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type) 983 { 984 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE; 985 } 986 987 static inline const struct mlx5_flow_tunnel * 988 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 989 { 990 return actions[0].conf; 991 } 992 993 static inline const struct mlx5_flow_tunnel * 994 flow_items_to_tunnel(const struct rte_flow_item items[]) 995 { 996 return items[0].spec; 997 } 998 999 /* Flow structure. */ 1000 struct rte_flow { 1001 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 1002 uint32_t dev_handles; 1003 /**< Device flow handles that are part of the flow. */ 1004 uint32_t drv_type:2; /**< Driver type. */ 1005 uint32_t tunnel:1; 1006 uint32_t meter:24; /**< Holds flow meter id. */ 1007 uint32_t indirect_type:2; /**< Indirect action type. */ 1008 uint32_t rix_mreg_copy; 1009 /**< Index to metadata register copy table resource. */ 1010 uint32_t counter; /**< Holds flow counter. */ 1011 uint32_t tunnel_id; /**< Tunnel id */ 1012 union { 1013 uint32_t age; /**< Holds ASO age bit index. */ 1014 uint32_t ct; /**< Holds ASO CT index. */ 1015 }; 1016 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 1017 } __rte_packed; 1018 1019 /* 1020 * Define list of valid combinations of RX Hash fields 1021 * (see enum ibv_rx_hash_fields). 1022 */ 1023 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1024 #define MLX5_RSS_HASH_IPV4_TCP \ 1025 (MLX5_RSS_HASH_IPV4 | \ 1026 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1027 #define MLX5_RSS_HASH_IPV4_UDP \ 1028 (MLX5_RSS_HASH_IPV4 | \ 1029 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1030 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1031 #define MLX5_RSS_HASH_IPV6_TCP \ 1032 (MLX5_RSS_HASH_IPV6 | \ 1033 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1034 #define MLX5_RSS_HASH_IPV6_UDP \ 1035 (MLX5_RSS_HASH_IPV6 | \ 1036 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1037 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 1038 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 1039 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 1040 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1041 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1042 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1043 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1044 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1045 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1046 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1047 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1048 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1049 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1050 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1051 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1052 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1053 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1054 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1055 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1056 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1057 #define MLX5_RSS_HASH_NONE 0ULL 1058 1059 1060 /* extract next protocol type from Ethernet & VLAN headers */ 1061 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \ 1062 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \ 1063 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \ 1064 (_prt) = rte_be_to_cpu_16((_prt)); \ 1065 } while (0) 1066 1067 /* array of valid combinations of RX Hash fields for RSS */ 1068 static const uint64_t mlx5_rss_hash_fields[] = { 1069 MLX5_RSS_HASH_IPV4, 1070 MLX5_RSS_HASH_IPV4_TCP, 1071 MLX5_RSS_HASH_IPV4_UDP, 1072 MLX5_RSS_HASH_IPV6, 1073 MLX5_RSS_HASH_IPV6_TCP, 1074 MLX5_RSS_HASH_IPV6_UDP, 1075 MLX5_RSS_HASH_NONE, 1076 }; 1077 1078 /* Shared RSS action structure */ 1079 struct mlx5_shared_action_rss { 1080 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1081 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1082 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1083 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1084 struct mlx5_ind_table_obj *ind_tbl; 1085 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1086 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1087 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1088 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1089 }; 1090 1091 struct rte_flow_action_handle { 1092 uint32_t id; 1093 }; 1094 1095 /* Thread specific flow workspace intermediate data. */ 1096 struct mlx5_flow_workspace { 1097 /* If creating another flow in same thread, push new as stack. */ 1098 struct mlx5_flow_workspace *prev; 1099 struct mlx5_flow_workspace *next; 1100 uint32_t inuse; /* can't create new flow with current. */ 1101 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1102 struct mlx5_flow_rss_desc rss_desc; 1103 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1104 uint32_t flow_idx; /* Intermediate device flow index. */ 1105 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */ 1106 struct mlx5_flow_meter_policy *policy; 1107 /* The meter policy used by meter in flow. */ 1108 struct mlx5_flow_meter_policy *final_policy; 1109 /* The final policy when meter policy is hierarchy. */ 1110 uint32_t skip_matcher_reg:1; 1111 /* Indicates if need to skip matcher register in translate. */ 1112 }; 1113 1114 struct mlx5_flow_split_info { 1115 bool external; 1116 /**< True if flow is created by request external to PMD. */ 1117 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1118 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1119 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1120 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1121 uint32_t table_id; /**< Flow table identifier. */ 1122 }; 1123 1124 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1125 const struct rte_flow_attr *attr, 1126 const struct rte_flow_item items[], 1127 const struct rte_flow_action actions[], 1128 bool external, 1129 int hairpin, 1130 struct rte_flow_error *error); 1131 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1132 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1133 const struct rte_flow_item items[], 1134 const struct rte_flow_action actions[], struct rte_flow_error *error); 1135 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1136 struct mlx5_flow *dev_flow, 1137 const struct rte_flow_attr *attr, 1138 const struct rte_flow_item items[], 1139 const struct rte_flow_action actions[], 1140 struct rte_flow_error *error); 1141 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1142 struct rte_flow_error *error); 1143 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1144 struct rte_flow *flow); 1145 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1146 struct rte_flow *flow); 1147 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1148 struct rte_flow *flow, 1149 const struct rte_flow_action *actions, 1150 void *data, 1151 struct rte_flow_error *error); 1152 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev, 1153 struct mlx5_flow_meter_info *fm, 1154 uint32_t mtr_idx, 1155 uint8_t domain_bitmap); 1156 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1157 struct mlx5_flow_meter_info *fm); 1158 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev); 1159 typedef struct mlx5_flow_meter_sub_policy * 1160 (*mlx5_flow_meter_sub_policy_rss_prepare_t) 1161 (struct rte_eth_dev *dev, 1162 struct mlx5_flow_meter_policy *mtr_policy, 1163 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1164 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t) 1165 (struct rte_eth_dev *dev, 1166 struct mlx5_flow_meter_info *fm, 1167 int32_t src_port, 1168 const struct rte_flow_item *item, 1169 struct rte_flow_error *error); 1170 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t) 1171 (struct rte_eth_dev *dev, 1172 struct mlx5_flow_meter_policy *mtr_policy); 1173 typedef uint32_t (*mlx5_flow_mtr_alloc_t) 1174 (struct rte_eth_dev *dev); 1175 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev, 1176 uint32_t mtr_idx); 1177 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1178 (struct rte_eth_dev *dev); 1179 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1180 uint32_t cnt); 1181 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1182 uint32_t cnt, 1183 bool clear, uint64_t *pkts, 1184 uint64_t *bytes); 1185 typedef int (*mlx5_flow_get_aged_flows_t) 1186 (struct rte_eth_dev *dev, 1187 void **context, 1188 uint32_t nb_contexts, 1189 struct rte_flow_error *error); 1190 typedef int (*mlx5_flow_action_validate_t) 1191 (struct rte_eth_dev *dev, 1192 const struct rte_flow_indir_action_conf *conf, 1193 const struct rte_flow_action *action, 1194 struct rte_flow_error *error); 1195 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1196 (struct rte_eth_dev *dev, 1197 const struct rte_flow_indir_action_conf *conf, 1198 const struct rte_flow_action *action, 1199 struct rte_flow_error *error); 1200 typedef int (*mlx5_flow_action_destroy_t) 1201 (struct rte_eth_dev *dev, 1202 struct rte_flow_action_handle *action, 1203 struct rte_flow_error *error); 1204 typedef int (*mlx5_flow_action_update_t) 1205 (struct rte_eth_dev *dev, 1206 struct rte_flow_action_handle *action, 1207 const void *update, 1208 struct rte_flow_error *error); 1209 typedef int (*mlx5_flow_action_query_t) 1210 (struct rte_eth_dev *dev, 1211 const struct rte_flow_action_handle *action, 1212 void *data, 1213 struct rte_flow_error *error); 1214 typedef int (*mlx5_flow_sync_domain_t) 1215 (struct rte_eth_dev *dev, 1216 uint32_t domains, 1217 uint32_t flags); 1218 typedef int (*mlx5_flow_validate_mtr_acts_t) 1219 (struct rte_eth_dev *dev, 1220 const struct rte_flow_action *actions[RTE_COLORS], 1221 struct rte_flow_attr *attr, 1222 bool *is_rss, 1223 uint8_t *domain_bitmap, 1224 bool *is_def_policy, 1225 struct rte_mtr_error *error); 1226 typedef int (*mlx5_flow_create_mtr_acts_t) 1227 (struct rte_eth_dev *dev, 1228 struct mlx5_flow_meter_policy *mtr_policy, 1229 const struct rte_flow_action *actions[RTE_COLORS], 1230 struct rte_mtr_error *error); 1231 typedef void (*mlx5_flow_destroy_mtr_acts_t) 1232 (struct rte_eth_dev *dev, 1233 struct mlx5_flow_meter_policy *mtr_policy); 1234 typedef int (*mlx5_flow_create_policy_rules_t) 1235 (struct rte_eth_dev *dev, 1236 struct mlx5_flow_meter_policy *mtr_policy); 1237 typedef void (*mlx5_flow_destroy_policy_rules_t) 1238 (struct rte_eth_dev *dev, 1239 struct mlx5_flow_meter_policy *mtr_policy); 1240 typedef int (*mlx5_flow_create_def_policy_t) 1241 (struct rte_eth_dev *dev); 1242 typedef void (*mlx5_flow_destroy_def_policy_t) 1243 (struct rte_eth_dev *dev); 1244 1245 struct mlx5_flow_driver_ops { 1246 mlx5_flow_validate_t validate; 1247 mlx5_flow_prepare_t prepare; 1248 mlx5_flow_translate_t translate; 1249 mlx5_flow_apply_t apply; 1250 mlx5_flow_remove_t remove; 1251 mlx5_flow_destroy_t destroy; 1252 mlx5_flow_query_t query; 1253 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1254 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1255 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls; 1256 mlx5_flow_mtr_alloc_t create_meter; 1257 mlx5_flow_mtr_free_t free_meter; 1258 mlx5_flow_validate_mtr_acts_t validate_mtr_acts; 1259 mlx5_flow_create_mtr_acts_t create_mtr_acts; 1260 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts; 1261 mlx5_flow_create_policy_rules_t create_policy_rules; 1262 mlx5_flow_destroy_policy_rules_t destroy_policy_rules; 1263 mlx5_flow_create_def_policy_t create_def_policy; 1264 mlx5_flow_destroy_def_policy_t destroy_def_policy; 1265 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare; 1266 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create; 1267 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq; 1268 mlx5_flow_counter_alloc_t counter_alloc; 1269 mlx5_flow_counter_free_t counter_free; 1270 mlx5_flow_counter_query_t counter_query; 1271 mlx5_flow_get_aged_flows_t get_aged_flows; 1272 mlx5_flow_action_validate_t action_validate; 1273 mlx5_flow_action_create_t action_create; 1274 mlx5_flow_action_destroy_t action_destroy; 1275 mlx5_flow_action_update_t action_update; 1276 mlx5_flow_action_query_t action_query; 1277 mlx5_flow_sync_domain_t sync_domain; 1278 }; 1279 1280 /* mlx5_flow.c */ 1281 1282 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1283 __extension__ 1284 struct flow_grp_info { 1285 uint64_t external:1; 1286 uint64_t transfer:1; 1287 uint64_t fdb_def_rule:1; 1288 /* force standard group translation */ 1289 uint64_t std_tbl_fix:1; 1290 uint64_t skip_scale:2; 1291 }; 1292 1293 static inline bool 1294 tunnel_use_standard_attr_group_translate 1295 (const struct rte_eth_dev *dev, 1296 const struct rte_flow_attr *attr, 1297 const struct mlx5_flow_tunnel *tunnel, 1298 enum mlx5_tof_rule_type tof_rule_type) 1299 { 1300 bool verdict; 1301 1302 if (!is_tunnel_offload_active(dev)) 1303 /* no tunnel offload API */ 1304 verdict = true; 1305 else if (tunnel) { 1306 /* 1307 * OvS will use jump to group 0 in tunnel steer rule. 1308 * If tunnel steer rule starts from group 0 (attr.group == 0) 1309 * that 0 group must be translated with standard method. 1310 * attr.group == 0 in tunnel match rule translated with tunnel 1311 * method 1312 */ 1313 verdict = !attr->group && 1314 is_flow_tunnel_steer_rule(tof_rule_type); 1315 } else { 1316 /* 1317 * non-tunnel group translation uses standard method for 1318 * root group only: attr.group == 0 1319 */ 1320 verdict = !attr->group; 1321 } 1322 1323 return verdict; 1324 } 1325 1326 /** 1327 * Get DV flow aso meter by index. 1328 * 1329 * @param[in] dev 1330 * Pointer to the Ethernet device structure. 1331 * @param[in] idx 1332 * mlx5 flow aso meter index in the container. 1333 * @param[out] ppool 1334 * mlx5 flow aso meter pool in the container, 1335 * 1336 * @return 1337 * Pointer to the aso meter, NULL otherwise. 1338 */ 1339 static inline struct mlx5_aso_mtr * 1340 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) 1341 { 1342 struct mlx5_aso_mtr_pool *pool; 1343 struct mlx5_aso_mtr_pools_mng *pools_mng = 1344 &priv->sh->mtrmng->pools_mng; 1345 1346 /* Decrease to original index. */ 1347 idx--; 1348 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n); 1349 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL]; 1350 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; 1351 } 1352 1353 static __rte_always_inline const struct rte_flow_item * 1354 mlx5_find_end_item(const struct rte_flow_item *item) 1355 { 1356 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++); 1357 return item; 1358 } 1359 1360 static __rte_always_inline bool 1361 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) 1362 { 1363 struct rte_flow_item_integrity test = *item; 1364 test.l3_ok = 0; 1365 test.l4_ok = 0; 1366 test.ipv4_csum_ok = 0; 1367 test.l4_csum_ok = 0; 1368 return (test.value == 0); 1369 } 1370 1371 /* 1372 * Get ASO CT action by device and index. 1373 * 1374 * @param[in] dev 1375 * Pointer to the Ethernet device structure. 1376 * @param[in] idx 1377 * Index to the ASO CT action. 1378 * 1379 * @return 1380 * The specified ASO CT action pointer. 1381 */ 1382 static inline struct mlx5_aso_ct_action * 1383 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx) 1384 { 1385 struct mlx5_priv *priv = dev->data->dev_private; 1386 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng; 1387 struct mlx5_aso_ct_pool *pool; 1388 1389 idx--; 1390 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n); 1391 /* Bit operation AND could be used. */ 1392 rte_rwlock_read_lock(&mng->resize_rwl); 1393 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL]; 1394 rte_rwlock_read_unlock(&mng->resize_rwl); 1395 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL]; 1396 } 1397 1398 /* 1399 * Get ASO CT action by owner & index. 1400 * 1401 * @param[in] dev 1402 * Pointer to the Ethernet device structure. 1403 * @param[in] idx 1404 * Index to the ASO CT action and owner port combination. 1405 * 1406 * @return 1407 * The specified ASO CT action pointer. 1408 */ 1409 static inline struct mlx5_aso_ct_action * 1410 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx) 1411 { 1412 struct mlx5_priv *priv = dev->data->dev_private; 1413 struct mlx5_aso_ct_action *ct; 1414 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx); 1415 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx); 1416 1417 if (owner == PORT_ID(priv)) { 1418 ct = flow_aso_ct_get_by_dev_idx(dev, idx); 1419 } else { 1420 struct rte_eth_dev *owndev = &rte_eth_devices[owner]; 1421 1422 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS); 1423 if (dev->data->dev_started != 1) 1424 return NULL; 1425 ct = flow_aso_ct_get_by_dev_idx(owndev, idx); 1426 if (ct->peer != PORT_ID(priv)) 1427 return NULL; 1428 } 1429 return ct; 1430 } 1431 1432 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1433 const struct mlx5_flow_tunnel *tunnel, 1434 uint32_t group, uint32_t *table, 1435 const struct flow_grp_info *flags, 1436 struct rte_flow_error *error); 1437 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1438 int tunnel, uint64_t layer_types, 1439 uint64_t hash_fields); 1440 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1441 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1442 uint32_t subpriority); 1443 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1444 const struct rte_flow_attr *attr); 1445 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1446 const struct rte_flow_attr *attr, 1447 uint32_t subpriority); 1448 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1449 enum mlx5_feature_name feature, 1450 uint32_t id, 1451 struct rte_flow_error *error); 1452 const struct rte_flow_action *mlx5_flow_find_action 1453 (const struct rte_flow_action *actions, 1454 enum rte_flow_action_type action); 1455 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1456 const struct rte_flow_action *action, 1457 struct rte_flow_error *error); 1458 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1459 const struct rte_flow_attr *attr, 1460 struct rte_flow_error *error); 1461 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1462 const struct rte_flow_attr *attr, 1463 struct rte_flow_error *error); 1464 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1465 const struct rte_flow_attr *attr, 1466 struct rte_flow_error *error); 1467 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1468 uint64_t action_flags, 1469 const struct rte_flow_attr *attr, 1470 struct rte_flow_error *error); 1471 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1472 uint64_t action_flags, 1473 struct rte_eth_dev *dev, 1474 const struct rte_flow_attr *attr, 1475 struct rte_flow_error *error); 1476 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1477 uint64_t action_flags, 1478 struct rte_eth_dev *dev, 1479 const struct rte_flow_attr *attr, 1480 uint64_t item_flags, 1481 struct rte_flow_error *error); 1482 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1483 const struct rte_flow_attr *attr, 1484 struct rte_flow_error *error); 1485 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1486 const struct rte_flow_attr *attributes, 1487 struct rte_flow_error *error); 1488 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1489 const uint8_t *mask, 1490 const uint8_t *nic_mask, 1491 unsigned int size, 1492 bool range_accepted, 1493 struct rte_flow_error *error); 1494 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1495 uint64_t item_flags, bool ext_vlan_sup, 1496 struct rte_flow_error *error); 1497 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1498 uint64_t item_flags, 1499 uint8_t target_protocol, 1500 struct rte_flow_error *error); 1501 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1502 uint64_t item_flags, 1503 const struct rte_flow_item *gre_item, 1504 struct rte_flow_error *error); 1505 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1506 uint64_t item_flags, 1507 uint64_t last_item, 1508 uint16_t ether_type, 1509 const struct rte_flow_item_ipv4 *acc_mask, 1510 bool range_accepted, 1511 struct rte_flow_error *error); 1512 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1513 uint64_t item_flags, 1514 uint64_t last_item, 1515 uint16_t ether_type, 1516 const struct rte_flow_item_ipv6 *acc_mask, 1517 struct rte_flow_error *error); 1518 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1519 const struct rte_flow_item *item, 1520 uint64_t item_flags, 1521 uint64_t prev_layer, 1522 struct rte_flow_error *error); 1523 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1524 uint64_t item_flags, 1525 uint8_t target_protocol, 1526 const struct rte_flow_item_tcp *flow_mask, 1527 struct rte_flow_error *error); 1528 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1529 uint64_t item_flags, 1530 uint8_t target_protocol, 1531 struct rte_flow_error *error); 1532 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1533 uint64_t item_flags, 1534 struct rte_eth_dev *dev, 1535 struct rte_flow_error *error); 1536 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 1537 const struct rte_flow_item *item, 1538 uint64_t item_flags, 1539 const struct rte_flow_attr *attr, 1540 struct rte_flow_error *error); 1541 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1542 uint64_t item_flags, 1543 struct rte_eth_dev *dev, 1544 struct rte_flow_error *error); 1545 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1546 uint64_t item_flags, 1547 uint8_t target_protocol, 1548 struct rte_flow_error *error); 1549 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1550 uint64_t item_flags, 1551 uint8_t target_protocol, 1552 struct rte_flow_error *error); 1553 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1554 uint64_t item_flags, 1555 uint8_t target_protocol, 1556 struct rte_flow_error *error); 1557 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1558 uint64_t item_flags, 1559 struct rte_eth_dev *dev, 1560 struct rte_flow_error *error); 1561 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1562 uint64_t last_item, 1563 const struct rte_flow_item *geneve_item, 1564 struct rte_eth_dev *dev, 1565 struct rte_flow_error *error); 1566 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1567 uint64_t item_flags, 1568 uint64_t last_item, 1569 uint16_t ether_type, 1570 const struct rte_flow_item_ecpri *acc_mask, 1571 struct rte_flow_error *error); 1572 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 1573 struct mlx5_flow_meter_info *fm, 1574 uint32_t mtr_idx, 1575 uint8_t domain_bitmap); 1576 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1577 struct mlx5_flow_meter_info *fm); 1578 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev); 1579 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare 1580 (struct rte_eth_dev *dev, 1581 struct mlx5_flow_meter_policy *mtr_policy, 1582 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1583 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 1584 struct mlx5_flow_meter_policy *mtr_policy); 1585 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1586 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1587 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1588 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1589 1590 /* Hash list callbacks for flow tables: */ 1591 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1592 uint64_t key, void *entry_ctx); 1593 int flow_dv_tbl_match_cb(struct mlx5_hlist *list, 1594 struct mlx5_hlist_entry *entry, uint64_t key, 1595 void *cb_ctx); 1596 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1597 struct mlx5_hlist_entry *entry); 1598 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1599 uint32_t table_level, uint8_t egress, uint8_t transfer, 1600 bool external, const struct mlx5_flow_tunnel *tunnel, 1601 uint32_t group_id, uint8_t dummy, 1602 uint32_t table_id, struct rte_flow_error *error); 1603 1604 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1605 uint64_t key, void *cb_ctx); 1606 int flow_dv_tag_match_cb(struct mlx5_hlist *list, 1607 struct mlx5_hlist_entry *entry, uint64_t key, 1608 void *cb_ctx); 1609 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1610 struct mlx5_hlist_entry *entry); 1611 1612 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1613 struct mlx5_hlist_entry *entry, 1614 uint64_t key, void *cb_ctx); 1615 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1616 uint64_t key, void *ctx); 1617 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1618 struct mlx5_hlist_entry *entry); 1619 1620 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1621 uint64_t key, void *ctx); 1622 int flow_dv_mreg_match_cb(struct mlx5_hlist *list, 1623 struct mlx5_hlist_entry *entry, uint64_t key, 1624 void *cb_ctx); 1625 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1626 struct mlx5_hlist_entry *entry); 1627 1628 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1629 struct mlx5_hlist_entry *entry, 1630 uint64_t key, void *cb_ctx); 1631 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1632 uint64_t key, void *cb_ctx); 1633 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1634 struct mlx5_hlist_entry *entry); 1635 1636 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1637 struct mlx5_cache_entry *entry, void *ctx); 1638 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1639 struct mlx5_cache_entry *entry, void *ctx); 1640 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1641 struct mlx5_cache_entry *entry); 1642 1643 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1644 struct mlx5_cache_entry *entry, void *cb_ctx); 1645 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1646 struct mlx5_cache_entry *entry, void *cb_ctx); 1647 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1648 struct mlx5_cache_entry *entry); 1649 1650 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1651 struct mlx5_cache_entry *entry, void *cb_ctx); 1652 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1653 (struct mlx5_cache_list *list, 1654 struct mlx5_cache_entry *entry, void *cb_ctx); 1655 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1656 struct mlx5_cache_entry *entry); 1657 1658 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1659 struct mlx5_cache_entry *entry, void *cb_ctx); 1660 struct mlx5_cache_entry *flow_dv_sample_create_cb 1661 (struct mlx5_cache_list *list, 1662 struct mlx5_cache_entry *entry, void *cb_ctx); 1663 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1664 struct mlx5_cache_entry *entry); 1665 1666 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1667 struct mlx5_cache_entry *entry, void *cb_ctx); 1668 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1669 (struct mlx5_cache_list *list, 1670 struct mlx5_cache_entry *entry, void *cb_ctx); 1671 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1672 struct mlx5_cache_entry *entry); 1673 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1674 uint32_t age_idx); 1675 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1676 const struct rte_flow_item *item, 1677 struct rte_flow_error *error); 1678 void flow_release_workspace(void *data); 1679 int mlx5_flow_os_init_workspace_once(void); 1680 void *mlx5_flow_os_get_specific_workspace(void); 1681 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1682 void mlx5_flow_os_release_workspace(void); 1683 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev); 1684 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx); 1685 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 1686 const struct rte_flow_action *actions[RTE_COLORS], 1687 struct rte_flow_attr *attr, 1688 bool *is_rss, 1689 uint8_t *domain_bitmap, 1690 bool *is_def_policy, 1691 struct rte_mtr_error *error); 1692 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 1693 struct mlx5_flow_meter_policy *mtr_policy); 1694 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 1695 struct mlx5_flow_meter_policy *mtr_policy, 1696 const struct rte_flow_action *actions[RTE_COLORS], 1697 struct rte_mtr_error *error); 1698 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 1699 struct mlx5_flow_meter_policy *mtr_policy); 1700 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 1701 struct mlx5_flow_meter_policy *mtr_policy); 1702 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev); 1703 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev); 1704 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1705 struct mlx5_flow_handle *dev_handle); 1706 const struct mlx5_flow_tunnel * 1707 mlx5_get_tof(const struct rte_flow_item *items, 1708 const struct rte_flow_action *actions, 1709 enum mlx5_tof_rule_type *rule_type); 1710 1711 1712 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1713