1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* E-Switch Manager port, used for rte_flow_item_port_id. */ 22 #define MLX5_PORT_ESW_MGR UINT32_MAX 23 24 /* Private rte flow items. */ 25 enum mlx5_rte_flow_item_type { 26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 31 }; 32 33 /* Private (internal) rte flow actions. */ 34 enum mlx5_rte_flow_action_type { 35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 36 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 37 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 41 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT, 43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP, 44 }; 45 46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 47 48 enum { 49 MLX5_INDIRECT_ACTION_TYPE_RSS, 50 MLX5_INDIRECT_ACTION_TYPE_AGE, 51 MLX5_INDIRECT_ACTION_TYPE_COUNT, 52 MLX5_INDIRECT_ACTION_TYPE_CT, 53 }; 54 55 /* Now, the maximal ports will be supported is 256, action number is 4M. */ 56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100 57 58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22 59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1) 60 61 /* 30-31: type, 22-29: owner port, 0-21: index. */ 62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \ 63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \ 64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \ 65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index)) 66 67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \ 68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \ 69 MLX5_INDIRECT_ACT_CT_OWNER_MASK) 70 71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \ 72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1)) 73 74 /* Matches on selected register. */ 75 struct mlx5_rte_flow_item_tag { 76 enum modify_reg id; 77 uint32_t data; 78 }; 79 80 /* Modify selected register. */ 81 struct mlx5_rte_flow_action_set_tag { 82 enum modify_reg id; 83 uint8_t offset; 84 uint8_t length; 85 uint32_t data; 86 }; 87 88 struct mlx5_flow_action_copy_mreg { 89 enum modify_reg dst; 90 enum modify_reg src; 91 }; 92 93 /* Matches on source queue. */ 94 struct mlx5_rte_flow_item_tx_queue { 95 uint32_t queue; 96 }; 97 98 /* Feature name to allocate metadata register. */ 99 enum mlx5_feature_name { 100 MLX5_HAIRPIN_RX, 101 MLX5_HAIRPIN_TX, 102 MLX5_METADATA_RX, 103 MLX5_METADATA_TX, 104 MLX5_METADATA_FDB, 105 MLX5_FLOW_MARK, 106 MLX5_APP_TAG, 107 MLX5_COPY_MARK, 108 MLX5_MTR_COLOR, 109 MLX5_MTR_ID, 110 MLX5_ASO_FLOW_HIT, 111 MLX5_ASO_CONNTRACK, 112 }; 113 114 /* Default queue number. */ 115 #define MLX5_RSSQ_DEFAULT_NUM 16 116 117 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 118 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 120 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 121 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 122 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 123 124 /* Pattern inner Layer bits. */ 125 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 126 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 127 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 128 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 129 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 130 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 131 132 /* Pattern tunnel Layer bits. */ 133 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 134 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 135 #define MLX5_FLOW_LAYER_GRE (1u << 14) 136 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 137 /* List of tunnel Layer bits continued below. */ 138 139 /* General pattern items bits. */ 140 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 141 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 142 #define MLX5_FLOW_ITEM_TAG (1u << 18) 143 #define MLX5_FLOW_ITEM_MARK (1u << 19) 144 145 /* Pattern MISC bits. */ 146 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 147 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 148 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 149 150 /* Pattern tunnel Layer bits (continued). */ 151 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 152 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 153 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 154 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 155 156 /* Queue items. */ 157 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 158 159 /* Pattern tunnel Layer bits (continued). */ 160 #define MLX5_FLOW_LAYER_GTP (1u << 28) 161 162 /* Pattern eCPRI Layer bit. */ 163 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 164 165 /* IPv6 Fragment Extension Header bit. */ 166 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 167 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 168 169 /* Pattern tunnel Layer bits (continued). */ 170 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 171 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 172 173 /* INTEGRITY item bit */ 174 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34) 175 176 /* Conntrack item. */ 177 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35) 178 179 /* Outer Masks. */ 180 #define MLX5_FLOW_LAYER_OUTER_L3 \ 181 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 182 #define MLX5_FLOW_LAYER_OUTER_L4 \ 183 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 184 #define MLX5_FLOW_LAYER_OUTER \ 185 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 186 MLX5_FLOW_LAYER_OUTER_L4) 187 188 /* Tunnel Masks. */ 189 #define MLX5_FLOW_LAYER_TUNNEL \ 190 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 191 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 192 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 193 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 194 195 /* Inner Masks. */ 196 #define MLX5_FLOW_LAYER_INNER_L3 \ 197 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 198 #define MLX5_FLOW_LAYER_INNER_L4 \ 199 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 200 #define MLX5_FLOW_LAYER_INNER \ 201 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 202 MLX5_FLOW_LAYER_INNER_L4) 203 204 /* Layer Masks. */ 205 #define MLX5_FLOW_LAYER_L2 \ 206 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 207 #define MLX5_FLOW_LAYER_L3_IPV4 \ 208 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 209 #define MLX5_FLOW_LAYER_L3_IPV6 \ 210 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 211 #define MLX5_FLOW_LAYER_L3 \ 212 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 213 #define MLX5_FLOW_LAYER_L4 \ 214 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 215 216 /* Actions */ 217 #define MLX5_FLOW_ACTION_DROP (1u << 0) 218 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 219 #define MLX5_FLOW_ACTION_RSS (1u << 2) 220 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 221 #define MLX5_FLOW_ACTION_MARK (1u << 4) 222 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 223 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 224 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 225 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 226 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 227 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 228 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 229 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 230 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 231 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 232 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 233 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 234 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 235 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 236 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 237 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 238 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 239 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 240 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 241 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 242 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 243 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 244 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 245 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 246 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 247 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 248 #define MLX5_FLOW_ACTION_METER (1ull << 31) 249 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 250 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 251 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 252 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 253 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 254 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 255 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 256 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 257 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40) 258 #define MLX5_FLOW_ACTION_CT (1ull << 41) 259 260 #define MLX5_FLOW_FATE_ACTIONS \ 261 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 262 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 263 MLX5_FLOW_ACTION_DEFAULT_MISS | \ 264 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 265 266 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 267 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 268 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 269 270 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 271 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 272 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 273 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 274 MLX5_FLOW_ACTION_SET_TP_SRC | \ 275 MLX5_FLOW_ACTION_SET_TP_DST | \ 276 MLX5_FLOW_ACTION_SET_TTL | \ 277 MLX5_FLOW_ACTION_DEC_TTL | \ 278 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 279 MLX5_FLOW_ACTION_SET_MAC_DST | \ 280 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 281 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 282 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 283 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 284 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 285 MLX5_FLOW_ACTION_SET_TAG | \ 286 MLX5_FLOW_ACTION_MARK_EXT | \ 287 MLX5_FLOW_ACTION_SET_META | \ 288 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 289 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 290 MLX5_FLOW_ACTION_MODIFY_FIELD) 291 292 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 293 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 294 295 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 296 297 #ifndef IPPROTO_MPLS 298 #define IPPROTO_MPLS 137 299 #endif 300 301 /* UDP port number for MPLS */ 302 #define MLX5_UDP_PORT_MPLS 6635 303 304 /* UDP port numbers for VxLAN. */ 305 #define MLX5_UDP_PORT_VXLAN 4789 306 #define MLX5_UDP_PORT_VXLAN_GPE 4790 307 308 /* UDP port numbers for GENEVE. */ 309 #define MLX5_UDP_PORT_GENEVE 6081 310 311 /* Lowest priority indicator. */ 312 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 313 314 /* 315 * Max priority for ingress\egress flow groups 316 * greater than 0 and for any transfer flow group. 317 * From user configation: 0 - 21843. 318 */ 319 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 320 321 /* 322 * Number of sub priorities. 323 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 324 * matching on the NIC (firmware dependent) L4 most have the higher priority 325 * followed by L3 and ending with L2. 326 */ 327 #define MLX5_PRIORITY_MAP_L2 2 328 #define MLX5_PRIORITY_MAP_L3 1 329 #define MLX5_PRIORITY_MAP_L4 0 330 #define MLX5_PRIORITY_MAP_MAX 3 331 332 /* Valid layer type for IPV4 RSS. */ 333 #define MLX5_IPV4_LAYER_TYPES \ 334 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \ 335 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 336 RTE_ETH_RSS_NONFRAG_IPV4_OTHER) 337 338 /* IBV hash source bits for IPV4. */ 339 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 340 341 /* Valid layer type for IPV6 RSS. */ 342 #define MLX5_IPV6_LAYER_TYPES \ 343 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 344 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \ 345 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER) 346 347 /* IBV hash source bits for IPV6. */ 348 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 349 350 /* IBV hash bits for L3 SRC. */ 351 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 352 353 /* IBV hash bits for L3 DST. */ 354 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 355 356 /* IBV hash bits for TCP. */ 357 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 358 IBV_RX_HASH_DST_PORT_TCP) 359 360 /* IBV hash bits for UDP. */ 361 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 362 IBV_RX_HASH_DST_PORT_UDP) 363 364 /* IBV hash bits for L4 SRC. */ 365 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 366 IBV_RX_HASH_SRC_PORT_UDP) 367 368 /* IBV hash bits for L4 DST. */ 369 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 370 IBV_RX_HASH_DST_PORT_UDP) 371 372 /* Geneve header first 16Bit */ 373 #define MLX5_GENEVE_VER_MASK 0x3 374 #define MLX5_GENEVE_VER_SHIFT 14 375 #define MLX5_GENEVE_VER_VAL(a) \ 376 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 377 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 378 #define MLX5_GENEVE_OPTLEN_SHIFT 8 379 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 380 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 381 #define MLX5_GENEVE_OAMF_MASK 0x1 382 #define MLX5_GENEVE_OAMF_SHIFT 7 383 #define MLX5_GENEVE_OAMF_VAL(a) \ 384 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 385 #define MLX5_GENEVE_CRITO_MASK 0x1 386 #define MLX5_GENEVE_CRITO_SHIFT 6 387 #define MLX5_GENEVE_CRITO_VAL(a) \ 388 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 389 #define MLX5_GENEVE_RSVD_MASK 0x3F 390 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 391 /* 392 * The length of the Geneve options fields, expressed in four byte multiples, 393 * not including the eight byte fixed tunnel. 394 */ 395 #define MLX5_GENEVE_OPT_LEN_0 14 396 #define MLX5_GENEVE_OPT_LEN_1 63 397 398 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 399 sizeof(struct rte_ipv4_hdr)) 400 /* GTP extension header flag. */ 401 #define MLX5_GTP_EXT_HEADER_FLAG 4 402 403 /* GTP extension header PDU type shift. */ 404 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 405 406 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 407 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 408 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 409 410 /* Specific item's fields can accept a range of values (using spec and last). */ 411 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 412 #define MLX5_ITEM_RANGE_ACCEPTED true 413 414 /* Software header modify action numbers of a flow. */ 415 #define MLX5_ACT_NUM_MDF_IPV4 1 416 #define MLX5_ACT_NUM_MDF_IPV6 4 417 #define MLX5_ACT_NUM_MDF_MAC 2 418 #define MLX5_ACT_NUM_MDF_VID 1 419 #define MLX5_ACT_NUM_MDF_PORT 2 420 #define MLX5_ACT_NUM_MDF_TTL 1 421 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 422 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 423 #define MLX5_ACT_NUM_MDF_TCPACK 1 424 #define MLX5_ACT_NUM_SET_REG 1 425 #define MLX5_ACT_NUM_SET_TAG 1 426 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 427 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 428 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 429 #define MLX5_ACT_NUM_SET_DSCP 1 430 431 /* Maximum number of fields to modify in MODIFY_FIELD */ 432 #define MLX5_ACT_MAX_MOD_FIELDS 5 433 434 /* Syndrome bits definition for connection tracking. */ 435 #define MLX5_CT_SYNDROME_VALID (0x0 << 6) 436 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6) 437 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6) 438 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1) 439 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0) 440 441 enum mlx5_flow_drv_type { 442 MLX5_FLOW_TYPE_MIN, 443 MLX5_FLOW_TYPE_DV, 444 MLX5_FLOW_TYPE_VERBS, 445 MLX5_FLOW_TYPE_MAX, 446 }; 447 448 /* Fate action type. */ 449 enum mlx5_flow_fate_type { 450 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 451 MLX5_FLOW_FATE_QUEUE, 452 MLX5_FLOW_FATE_JUMP, 453 MLX5_FLOW_FATE_PORT_ID, 454 MLX5_FLOW_FATE_DROP, 455 MLX5_FLOW_FATE_DEFAULT_MISS, 456 MLX5_FLOW_FATE_SHARED_RSS, 457 MLX5_FLOW_FATE_MTR, 458 MLX5_FLOW_FATE_MAX, 459 }; 460 461 /* Matcher PRM representation */ 462 struct mlx5_flow_dv_match_params { 463 size_t size; 464 /**< Size of match value. Do NOT split size and key! */ 465 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 466 /**< Matcher value. This value is used as the mask or as a key. */ 467 }; 468 469 /* Matcher structure. */ 470 struct mlx5_flow_dv_matcher { 471 struct mlx5_list_entry entry; /**< Pointer to the next element. */ 472 struct mlx5_flow_tbl_resource *tbl; 473 /**< Pointer to the table(group) the matcher associated with. */ 474 void *matcher_object; /**< Pointer to DV matcher */ 475 uint16_t crc; /**< CRC of key. */ 476 uint16_t priority; /**< Priority of matcher. */ 477 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 478 }; 479 480 #define MLX5_ENCAP_MAX_LEN 132 481 482 /* Encap/decap resource structure. */ 483 struct mlx5_flow_dv_encap_decap_resource { 484 struct mlx5_list_entry entry; 485 /* Pointer to next element. */ 486 uint32_t refcnt; /**< Reference counter. */ 487 void *action; 488 /**< Encap/decap action object. */ 489 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 490 size_t size; 491 uint8_t reformat_type; 492 uint8_t ft_type; 493 uint64_t flags; /**< Flags for RDMA API. */ 494 uint32_t idx; /**< Index for the index memory pool. */ 495 }; 496 497 /* Tag resource structure. */ 498 struct mlx5_flow_dv_tag_resource { 499 struct mlx5_list_entry entry; 500 /**< hash list entry for tag resource, tag value as the key. */ 501 void *action; 502 /**< Tag action object. */ 503 uint32_t refcnt; /**< Reference counter. */ 504 uint32_t idx; /**< Index for the index memory pool. */ 505 uint32_t tag_id; /**< Tag ID. */ 506 }; 507 508 /* Modify resource structure */ 509 struct mlx5_flow_dv_modify_hdr_resource { 510 struct mlx5_list_entry entry; 511 void *action; /**< Modify header action object. */ 512 uint32_t idx; 513 /* Key area for hash list matching: */ 514 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 515 uint8_t actions_num; /**< Number of modification actions. */ 516 bool root; /**< Whether action is in root table. */ 517 struct mlx5_modification_cmd actions[]; 518 /**< Modification actions. */ 519 } __rte_packed; 520 521 /* Modify resource key of the hash organization. */ 522 union mlx5_flow_modify_hdr_key { 523 struct { 524 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 525 uint32_t actions_num:5; /**< Number of modification actions. */ 526 uint32_t group:19; /**< Flow group id. */ 527 uint32_t cksum; /**< Actions check sum. */ 528 }; 529 uint64_t v64; /**< full 64bits value of key */ 530 }; 531 532 /* Jump action resource structure. */ 533 struct mlx5_flow_dv_jump_tbl_resource { 534 void *action; /**< Pointer to the rdma core action. */ 535 }; 536 537 /* Port ID resource structure. */ 538 struct mlx5_flow_dv_port_id_action_resource { 539 struct mlx5_list_entry entry; 540 void *action; /**< Action object. */ 541 uint32_t port_id; /**< Port ID value. */ 542 uint32_t idx; /**< Indexed pool memory index. */ 543 }; 544 545 /* Push VLAN action resource structure */ 546 struct mlx5_flow_dv_push_vlan_action_resource { 547 struct mlx5_list_entry entry; /* Cache entry. */ 548 void *action; /**< Action object. */ 549 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 550 rte_be32_t vlan_tag; /**< VLAN tag value. */ 551 uint32_t idx; /**< Indexed pool memory index. */ 552 }; 553 554 /* Metadata register copy table entry. */ 555 struct mlx5_flow_mreg_copy_resource { 556 /* 557 * Hash list entry for copy table. 558 * - Key is 32/64-bit MARK action ID. 559 * - MUST be the first entry. 560 */ 561 struct mlx5_list_entry hlist_ent; 562 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 563 /* List entry for device flows. */ 564 uint32_t idx; 565 uint32_t rix_flow; /* Built flow for copy. */ 566 uint32_t mark_id; 567 }; 568 569 /* Table tunnel parameter. */ 570 struct mlx5_flow_tbl_tunnel_prm { 571 const struct mlx5_flow_tunnel *tunnel; 572 uint32_t group_id; 573 bool external; 574 }; 575 576 /* Table data structure of the hash organization. */ 577 struct mlx5_flow_tbl_data_entry { 578 struct mlx5_list_entry entry; 579 /**< hash list entry, 64-bits key inside. */ 580 struct mlx5_flow_tbl_resource tbl; 581 /**< flow table resource. */ 582 struct mlx5_list *matchers; 583 /**< matchers' header associated with the flow table. */ 584 struct mlx5_flow_dv_jump_tbl_resource jump; 585 /**< jump resource, at most one for each table created. */ 586 uint32_t idx; /**< index for the indexed mempool. */ 587 /**< tunnel offload */ 588 const struct mlx5_flow_tunnel *tunnel; 589 uint32_t group_id; 590 uint32_t external:1; 591 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 592 uint32_t is_egress:1; /**< Egress table. */ 593 uint32_t is_transfer:1; /**< Transfer table. */ 594 uint32_t dummy:1; /**< DR table. */ 595 uint32_t id:22; /**< Table ID. */ 596 uint32_t reserve:5; /**< Reserved to future using. */ 597 uint32_t level; /**< Table level. */ 598 }; 599 600 /* Sub rdma-core actions list. */ 601 struct mlx5_flow_sub_actions_list { 602 uint32_t actions_num; /**< Number of sample actions. */ 603 uint64_t action_flags; 604 void *dr_queue_action; 605 void *dr_tag_action; 606 void *dr_cnt_action; 607 void *dr_port_id_action; 608 void *dr_encap_action; 609 void *dr_jump_action; 610 }; 611 612 /* Sample sub-actions resource list. */ 613 struct mlx5_flow_sub_actions_idx { 614 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 615 uint32_t rix_tag; /**< Index to the tag action. */ 616 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 617 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 618 uint32_t rix_jump; /**< Index to the jump action resource. */ 619 }; 620 621 /* Sample action resource structure. */ 622 struct mlx5_flow_dv_sample_resource { 623 struct mlx5_list_entry entry; /**< Cache entry. */ 624 union { 625 void *verbs_action; /**< Verbs sample action object. */ 626 void **sub_actions; /**< Sample sub-action array. */ 627 }; 628 struct rte_eth_dev *dev; /**< Device registers the action. */ 629 uint32_t idx; /** Sample object index. */ 630 uint8_t ft_type; /** Flow Table Type */ 631 uint32_t ft_id; /** Flow Table Level */ 632 uint32_t ratio; /** Sample Ratio */ 633 uint64_t set_action; /** Restore reg_c0 value */ 634 void *normal_path_tbl; /** Flow Table pointer */ 635 struct mlx5_flow_sub_actions_idx sample_idx; 636 /**< Action index resources. */ 637 struct mlx5_flow_sub_actions_list sample_act; 638 /**< Action resources. */ 639 }; 640 641 #define MLX5_MAX_DEST_NUM 2 642 643 /* Destination array action resource structure. */ 644 struct mlx5_flow_dv_dest_array_resource { 645 struct mlx5_list_entry entry; /**< Cache entry. */ 646 uint32_t idx; /** Destination array action object index. */ 647 uint8_t ft_type; /** Flow Table Type */ 648 uint8_t num_of_dest; /**< Number of destination actions. */ 649 struct rte_eth_dev *dev; /**< Device registers the action. */ 650 void *action; /**< Pointer to the rdma core action. */ 651 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 652 /**< Action index resources. */ 653 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 654 /**< Action resources. */ 655 }; 656 657 /* PMD flow priority for tunnel */ 658 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 659 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 660 661 662 /** Device flow handle structure for DV mode only. */ 663 struct mlx5_flow_handle_dv { 664 /* Flow DV api: */ 665 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 666 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 667 /**< Pointer to modify header resource in cache. */ 668 uint32_t rix_encap_decap; 669 /**< Index to encap/decap resource in cache. */ 670 uint32_t rix_push_vlan; 671 /**< Index to push VLAN action resource in cache. */ 672 uint32_t rix_tag; 673 /**< Index to the tag action. */ 674 uint32_t rix_sample; 675 /**< Index to sample action resource in cache. */ 676 uint32_t rix_dest_array; 677 /**< Index to destination array resource in cache. */ 678 } __rte_packed; 679 680 /** Device flow handle structure: used both for creating & destroying. */ 681 struct mlx5_flow_handle { 682 SILIST_ENTRY(uint32_t)next; 683 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 684 /**< Index to next device flow handle. */ 685 uint64_t layers; 686 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 687 void *drv_flow; /**< pointer to driver flow object. */ 688 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */ 689 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */ 690 uint32_t mark:1; /**< Metadate rxq mark flag. */ 691 uint32_t fate_action:3; /**< Fate action type. */ 692 union { 693 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 694 uint32_t rix_jump; /**< Index to the jump action resource. */ 695 uint32_t rix_port_id_action; 696 /**< Index to port ID action resource. */ 697 uint32_t rix_fate; 698 /**< Generic value indicates the fate action. */ 699 uint32_t rix_default_fate; 700 /**< Indicates default miss fate action. */ 701 uint32_t rix_srss; 702 /**< Indicates shared RSS fate action. */ 703 }; 704 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 705 struct mlx5_flow_handle_dv dvh; 706 #endif 707 } __rte_packed; 708 709 /* 710 * Size for Verbs device flow handle structure only. Do not use the DV only 711 * structure in Verbs. No DV flows attributes will be accessed. 712 * Macro offsetof() could also be used here. 713 */ 714 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 715 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 716 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 717 #else 718 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 719 #endif 720 721 /** Device flow structure only for DV flow creation. */ 722 struct mlx5_flow_dv_workspace { 723 uint32_t group; /**< The group index. */ 724 uint32_t table_id; /**< Flow table identifier. */ 725 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 726 int actions_n; /**< number of actions. */ 727 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 728 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 729 /**< Pointer to encap/decap resource in cache. */ 730 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 731 /**< Pointer to push VLAN action resource in cache. */ 732 struct mlx5_flow_dv_tag_resource *tag_resource; 733 /**< pointer to the tag action. */ 734 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 735 /**< Pointer to port ID action resource. */ 736 struct mlx5_flow_dv_jump_tbl_resource *jump; 737 /**< Pointer to the jump action resource. */ 738 struct mlx5_flow_dv_match_params value; 739 /**< Holds the value that the packet is compared to. */ 740 struct mlx5_flow_dv_sample_resource *sample_res; 741 /**< Pointer to the sample action resource. */ 742 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 743 /**< Pointer to the destination array resource. */ 744 }; 745 746 #ifdef HAVE_INFINIBAND_VERBS_H 747 /* 748 * Maximal Verbs flow specifications & actions size. 749 * Some elements are mutually exclusive, but enough space should be allocated. 750 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 751 * 2. One tunnel header (exception: GRE + MPLS), 752 * SPEC length: GRE == tunnel. 753 * Actions: 1. 1 Mark OR Flag. 754 * 2. 1 Drop (if any). 755 * 3. No limitation for counters, but it makes no sense to support too 756 * many counters in a single device flow. 757 */ 758 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 759 #define MLX5_VERBS_MAX_SPEC_SIZE \ 760 ( \ 761 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 762 sizeof(struct ibv_flow_spec_ipv6) + \ 763 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 764 sizeof(struct ibv_flow_spec_gre) + \ 765 sizeof(struct ibv_flow_spec_mpls)) \ 766 ) 767 #else 768 #define MLX5_VERBS_MAX_SPEC_SIZE \ 769 ( \ 770 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 771 sizeof(struct ibv_flow_spec_ipv6) + \ 772 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 773 sizeof(struct ibv_flow_spec_tunnel)) \ 774 ) 775 #endif 776 777 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 778 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 779 #define MLX5_VERBS_MAX_ACT_SIZE \ 780 ( \ 781 sizeof(struct ibv_flow_spec_action_tag) + \ 782 sizeof(struct ibv_flow_spec_action_drop) + \ 783 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 784 ) 785 #else 786 #define MLX5_VERBS_MAX_ACT_SIZE \ 787 ( \ 788 sizeof(struct ibv_flow_spec_action_tag) + \ 789 sizeof(struct ibv_flow_spec_action_drop) \ 790 ) 791 #endif 792 793 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 794 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 795 796 /** Device flow structure only for Verbs flow creation. */ 797 struct mlx5_flow_verbs_workspace { 798 unsigned int size; /**< Size of the attribute. */ 799 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 800 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 801 /**< Specifications & actions buffer of verbs flow. */ 802 }; 803 #endif /* HAVE_INFINIBAND_VERBS_H */ 804 805 #define MLX5_SCALE_FLOW_GROUP_BIT 0 806 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 807 808 /** Maximal number of device sub-flows supported. */ 809 #define MLX5_NUM_MAX_DEV_FLOWS 32 810 811 /** 812 * tunnel offload rules type 813 */ 814 enum mlx5_tof_rule_type { 815 MLX5_TUNNEL_OFFLOAD_NONE = 0, 816 MLX5_TUNNEL_OFFLOAD_SET_RULE, 817 MLX5_TUNNEL_OFFLOAD_MATCH_RULE, 818 MLX5_TUNNEL_OFFLOAD_MISS_RULE, 819 }; 820 821 /** Device flow structure. */ 822 __extension__ 823 struct mlx5_flow { 824 struct rte_flow *flow; /**< Pointer to the main flow. */ 825 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 826 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 827 uint64_t act_flags; 828 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 829 bool external; /**< true if the flow is created external to PMD. */ 830 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 831 uint8_t skip_scale:2; 832 /** 833 * Each Bit be set to 1 if Skip the scale the flow group with factor. 834 * If bit0 be set to 1, then skip the scale the original flow group; 835 * If bit1 be set to 1, then skip the scale the jump flow group if 836 * having jump action. 837 * 00: Enable scale in a flow, default value. 838 * 01: Skip scale the flow group with factor, enable scale the group 839 * of jump action. 840 * 10: Enable scale the group with factor, skip scale the group of 841 * jump action. 842 * 11: Skip scale the table with factor both for flow group and jump 843 * group. 844 */ 845 union { 846 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 847 struct mlx5_flow_dv_workspace dv; 848 #endif 849 #ifdef HAVE_INFINIBAND_VERBS_H 850 struct mlx5_flow_verbs_workspace verbs; 851 #endif 852 }; 853 struct mlx5_flow_handle *handle; 854 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 855 const struct mlx5_flow_tunnel *tunnel; 856 enum mlx5_tof_rule_type tof_type; 857 }; 858 859 /* Flow meter state. */ 860 #define MLX5_FLOW_METER_DISABLE 0 861 #define MLX5_FLOW_METER_ENABLE 1 862 863 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u 864 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u 865 866 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES 867 868 #define MLX5_MAN_WIDTH 8 869 /* Legacy Meter parameter structure. */ 870 struct mlx5_legacy_flow_meter { 871 struct mlx5_flow_meter_info fm; 872 /* Must be the first in struct. */ 873 TAILQ_ENTRY(mlx5_legacy_flow_meter) next; 874 /**< Pointer to the next flow meter structure. */ 875 uint32_t idx; 876 /* Index to meter object. */ 877 }; 878 879 #define MLX5_MAX_TUNNELS 256 880 #define MLX5_TNL_MISS_RULE_PRIORITY 3 881 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 882 883 /* 884 * When tunnel offload is active, all JUMP group ids are converted 885 * using the same method. That conversion is applied both to tunnel and 886 * regular rule types. 887 * Group ids used in tunnel rules are relative to it's tunnel (!). 888 * Application can create number of steer rules, using the same 889 * tunnel, with different group id in each rule. 890 * Each tunnel stores its groups internally in PMD tunnel object. 891 * Groups used in regular rules do not belong to any tunnel and are stored 892 * in tunnel hub. 893 */ 894 895 struct mlx5_flow_tunnel { 896 LIST_ENTRY(mlx5_flow_tunnel) chain; 897 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 898 uint32_t tunnel_id; /** unique tunnel ID */ 899 uint32_t refctn; 900 struct rte_flow_action action; 901 struct rte_flow_item item; 902 struct mlx5_hlist *groups; /** tunnel groups */ 903 }; 904 905 /** PMD tunnel related context */ 906 struct mlx5_flow_tunnel_hub { 907 /* Tunnels list 908 * Access to the list MUST be MT protected 909 */ 910 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 911 /* protect access to the tunnels list */ 912 rte_spinlock_t sl; 913 struct mlx5_hlist *groups; /** non tunnel groups */ 914 }; 915 916 /* convert jump group to flow table ID in tunnel rules */ 917 struct tunnel_tbl_entry { 918 struct mlx5_list_entry hash; 919 uint32_t flow_table; 920 uint32_t tunnel_id; 921 uint32_t group; 922 }; 923 924 static inline uint32_t 925 tunnel_id_to_flow_tbl(uint32_t id) 926 { 927 return id | (1u << 16); 928 } 929 930 static inline uint32_t 931 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 932 { 933 return flow_tbl & ~(1u << 16); 934 } 935 936 union tunnel_tbl_key { 937 uint64_t val; 938 struct { 939 uint32_t tunnel_id; 940 uint32_t group; 941 }; 942 }; 943 944 static inline struct mlx5_flow_tunnel_hub * 945 mlx5_tunnel_hub(struct rte_eth_dev *dev) 946 { 947 struct mlx5_priv *priv = dev->data->dev_private; 948 return priv->sh->tunnel_hub; 949 } 950 951 static inline bool 952 is_tunnel_offload_active(const struct rte_eth_dev *dev) 953 { 954 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 955 const struct mlx5_priv *priv = dev->data->dev_private; 956 return !!priv->config.dv_miss_info; 957 #else 958 RTE_SET_USED(dev); 959 return false; 960 #endif 961 } 962 963 static inline bool 964 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type) 965 { 966 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 967 } 968 969 static inline bool 970 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type) 971 { 972 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE; 973 } 974 975 static inline const struct mlx5_flow_tunnel * 976 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 977 { 978 return actions[0].conf; 979 } 980 981 static inline const struct mlx5_flow_tunnel * 982 flow_items_to_tunnel(const struct rte_flow_item items[]) 983 { 984 return items[0].spec; 985 } 986 987 /* Flow structure. */ 988 struct rte_flow { 989 uint32_t dev_handles; 990 /**< Device flow handles that are part of the flow. */ 991 uint32_t type:2; 992 uint32_t drv_type:2; /**< Driver type. */ 993 uint32_t tunnel:1; 994 uint32_t meter:24; /**< Holds flow meter id. */ 995 uint32_t indirect_type:2; /**< Indirect action type. */ 996 uint32_t rix_mreg_copy; 997 /**< Index to metadata register copy table resource. */ 998 uint32_t counter; /**< Holds flow counter. */ 999 uint32_t tunnel_id; /**< Tunnel id */ 1000 union { 1001 uint32_t age; /**< Holds ASO age bit index. */ 1002 uint32_t ct; /**< Holds ASO CT index. */ 1003 }; 1004 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 1005 } __rte_packed; 1006 1007 /* 1008 * Define list of valid combinations of RX Hash fields 1009 * (see enum ibv_rx_hash_fields). 1010 */ 1011 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1012 #define MLX5_RSS_HASH_IPV4_TCP \ 1013 (MLX5_RSS_HASH_IPV4 | \ 1014 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1015 #define MLX5_RSS_HASH_IPV4_UDP \ 1016 (MLX5_RSS_HASH_IPV4 | \ 1017 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1018 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1019 #define MLX5_RSS_HASH_IPV6_TCP \ 1020 (MLX5_RSS_HASH_IPV6 | \ 1021 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1022 #define MLX5_RSS_HASH_IPV6_UDP \ 1023 (MLX5_RSS_HASH_IPV6 | \ 1024 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1025 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 1026 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 1027 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 1028 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1029 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1030 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1031 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1032 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1033 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1034 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1035 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1036 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1037 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1038 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1039 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1040 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1041 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1042 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1043 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1044 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1045 #define MLX5_RSS_HASH_NONE 0ULL 1046 1047 1048 /* extract next protocol type from Ethernet & VLAN headers */ 1049 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \ 1050 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \ 1051 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \ 1052 (_prt) = rte_be_to_cpu_16((_prt)); \ 1053 } while (0) 1054 1055 /* array of valid combinations of RX Hash fields for RSS */ 1056 static const uint64_t mlx5_rss_hash_fields[] = { 1057 MLX5_RSS_HASH_IPV4, 1058 MLX5_RSS_HASH_IPV4_TCP, 1059 MLX5_RSS_HASH_IPV4_UDP, 1060 MLX5_RSS_HASH_IPV6, 1061 MLX5_RSS_HASH_IPV6_TCP, 1062 MLX5_RSS_HASH_IPV6_UDP, 1063 MLX5_RSS_HASH_NONE, 1064 }; 1065 1066 /* Shared RSS action structure */ 1067 struct mlx5_shared_action_rss { 1068 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1069 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1070 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1071 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1072 struct mlx5_ind_table_obj *ind_tbl; 1073 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1074 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1075 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1076 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1077 }; 1078 1079 struct rte_flow_action_handle { 1080 uint32_t id; 1081 }; 1082 1083 /* Thread specific flow workspace intermediate data. */ 1084 struct mlx5_flow_workspace { 1085 /* If creating another flow in same thread, push new as stack. */ 1086 struct mlx5_flow_workspace *prev; 1087 struct mlx5_flow_workspace *next; 1088 uint32_t inuse; /* can't create new flow with current. */ 1089 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1090 struct mlx5_flow_rss_desc rss_desc; 1091 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1092 uint32_t flow_idx; /* Intermediate device flow index. */ 1093 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */ 1094 struct mlx5_flow_meter_policy *policy; 1095 /* The meter policy used by meter in flow. */ 1096 struct mlx5_flow_meter_policy *final_policy; 1097 /* The final policy when meter policy is hierarchy. */ 1098 uint32_t skip_matcher_reg:1; 1099 /* Indicates if need to skip matcher register in translate. */ 1100 }; 1101 1102 struct mlx5_flow_split_info { 1103 bool external; 1104 /**< True if flow is created by request external to PMD. */ 1105 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1106 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1107 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1108 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1109 uint32_t table_id; /**< Flow table identifier. */ 1110 }; 1111 1112 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1113 const struct rte_flow_attr *attr, 1114 const struct rte_flow_item items[], 1115 const struct rte_flow_action actions[], 1116 bool external, 1117 int hairpin, 1118 struct rte_flow_error *error); 1119 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1120 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1121 const struct rte_flow_item items[], 1122 const struct rte_flow_action actions[], struct rte_flow_error *error); 1123 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1124 struct mlx5_flow *dev_flow, 1125 const struct rte_flow_attr *attr, 1126 const struct rte_flow_item items[], 1127 const struct rte_flow_action actions[], 1128 struct rte_flow_error *error); 1129 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1130 struct rte_flow_error *error); 1131 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1132 struct rte_flow *flow); 1133 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1134 struct rte_flow *flow); 1135 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1136 struct rte_flow *flow, 1137 const struct rte_flow_action *actions, 1138 void *data, 1139 struct rte_flow_error *error); 1140 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev, 1141 struct mlx5_flow_meter_info *fm, 1142 uint32_t mtr_idx, 1143 uint8_t domain_bitmap); 1144 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1145 struct mlx5_flow_meter_info *fm); 1146 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev); 1147 typedef struct mlx5_flow_meter_sub_policy * 1148 (*mlx5_flow_meter_sub_policy_rss_prepare_t) 1149 (struct rte_eth_dev *dev, 1150 struct mlx5_flow_meter_policy *mtr_policy, 1151 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1152 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t) 1153 (struct rte_eth_dev *dev, 1154 struct mlx5_flow_meter_info *fm, 1155 int32_t src_port, 1156 const struct rte_flow_item *item, 1157 struct rte_flow_error *error); 1158 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t) 1159 (struct rte_eth_dev *dev, 1160 struct mlx5_flow_meter_policy *mtr_policy); 1161 typedef uint32_t (*mlx5_flow_mtr_alloc_t) 1162 (struct rte_eth_dev *dev); 1163 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev, 1164 uint32_t mtr_idx); 1165 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1166 (struct rte_eth_dev *dev); 1167 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1168 uint32_t cnt); 1169 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1170 uint32_t cnt, 1171 bool clear, uint64_t *pkts, 1172 uint64_t *bytes); 1173 typedef int (*mlx5_flow_get_aged_flows_t) 1174 (struct rte_eth_dev *dev, 1175 void **context, 1176 uint32_t nb_contexts, 1177 struct rte_flow_error *error); 1178 typedef int (*mlx5_flow_action_validate_t) 1179 (struct rte_eth_dev *dev, 1180 const struct rte_flow_indir_action_conf *conf, 1181 const struct rte_flow_action *action, 1182 struct rte_flow_error *error); 1183 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1184 (struct rte_eth_dev *dev, 1185 const struct rte_flow_indir_action_conf *conf, 1186 const struct rte_flow_action *action, 1187 struct rte_flow_error *error); 1188 typedef int (*mlx5_flow_action_destroy_t) 1189 (struct rte_eth_dev *dev, 1190 struct rte_flow_action_handle *action, 1191 struct rte_flow_error *error); 1192 typedef int (*mlx5_flow_action_update_t) 1193 (struct rte_eth_dev *dev, 1194 struct rte_flow_action_handle *action, 1195 const void *update, 1196 struct rte_flow_error *error); 1197 typedef int (*mlx5_flow_action_query_t) 1198 (struct rte_eth_dev *dev, 1199 const struct rte_flow_action_handle *action, 1200 void *data, 1201 struct rte_flow_error *error); 1202 typedef int (*mlx5_flow_sync_domain_t) 1203 (struct rte_eth_dev *dev, 1204 uint32_t domains, 1205 uint32_t flags); 1206 typedef int (*mlx5_flow_validate_mtr_acts_t) 1207 (struct rte_eth_dev *dev, 1208 const struct rte_flow_action *actions[RTE_COLORS], 1209 struct rte_flow_attr *attr, 1210 bool *is_rss, 1211 uint8_t *domain_bitmap, 1212 uint8_t *policy_mode, 1213 struct rte_mtr_error *error); 1214 typedef int (*mlx5_flow_create_mtr_acts_t) 1215 (struct rte_eth_dev *dev, 1216 struct mlx5_flow_meter_policy *mtr_policy, 1217 const struct rte_flow_action *actions[RTE_COLORS], 1218 struct rte_mtr_error *error); 1219 typedef void (*mlx5_flow_destroy_mtr_acts_t) 1220 (struct rte_eth_dev *dev, 1221 struct mlx5_flow_meter_policy *mtr_policy); 1222 typedef int (*mlx5_flow_create_policy_rules_t) 1223 (struct rte_eth_dev *dev, 1224 struct mlx5_flow_meter_policy *mtr_policy); 1225 typedef void (*mlx5_flow_destroy_policy_rules_t) 1226 (struct rte_eth_dev *dev, 1227 struct mlx5_flow_meter_policy *mtr_policy); 1228 typedef int (*mlx5_flow_create_def_policy_t) 1229 (struct rte_eth_dev *dev); 1230 typedef void (*mlx5_flow_destroy_def_policy_t) 1231 (struct rte_eth_dev *dev); 1232 1233 struct mlx5_flow_driver_ops { 1234 mlx5_flow_validate_t validate; 1235 mlx5_flow_prepare_t prepare; 1236 mlx5_flow_translate_t translate; 1237 mlx5_flow_apply_t apply; 1238 mlx5_flow_remove_t remove; 1239 mlx5_flow_destroy_t destroy; 1240 mlx5_flow_query_t query; 1241 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1242 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1243 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls; 1244 mlx5_flow_mtr_alloc_t create_meter; 1245 mlx5_flow_mtr_free_t free_meter; 1246 mlx5_flow_validate_mtr_acts_t validate_mtr_acts; 1247 mlx5_flow_create_mtr_acts_t create_mtr_acts; 1248 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts; 1249 mlx5_flow_create_policy_rules_t create_policy_rules; 1250 mlx5_flow_destroy_policy_rules_t destroy_policy_rules; 1251 mlx5_flow_create_def_policy_t create_def_policy; 1252 mlx5_flow_destroy_def_policy_t destroy_def_policy; 1253 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare; 1254 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create; 1255 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq; 1256 mlx5_flow_counter_alloc_t counter_alloc; 1257 mlx5_flow_counter_free_t counter_free; 1258 mlx5_flow_counter_query_t counter_query; 1259 mlx5_flow_get_aged_flows_t get_aged_flows; 1260 mlx5_flow_action_validate_t action_validate; 1261 mlx5_flow_action_create_t action_create; 1262 mlx5_flow_action_destroy_t action_destroy; 1263 mlx5_flow_action_update_t action_update; 1264 mlx5_flow_action_query_t action_query; 1265 mlx5_flow_sync_domain_t sync_domain; 1266 }; 1267 1268 /* mlx5_flow.c */ 1269 1270 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1271 __extension__ 1272 struct flow_grp_info { 1273 uint64_t external:1; 1274 uint64_t transfer:1; 1275 uint64_t fdb_def_rule:1; 1276 /* force standard group translation */ 1277 uint64_t std_tbl_fix:1; 1278 uint64_t skip_scale:2; 1279 }; 1280 1281 static inline bool 1282 tunnel_use_standard_attr_group_translate 1283 (const struct rte_eth_dev *dev, 1284 const struct rte_flow_attr *attr, 1285 const struct mlx5_flow_tunnel *tunnel, 1286 enum mlx5_tof_rule_type tof_rule_type) 1287 { 1288 bool verdict; 1289 1290 if (!is_tunnel_offload_active(dev)) 1291 /* no tunnel offload API */ 1292 verdict = true; 1293 else if (tunnel) { 1294 /* 1295 * OvS will use jump to group 0 in tunnel steer rule. 1296 * If tunnel steer rule starts from group 0 (attr.group == 0) 1297 * that 0 group must be translated with standard method. 1298 * attr.group == 0 in tunnel match rule translated with tunnel 1299 * method 1300 */ 1301 verdict = !attr->group && 1302 is_flow_tunnel_steer_rule(tof_rule_type); 1303 } else { 1304 /* 1305 * non-tunnel group translation uses standard method for 1306 * root group only: attr.group == 0 1307 */ 1308 verdict = !attr->group; 1309 } 1310 1311 return verdict; 1312 } 1313 1314 /** 1315 * Get DV flow aso meter by index. 1316 * 1317 * @param[in] dev 1318 * Pointer to the Ethernet device structure. 1319 * @param[in] idx 1320 * mlx5 flow aso meter index in the container. 1321 * @param[out] ppool 1322 * mlx5 flow aso meter pool in the container, 1323 * 1324 * @return 1325 * Pointer to the aso meter, NULL otherwise. 1326 */ 1327 static inline struct mlx5_aso_mtr * 1328 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) 1329 { 1330 struct mlx5_aso_mtr_pool *pool; 1331 struct mlx5_aso_mtr_pools_mng *pools_mng = 1332 &priv->sh->mtrmng->pools_mng; 1333 1334 /* Decrease to original index. */ 1335 idx--; 1336 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n); 1337 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL]; 1338 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; 1339 } 1340 1341 static __rte_always_inline const struct rte_flow_item * 1342 mlx5_find_end_item(const struct rte_flow_item *item) 1343 { 1344 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++); 1345 return item; 1346 } 1347 1348 static __rte_always_inline bool 1349 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) 1350 { 1351 struct rte_flow_item_integrity test = *item; 1352 test.l3_ok = 0; 1353 test.l4_ok = 0; 1354 test.ipv4_csum_ok = 0; 1355 test.l4_csum_ok = 0; 1356 return (test.value == 0); 1357 } 1358 1359 /* 1360 * Get ASO CT action by device and index. 1361 * 1362 * @param[in] dev 1363 * Pointer to the Ethernet device structure. 1364 * @param[in] idx 1365 * Index to the ASO CT action. 1366 * 1367 * @return 1368 * The specified ASO CT action pointer. 1369 */ 1370 static inline struct mlx5_aso_ct_action * 1371 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx) 1372 { 1373 struct mlx5_priv *priv = dev->data->dev_private; 1374 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng; 1375 struct mlx5_aso_ct_pool *pool; 1376 1377 idx--; 1378 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n); 1379 /* Bit operation AND could be used. */ 1380 rte_rwlock_read_lock(&mng->resize_rwl); 1381 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL]; 1382 rte_rwlock_read_unlock(&mng->resize_rwl); 1383 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL]; 1384 } 1385 1386 /* 1387 * Get ASO CT action by owner & index. 1388 * 1389 * @param[in] dev 1390 * Pointer to the Ethernet device structure. 1391 * @param[in] idx 1392 * Index to the ASO CT action and owner port combination. 1393 * 1394 * @return 1395 * The specified ASO CT action pointer. 1396 */ 1397 static inline struct mlx5_aso_ct_action * 1398 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx) 1399 { 1400 struct mlx5_priv *priv = dev->data->dev_private; 1401 struct mlx5_aso_ct_action *ct; 1402 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx); 1403 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx); 1404 1405 if (owner == PORT_ID(priv)) { 1406 ct = flow_aso_ct_get_by_dev_idx(dev, idx); 1407 } else { 1408 struct rte_eth_dev *owndev = &rte_eth_devices[owner]; 1409 1410 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS); 1411 if (dev->data->dev_started != 1) 1412 return NULL; 1413 ct = flow_aso_ct_get_by_dev_idx(owndev, idx); 1414 if (ct->peer != PORT_ID(priv)) 1415 return NULL; 1416 } 1417 return ct; 1418 } 1419 1420 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1421 const struct mlx5_flow_tunnel *tunnel, 1422 uint32_t group, uint32_t *table, 1423 const struct flow_grp_info *flags, 1424 struct rte_flow_error *error); 1425 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1426 int tunnel, uint64_t layer_types, 1427 uint64_t hash_fields); 1428 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1429 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1430 uint32_t subpriority); 1431 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1432 const struct rte_flow_attr *attr); 1433 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1434 const struct rte_flow_attr *attr, 1435 uint32_t subpriority, bool external); 1436 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1437 enum mlx5_feature_name feature, 1438 uint32_t id, 1439 struct rte_flow_error *error); 1440 const struct rte_flow_action *mlx5_flow_find_action 1441 (const struct rte_flow_action *actions, 1442 enum rte_flow_action_type action); 1443 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1444 const struct rte_flow_action *action, 1445 struct rte_flow_error *error); 1446 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1447 const struct rte_flow_attr *attr, 1448 struct rte_flow_error *error); 1449 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1450 const struct rte_flow_attr *attr, 1451 struct rte_flow_error *error); 1452 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1453 const struct rte_flow_attr *attr, 1454 struct rte_flow_error *error); 1455 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1456 uint64_t action_flags, 1457 const struct rte_flow_attr *attr, 1458 struct rte_flow_error *error); 1459 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1460 uint64_t action_flags, 1461 struct rte_eth_dev *dev, 1462 const struct rte_flow_attr *attr, 1463 struct rte_flow_error *error); 1464 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1465 uint64_t action_flags, 1466 struct rte_eth_dev *dev, 1467 const struct rte_flow_attr *attr, 1468 uint64_t item_flags, 1469 struct rte_flow_error *error); 1470 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1471 const struct rte_flow_attr *attr, 1472 struct rte_flow_error *error); 1473 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1474 const struct rte_flow_attr *attributes, 1475 struct rte_flow_error *error); 1476 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1477 const uint8_t *mask, 1478 const uint8_t *nic_mask, 1479 unsigned int size, 1480 bool range_accepted, 1481 struct rte_flow_error *error); 1482 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1483 uint64_t item_flags, bool ext_vlan_sup, 1484 struct rte_flow_error *error); 1485 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1486 uint64_t item_flags, 1487 uint8_t target_protocol, 1488 struct rte_flow_error *error); 1489 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1490 uint64_t item_flags, 1491 const struct rte_flow_item *gre_item, 1492 struct rte_flow_error *error); 1493 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1494 uint64_t item_flags, 1495 uint64_t last_item, 1496 uint16_t ether_type, 1497 const struct rte_flow_item_ipv4 *acc_mask, 1498 bool range_accepted, 1499 struct rte_flow_error *error); 1500 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1501 uint64_t item_flags, 1502 uint64_t last_item, 1503 uint16_t ether_type, 1504 const struct rte_flow_item_ipv6 *acc_mask, 1505 struct rte_flow_error *error); 1506 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1507 const struct rte_flow_item *item, 1508 uint64_t item_flags, 1509 uint64_t prev_layer, 1510 struct rte_flow_error *error); 1511 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1512 uint64_t item_flags, 1513 uint8_t target_protocol, 1514 const struct rte_flow_item_tcp *flow_mask, 1515 struct rte_flow_error *error); 1516 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1517 uint64_t item_flags, 1518 uint8_t target_protocol, 1519 struct rte_flow_error *error); 1520 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1521 uint64_t item_flags, 1522 struct rte_eth_dev *dev, 1523 struct rte_flow_error *error); 1524 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 1525 uint16_t udp_dport, 1526 const struct rte_flow_item *item, 1527 uint64_t item_flags, 1528 const struct rte_flow_attr *attr, 1529 struct rte_flow_error *error); 1530 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1531 uint64_t item_flags, 1532 struct rte_eth_dev *dev, 1533 struct rte_flow_error *error); 1534 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1535 uint64_t item_flags, 1536 uint8_t target_protocol, 1537 struct rte_flow_error *error); 1538 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1539 uint64_t item_flags, 1540 uint8_t target_protocol, 1541 struct rte_flow_error *error); 1542 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1543 uint64_t item_flags, 1544 uint8_t target_protocol, 1545 struct rte_flow_error *error); 1546 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1547 uint64_t item_flags, 1548 struct rte_eth_dev *dev, 1549 struct rte_flow_error *error); 1550 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1551 uint64_t last_item, 1552 const struct rte_flow_item *geneve_item, 1553 struct rte_eth_dev *dev, 1554 struct rte_flow_error *error); 1555 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1556 uint64_t item_flags, 1557 uint64_t last_item, 1558 uint16_t ether_type, 1559 const struct rte_flow_item_ecpri *acc_mask, 1560 struct rte_flow_error *error); 1561 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 1562 struct mlx5_flow_meter_info *fm, 1563 uint32_t mtr_idx, 1564 uint8_t domain_bitmap); 1565 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1566 struct mlx5_flow_meter_info *fm); 1567 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev); 1568 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare 1569 (struct rte_eth_dev *dev, 1570 struct mlx5_flow_meter_policy *mtr_policy, 1571 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1572 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 1573 struct mlx5_flow_meter_policy *mtr_policy); 1574 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1575 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev); 1576 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1577 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1578 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1579 1580 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx); 1581 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1582 void *cb_ctx); 1583 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1584 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx, 1585 struct mlx5_list_entry *oentry, 1586 void *entry_ctx); 1587 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1588 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1589 uint32_t table_level, uint8_t egress, uint8_t transfer, 1590 bool external, const struct mlx5_flow_tunnel *tunnel, 1591 uint32_t group_id, uint8_t dummy, 1592 uint32_t table_id, struct rte_flow_error *error); 1593 1594 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx); 1595 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1596 void *cb_ctx); 1597 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1598 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx, 1599 struct mlx5_list_entry *oentry, 1600 void *cb_ctx); 1601 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1602 1603 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1604 void *cb_ctx); 1605 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx); 1606 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1607 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx, 1608 struct mlx5_list_entry *oentry, 1609 void *ctx); 1610 void flow_dv_modify_clone_free_cb(void *tool_ctx, 1611 struct mlx5_list_entry *entry); 1612 1613 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx); 1614 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1615 void *cb_ctx); 1616 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1617 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx, 1618 struct mlx5_list_entry *entry, 1619 void *ctx); 1620 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1621 1622 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1623 void *cb_ctx); 1624 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx, 1625 void *cb_ctx); 1626 void flow_dv_encap_decap_remove_cb(void *tool_ctx, 1627 struct mlx5_list_entry *entry); 1628 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx, 1629 struct mlx5_list_entry *entry, 1630 void *cb_ctx); 1631 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx, 1632 struct mlx5_list_entry *entry); 1633 1634 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1635 void *ctx); 1636 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx); 1637 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1638 1639 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1640 void *cb_ctx); 1641 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx); 1642 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1643 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx, 1644 struct mlx5_list_entry *entry, void *cb_ctx); 1645 void flow_dv_port_id_clone_free_cb(void *tool_ctx, 1646 struct mlx5_list_entry *entry); 1647 1648 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1649 void *cb_ctx); 1650 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx, 1651 void *cb_ctx); 1652 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1653 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx, 1654 struct mlx5_list_entry *entry, void *cb_ctx); 1655 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx, 1656 struct mlx5_list_entry *entry); 1657 1658 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1659 void *cb_ctx); 1660 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx); 1661 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1662 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx, 1663 struct mlx5_list_entry *entry, void *cb_ctx); 1664 void flow_dv_sample_clone_free_cb(void *tool_ctx, 1665 struct mlx5_list_entry *entry); 1666 1667 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1668 void *cb_ctx); 1669 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx, 1670 void *cb_ctx); 1671 void flow_dv_dest_array_remove_cb(void *tool_ctx, 1672 struct mlx5_list_entry *entry); 1673 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx, 1674 struct mlx5_list_entry *entry, void *cb_ctx); 1675 void flow_dv_dest_array_clone_free_cb(void *tool_ctx, 1676 struct mlx5_list_entry *entry); 1677 1678 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1679 uint32_t age_idx); 1680 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1681 const struct rte_flow_item *item, 1682 struct rte_flow_error *error); 1683 void flow_release_workspace(void *data); 1684 int mlx5_flow_os_init_workspace_once(void); 1685 void *mlx5_flow_os_get_specific_workspace(void); 1686 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1687 void mlx5_flow_os_release_workspace(void); 1688 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev); 1689 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx); 1690 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 1691 const struct rte_flow_action *actions[RTE_COLORS], 1692 struct rte_flow_attr *attr, 1693 bool *is_rss, 1694 uint8_t *domain_bitmap, 1695 uint8_t *policy_mode, 1696 struct rte_mtr_error *error); 1697 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 1698 struct mlx5_flow_meter_policy *mtr_policy); 1699 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 1700 struct mlx5_flow_meter_policy *mtr_policy, 1701 const struct rte_flow_action *actions[RTE_COLORS], 1702 struct rte_mtr_error *error); 1703 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 1704 struct mlx5_flow_meter_policy *mtr_policy); 1705 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 1706 struct mlx5_flow_meter_policy *mtr_policy); 1707 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev); 1708 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev); 1709 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1710 struct mlx5_flow_handle *dev_handle); 1711 const struct mlx5_flow_tunnel * 1712 mlx5_get_tof(const struct rte_flow_item *items, 1713 const struct rte_flow_action *actions, 1714 enum mlx5_tof_rule_type *rule_type); 1715 1716 1717 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1718