1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 /* Pattern outer Layer bits. */ 25 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 26 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 27 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 28 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 29 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 30 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 31 32 /* Pattern inner Layer bits. */ 33 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 34 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 35 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 36 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 37 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 38 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 39 40 /* Pattern tunnel Layer bits. */ 41 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 42 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 43 #define MLX5_FLOW_LAYER_GRE (1u << 14) 44 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 45 46 /* General pattern items bits. */ 47 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 48 49 /* Outer Masks. */ 50 #define MLX5_FLOW_LAYER_OUTER_L3 \ 51 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 52 #define MLX5_FLOW_LAYER_OUTER_L4 \ 53 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 54 #define MLX5_FLOW_LAYER_OUTER \ 55 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 56 MLX5_FLOW_LAYER_OUTER_L4) 57 58 /* Tunnel Masks. */ 59 #define MLX5_FLOW_LAYER_TUNNEL \ 60 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 61 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS) 62 63 /* Inner Masks. */ 64 #define MLX5_FLOW_LAYER_INNER_L3 \ 65 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 66 #define MLX5_FLOW_LAYER_INNER_L4 \ 67 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 68 #define MLX5_FLOW_LAYER_INNER \ 69 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 70 MLX5_FLOW_LAYER_INNER_L4) 71 72 /* Actions */ 73 #define MLX5_FLOW_ACTION_DROP (1u << 0) 74 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 75 #define MLX5_FLOW_ACTION_RSS (1u << 2) 76 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 77 #define MLX5_FLOW_ACTION_MARK (1u << 4) 78 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 79 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 80 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 81 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 82 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 83 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 84 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 85 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 86 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 87 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 88 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 89 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 90 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 91 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 92 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 93 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 94 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 95 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 96 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 97 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 98 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 99 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 100 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 101 102 #define MLX5_FLOW_FATE_ACTIONS \ 103 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS) 104 105 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 106 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 107 MLX5_FLOW_ACTION_RAW_ENCAP) 108 109 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 110 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 111 MLX5_FLOW_ACTION_RAW_DECAP) 112 113 #ifndef IPPROTO_MPLS 114 #define IPPROTO_MPLS 137 115 #endif 116 117 /* UDP port number for MPLS */ 118 #define MLX5_UDP_PORT_MPLS 6635 119 120 /* UDP port numbers for VxLAN. */ 121 #define MLX5_UDP_PORT_VXLAN 4789 122 #define MLX5_UDP_PORT_VXLAN_GPE 4790 123 124 /* Priority reserved for default flows. */ 125 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 126 127 /* 128 * Number of sub priorities. 129 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 130 * matching on the NIC (firmware dependent) L4 most have the higher priority 131 * followed by L3 and ending with L2. 132 */ 133 #define MLX5_PRIORITY_MAP_L2 2 134 #define MLX5_PRIORITY_MAP_L3 1 135 #define MLX5_PRIORITY_MAP_L4 0 136 #define MLX5_PRIORITY_MAP_MAX 3 137 138 /* Valid layer type for IPV4 RSS. */ 139 #define MLX5_IPV4_LAYER_TYPES \ 140 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 141 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 142 ETH_RSS_NONFRAG_IPV4_OTHER) 143 144 /* IBV hash source bits for IPV4. */ 145 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 146 147 /* Valid layer type for IPV6 RSS. */ 148 #define MLX5_IPV6_LAYER_TYPES \ 149 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 150 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 151 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 152 153 /* IBV hash source bits for IPV6. */ 154 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 155 156 /* Max number of actions per DV flow. */ 157 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 158 159 enum mlx5_flow_drv_type { 160 MLX5_FLOW_TYPE_MIN, 161 MLX5_FLOW_TYPE_DV, 162 MLX5_FLOW_TYPE_TCF, 163 MLX5_FLOW_TYPE_VERBS, 164 MLX5_FLOW_TYPE_MAX, 165 }; 166 167 /* Matcher PRM representation */ 168 struct mlx5_flow_dv_match_params { 169 size_t size; 170 /**< Size of match value. Do NOT split size and key! */ 171 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 172 /**< Matcher value. This value is used as the mask or as a key. */ 173 }; 174 175 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 176 #define MLX5_ENCAP_MAX_LEN 132 177 178 /* Matcher structure. */ 179 struct mlx5_flow_dv_matcher { 180 LIST_ENTRY(mlx5_flow_dv_matcher) next; 181 /* Pointer to the next element. */ 182 rte_atomic32_t refcnt; /**< Reference counter. */ 183 void *matcher_object; /**< Pointer to DV matcher */ 184 uint16_t crc; /**< CRC of key. */ 185 uint16_t priority; /**< Priority of matcher. */ 186 uint8_t egress; /**< Egress matcher. */ 187 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 188 }; 189 190 /* Encap/decap resource structure. */ 191 struct mlx5_flow_dv_encap_decap_resource { 192 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 193 /* Pointer to next element. */ 194 rte_atomic32_t refcnt; /**< Reference counter. */ 195 struct ibv_flow_action *verbs_action; 196 /**< Verbs encap/decap action object. */ 197 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 198 size_t size; 199 uint8_t reformat_type; 200 uint8_t ft_type; 201 }; 202 203 /* DV flows structure. */ 204 struct mlx5_flow_dv { 205 uint64_t hash_fields; /**< Fields that participate in the hash. */ 206 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 207 /* Flow DV api: */ 208 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 209 struct mlx5_flow_dv_match_params value; 210 /**< Holds the value that the packet is compared to. */ 211 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 212 /**< Pointer to encap/decap resource in cache. */ 213 struct ibv_flow *flow; /**< Installed flow. */ 214 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 215 struct mlx5dv_flow_action_attr actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 216 /**< Action list. */ 217 #endif 218 int actions_n; /**< number of actions. */ 219 }; 220 221 /** Linux TC flower driver for E-Switch flow. */ 222 struct mlx5_flow_tcf { 223 struct nlmsghdr *nlh; 224 struct tcmsg *tcm; 225 uint32_t *ptc_flags; /**< tc rule applied flags. */ 226 union { /**< Tunnel encap/decap descriptor. */ 227 struct flow_tcf_tunnel_hdr *tunnel; 228 struct flow_tcf_vxlan_decap *vxlan_decap; 229 struct flow_tcf_vxlan_encap *vxlan_encap; 230 }; 231 uint32_t applied:1; /**< Whether rule is currently applied. */ 232 #ifndef NDEBUG 233 uint32_t nlsize; /**< Size of NL message buffer for debug check. */ 234 #endif 235 }; 236 237 /* Verbs specification header. */ 238 struct ibv_spec_header { 239 enum ibv_flow_spec_type type; 240 uint16_t size; 241 }; 242 243 /** Handles information leading to a drop fate. */ 244 struct mlx5_flow_verbs { 245 LIST_ENTRY(mlx5_flow_verbs) next; 246 unsigned int size; /**< Size of the attribute. */ 247 struct { 248 struct ibv_flow_attr *attr; 249 /**< Pointer to the Specification buffer. */ 250 uint8_t *specs; /**< Pointer to the specifications. */ 251 }; 252 struct ibv_flow *flow; /**< Verbs flow pointer. */ 253 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 254 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 255 }; 256 257 /** Device flow structure. */ 258 struct mlx5_flow { 259 LIST_ENTRY(mlx5_flow) next; 260 struct rte_flow *flow; /**< Pointer to the main flow. */ 261 uint64_t layers; 262 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 263 union { 264 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 265 struct mlx5_flow_dv dv; 266 #endif 267 struct mlx5_flow_tcf tcf; 268 struct mlx5_flow_verbs verbs; 269 }; 270 }; 271 272 /* Counters information. */ 273 struct mlx5_flow_counter { 274 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */ 275 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 276 uint32_t ref_cnt:31; /**< Reference counter. */ 277 uint32_t id; /**< Counter ID. */ 278 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 279 struct ibv_counter_set *cs; /**< Holds the counters for the rule. */ 280 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 281 struct ibv_counters *cs; /**< Holds the counters for the rule. */ 282 #endif 283 uint64_t hits; /**< Number of packets matched by the rule. */ 284 uint64_t bytes; /**< Number of bytes matched by the rule. */ 285 }; 286 287 /* Flow structure. */ 288 struct rte_flow { 289 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 290 enum mlx5_flow_drv_type drv_type; /**< Drvier type. */ 291 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 292 struct rte_flow_action_rss rss;/**< RSS context. */ 293 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 294 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 295 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 296 /**< Device flows that are part of the flow. */ 297 uint64_t actions; 298 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 299 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 300 }; 301 302 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 303 const struct rte_flow_attr *attr, 304 const struct rte_flow_item items[], 305 const struct rte_flow_action actions[], 306 struct rte_flow_error *error); 307 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 308 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 309 const struct rte_flow_action actions[], struct rte_flow_error *error); 310 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 311 struct mlx5_flow *dev_flow, 312 const struct rte_flow_attr *attr, 313 const struct rte_flow_item items[], 314 const struct rte_flow_action actions[], 315 struct rte_flow_error *error); 316 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 317 struct rte_flow_error *error); 318 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 319 struct rte_flow *flow); 320 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 321 struct rte_flow *flow); 322 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 323 struct rte_flow *flow, 324 const struct rte_flow_action *actions, 325 void *data, 326 struct rte_flow_error *error); 327 struct mlx5_flow_driver_ops { 328 mlx5_flow_validate_t validate; 329 mlx5_flow_prepare_t prepare; 330 mlx5_flow_translate_t translate; 331 mlx5_flow_apply_t apply; 332 mlx5_flow_remove_t remove; 333 mlx5_flow_destroy_t destroy; 334 mlx5_flow_query_t query; 335 }; 336 337 /* mlx5_flow.c */ 338 339 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 340 uint64_t layer_types, 341 uint64_t hash_fields); 342 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 343 uint32_t subpriority); 344 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 345 const struct rte_flow_attr *attr, 346 struct rte_flow_error *error); 347 int mlx5_flow_validate_action_drop(uint64_t action_flags, 348 const struct rte_flow_attr *attr, 349 struct rte_flow_error *error); 350 int mlx5_flow_validate_action_flag(uint64_t action_flags, 351 const struct rte_flow_attr *attr, 352 struct rte_flow_error *error); 353 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 354 uint64_t action_flags, 355 const struct rte_flow_attr *attr, 356 struct rte_flow_error *error); 357 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 358 uint64_t action_flags, 359 struct rte_eth_dev *dev, 360 const struct rte_flow_attr *attr, 361 struct rte_flow_error *error); 362 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 363 uint64_t action_flags, 364 struct rte_eth_dev *dev, 365 const struct rte_flow_attr *attr, 366 struct rte_flow_error *error); 367 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 368 const struct rte_flow_attr *attributes, 369 struct rte_flow_error *error); 370 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 371 const uint8_t *mask, 372 const uint8_t *nic_mask, 373 unsigned int size, 374 struct rte_flow_error *error); 375 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 376 uint64_t item_flags, 377 struct rte_flow_error *error); 378 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 379 uint64_t item_flags, 380 uint8_t target_protocol, 381 struct rte_flow_error *error); 382 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 383 uint64_t item_flags, 384 struct rte_flow_error *error); 385 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 386 uint64_t item_flags, 387 struct rte_flow_error *error); 388 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 389 const struct rte_flow_item *item, 390 uint64_t item_flags, 391 uint64_t prev_layer, 392 struct rte_flow_error *error); 393 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 394 uint64_t item_flags, 395 uint8_t target_protocol, 396 const struct rte_flow_item_tcp *flow_mask, 397 struct rte_flow_error *error); 398 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 399 uint64_t item_flags, 400 uint8_t target_protocol, 401 struct rte_flow_error *error); 402 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 403 uint64_t item_flags, 404 struct rte_flow_error *error); 405 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 406 uint64_t item_flags, 407 struct rte_flow_error *error); 408 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 409 uint64_t item_flags, 410 struct rte_eth_dev *dev, 411 struct rte_flow_error *error); 412 413 /* mlx5_flow_tcf.c */ 414 415 int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx, 416 unsigned int ifindex, struct rte_flow_error *error); 417 struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void); 418 void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx); 419 420 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 421