1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 /* Pattern outer Layer bits. */ 25 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 26 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 27 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 28 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 29 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 30 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 31 32 /* Pattern inner Layer bits. */ 33 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 34 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 35 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 36 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 37 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 38 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 39 40 /* Pattern tunnel Layer bits. */ 41 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 42 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 43 #define MLX5_FLOW_LAYER_GRE (1u << 14) 44 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 45 46 /* General pattern items bits. */ 47 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 48 49 /* Outer Masks. */ 50 #define MLX5_FLOW_LAYER_OUTER_L3 \ 51 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 52 #define MLX5_FLOW_LAYER_OUTER_L4 \ 53 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 54 #define MLX5_FLOW_LAYER_OUTER \ 55 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 56 MLX5_FLOW_LAYER_OUTER_L4) 57 58 /* Tunnel Masks. */ 59 #define MLX5_FLOW_LAYER_TUNNEL \ 60 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 61 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS) 62 63 /* Inner Masks. */ 64 #define MLX5_FLOW_LAYER_INNER_L3 \ 65 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 66 #define MLX5_FLOW_LAYER_INNER_L4 \ 67 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 68 #define MLX5_FLOW_LAYER_INNER \ 69 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 70 MLX5_FLOW_LAYER_INNER_L4) 71 72 /* Layer Masks. */ 73 #define MLX5_FLOW_LAYER_L2 \ 74 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 75 #define MLX5_FLOW_LAYER_L3_IPV4 \ 76 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 77 #define MLX5_FLOW_LAYER_L3_IPV6 \ 78 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 79 #define MLX5_FLOW_LAYER_L3 \ 80 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 81 #define MLX5_FLOW_LAYER_L4 \ 82 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 83 84 /* Actions */ 85 #define MLX5_FLOW_ACTION_DROP (1u << 0) 86 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 87 #define MLX5_FLOW_ACTION_RSS (1u << 2) 88 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 89 #define MLX5_FLOW_ACTION_MARK (1u << 4) 90 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 91 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 92 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 93 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 94 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 95 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 96 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 97 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 98 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 99 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 100 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 101 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 102 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 103 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 104 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 105 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 106 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 107 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 108 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 109 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 110 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 111 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 112 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 113 114 #define MLX5_FLOW_FATE_ACTIONS \ 115 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS) 116 117 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 118 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 119 MLX5_FLOW_ACTION_RAW_ENCAP) 120 121 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 122 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 123 MLX5_FLOW_ACTION_RAW_DECAP) 124 125 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 126 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 127 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 128 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 129 MLX5_FLOW_ACTION_SET_TP_SRC | \ 130 MLX5_FLOW_ACTION_SET_TP_DST | \ 131 MLX5_FLOW_ACTION_SET_TTL | \ 132 MLX5_FLOW_ACTION_DEC_TTL | \ 133 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 134 MLX5_FLOW_ACTION_SET_MAC_DST) 135 136 #ifndef IPPROTO_MPLS 137 #define IPPROTO_MPLS 137 138 #endif 139 140 /* UDP port number for MPLS */ 141 #define MLX5_UDP_PORT_MPLS 6635 142 143 /* UDP port numbers for VxLAN. */ 144 #define MLX5_UDP_PORT_VXLAN 4789 145 #define MLX5_UDP_PORT_VXLAN_GPE 4790 146 147 /* Priority reserved for default flows. */ 148 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 149 150 /* 151 * Number of sub priorities. 152 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 153 * matching on the NIC (firmware dependent) L4 most have the higher priority 154 * followed by L3 and ending with L2. 155 */ 156 #define MLX5_PRIORITY_MAP_L2 2 157 #define MLX5_PRIORITY_MAP_L3 1 158 #define MLX5_PRIORITY_MAP_L4 0 159 #define MLX5_PRIORITY_MAP_MAX 3 160 161 /* Valid layer type for IPV4 RSS. */ 162 #define MLX5_IPV4_LAYER_TYPES \ 163 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 164 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 165 ETH_RSS_NONFRAG_IPV4_OTHER) 166 167 /* IBV hash source bits for IPV4. */ 168 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 169 170 /* Valid layer type for IPV6 RSS. */ 171 #define MLX5_IPV6_LAYER_TYPES \ 172 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 173 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 174 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 175 176 /* IBV hash source bits for IPV6. */ 177 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 178 179 enum mlx5_flow_drv_type { 180 MLX5_FLOW_TYPE_MIN, 181 MLX5_FLOW_TYPE_DV, 182 MLX5_FLOW_TYPE_TCF, 183 MLX5_FLOW_TYPE_VERBS, 184 MLX5_FLOW_TYPE_MAX, 185 }; 186 187 /* Matcher PRM representation */ 188 struct mlx5_flow_dv_match_params { 189 size_t size; 190 /**< Size of match value. Do NOT split size and key! */ 191 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 192 /**< Matcher value. This value is used as the mask or as a key. */ 193 }; 194 195 /* Matcher structure. */ 196 struct mlx5_flow_dv_matcher { 197 LIST_ENTRY(mlx5_flow_dv_matcher) next; 198 /* Pointer to the next element. */ 199 rte_atomic32_t refcnt; /**< Reference counter. */ 200 void *matcher_object; /**< Pointer to DV matcher */ 201 uint16_t crc; /**< CRC of key. */ 202 uint16_t priority; /**< Priority of matcher. */ 203 uint8_t egress; /**< Egress matcher. */ 204 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 205 }; 206 207 #define MLX5_ENCAP_MAX_LEN 132 208 209 /* Encap/decap resource structure. */ 210 struct mlx5_flow_dv_encap_decap_resource { 211 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 212 /* Pointer to next element. */ 213 rte_atomic32_t refcnt; /**< Reference counter. */ 214 struct ibv_flow_action *verbs_action; 215 /**< Verbs encap/decap action object. */ 216 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 217 size_t size; 218 uint8_t reformat_type; 219 uint8_t ft_type; 220 }; 221 222 /* Number of modification commands. */ 223 #define MLX5_MODIFY_NUM 8 224 225 /* Modify resource structure */ 226 struct mlx5_flow_dv_modify_hdr_resource { 227 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 228 /* Pointer to next element. */ 229 rte_atomic32_t refcnt; /**< Reference counter. */ 230 struct ibv_flow_action *verbs_action; 231 /**< Verbs modify header action object. */ 232 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 233 uint32_t actions_num; /**< Number of modification actions. */ 234 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM]; 235 /**< Modification actions. */ 236 }; 237 238 /* 239 * Max number of actions per DV flow. 240 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 241 * In rdma-core file providers/mlx5/verbs.c 242 */ 243 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 244 245 /* DV flows structure. */ 246 struct mlx5_flow_dv { 247 uint64_t hash_fields; /**< Fields that participate in the hash. */ 248 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 249 /* Flow DV api: */ 250 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 251 struct mlx5_flow_dv_match_params value; 252 /**< Holds the value that the packet is compared to. */ 253 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 254 /**< Pointer to encap/decap resource in cache. */ 255 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 256 /**< Pointer to modify header resource in cache. */ 257 struct ibv_flow *flow; /**< Installed flow. */ 258 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 259 struct mlx5dv_flow_action_attr actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 260 /**< Action list. */ 261 #endif 262 int actions_n; /**< number of actions. */ 263 }; 264 265 /** Linux TC flower driver for E-Switch flow. */ 266 struct mlx5_flow_tcf { 267 struct nlmsghdr *nlh; 268 struct tcmsg *tcm; 269 uint32_t *ptc_flags; /**< tc rule applied flags. */ 270 union { /**< Tunnel encap/decap descriptor. */ 271 struct flow_tcf_tunnel_hdr *tunnel; 272 struct flow_tcf_vxlan_decap *vxlan_decap; 273 struct flow_tcf_vxlan_encap *vxlan_encap; 274 }; 275 uint32_t applied:1; /**< Whether rule is currently applied. */ 276 #ifndef NDEBUG 277 uint32_t nlsize; /**< Size of NL message buffer for debug check. */ 278 #endif 279 }; 280 281 /* Verbs specification header. */ 282 struct ibv_spec_header { 283 enum ibv_flow_spec_type type; 284 uint16_t size; 285 }; 286 287 /** Handles information leading to a drop fate. */ 288 struct mlx5_flow_verbs { 289 LIST_ENTRY(mlx5_flow_verbs) next; 290 unsigned int size; /**< Size of the attribute. */ 291 struct { 292 struct ibv_flow_attr *attr; 293 /**< Pointer to the Specification buffer. */ 294 uint8_t *specs; /**< Pointer to the specifications. */ 295 }; 296 struct ibv_flow *flow; /**< Verbs flow pointer. */ 297 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 298 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 299 }; 300 301 /** Device flow structure. */ 302 struct mlx5_flow { 303 LIST_ENTRY(mlx5_flow) next; 304 struct rte_flow *flow; /**< Pointer to the main flow. */ 305 uint64_t layers; 306 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 307 union { 308 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 309 struct mlx5_flow_dv dv; 310 #endif 311 struct mlx5_flow_tcf tcf; 312 struct mlx5_flow_verbs verbs; 313 }; 314 }; 315 316 /* Counters information. */ 317 struct mlx5_flow_counter { 318 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */ 319 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 320 uint32_t ref_cnt:31; /**< Reference counter. */ 321 uint32_t id; /**< Counter ID. */ 322 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 323 struct ibv_counter_set *cs; /**< Holds the counters for the rule. */ 324 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 325 struct ibv_counters *cs; /**< Holds the counters for the rule. */ 326 #endif 327 uint64_t hits; /**< Number of packets matched by the rule. */ 328 uint64_t bytes; /**< Number of bytes matched by the rule. */ 329 }; 330 331 /* Flow structure. */ 332 struct rte_flow { 333 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 334 enum mlx5_flow_drv_type drv_type; /**< Drvier type. */ 335 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 336 struct rte_flow_action_rss rss;/**< RSS context. */ 337 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 338 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 339 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 340 /**< Device flows that are part of the flow. */ 341 uint64_t actions; 342 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 343 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 344 }; 345 346 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 347 const struct rte_flow_attr *attr, 348 const struct rte_flow_item items[], 349 const struct rte_flow_action actions[], 350 struct rte_flow_error *error); 351 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 352 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 353 const struct rte_flow_action actions[], struct rte_flow_error *error); 354 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 355 struct mlx5_flow *dev_flow, 356 const struct rte_flow_attr *attr, 357 const struct rte_flow_item items[], 358 const struct rte_flow_action actions[], 359 struct rte_flow_error *error); 360 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 361 struct rte_flow_error *error); 362 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 363 struct rte_flow *flow); 364 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 365 struct rte_flow *flow); 366 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 367 struct rte_flow *flow, 368 const struct rte_flow_action *actions, 369 void *data, 370 struct rte_flow_error *error); 371 struct mlx5_flow_driver_ops { 372 mlx5_flow_validate_t validate; 373 mlx5_flow_prepare_t prepare; 374 mlx5_flow_translate_t translate; 375 mlx5_flow_apply_t apply; 376 mlx5_flow_remove_t remove; 377 mlx5_flow_destroy_t destroy; 378 mlx5_flow_query_t query; 379 }; 380 381 /* mlx5_flow.c */ 382 383 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 384 uint64_t layer_types, 385 uint64_t hash_fields); 386 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 387 uint32_t subpriority); 388 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 389 const struct rte_flow_attr *attr, 390 struct rte_flow_error *error); 391 int mlx5_flow_validate_action_drop(uint64_t action_flags, 392 const struct rte_flow_attr *attr, 393 struct rte_flow_error *error); 394 int mlx5_flow_validate_action_flag(uint64_t action_flags, 395 const struct rte_flow_attr *attr, 396 struct rte_flow_error *error); 397 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 398 uint64_t action_flags, 399 const struct rte_flow_attr *attr, 400 struct rte_flow_error *error); 401 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 402 uint64_t action_flags, 403 struct rte_eth_dev *dev, 404 const struct rte_flow_attr *attr, 405 struct rte_flow_error *error); 406 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 407 uint64_t action_flags, 408 struct rte_eth_dev *dev, 409 const struct rte_flow_attr *attr, 410 struct rte_flow_error *error); 411 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 412 const struct rte_flow_attr *attributes, 413 struct rte_flow_error *error); 414 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 415 const uint8_t *mask, 416 const uint8_t *nic_mask, 417 unsigned int size, 418 struct rte_flow_error *error); 419 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 420 uint64_t item_flags, 421 struct rte_flow_error *error); 422 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 423 uint64_t item_flags, 424 uint8_t target_protocol, 425 struct rte_flow_error *error); 426 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 427 uint64_t item_flags, 428 struct rte_flow_error *error); 429 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 430 uint64_t item_flags, 431 struct rte_flow_error *error); 432 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 433 const struct rte_flow_item *item, 434 uint64_t item_flags, 435 uint64_t prev_layer, 436 struct rte_flow_error *error); 437 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 438 uint64_t item_flags, 439 uint8_t target_protocol, 440 const struct rte_flow_item_tcp *flow_mask, 441 struct rte_flow_error *error); 442 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 443 uint64_t item_flags, 444 uint8_t target_protocol, 445 struct rte_flow_error *error); 446 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 447 uint64_t item_flags, 448 struct rte_flow_error *error); 449 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 450 uint64_t item_flags, 451 struct rte_flow_error *error); 452 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 453 uint64_t item_flags, 454 struct rte_eth_dev *dev, 455 struct rte_flow_error *error); 456 457 /* mlx5_flow_tcf.c */ 458 459 int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx, 460 unsigned int ifindex, struct rte_flow_error *error); 461 struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void); 462 void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx); 463 464 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 465