1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 #include <rte_alarm.h> 15 #include <rte_mtr.h> 16 17 #include <mlx5_glue.h> 18 #include <mlx5_prm.h> 19 20 #include "mlx5.h" 21 22 /* Private rte flow items. */ 23 enum mlx5_rte_flow_item_type { 24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 25 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 29 }; 30 31 /* Private (internal) rte flow actions. */ 32 enum mlx5_rte_flow_action_type { 33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 35 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 39 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 40 }; 41 42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30 43 44 enum { 45 MLX5_SHARED_ACTION_TYPE_RSS, 46 MLX5_SHARED_ACTION_TYPE_AGE, 47 }; 48 49 /* Matches on selected register. */ 50 struct mlx5_rte_flow_item_tag { 51 enum modify_reg id; 52 uint32_t data; 53 }; 54 55 /* Modify selected register. */ 56 struct mlx5_rte_flow_action_set_tag { 57 enum modify_reg id; 58 uint32_t data; 59 }; 60 61 struct mlx5_flow_action_copy_mreg { 62 enum modify_reg dst; 63 enum modify_reg src; 64 }; 65 66 /* Matches on source queue. */ 67 struct mlx5_rte_flow_item_tx_queue { 68 uint32_t queue; 69 }; 70 71 /* Feature name to allocate metadata register. */ 72 enum mlx5_feature_name { 73 MLX5_HAIRPIN_RX, 74 MLX5_HAIRPIN_TX, 75 MLX5_METADATA_RX, 76 MLX5_METADATA_TX, 77 MLX5_METADATA_FDB, 78 MLX5_FLOW_MARK, 79 MLX5_APP_TAG, 80 MLX5_COPY_MARK, 81 MLX5_MTR_COLOR, 82 MLX5_MTR_SFX, 83 }; 84 85 /* Default queue number. */ 86 #define MLX5_RSSQ_DEFAULT_NUM 16 87 88 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 89 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 91 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 92 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 93 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 94 95 /* Pattern inner Layer bits. */ 96 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 97 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 98 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 99 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 100 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 101 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 102 103 /* Pattern tunnel Layer bits. */ 104 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 105 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 106 #define MLX5_FLOW_LAYER_GRE (1u << 14) 107 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 108 /* List of tunnel Layer bits continued below. */ 109 110 /* General pattern items bits. */ 111 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 112 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 113 #define MLX5_FLOW_ITEM_TAG (1u << 18) 114 #define MLX5_FLOW_ITEM_MARK (1u << 19) 115 116 /* Pattern MISC bits. */ 117 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 118 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 119 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 120 121 /* Pattern tunnel Layer bits (continued). */ 122 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 123 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 124 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 125 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 126 127 /* Queue items. */ 128 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 129 130 /* Pattern tunnel Layer bits (continued). */ 131 #define MLX5_FLOW_LAYER_GTP (1u << 28) 132 133 /* Pattern eCPRI Layer bit. */ 134 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 135 136 /* IPv6 Fragment Extension Header bit. */ 137 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 138 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 139 140 /* Outer Masks. */ 141 #define MLX5_FLOW_LAYER_OUTER_L3 \ 142 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 143 #define MLX5_FLOW_LAYER_OUTER_L4 \ 144 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 145 #define MLX5_FLOW_LAYER_OUTER \ 146 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 147 MLX5_FLOW_LAYER_OUTER_L4) 148 149 /* Tunnel Masks. */ 150 #define MLX5_FLOW_LAYER_TUNNEL \ 151 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 152 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 153 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 154 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 155 156 /* Inner Masks. */ 157 #define MLX5_FLOW_LAYER_INNER_L3 \ 158 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 159 #define MLX5_FLOW_LAYER_INNER_L4 \ 160 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 161 #define MLX5_FLOW_LAYER_INNER \ 162 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 163 MLX5_FLOW_LAYER_INNER_L4) 164 165 /* Layer Masks. */ 166 #define MLX5_FLOW_LAYER_L2 \ 167 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 168 #define MLX5_FLOW_LAYER_L3_IPV4 \ 169 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 170 #define MLX5_FLOW_LAYER_L3_IPV6 \ 171 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 172 #define MLX5_FLOW_LAYER_L3 \ 173 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 174 #define MLX5_FLOW_LAYER_L4 \ 175 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 176 177 /* Actions */ 178 #define MLX5_FLOW_ACTION_DROP (1u << 0) 179 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 180 #define MLX5_FLOW_ACTION_RSS (1u << 2) 181 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 182 #define MLX5_FLOW_ACTION_MARK (1u << 4) 183 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 184 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 185 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 186 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 187 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 188 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 189 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 190 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 191 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 192 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 193 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 194 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 195 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 196 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 197 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 198 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 199 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 200 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 201 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 202 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 203 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 204 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 205 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 206 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 207 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 208 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 209 #define MLX5_FLOW_ACTION_METER (1ull << 31) 210 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 211 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 212 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 213 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 214 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 215 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 216 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 217 218 #define MLX5_FLOW_FATE_ACTIONS \ 219 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 220 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 221 MLX5_FLOW_ACTION_DEFAULT_MISS) 222 223 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 224 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 225 MLX5_FLOW_ACTION_JUMP) 226 227 228 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 229 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 230 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 231 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 232 MLX5_FLOW_ACTION_SET_TP_SRC | \ 233 MLX5_FLOW_ACTION_SET_TP_DST | \ 234 MLX5_FLOW_ACTION_SET_TTL | \ 235 MLX5_FLOW_ACTION_DEC_TTL | \ 236 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 237 MLX5_FLOW_ACTION_SET_MAC_DST | \ 238 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 239 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 240 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 241 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 242 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 243 MLX5_FLOW_ACTION_SET_TAG | \ 244 MLX5_FLOW_ACTION_MARK_EXT | \ 245 MLX5_FLOW_ACTION_SET_META | \ 246 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 247 MLX5_FLOW_ACTION_SET_IPV6_DSCP) 248 249 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 250 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 251 252 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 253 254 #ifndef IPPROTO_MPLS 255 #define IPPROTO_MPLS 137 256 #endif 257 258 /* UDP port number for MPLS */ 259 #define MLX5_UDP_PORT_MPLS 6635 260 261 /* UDP port numbers for VxLAN. */ 262 #define MLX5_UDP_PORT_VXLAN 4789 263 #define MLX5_UDP_PORT_VXLAN_GPE 4790 264 265 /* UDP port numbers for GENEVE. */ 266 #define MLX5_UDP_PORT_GENEVE 6081 267 268 /* Priority reserved for default flows. */ 269 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 270 271 /* 272 * Number of sub priorities. 273 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 274 * matching on the NIC (firmware dependent) L4 most have the higher priority 275 * followed by L3 and ending with L2. 276 */ 277 #define MLX5_PRIORITY_MAP_L2 2 278 #define MLX5_PRIORITY_MAP_L3 1 279 #define MLX5_PRIORITY_MAP_L4 0 280 #define MLX5_PRIORITY_MAP_MAX 3 281 282 /* Valid layer type for IPV4 RSS. */ 283 #define MLX5_IPV4_LAYER_TYPES \ 284 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 285 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 286 ETH_RSS_NONFRAG_IPV4_OTHER) 287 288 /* IBV hash source bits for IPV4. */ 289 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 290 291 /* Valid layer type for IPV6 RSS. */ 292 #define MLX5_IPV6_LAYER_TYPES \ 293 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 294 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 295 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 296 297 /* IBV hash source bits for IPV6. */ 298 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 299 300 /* IBV hash bits for L3 SRC. */ 301 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 302 303 /* IBV hash bits for L3 DST. */ 304 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 305 306 /* IBV hash bits for TCP. */ 307 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 308 IBV_RX_HASH_DST_PORT_TCP) 309 310 /* IBV hash bits for UDP. */ 311 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 312 IBV_RX_HASH_DST_PORT_UDP) 313 314 /* IBV hash bits for L4 SRC. */ 315 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 316 IBV_RX_HASH_SRC_PORT_UDP) 317 318 /* IBV hash bits for L4 DST. */ 319 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 320 IBV_RX_HASH_DST_PORT_UDP) 321 322 /* Geneve header first 16Bit */ 323 #define MLX5_GENEVE_VER_MASK 0x3 324 #define MLX5_GENEVE_VER_SHIFT 14 325 #define MLX5_GENEVE_VER_VAL(a) \ 326 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 327 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 328 #define MLX5_GENEVE_OPTLEN_SHIFT 7 329 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 330 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 331 #define MLX5_GENEVE_OAMF_MASK 0x1 332 #define MLX5_GENEVE_OAMF_SHIFT 7 333 #define MLX5_GENEVE_OAMF_VAL(a) \ 334 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 335 #define MLX5_GENEVE_CRITO_MASK 0x1 336 #define MLX5_GENEVE_CRITO_SHIFT 6 337 #define MLX5_GENEVE_CRITO_VAL(a) \ 338 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 339 #define MLX5_GENEVE_RSVD_MASK 0x3F 340 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 341 /* 342 * The length of the Geneve options fields, expressed in four byte multiples, 343 * not including the eight byte fixed tunnel. 344 */ 345 #define MLX5_GENEVE_OPT_LEN_0 14 346 #define MLX5_GENEVE_OPT_LEN_1 63 347 348 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \ 349 sizeof(struct rte_flow_item_ipv4)) 350 351 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 352 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 353 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 354 355 /* Specific item's fields can accept a range of values (using spec and last). */ 356 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 357 #define MLX5_ITEM_RANGE_ACCEPTED true 358 359 /* Software header modify action numbers of a flow. */ 360 #define MLX5_ACT_NUM_MDF_IPV4 1 361 #define MLX5_ACT_NUM_MDF_IPV6 4 362 #define MLX5_ACT_NUM_MDF_MAC 2 363 #define MLX5_ACT_NUM_MDF_VID 1 364 #define MLX5_ACT_NUM_MDF_PORT 2 365 #define MLX5_ACT_NUM_MDF_TTL 1 366 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 367 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 368 #define MLX5_ACT_NUM_MDF_TCPACK 1 369 #define MLX5_ACT_NUM_SET_REG 1 370 #define MLX5_ACT_NUM_SET_TAG 1 371 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 372 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 373 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 374 #define MLX5_ACT_NUM_SET_DSCP 1 375 376 enum mlx5_flow_drv_type { 377 MLX5_FLOW_TYPE_MIN, 378 MLX5_FLOW_TYPE_DV, 379 MLX5_FLOW_TYPE_VERBS, 380 MLX5_FLOW_TYPE_MAX, 381 }; 382 383 /* Fate action type. */ 384 enum mlx5_flow_fate_type { 385 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 386 MLX5_FLOW_FATE_QUEUE, 387 MLX5_FLOW_FATE_JUMP, 388 MLX5_FLOW_FATE_PORT_ID, 389 MLX5_FLOW_FATE_DROP, 390 MLX5_FLOW_FATE_DEFAULT_MISS, 391 MLX5_FLOW_FATE_SHARED_RSS, 392 MLX5_FLOW_FATE_MAX, 393 }; 394 395 /* Matcher PRM representation */ 396 struct mlx5_flow_dv_match_params { 397 size_t size; 398 /**< Size of match value. Do NOT split size and key! */ 399 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 400 /**< Matcher value. This value is used as the mask or as a key. */ 401 }; 402 403 /* Matcher structure. */ 404 struct mlx5_flow_dv_matcher { 405 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 406 struct mlx5_flow_tbl_resource *tbl; 407 /**< Pointer to the table(group) the matcher associated with. */ 408 void *matcher_object; /**< Pointer to DV matcher */ 409 uint16_t crc; /**< CRC of key. */ 410 uint16_t priority; /**< Priority of matcher. */ 411 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 412 }; 413 414 #define MLX5_ENCAP_MAX_LEN 132 415 416 /* Encap/decap resource key of the hash organization. */ 417 union mlx5_flow_encap_decap_key { 418 struct { 419 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 420 uint32_t refmt_type:8; /**< Header reformat type. */ 421 uint32_t buf_size:8; /**< Encap buf size. */ 422 uint32_t table_level:8; /**< Root table or not. */ 423 uint32_t cksum; /**< Encap buf check sum. */ 424 }; 425 uint64_t v64; /**< full 64bits value of key */ 426 }; 427 428 /* Encap/decap resource structure. */ 429 struct mlx5_flow_dv_encap_decap_resource { 430 struct mlx5_hlist_entry entry; 431 /* Pointer to next element. */ 432 uint32_t refcnt; /**< Reference counter. */ 433 void *action; 434 /**< Encap/decap action object. */ 435 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 436 size_t size; 437 uint8_t reformat_type; 438 uint8_t ft_type; 439 uint64_t flags; /**< Flags for RDMA API. */ 440 uint32_t idx; /**< Index for the index memory pool. */ 441 }; 442 443 /* Tag resource structure. */ 444 struct mlx5_flow_dv_tag_resource { 445 struct mlx5_hlist_entry entry; 446 /**< hash list entry for tag resource, tag value as the key. */ 447 void *action; 448 /**< Tag action object. */ 449 uint32_t refcnt; /**< Reference counter. */ 450 uint32_t idx; /**< Index for the index memory pool. */ 451 }; 452 453 /* 454 * Number of modification commands. 455 * The maximal actions amount in FW is some constant, and it is 16 in the 456 * latest releases. In some old releases, it will be limited to 8. 457 * Since there is no interface to query the capacity, the maximal value should 458 * be used to allow PMD to create the flow. The validation will be done in the 459 * lower driver layer or FW. A failure will be returned if exceeds the maximal 460 * supported actions number on the root table. 461 * On non-root tables, there is no limitation, but 32 is enough right now. 462 */ 463 #define MLX5_MAX_MODIFY_NUM 32 464 #define MLX5_ROOT_TBL_MODIFY_NUM 16 465 466 /* Modify resource structure */ 467 struct mlx5_flow_dv_modify_hdr_resource { 468 struct mlx5_hlist_entry entry; 469 void *action; /**< Modify header action object. */ 470 /* Key area for hash list matching: */ 471 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 472 uint32_t actions_num; /**< Number of modification actions. */ 473 uint64_t flags; /**< Flags for RDMA API. */ 474 struct mlx5_modification_cmd actions[]; 475 /**< Modification actions. */ 476 }; 477 478 /* Modify resource key of the hash organization. */ 479 union mlx5_flow_modify_hdr_key { 480 struct { 481 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 482 uint32_t actions_num:5; /**< Number of modification actions. */ 483 uint32_t group:19; /**< Flow group id. */ 484 uint32_t cksum; /**< Actions check sum. */ 485 }; 486 uint64_t v64; /**< full 64bits value of key */ 487 }; 488 489 /* Jump action resource structure. */ 490 struct mlx5_flow_dv_jump_tbl_resource { 491 void *action; /**< Pointer to the rdma core action. */ 492 }; 493 494 /* Port ID resource structure. */ 495 struct mlx5_flow_dv_port_id_action_resource { 496 struct mlx5_cache_entry entry; 497 void *action; /**< Action object. */ 498 uint32_t port_id; /**< Port ID value. */ 499 uint32_t idx; /**< Indexed pool memory index. */ 500 }; 501 502 /* Push VLAN action resource structure */ 503 struct mlx5_flow_dv_push_vlan_action_resource { 504 struct mlx5_cache_entry entry; /* Cache entry. */ 505 void *action; /**< Action object. */ 506 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 507 rte_be32_t vlan_tag; /**< VLAN tag value. */ 508 uint32_t idx; /**< Indexed pool memory index. */ 509 }; 510 511 /* Metadata register copy table entry. */ 512 struct mlx5_flow_mreg_copy_resource { 513 /* 514 * Hash list entry for copy table. 515 * - Key is 32/64-bit MARK action ID. 516 * - MUST be the first entry. 517 */ 518 struct mlx5_hlist_entry hlist_ent; 519 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 520 /* List entry for device flows. */ 521 uint32_t idx; 522 uint32_t rix_flow; /* Built flow for copy. */ 523 }; 524 525 /* Table tunnel parameter. */ 526 struct mlx5_flow_tbl_tunnel_prm { 527 const struct mlx5_flow_tunnel *tunnel; 528 uint32_t group_id; 529 bool external; 530 }; 531 532 /* Table data structure of the hash organization. */ 533 struct mlx5_flow_tbl_data_entry { 534 struct mlx5_hlist_entry entry; 535 /**< hash list entry, 64-bits key inside. */ 536 struct mlx5_flow_tbl_resource tbl; 537 /**< flow table resource. */ 538 struct mlx5_cache_list matchers; 539 /**< matchers' header associated with the flow table. */ 540 struct mlx5_flow_dv_jump_tbl_resource jump; 541 /**< jump resource, at most one for each table created. */ 542 uint32_t idx; /**< index for the indexed mempool. */ 543 /**< tunnel offload */ 544 const struct mlx5_flow_tunnel *tunnel; 545 uint32_t group_id; 546 bool external; 547 bool tunnel_offload; /* Tunnel offlod table or not. */ 548 bool is_egress; /**< Egress table. */ 549 }; 550 551 /* Sub rdma-core actions list. */ 552 struct mlx5_flow_sub_actions_list { 553 uint32_t actions_num; /**< Number of sample actions. */ 554 uint64_t action_flags; 555 void *dr_queue_action; 556 void *dr_tag_action; 557 void *dr_cnt_action; 558 void *dr_port_id_action; 559 void *dr_encap_action; 560 }; 561 562 /* Sample sub-actions resource list. */ 563 struct mlx5_flow_sub_actions_idx { 564 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 565 uint32_t rix_tag; /**< Index to the tag action. */ 566 uint32_t cnt; 567 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 568 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 569 }; 570 571 /* Sample action resource structure. */ 572 struct mlx5_flow_dv_sample_resource { 573 struct mlx5_cache_entry entry; /**< Cache entry. */ 574 union { 575 void *verbs_action; /**< Verbs sample action object. */ 576 void **sub_actions; /**< Sample sub-action array. */ 577 }; 578 uint32_t idx; /** Sample object index. */ 579 uint8_t ft_type; /** Flow Table Type */ 580 uint32_t ft_id; /** Flow Table Level */ 581 uint32_t ratio; /** Sample Ratio */ 582 uint64_t set_action; /** Restore reg_c0 value */ 583 void *normal_path_tbl; /** Flow Table pointer */ 584 void *default_miss; /** default_miss dr_action. */ 585 struct mlx5_flow_sub_actions_idx sample_idx; 586 /**< Action index resources. */ 587 struct mlx5_flow_sub_actions_list sample_act; 588 /**< Action resources. */ 589 }; 590 591 #define MLX5_MAX_DEST_NUM 2 592 593 /* Destination array action resource structure. */ 594 struct mlx5_flow_dv_dest_array_resource { 595 struct mlx5_cache_entry entry; /**< Cache entry. */ 596 uint32_t idx; /** Destination array action object index. */ 597 uint8_t ft_type; /** Flow Table Type */ 598 uint8_t num_of_dest; /**< Number of destination actions. */ 599 void *action; /**< Pointer to the rdma core action. */ 600 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 601 /**< Action index resources. */ 602 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 603 /**< Action resources. */ 604 }; 605 606 /* Verbs specification header. */ 607 struct ibv_spec_header { 608 enum ibv_flow_spec_type type; 609 uint16_t size; 610 }; 611 612 /* PMD flow priority for tunnel */ 613 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 614 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 615 616 617 /** Device flow handle structure for DV mode only. */ 618 struct mlx5_flow_handle_dv { 619 /* Flow DV api: */ 620 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 621 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 622 /**< Pointer to modify header resource in cache. */ 623 uint32_t rix_encap_decap; 624 /**< Index to encap/decap resource in cache. */ 625 uint32_t rix_push_vlan; 626 /**< Index to push VLAN action resource in cache. */ 627 uint32_t rix_tag; 628 /**< Index to the tag action. */ 629 uint32_t rix_sample; 630 /**< Index to sample action resource in cache. */ 631 uint32_t rix_dest_array; 632 /**< Index to destination array resource in cache. */ 633 } __rte_packed; 634 635 /** Device flow handle structure: used both for creating & destroying. */ 636 struct mlx5_flow_handle { 637 SILIST_ENTRY(uint32_t)next; 638 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 639 /**< Index to next device flow handle. */ 640 uint64_t layers; 641 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 642 void *drv_flow; /**< pointer to driver flow object. */ 643 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 644 uint32_t mark:1; /**< Metadate rxq mark flag. */ 645 uint32_t fate_action:3; /**< Fate action type. */ 646 union { 647 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 648 uint32_t rix_jump; /**< Index to the jump action resource. */ 649 uint32_t rix_port_id_action; 650 /**< Index to port ID action resource. */ 651 uint32_t rix_fate; 652 /**< Generic value indicates the fate action. */ 653 uint32_t rix_default_fate; 654 /**< Indicates default miss fate action. */ 655 uint32_t rix_srss; 656 /**< Indicates shared RSS fate action. */ 657 }; 658 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 659 struct mlx5_flow_handle_dv dvh; 660 #endif 661 } __rte_packed; 662 663 /* 664 * Size for Verbs device flow handle structure only. Do not use the DV only 665 * structure in Verbs. No DV flows attributes will be accessed. 666 * Macro offsetof() could also be used here. 667 */ 668 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 669 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 670 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 671 #else 672 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 673 #endif 674 675 /* 676 * Max number of actions per DV flow. 677 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 678 * in rdma-core file providers/mlx5/verbs.c. 679 */ 680 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 681 682 /** Device flow structure only for DV flow creation. */ 683 struct mlx5_flow_dv_workspace { 684 uint32_t group; /**< The group index. */ 685 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 686 int actions_n; /**< number of actions. */ 687 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 688 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 689 /**< Pointer to encap/decap resource in cache. */ 690 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 691 /**< Pointer to push VLAN action resource in cache. */ 692 struct mlx5_flow_dv_tag_resource *tag_resource; 693 /**< pointer to the tag action. */ 694 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 695 /**< Pointer to port ID action resource. */ 696 struct mlx5_flow_dv_jump_tbl_resource *jump; 697 /**< Pointer to the jump action resource. */ 698 struct mlx5_flow_dv_match_params value; 699 /**< Holds the value that the packet is compared to. */ 700 struct mlx5_flow_dv_sample_resource *sample_res; 701 /**< Pointer to the sample action resource. */ 702 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 703 /**< Pointer to the destination array resource. */ 704 }; 705 706 /* 707 * Maximal Verbs flow specifications & actions size. 708 * Some elements are mutually exclusive, but enough space should be allocated. 709 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 710 * 2. One tunnel header (exception: GRE + MPLS), 711 * SPEC length: GRE == tunnel. 712 * Actions: 1. 1 Mark OR Flag. 713 * 2. 1 Drop (if any). 714 * 3. No limitation for counters, but it makes no sense to support too 715 * many counters in a single device flow. 716 */ 717 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 718 #define MLX5_VERBS_MAX_SPEC_SIZE \ 719 ( \ 720 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 721 sizeof(struct ibv_flow_spec_ipv6) + \ 722 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 723 sizeof(struct ibv_flow_spec_gre) + \ 724 sizeof(struct ibv_flow_spec_mpls)) \ 725 ) 726 #else 727 #define MLX5_VERBS_MAX_SPEC_SIZE \ 728 ( \ 729 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 730 sizeof(struct ibv_flow_spec_ipv6) + \ 731 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 732 sizeof(struct ibv_flow_spec_tunnel)) \ 733 ) 734 #endif 735 736 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 737 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 738 #define MLX5_VERBS_MAX_ACT_SIZE \ 739 ( \ 740 sizeof(struct ibv_flow_spec_action_tag) + \ 741 sizeof(struct ibv_flow_spec_action_drop) + \ 742 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 743 ) 744 #else 745 #define MLX5_VERBS_MAX_ACT_SIZE \ 746 ( \ 747 sizeof(struct ibv_flow_spec_action_tag) + \ 748 sizeof(struct ibv_flow_spec_action_drop) \ 749 ) 750 #endif 751 752 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 753 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 754 755 /** Device flow structure only for Verbs flow creation. */ 756 struct mlx5_flow_verbs_workspace { 757 unsigned int size; /**< Size of the attribute. */ 758 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 759 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 760 /**< Specifications & actions buffer of verbs flow. */ 761 }; 762 763 /** Maximal number of device sub-flows supported. */ 764 #define MLX5_NUM_MAX_DEV_FLOWS 32 765 766 /** Device flow structure. */ 767 __extension__ 768 struct mlx5_flow { 769 struct rte_flow *flow; /**< Pointer to the main flow. */ 770 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 771 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 772 uint64_t act_flags; 773 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 774 bool external; /**< true if the flow is created external to PMD. */ 775 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 776 uint8_t skip_scale:1; 777 /**< 1 if skip the scale the table with factor. */ 778 union { 779 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 780 struct mlx5_flow_dv_workspace dv; 781 #endif 782 struct mlx5_flow_verbs_workspace verbs; 783 }; 784 struct mlx5_flow_handle *handle; 785 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 786 const struct mlx5_flow_tunnel *tunnel; 787 }; 788 789 /* Flow meter state. */ 790 #define MLX5_FLOW_METER_DISABLE 0 791 #define MLX5_FLOW_METER_ENABLE 1 792 793 #define MLX5_MAN_WIDTH 8 794 /* Modify this value if enum rte_mtr_color changes. */ 795 #define RTE_MTR_DROPPED RTE_COLORS 796 797 /* Meter policer statistics */ 798 struct mlx5_flow_policer_stats { 799 uint32_t cnt[RTE_COLORS + 1]; 800 /**< Color counter, extra for drop. */ 801 uint64_t stats_mask; 802 /**< Statistics mask for the colors. */ 803 }; 804 805 /* Meter table structure. */ 806 struct mlx5_meter_domain_info { 807 struct mlx5_flow_tbl_resource *tbl; 808 /**< Meter table. */ 809 struct mlx5_flow_tbl_resource *sfx_tbl; 810 /**< Meter suffix table. */ 811 void *any_matcher; 812 /**< Meter color not match default criteria. */ 813 void *color_matcher; 814 /**< Meter color match criteria. */ 815 void *jump_actn; 816 /**< Meter match action. */ 817 void *policer_rules[RTE_MTR_DROPPED + 1]; 818 /**< Meter policer for the match. */ 819 }; 820 821 /* Meter table set for TX RX FDB. */ 822 struct mlx5_meter_domains_infos { 823 uint32_t ref_cnt; 824 /**< Table user count. */ 825 struct mlx5_meter_domain_info egress; 826 /**< TX meter table. */ 827 struct mlx5_meter_domain_info ingress; 828 /**< RX meter table. */ 829 struct mlx5_meter_domain_info transfer; 830 /**< FDB meter table. */ 831 void *drop_actn; 832 /**< Drop action as not matched. */ 833 void *count_actns[RTE_MTR_DROPPED + 1]; 834 /**< Counters for match and unmatched statistics. */ 835 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 836 /**< Flow meter parameter. */ 837 size_t fmp_size; 838 /**< Flow meter parameter size. */ 839 void *meter_action; 840 /**< Flow meter action. */ 841 }; 842 843 /* Meter parameter structure. */ 844 struct mlx5_flow_meter { 845 TAILQ_ENTRY(mlx5_flow_meter) next; 846 /**< Pointer to the next flow meter structure. */ 847 uint32_t idx; /* Index to meter object. */ 848 uint32_t meter_id; 849 /**< Meter id. */ 850 struct mlx5_flow_meter_profile *profile; 851 /**< Meter profile parameters. */ 852 853 rte_spinlock_t sl; /**< Meter action spinlock. */ 854 855 /** Policer actions (per meter output color). */ 856 enum rte_mtr_policer_action action[RTE_COLORS]; 857 858 /** Set of stats counters to be enabled. 859 * @see enum rte_mtr_stats_type 860 */ 861 uint64_t stats_mask; 862 863 /**< Rule applies to ingress traffic. */ 864 uint32_t ingress:1; 865 866 /**< Rule applies to egress traffic. */ 867 uint32_t egress:1; 868 /** 869 * Instead of simply matching the properties of traffic as it would 870 * appear on a given DPDK port ID, enabling this attribute transfers 871 * a flow rule to the lowest possible level of any device endpoints 872 * found in the pattern. 873 * 874 * When supported, this effectively enables an application to 875 * re-route traffic not necessarily intended for it (e.g. coming 876 * from or addressed to different physical ports, VFs or 877 * applications) at the device level. 878 * 879 * It complements the behavior of some pattern items such as 880 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 881 * 882 * When transferring flow rules, ingress and egress attributes keep 883 * their original meaning, as if processing traffic emitted or 884 * received by the application. 885 */ 886 uint32_t transfer:1; 887 struct mlx5_meter_domains_infos *mfts; 888 /**< Flow table created for this meter. */ 889 struct mlx5_flow_policer_stats policer_stats; 890 /**< Meter policer statistics. */ 891 uint32_t ref_cnt; 892 /**< Use count. */ 893 uint32_t active_state:1; 894 /**< Meter state. */ 895 uint32_t shared:1; 896 /**< Meter shared or not. */ 897 }; 898 899 /* RFC2697 parameter structure. */ 900 struct mlx5_flow_meter_srtcm_rfc2697_prm { 901 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 902 uint32_t cbs_exponent:5; 903 uint32_t cbs_mantissa:8; 904 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 905 uint32_t cir_exponent:5; 906 uint32_t cir_mantissa:8; 907 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 908 uint32_t ebs_exponent:5; 909 uint32_t ebs_mantissa:8; 910 }; 911 912 /* Flow meter profile structure. */ 913 struct mlx5_flow_meter_profile { 914 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 915 /**< Pointer to the next flow meter structure. */ 916 uint32_t meter_profile_id; /**< Profile id. */ 917 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 918 union { 919 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 920 /**< srtcm_rfc2697 struct. */ 921 }; 922 uint32_t ref_cnt; /**< Use count. */ 923 }; 924 925 #define MLX5_MAX_TUNNELS 256 926 #define MLX5_TNL_MISS_RULE_PRIORITY 3 927 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 928 929 /* 930 * When tunnel offload is active, all JUMP group ids are converted 931 * using the same method. That conversion is applied both to tunnel and 932 * regular rule types. 933 * Group ids used in tunnel rules are relative to it's tunnel (!). 934 * Application can create number of steer rules, using the same 935 * tunnel, with different group id in each rule. 936 * Each tunnel stores its groups internally in PMD tunnel object. 937 * Groups used in regular rules do not belong to any tunnel and are stored 938 * in tunnel hub. 939 */ 940 941 struct mlx5_flow_tunnel { 942 LIST_ENTRY(mlx5_flow_tunnel) chain; 943 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 944 uint32_t tunnel_id; /** unique tunnel ID */ 945 uint32_t refctn; 946 struct rte_flow_action action; 947 struct rte_flow_item item; 948 struct mlx5_hlist *groups; /** tunnel groups */ 949 }; 950 951 /** PMD tunnel related context */ 952 struct mlx5_flow_tunnel_hub { 953 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 954 rte_spinlock_t sl; /* Tunnel list spinlock. */ 955 struct mlx5_hlist *groups; /** non tunnel groups */ 956 }; 957 958 /* convert jump group to flow table ID in tunnel rules */ 959 struct tunnel_tbl_entry { 960 struct mlx5_hlist_entry hash; 961 uint32_t flow_table; 962 }; 963 964 static inline uint32_t 965 tunnel_id_to_flow_tbl(uint32_t id) 966 { 967 return id | (1u << 16); 968 } 969 970 static inline uint32_t 971 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 972 { 973 return flow_tbl & ~(1u << 16); 974 } 975 976 union tunnel_tbl_key { 977 uint64_t val; 978 struct { 979 uint32_t tunnel_id; 980 uint32_t group; 981 }; 982 }; 983 984 static inline struct mlx5_flow_tunnel_hub * 985 mlx5_tunnel_hub(struct rte_eth_dev *dev) 986 { 987 struct mlx5_priv *priv = dev->data->dev_private; 988 return priv->sh->tunnel_hub; 989 } 990 991 static inline bool 992 is_tunnel_offload_active(struct rte_eth_dev *dev) 993 { 994 struct mlx5_priv *priv = dev->data->dev_private; 995 return !!priv->config.dv_miss_info; 996 } 997 998 static inline bool 999 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev, 1000 __rte_unused const struct rte_flow_attr *attr, 1001 __rte_unused const struct rte_flow_item items[], 1002 __rte_unused const struct rte_flow_action actions[]) 1003 { 1004 return (items[0].type == (typeof(items[0].type)) 1005 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL); 1006 } 1007 1008 static inline bool 1009 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev, 1010 __rte_unused const struct rte_flow_attr *attr, 1011 __rte_unused const struct rte_flow_item items[], 1012 __rte_unused const struct rte_flow_action actions[]) 1013 { 1014 return (actions[0].type == (typeof(actions[0].type)) 1015 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET); 1016 } 1017 1018 static inline const struct mlx5_flow_tunnel * 1019 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 1020 { 1021 return actions[0].conf; 1022 } 1023 1024 static inline const struct mlx5_flow_tunnel * 1025 flow_items_to_tunnel(const struct rte_flow_item items[]) 1026 { 1027 return items[0].spec; 1028 } 1029 1030 /* Flow structure. */ 1031 struct rte_flow { 1032 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 1033 uint32_t dev_handles; 1034 /**< Device flow handles that are part of the flow. */ 1035 uint32_t drv_type:2; /**< Driver type. */ 1036 uint32_t tunnel:1; 1037 uint32_t meter:16; /**< Holds flow meter id. */ 1038 uint32_t rix_mreg_copy; 1039 /**< Index to metadata register copy table resource. */ 1040 uint32_t counter; /**< Holds flow counter. */ 1041 uint32_t tunnel_id; /**< Tunnel id */ 1042 uint32_t age; /**< Holds ASO age bit index. */ 1043 } __rte_packed; 1044 1045 /* 1046 * Define list of valid combinations of RX Hash fields 1047 * (see enum ibv_rx_hash_fields). 1048 */ 1049 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1050 #define MLX5_RSS_HASH_IPV4_TCP \ 1051 (MLX5_RSS_HASH_IPV4 | \ 1052 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP) 1053 #define MLX5_RSS_HASH_IPV4_UDP \ 1054 (MLX5_RSS_HASH_IPV4 | \ 1055 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP) 1056 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1057 #define MLX5_RSS_HASH_IPV6_TCP \ 1058 (MLX5_RSS_HASH_IPV6 | \ 1059 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP) 1060 #define MLX5_RSS_HASH_IPV6_UDP \ 1061 (MLX5_RSS_HASH_IPV6 | \ 1062 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP) 1063 #define MLX5_RSS_HASH_NONE 0ULL 1064 1065 /* array of valid combinations of RX Hash fields for RSS */ 1066 static const uint64_t mlx5_rss_hash_fields[] = { 1067 MLX5_RSS_HASH_IPV4, 1068 MLX5_RSS_HASH_IPV4_TCP, 1069 MLX5_RSS_HASH_IPV4_UDP, 1070 MLX5_RSS_HASH_IPV6, 1071 MLX5_RSS_HASH_IPV6_TCP, 1072 MLX5_RSS_HASH_IPV6_UDP, 1073 MLX5_RSS_HASH_NONE, 1074 }; 1075 1076 /* Shared RSS action structure */ 1077 struct mlx5_shared_action_rss { 1078 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1079 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1080 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1081 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1082 uint16_t *queue; /**< Queue indices to use. */ 1083 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1084 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1085 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN]; 1086 /**< Hash RX queue indexes for tunneled RSS */ 1087 }; 1088 1089 struct rte_flow_shared_action { 1090 uint32_t id; 1091 }; 1092 1093 /* Thread specific flow workspace intermediate data. */ 1094 struct mlx5_flow_workspace { 1095 /* If creating another flow in same thread, push new as stack. */ 1096 struct mlx5_flow_workspace *prev; 1097 struct mlx5_flow_workspace *next; 1098 uint32_t inuse; /* can't create new flow with current. */ 1099 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1100 struct mlx5_flow_rss_desc rss_desc; 1101 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1102 int flow_idx; /* Intermediate device flow index. */ 1103 }; 1104 1105 struct mlx5_flow_split_info { 1106 bool external; 1107 /**< True if flow is created by request external to PMD. */ 1108 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1109 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1110 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1111 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1112 }; 1113 1114 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1115 const struct rte_flow_attr *attr, 1116 const struct rte_flow_item items[], 1117 const struct rte_flow_action actions[], 1118 bool external, 1119 int hairpin, 1120 struct rte_flow_error *error); 1121 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1122 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1123 const struct rte_flow_item items[], 1124 const struct rte_flow_action actions[], struct rte_flow_error *error); 1125 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1126 struct mlx5_flow *dev_flow, 1127 const struct rte_flow_attr *attr, 1128 const struct rte_flow_item items[], 1129 const struct rte_flow_action actions[], 1130 struct rte_flow_error *error); 1131 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1132 struct rte_flow_error *error); 1133 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1134 struct rte_flow *flow); 1135 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1136 struct rte_flow *flow); 1137 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1138 struct rte_flow *flow, 1139 const struct rte_flow_action *actions, 1140 void *data, 1141 struct rte_flow_error *error); 1142 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 1143 (struct rte_eth_dev *dev, 1144 const struct mlx5_flow_meter *fm); 1145 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1146 struct mlx5_meter_domains_infos *tbls); 1147 typedef int (*mlx5_flow_create_policer_rules_t) 1148 (struct rte_eth_dev *dev, 1149 struct mlx5_flow_meter *fm, 1150 const struct rte_flow_attr *attr); 1151 typedef int (*mlx5_flow_destroy_policer_rules_t) 1152 (struct rte_eth_dev *dev, 1153 const struct mlx5_flow_meter *fm, 1154 const struct rte_flow_attr *attr); 1155 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1156 (struct rte_eth_dev *dev); 1157 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1158 uint32_t cnt); 1159 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1160 uint32_t cnt, 1161 bool clear, uint64_t *pkts, 1162 uint64_t *bytes); 1163 typedef int (*mlx5_flow_get_aged_flows_t) 1164 (struct rte_eth_dev *dev, 1165 void **context, 1166 uint32_t nb_contexts, 1167 struct rte_flow_error *error); 1168 typedef int (*mlx5_flow_action_validate_t) 1169 (struct rte_eth_dev *dev, 1170 const struct rte_flow_shared_action_conf *conf, 1171 const struct rte_flow_action *action, 1172 struct rte_flow_error *error); 1173 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t) 1174 (struct rte_eth_dev *dev, 1175 const struct rte_flow_shared_action_conf *conf, 1176 const struct rte_flow_action *action, 1177 struct rte_flow_error *error); 1178 typedef int (*mlx5_flow_action_destroy_t) 1179 (struct rte_eth_dev *dev, 1180 struct rte_flow_shared_action *action, 1181 struct rte_flow_error *error); 1182 typedef int (*mlx5_flow_action_update_t) 1183 (struct rte_eth_dev *dev, 1184 struct rte_flow_shared_action *action, 1185 const void *action_conf, 1186 struct rte_flow_error *error); 1187 typedef int (*mlx5_flow_action_query_t) 1188 (struct rte_eth_dev *dev, 1189 const struct rte_flow_shared_action *action, 1190 void *data, 1191 struct rte_flow_error *error); 1192 typedef int (*mlx5_flow_sync_domain_t) 1193 (struct rte_eth_dev *dev, 1194 uint32_t domains, 1195 uint32_t flags); 1196 1197 struct mlx5_flow_driver_ops { 1198 mlx5_flow_validate_t validate; 1199 mlx5_flow_prepare_t prepare; 1200 mlx5_flow_translate_t translate; 1201 mlx5_flow_apply_t apply; 1202 mlx5_flow_remove_t remove; 1203 mlx5_flow_destroy_t destroy; 1204 mlx5_flow_query_t query; 1205 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1206 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1207 mlx5_flow_create_policer_rules_t create_policer_rules; 1208 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 1209 mlx5_flow_counter_alloc_t counter_alloc; 1210 mlx5_flow_counter_free_t counter_free; 1211 mlx5_flow_counter_query_t counter_query; 1212 mlx5_flow_get_aged_flows_t get_aged_flows; 1213 mlx5_flow_action_validate_t action_validate; 1214 mlx5_flow_action_create_t action_create; 1215 mlx5_flow_action_destroy_t action_destroy; 1216 mlx5_flow_action_update_t action_update; 1217 mlx5_flow_action_query_t action_query; 1218 mlx5_flow_sync_domain_t sync_domain; 1219 }; 1220 1221 /* mlx5_flow.c */ 1222 1223 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1224 __extension__ 1225 struct flow_grp_info { 1226 uint64_t external:1; 1227 uint64_t transfer:1; 1228 uint64_t fdb_def_rule:1; 1229 /* force standard group translation */ 1230 uint64_t std_tbl_fix:1; 1231 uint64_t skip_scale:1; 1232 }; 1233 1234 static inline bool 1235 tunnel_use_standard_attr_group_translate 1236 (struct rte_eth_dev *dev, 1237 const struct mlx5_flow_tunnel *tunnel, 1238 const struct rte_flow_attr *attr, 1239 const struct rte_flow_item items[], 1240 const struct rte_flow_action actions[]) 1241 { 1242 bool verdict; 1243 1244 if (!is_tunnel_offload_active(dev)) 1245 /* no tunnel offload API */ 1246 verdict = true; 1247 else if (tunnel) { 1248 /* 1249 * OvS will use jump to group 0 in tunnel steer rule. 1250 * If tunnel steer rule starts from group 0 (attr.group == 0) 1251 * that 0 group must be translated with standard method. 1252 * attr.group == 0 in tunnel match rule translated with tunnel 1253 * method 1254 */ 1255 verdict = !attr->group && 1256 is_flow_tunnel_steer_rule(dev, attr, items, actions); 1257 } else { 1258 /* 1259 * non-tunnel group translation uses standard method for 1260 * root group only: attr.group == 0 1261 */ 1262 verdict = !attr->group; 1263 } 1264 1265 return verdict; 1266 } 1267 1268 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1269 const struct mlx5_flow_tunnel *tunnel, 1270 uint32_t group, uint32_t *table, 1271 struct flow_grp_info flags, 1272 struct rte_flow_error *error); 1273 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1274 int tunnel, uint64_t layer_types, 1275 uint64_t hash_fields); 1276 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1277 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1278 uint32_t subpriority); 1279 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1280 enum mlx5_feature_name feature, 1281 uint32_t id, 1282 struct rte_flow_error *error); 1283 const struct rte_flow_action *mlx5_flow_find_action 1284 (const struct rte_flow_action *actions, 1285 enum rte_flow_action_type action); 1286 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1287 const struct rte_flow_action *action, 1288 struct rte_flow_error *error); 1289 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1290 const struct rte_flow_attr *attr, 1291 struct rte_flow_error *error); 1292 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1293 const struct rte_flow_attr *attr, 1294 struct rte_flow_error *error); 1295 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1296 const struct rte_flow_attr *attr, 1297 struct rte_flow_error *error); 1298 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1299 uint64_t action_flags, 1300 const struct rte_flow_attr *attr, 1301 struct rte_flow_error *error); 1302 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1303 uint64_t action_flags, 1304 struct rte_eth_dev *dev, 1305 const struct rte_flow_attr *attr, 1306 struct rte_flow_error *error); 1307 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1308 uint64_t action_flags, 1309 struct rte_eth_dev *dev, 1310 const struct rte_flow_attr *attr, 1311 uint64_t item_flags, 1312 struct rte_flow_error *error); 1313 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1314 const struct rte_flow_attr *attr, 1315 struct rte_flow_error *error); 1316 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1317 const struct rte_flow_attr *attributes, 1318 struct rte_flow_error *error); 1319 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1320 const uint8_t *mask, 1321 const uint8_t *nic_mask, 1322 unsigned int size, 1323 bool range_accepted, 1324 struct rte_flow_error *error); 1325 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1326 uint64_t item_flags, bool ext_vlan_sup, 1327 struct rte_flow_error *error); 1328 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1329 uint64_t item_flags, 1330 uint8_t target_protocol, 1331 struct rte_flow_error *error); 1332 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1333 uint64_t item_flags, 1334 const struct rte_flow_item *gre_item, 1335 struct rte_flow_error *error); 1336 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1337 uint64_t item_flags, 1338 uint64_t last_item, 1339 uint16_t ether_type, 1340 const struct rte_flow_item_ipv4 *acc_mask, 1341 bool range_accepted, 1342 struct rte_flow_error *error); 1343 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1344 uint64_t item_flags, 1345 uint64_t last_item, 1346 uint16_t ether_type, 1347 const struct rte_flow_item_ipv6 *acc_mask, 1348 struct rte_flow_error *error); 1349 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1350 const struct rte_flow_item *item, 1351 uint64_t item_flags, 1352 uint64_t prev_layer, 1353 struct rte_flow_error *error); 1354 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1355 uint64_t item_flags, 1356 uint8_t target_protocol, 1357 const struct rte_flow_item_tcp *flow_mask, 1358 struct rte_flow_error *error); 1359 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1360 uint64_t item_flags, 1361 uint8_t target_protocol, 1362 struct rte_flow_error *error); 1363 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1364 uint64_t item_flags, 1365 struct rte_eth_dev *dev, 1366 struct rte_flow_error *error); 1367 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1368 uint64_t item_flags, 1369 struct rte_flow_error *error); 1370 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1371 uint64_t item_flags, 1372 struct rte_eth_dev *dev, 1373 struct rte_flow_error *error); 1374 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1375 uint64_t item_flags, 1376 uint8_t target_protocol, 1377 struct rte_flow_error *error); 1378 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1379 uint64_t item_flags, 1380 uint8_t target_protocol, 1381 struct rte_flow_error *error); 1382 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1383 uint64_t item_flags, 1384 uint8_t target_protocol, 1385 struct rte_flow_error *error); 1386 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1387 uint64_t item_flags, 1388 struct rte_eth_dev *dev, 1389 struct rte_flow_error *error); 1390 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1391 uint64_t item_flags, 1392 uint64_t last_item, 1393 uint16_t ether_type, 1394 const struct rte_flow_item_ecpri *acc_mask, 1395 struct rte_flow_error *error); 1396 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1397 (struct rte_eth_dev *dev, 1398 const struct mlx5_flow_meter *fm); 1399 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1400 struct mlx5_meter_domains_infos *tbl); 1401 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1402 struct mlx5_flow_meter *fm, 1403 const struct rte_flow_attr *attr); 1404 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1405 struct mlx5_flow_meter *fm, 1406 const struct rte_flow_attr *attr); 1407 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1408 struct rte_mtr_error *error); 1409 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1410 int mlx5_shared_action_flush(struct rte_eth_dev *dev); 1411 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1412 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1413 1414 /* Hash list callbacks for flow tables: */ 1415 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1416 uint64_t key, void *entry_ctx); 1417 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1418 struct mlx5_hlist_entry *entry); 1419 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1420 uint32_t table_id, uint8_t egress, uint8_t transfer, 1421 bool external, const struct mlx5_flow_tunnel *tunnel, 1422 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error); 1423 1424 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1425 uint64_t key, void *cb_ctx); 1426 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1427 struct mlx5_hlist_entry *entry); 1428 1429 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1430 struct mlx5_hlist_entry *entry, 1431 uint64_t key, void *cb_ctx); 1432 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1433 uint64_t key, void *ctx); 1434 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1435 struct mlx5_hlist_entry *entry); 1436 1437 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1438 uint64_t key, void *ctx); 1439 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1440 struct mlx5_hlist_entry *entry); 1441 1442 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1443 struct mlx5_hlist_entry *entry, 1444 uint64_t key, void *cb_ctx); 1445 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1446 uint64_t key, void *cb_ctx); 1447 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1448 struct mlx5_hlist_entry *entry); 1449 1450 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1451 struct mlx5_cache_entry *entry, void *ctx); 1452 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1453 struct mlx5_cache_entry *entry, void *ctx); 1454 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1455 struct mlx5_cache_entry *entry); 1456 1457 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1458 struct mlx5_cache_entry *entry, void *cb_ctx); 1459 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1460 struct mlx5_cache_entry *entry, void *cb_ctx); 1461 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1462 struct mlx5_cache_entry *entry); 1463 1464 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1465 struct mlx5_cache_entry *entry, void *cb_ctx); 1466 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1467 (struct mlx5_cache_list *list, 1468 struct mlx5_cache_entry *entry, void *cb_ctx); 1469 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1470 struct mlx5_cache_entry *entry); 1471 1472 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1473 struct mlx5_cache_entry *entry, void *cb_ctx); 1474 struct mlx5_cache_entry *flow_dv_sample_create_cb 1475 (struct mlx5_cache_list *list, 1476 struct mlx5_cache_entry *entry, void *cb_ctx); 1477 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1478 struct mlx5_cache_entry *entry); 1479 1480 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1481 struct mlx5_cache_entry *entry, void *cb_ctx); 1482 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1483 (struct mlx5_cache_list *list, 1484 struct mlx5_cache_entry *entry, void *cb_ctx); 1485 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1486 struct mlx5_cache_entry *entry); 1487 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1488 uint32_t age_idx); 1489 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1490