1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* E-Switch Manager port, used for rte_flow_item_port_id. */ 22 #define MLX5_PORT_ESW_MGR UINT32_MAX 23 24 /* Private rte flow items. */ 25 enum mlx5_rte_flow_item_type { 26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 31 }; 32 33 /* Private (internal) rte flow actions. */ 34 enum mlx5_rte_flow_action_type { 35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 36 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 37 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 41 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT, 43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP, 44 }; 45 46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 47 48 enum { 49 MLX5_INDIRECT_ACTION_TYPE_RSS, 50 MLX5_INDIRECT_ACTION_TYPE_AGE, 51 MLX5_INDIRECT_ACTION_TYPE_COUNT, 52 MLX5_INDIRECT_ACTION_TYPE_CT, 53 }; 54 55 /* Now, the maximal ports will be supported is 256, action number is 4M. */ 56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100 57 58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22 59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1) 60 61 /* 30-31: type, 22-29: owner port, 0-21: index. */ 62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \ 63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \ 64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \ 65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index)) 66 67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \ 68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \ 69 MLX5_INDIRECT_ACT_CT_OWNER_MASK) 70 71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \ 72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1)) 73 74 /* Matches on selected register. */ 75 struct mlx5_rte_flow_item_tag { 76 enum modify_reg id; 77 uint32_t data; 78 }; 79 80 /* Modify selected register. */ 81 struct mlx5_rte_flow_action_set_tag { 82 enum modify_reg id; 83 uint8_t offset; 84 uint8_t length; 85 uint32_t data; 86 }; 87 88 struct mlx5_flow_action_copy_mreg { 89 enum modify_reg dst; 90 enum modify_reg src; 91 }; 92 93 /* Matches on source queue. */ 94 struct mlx5_rte_flow_item_tx_queue { 95 uint32_t queue; 96 }; 97 98 /* Feature name to allocate metadata register. */ 99 enum mlx5_feature_name { 100 MLX5_HAIRPIN_RX, 101 MLX5_HAIRPIN_TX, 102 MLX5_METADATA_RX, 103 MLX5_METADATA_TX, 104 MLX5_METADATA_FDB, 105 MLX5_FLOW_MARK, 106 MLX5_APP_TAG, 107 MLX5_COPY_MARK, 108 MLX5_MTR_COLOR, 109 MLX5_MTR_ID, 110 MLX5_ASO_FLOW_HIT, 111 MLX5_ASO_CONNTRACK, 112 MLX5_SAMPLE_ID, 113 }; 114 115 /* Default queue number. */ 116 #define MLX5_RSSQ_DEFAULT_NUM 16 117 118 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 120 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 121 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 122 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 123 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 124 125 /* Pattern inner Layer bits. */ 126 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 127 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 128 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 129 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 130 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 131 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 132 133 /* Pattern tunnel Layer bits. */ 134 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 135 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 136 #define MLX5_FLOW_LAYER_GRE (1u << 14) 137 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 138 /* List of tunnel Layer bits continued below. */ 139 140 /* General pattern items bits. */ 141 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 142 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 143 #define MLX5_FLOW_ITEM_TAG (1u << 18) 144 #define MLX5_FLOW_ITEM_MARK (1u << 19) 145 146 /* Pattern MISC bits. */ 147 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 148 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 149 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 150 151 /* Pattern tunnel Layer bits (continued). */ 152 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 153 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 154 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 155 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 156 157 /* Queue items. */ 158 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 159 160 /* Pattern tunnel Layer bits (continued). */ 161 #define MLX5_FLOW_LAYER_GTP (1u << 28) 162 163 /* Pattern eCPRI Layer bit. */ 164 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 165 166 /* IPv6 Fragment Extension Header bit. */ 167 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 168 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 169 170 /* Pattern tunnel Layer bits (continued). */ 171 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 172 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 173 174 /* INTEGRITY item bits */ 175 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34) 176 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35) 177 #define MLX5_FLOW_ITEM_INTEGRITY \ 178 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY) 179 180 /* Conntrack item. */ 181 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36) 182 183 /* Flex item */ 184 #define MLX5_FLOW_ITEM_OUTER_FLEX (UINT64_C(1) << 37) 185 #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 38) 186 #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 39) 187 188 /* Outer Masks. */ 189 #define MLX5_FLOW_LAYER_OUTER_L3 \ 190 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 191 #define MLX5_FLOW_LAYER_OUTER_L4 \ 192 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 193 #define MLX5_FLOW_LAYER_OUTER \ 194 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 195 MLX5_FLOW_LAYER_OUTER_L4) 196 197 /* Tunnel Masks. */ 198 #define MLX5_FLOW_LAYER_TUNNEL \ 199 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 200 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 201 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 202 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP | \ 203 MLX5_FLOW_ITEM_FLEX_TUNNEL) 204 205 /* Inner Masks. */ 206 #define MLX5_FLOW_LAYER_INNER_L3 \ 207 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 208 #define MLX5_FLOW_LAYER_INNER_L4 \ 209 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 210 #define MLX5_FLOW_LAYER_INNER \ 211 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 212 MLX5_FLOW_LAYER_INNER_L4) 213 214 /* Layer Masks. */ 215 #define MLX5_FLOW_LAYER_L2 \ 216 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 217 #define MLX5_FLOW_LAYER_L3_IPV4 \ 218 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 219 #define MLX5_FLOW_LAYER_L3_IPV6 \ 220 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 221 #define MLX5_FLOW_LAYER_L3 \ 222 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 223 #define MLX5_FLOW_LAYER_L4 \ 224 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 225 226 /* Actions */ 227 #define MLX5_FLOW_ACTION_DROP (1u << 0) 228 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 229 #define MLX5_FLOW_ACTION_RSS (1u << 2) 230 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 231 #define MLX5_FLOW_ACTION_MARK (1u << 4) 232 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 233 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 234 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 235 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 236 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 237 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 238 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 239 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 240 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 241 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 242 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 243 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 244 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 245 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 246 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 247 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 248 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 249 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 250 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 251 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 252 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 253 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 254 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 255 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 256 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 257 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 258 #define MLX5_FLOW_ACTION_METER (1ull << 31) 259 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 260 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 261 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 262 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 263 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 264 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 265 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 266 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 267 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40) 268 #define MLX5_FLOW_ACTION_CT (1ull << 41) 269 270 #define MLX5_FLOW_FATE_ACTIONS \ 271 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 272 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 273 MLX5_FLOW_ACTION_DEFAULT_MISS | \ 274 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 275 276 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 277 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 278 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 279 280 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 281 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 282 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 283 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 284 MLX5_FLOW_ACTION_SET_TP_SRC | \ 285 MLX5_FLOW_ACTION_SET_TP_DST | \ 286 MLX5_FLOW_ACTION_SET_TTL | \ 287 MLX5_FLOW_ACTION_DEC_TTL | \ 288 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 289 MLX5_FLOW_ACTION_SET_MAC_DST | \ 290 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 291 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 292 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 293 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 294 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 295 MLX5_FLOW_ACTION_SET_TAG | \ 296 MLX5_FLOW_ACTION_MARK_EXT | \ 297 MLX5_FLOW_ACTION_SET_META | \ 298 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 299 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 300 MLX5_FLOW_ACTION_MODIFY_FIELD) 301 302 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 303 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 304 305 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 306 307 #ifndef IPPROTO_MPLS 308 #define IPPROTO_MPLS 137 309 #endif 310 311 /* UDP port number for MPLS */ 312 #define MLX5_UDP_PORT_MPLS 6635 313 314 /* UDP port numbers for VxLAN. */ 315 #define MLX5_UDP_PORT_VXLAN 4789 316 #define MLX5_UDP_PORT_VXLAN_GPE 4790 317 318 /* UDP port numbers for GENEVE. */ 319 #define MLX5_UDP_PORT_GENEVE 6081 320 321 /* Lowest priority indicator. */ 322 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 323 324 /* 325 * Max priority for ingress\egress flow groups 326 * greater than 0 and for any transfer flow group. 327 * From user configation: 0 - 21843. 328 */ 329 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 330 331 /* 332 * Number of sub priorities. 333 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 334 * matching on the NIC (firmware dependent) L4 most have the higher priority 335 * followed by L3 and ending with L2. 336 */ 337 #define MLX5_PRIORITY_MAP_L2 2 338 #define MLX5_PRIORITY_MAP_L3 1 339 #define MLX5_PRIORITY_MAP_L4 0 340 #define MLX5_PRIORITY_MAP_MAX 3 341 342 /* Valid layer type for IPV4 RSS. */ 343 #define MLX5_IPV4_LAYER_TYPES \ 344 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \ 345 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 346 RTE_ETH_RSS_NONFRAG_IPV4_OTHER) 347 348 /* IBV hash source bits for IPV4. */ 349 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 350 351 /* Valid layer type for IPV6 RSS. */ 352 #define MLX5_IPV6_LAYER_TYPES \ 353 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 354 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \ 355 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER) 356 357 /* IBV hash source bits for IPV6. */ 358 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 359 360 /* IBV hash bits for L3 SRC. */ 361 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 362 363 /* IBV hash bits for L3 DST. */ 364 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 365 366 /* IBV hash bits for TCP. */ 367 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 368 IBV_RX_HASH_DST_PORT_TCP) 369 370 /* IBV hash bits for UDP. */ 371 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 372 IBV_RX_HASH_DST_PORT_UDP) 373 374 /* IBV hash bits for L4 SRC. */ 375 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 376 IBV_RX_HASH_SRC_PORT_UDP) 377 378 /* IBV hash bits for L4 DST. */ 379 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 380 IBV_RX_HASH_DST_PORT_UDP) 381 382 /* Geneve header first 16Bit */ 383 #define MLX5_GENEVE_VER_MASK 0x3 384 #define MLX5_GENEVE_VER_SHIFT 14 385 #define MLX5_GENEVE_VER_VAL(a) \ 386 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 387 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 388 #define MLX5_GENEVE_OPTLEN_SHIFT 8 389 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 390 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 391 #define MLX5_GENEVE_OAMF_MASK 0x1 392 #define MLX5_GENEVE_OAMF_SHIFT 7 393 #define MLX5_GENEVE_OAMF_VAL(a) \ 394 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 395 #define MLX5_GENEVE_CRITO_MASK 0x1 396 #define MLX5_GENEVE_CRITO_SHIFT 6 397 #define MLX5_GENEVE_CRITO_VAL(a) \ 398 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 399 #define MLX5_GENEVE_RSVD_MASK 0x3F 400 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 401 /* 402 * The length of the Geneve options fields, expressed in four byte multiples, 403 * not including the eight byte fixed tunnel. 404 */ 405 #define MLX5_GENEVE_OPT_LEN_0 14 406 #define MLX5_GENEVE_OPT_LEN_1 63 407 408 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 409 sizeof(struct rte_ipv4_hdr)) 410 /* GTP extension header flag. */ 411 #define MLX5_GTP_EXT_HEADER_FLAG 4 412 413 /* GTP extension header PDU type shift. */ 414 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 415 416 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 417 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 418 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 419 420 /* Specific item's fields can accept a range of values (using spec and last). */ 421 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 422 #define MLX5_ITEM_RANGE_ACCEPTED true 423 424 /* Software header modify action numbers of a flow. */ 425 #define MLX5_ACT_NUM_MDF_IPV4 1 426 #define MLX5_ACT_NUM_MDF_IPV6 4 427 #define MLX5_ACT_NUM_MDF_MAC 2 428 #define MLX5_ACT_NUM_MDF_VID 1 429 #define MLX5_ACT_NUM_MDF_PORT 2 430 #define MLX5_ACT_NUM_MDF_TTL 1 431 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 432 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 433 #define MLX5_ACT_NUM_MDF_TCPACK 1 434 #define MLX5_ACT_NUM_SET_REG 1 435 #define MLX5_ACT_NUM_SET_TAG 1 436 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 437 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 438 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 439 #define MLX5_ACT_NUM_SET_DSCP 1 440 441 /* Maximum number of fields to modify in MODIFY_FIELD */ 442 #define MLX5_ACT_MAX_MOD_FIELDS 5 443 444 /* Syndrome bits definition for connection tracking. */ 445 #define MLX5_CT_SYNDROME_VALID (0x0 << 6) 446 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6) 447 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6) 448 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1) 449 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0) 450 451 enum mlx5_flow_drv_type { 452 MLX5_FLOW_TYPE_MIN, 453 MLX5_FLOW_TYPE_DV, 454 MLX5_FLOW_TYPE_VERBS, 455 MLX5_FLOW_TYPE_MAX, 456 }; 457 458 /* Fate action type. */ 459 enum mlx5_flow_fate_type { 460 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 461 MLX5_FLOW_FATE_QUEUE, 462 MLX5_FLOW_FATE_JUMP, 463 MLX5_FLOW_FATE_PORT_ID, 464 MLX5_FLOW_FATE_DROP, 465 MLX5_FLOW_FATE_DEFAULT_MISS, 466 MLX5_FLOW_FATE_SHARED_RSS, 467 MLX5_FLOW_FATE_MTR, 468 MLX5_FLOW_FATE_MAX, 469 }; 470 471 /* Matcher PRM representation */ 472 struct mlx5_flow_dv_match_params { 473 size_t size; 474 /**< Size of match value. Do NOT split size and key! */ 475 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 476 /**< Matcher value. This value is used as the mask or as a key. */ 477 }; 478 479 /* Matcher structure. */ 480 struct mlx5_flow_dv_matcher { 481 struct mlx5_list_entry entry; /**< Pointer to the next element. */ 482 struct mlx5_flow_tbl_resource *tbl; 483 /**< Pointer to the table(group) the matcher associated with. */ 484 void *matcher_object; /**< Pointer to DV matcher */ 485 uint16_t crc; /**< CRC of key. */ 486 uint16_t priority; /**< Priority of matcher. */ 487 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 488 }; 489 490 #define MLX5_ENCAP_MAX_LEN 132 491 492 /* Encap/decap resource structure. */ 493 struct mlx5_flow_dv_encap_decap_resource { 494 struct mlx5_list_entry entry; 495 /* Pointer to next element. */ 496 uint32_t refcnt; /**< Reference counter. */ 497 void *action; 498 /**< Encap/decap action object. */ 499 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 500 size_t size; 501 uint8_t reformat_type; 502 uint8_t ft_type; 503 uint64_t flags; /**< Flags for RDMA API. */ 504 uint32_t idx; /**< Index for the index memory pool. */ 505 }; 506 507 /* Tag resource structure. */ 508 struct mlx5_flow_dv_tag_resource { 509 struct mlx5_list_entry entry; 510 /**< hash list entry for tag resource, tag value as the key. */ 511 void *action; 512 /**< Tag action object. */ 513 uint32_t refcnt; /**< Reference counter. */ 514 uint32_t idx; /**< Index for the index memory pool. */ 515 uint32_t tag_id; /**< Tag ID. */ 516 }; 517 518 /* Modify resource structure */ 519 struct mlx5_flow_dv_modify_hdr_resource { 520 struct mlx5_list_entry entry; 521 void *action; /**< Modify header action object. */ 522 uint32_t idx; 523 /* Key area for hash list matching: */ 524 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 525 uint8_t actions_num; /**< Number of modification actions. */ 526 bool root; /**< Whether action is in root table. */ 527 struct mlx5_modification_cmd actions[]; 528 /**< Modification actions. */ 529 } __rte_packed; 530 531 /* Modify resource key of the hash organization. */ 532 union mlx5_flow_modify_hdr_key { 533 struct { 534 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 535 uint32_t actions_num:5; /**< Number of modification actions. */ 536 uint32_t group:19; /**< Flow group id. */ 537 uint32_t cksum; /**< Actions check sum. */ 538 }; 539 uint64_t v64; /**< full 64bits value of key */ 540 }; 541 542 /* Jump action resource structure. */ 543 struct mlx5_flow_dv_jump_tbl_resource { 544 void *action; /**< Pointer to the rdma core action. */ 545 }; 546 547 /* Port ID resource structure. */ 548 struct mlx5_flow_dv_port_id_action_resource { 549 struct mlx5_list_entry entry; 550 void *action; /**< Action object. */ 551 uint32_t port_id; /**< Port ID value. */ 552 uint32_t idx; /**< Indexed pool memory index. */ 553 }; 554 555 /* Push VLAN action resource structure */ 556 struct mlx5_flow_dv_push_vlan_action_resource { 557 struct mlx5_list_entry entry; /* Cache entry. */ 558 void *action; /**< Action object. */ 559 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 560 rte_be32_t vlan_tag; /**< VLAN tag value. */ 561 uint32_t idx; /**< Indexed pool memory index. */ 562 }; 563 564 /* Metadata register copy table entry. */ 565 struct mlx5_flow_mreg_copy_resource { 566 /* 567 * Hash list entry for copy table. 568 * - Key is 32/64-bit MARK action ID. 569 * - MUST be the first entry. 570 */ 571 struct mlx5_list_entry hlist_ent; 572 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 573 /* List entry for device flows. */ 574 uint32_t idx; 575 uint32_t rix_flow; /* Built flow for copy. */ 576 uint32_t mark_id; 577 }; 578 579 /* Table tunnel parameter. */ 580 struct mlx5_flow_tbl_tunnel_prm { 581 const struct mlx5_flow_tunnel *tunnel; 582 uint32_t group_id; 583 bool external; 584 }; 585 586 /* Table data structure of the hash organization. */ 587 struct mlx5_flow_tbl_data_entry { 588 struct mlx5_list_entry entry; 589 /**< hash list entry, 64-bits key inside. */ 590 struct mlx5_flow_tbl_resource tbl; 591 /**< flow table resource. */ 592 struct mlx5_list *matchers; 593 /**< matchers' header associated with the flow table. */ 594 struct mlx5_flow_dv_jump_tbl_resource jump; 595 /**< jump resource, at most one for each table created. */ 596 uint32_t idx; /**< index for the indexed mempool. */ 597 /**< tunnel offload */ 598 const struct mlx5_flow_tunnel *tunnel; 599 uint32_t group_id; 600 uint32_t external:1; 601 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 602 uint32_t is_egress:1; /**< Egress table. */ 603 uint32_t is_transfer:1; /**< Transfer table. */ 604 uint32_t dummy:1; /**< DR table. */ 605 uint32_t id:22; /**< Table ID. */ 606 uint32_t reserve:5; /**< Reserved to future using. */ 607 uint32_t level; /**< Table level. */ 608 }; 609 610 /* Sub rdma-core actions list. */ 611 struct mlx5_flow_sub_actions_list { 612 uint32_t actions_num; /**< Number of sample actions. */ 613 uint64_t action_flags; 614 void *dr_queue_action; 615 void *dr_tag_action; 616 void *dr_cnt_action; 617 void *dr_port_id_action; 618 void *dr_encap_action; 619 void *dr_jump_action; 620 }; 621 622 /* Sample sub-actions resource list. */ 623 struct mlx5_flow_sub_actions_idx { 624 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 625 uint32_t rix_tag; /**< Index to the tag action. */ 626 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 627 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 628 uint32_t rix_jump; /**< Index to the jump action resource. */ 629 }; 630 631 /* Sample action resource structure. */ 632 struct mlx5_flow_dv_sample_resource { 633 struct mlx5_list_entry entry; /**< Cache entry. */ 634 union { 635 void *verbs_action; /**< Verbs sample action object. */ 636 void **sub_actions; /**< Sample sub-action array. */ 637 }; 638 struct rte_eth_dev *dev; /**< Device registers the action. */ 639 uint32_t idx; /** Sample object index. */ 640 uint8_t ft_type; /** Flow Table Type */ 641 uint32_t ft_id; /** Flow Table Level */ 642 uint32_t ratio; /** Sample Ratio */ 643 uint64_t set_action; /** Restore reg_c0 value */ 644 void *normal_path_tbl; /** Flow Table pointer */ 645 struct mlx5_flow_sub_actions_idx sample_idx; 646 /**< Action index resources. */ 647 struct mlx5_flow_sub_actions_list sample_act; 648 /**< Action resources. */ 649 }; 650 651 #define MLX5_MAX_DEST_NUM 2 652 653 /* Destination array action resource structure. */ 654 struct mlx5_flow_dv_dest_array_resource { 655 struct mlx5_list_entry entry; /**< Cache entry. */ 656 uint32_t idx; /** Destination array action object index. */ 657 uint8_t ft_type; /** Flow Table Type */ 658 uint8_t num_of_dest; /**< Number of destination actions. */ 659 struct rte_eth_dev *dev; /**< Device registers the action. */ 660 void *action; /**< Pointer to the rdma core action. */ 661 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 662 /**< Action index resources. */ 663 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 664 /**< Action resources. */ 665 }; 666 667 /* PMD flow priority for tunnel */ 668 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 669 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 670 671 672 /** Device flow handle structure for DV mode only. */ 673 struct mlx5_flow_handle_dv { 674 /* Flow DV api: */ 675 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 676 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 677 /**< Pointer to modify header resource in cache. */ 678 uint32_t rix_encap_decap; 679 /**< Index to encap/decap resource in cache. */ 680 uint32_t rix_push_vlan; 681 /**< Index to push VLAN action resource in cache. */ 682 uint32_t rix_tag; 683 /**< Index to the tag action. */ 684 uint32_t rix_sample; 685 /**< Index to sample action resource in cache. */ 686 uint32_t rix_dest_array; 687 /**< Index to destination array resource in cache. */ 688 } __rte_packed; 689 690 /** Device flow handle structure: used both for creating & destroying. */ 691 struct mlx5_flow_handle { 692 SILIST_ENTRY(uint32_t)next; 693 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 694 /**< Index to next device flow handle. */ 695 uint64_t layers; 696 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 697 void *drv_flow; /**< pointer to driver flow object. */ 698 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */ 699 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */ 700 uint32_t mark:1; /**< Metadate rxq mark flag. */ 701 uint32_t fate_action:3; /**< Fate action type. */ 702 uint32_t flex_item; /**< referenced Flex Item bitmask. */ 703 union { 704 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 705 uint32_t rix_jump; /**< Index to the jump action resource. */ 706 uint32_t rix_port_id_action; 707 /**< Index to port ID action resource. */ 708 uint32_t rix_fate; 709 /**< Generic value indicates the fate action. */ 710 uint32_t rix_default_fate; 711 /**< Indicates default miss fate action. */ 712 uint32_t rix_srss; 713 /**< Indicates shared RSS fate action. */ 714 }; 715 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 716 struct mlx5_flow_handle_dv dvh; 717 #endif 718 } __rte_packed; 719 720 /* 721 * Size for Verbs device flow handle structure only. Do not use the DV only 722 * structure in Verbs. No DV flows attributes will be accessed. 723 * Macro offsetof() could also be used here. 724 */ 725 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 726 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 727 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 728 #else 729 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 730 #endif 731 732 /** Device flow structure only for DV flow creation. */ 733 struct mlx5_flow_dv_workspace { 734 uint32_t group; /**< The group index. */ 735 uint32_t table_id; /**< Flow table identifier. */ 736 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 737 int actions_n; /**< number of actions. */ 738 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 739 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 740 /**< Pointer to encap/decap resource in cache. */ 741 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 742 /**< Pointer to push VLAN action resource in cache. */ 743 struct mlx5_flow_dv_tag_resource *tag_resource; 744 /**< pointer to the tag action. */ 745 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 746 /**< Pointer to port ID action resource. */ 747 struct mlx5_flow_dv_jump_tbl_resource *jump; 748 /**< Pointer to the jump action resource. */ 749 struct mlx5_flow_dv_match_params value; 750 /**< Holds the value that the packet is compared to. */ 751 struct mlx5_flow_dv_sample_resource *sample_res; 752 /**< Pointer to the sample action resource. */ 753 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 754 /**< Pointer to the destination array resource. */ 755 }; 756 757 #ifdef HAVE_INFINIBAND_VERBS_H 758 /* 759 * Maximal Verbs flow specifications & actions size. 760 * Some elements are mutually exclusive, but enough space should be allocated. 761 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 762 * 2. One tunnel header (exception: GRE + MPLS), 763 * SPEC length: GRE == tunnel. 764 * Actions: 1. 1 Mark OR Flag. 765 * 2. 1 Drop (if any). 766 * 3. No limitation for counters, but it makes no sense to support too 767 * many counters in a single device flow. 768 */ 769 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 770 #define MLX5_VERBS_MAX_SPEC_SIZE \ 771 ( \ 772 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 773 sizeof(struct ibv_flow_spec_ipv6) + \ 774 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 775 sizeof(struct ibv_flow_spec_gre) + \ 776 sizeof(struct ibv_flow_spec_mpls)) \ 777 ) 778 #else 779 #define MLX5_VERBS_MAX_SPEC_SIZE \ 780 ( \ 781 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 782 sizeof(struct ibv_flow_spec_ipv6) + \ 783 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 784 sizeof(struct ibv_flow_spec_tunnel)) \ 785 ) 786 #endif 787 788 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 789 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 790 #define MLX5_VERBS_MAX_ACT_SIZE \ 791 ( \ 792 sizeof(struct ibv_flow_spec_action_tag) + \ 793 sizeof(struct ibv_flow_spec_action_drop) + \ 794 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 795 ) 796 #else 797 #define MLX5_VERBS_MAX_ACT_SIZE \ 798 ( \ 799 sizeof(struct ibv_flow_spec_action_tag) + \ 800 sizeof(struct ibv_flow_spec_action_drop) \ 801 ) 802 #endif 803 804 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 805 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 806 807 /** Device flow structure only for Verbs flow creation. */ 808 struct mlx5_flow_verbs_workspace { 809 unsigned int size; /**< Size of the attribute. */ 810 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 811 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 812 /**< Specifications & actions buffer of verbs flow. */ 813 }; 814 #endif /* HAVE_INFINIBAND_VERBS_H */ 815 816 #define MLX5_SCALE_FLOW_GROUP_BIT 0 817 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 818 819 /** Maximal number of device sub-flows supported. */ 820 #define MLX5_NUM_MAX_DEV_FLOWS 32 821 822 /** 823 * tunnel offload rules type 824 */ 825 enum mlx5_tof_rule_type { 826 MLX5_TUNNEL_OFFLOAD_NONE = 0, 827 MLX5_TUNNEL_OFFLOAD_SET_RULE, 828 MLX5_TUNNEL_OFFLOAD_MATCH_RULE, 829 MLX5_TUNNEL_OFFLOAD_MISS_RULE, 830 }; 831 832 /** Device flow structure. */ 833 __extension__ 834 struct mlx5_flow { 835 struct rte_flow *flow; /**< Pointer to the main flow. */ 836 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 837 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 838 uint64_t act_flags; 839 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 840 bool external; /**< true if the flow is created external to PMD. */ 841 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 842 uint8_t skip_scale:2; 843 /** 844 * Each Bit be set to 1 if Skip the scale the flow group with factor. 845 * If bit0 be set to 1, then skip the scale the original flow group; 846 * If bit1 be set to 1, then skip the scale the jump flow group if 847 * having jump action. 848 * 00: Enable scale in a flow, default value. 849 * 01: Skip scale the flow group with factor, enable scale the group 850 * of jump action. 851 * 10: Enable scale the group with factor, skip scale the group of 852 * jump action. 853 * 11: Skip scale the table with factor both for flow group and jump 854 * group. 855 */ 856 union { 857 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 858 struct mlx5_flow_dv_workspace dv; 859 #endif 860 #ifdef HAVE_INFINIBAND_VERBS_H 861 struct mlx5_flow_verbs_workspace verbs; 862 #endif 863 }; 864 struct mlx5_flow_handle *handle; 865 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 866 const struct mlx5_flow_tunnel *tunnel; 867 enum mlx5_tof_rule_type tof_type; 868 }; 869 870 /* Flow meter state. */ 871 #define MLX5_FLOW_METER_DISABLE 0 872 #define MLX5_FLOW_METER_ENABLE 1 873 874 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u 875 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u 876 877 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES 878 879 #define MLX5_MAN_WIDTH 8 880 /* Legacy Meter parameter structure. */ 881 struct mlx5_legacy_flow_meter { 882 struct mlx5_flow_meter_info fm; 883 /* Must be the first in struct. */ 884 TAILQ_ENTRY(mlx5_legacy_flow_meter) next; 885 /**< Pointer to the next flow meter structure. */ 886 uint32_t idx; 887 /* Index to meter object. */ 888 }; 889 890 #define MLX5_MAX_TUNNELS 256 891 #define MLX5_TNL_MISS_RULE_PRIORITY 3 892 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 893 894 /* 895 * When tunnel offload is active, all JUMP group ids are converted 896 * using the same method. That conversion is applied both to tunnel and 897 * regular rule types. 898 * Group ids used in tunnel rules are relative to it's tunnel (!). 899 * Application can create number of steer rules, using the same 900 * tunnel, with different group id in each rule. 901 * Each tunnel stores its groups internally in PMD tunnel object. 902 * Groups used in regular rules do not belong to any tunnel and are stored 903 * in tunnel hub. 904 */ 905 906 struct mlx5_flow_tunnel { 907 LIST_ENTRY(mlx5_flow_tunnel) chain; 908 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 909 uint32_t tunnel_id; /** unique tunnel ID */ 910 uint32_t refctn; 911 struct rte_flow_action action; 912 struct rte_flow_item item; 913 struct mlx5_hlist *groups; /** tunnel groups */ 914 }; 915 916 /** PMD tunnel related context */ 917 struct mlx5_flow_tunnel_hub { 918 /* Tunnels list 919 * Access to the list MUST be MT protected 920 */ 921 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 922 /* protect access to the tunnels list */ 923 rte_spinlock_t sl; 924 struct mlx5_hlist *groups; /** non tunnel groups */ 925 }; 926 927 /* convert jump group to flow table ID in tunnel rules */ 928 struct tunnel_tbl_entry { 929 struct mlx5_list_entry hash; 930 uint32_t flow_table; 931 uint32_t tunnel_id; 932 uint32_t group; 933 }; 934 935 static inline uint32_t 936 tunnel_id_to_flow_tbl(uint32_t id) 937 { 938 return id | (1u << 16); 939 } 940 941 static inline uint32_t 942 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 943 { 944 return flow_tbl & ~(1u << 16); 945 } 946 947 union tunnel_tbl_key { 948 uint64_t val; 949 struct { 950 uint32_t tunnel_id; 951 uint32_t group; 952 }; 953 }; 954 955 static inline struct mlx5_flow_tunnel_hub * 956 mlx5_tunnel_hub(struct rte_eth_dev *dev) 957 { 958 struct mlx5_priv *priv = dev->data->dev_private; 959 return priv->sh->tunnel_hub; 960 } 961 962 static inline bool 963 is_tunnel_offload_active(const struct rte_eth_dev *dev) 964 { 965 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 966 const struct mlx5_priv *priv = dev->data->dev_private; 967 return !!priv->config.dv_miss_info; 968 #else 969 RTE_SET_USED(dev); 970 return false; 971 #endif 972 } 973 974 static inline bool 975 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type) 976 { 977 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 978 } 979 980 static inline bool 981 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type) 982 { 983 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE; 984 } 985 986 static inline const struct mlx5_flow_tunnel * 987 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 988 { 989 return actions[0].conf; 990 } 991 992 static inline const struct mlx5_flow_tunnel * 993 flow_items_to_tunnel(const struct rte_flow_item items[]) 994 { 995 return items[0].spec; 996 } 997 998 /* Flow structure. */ 999 struct rte_flow { 1000 uint32_t dev_handles; 1001 /**< Device flow handles that are part of the flow. */ 1002 uint32_t type:2; 1003 uint32_t drv_type:2; /**< Driver type. */ 1004 uint32_t tunnel:1; 1005 uint32_t meter:24; /**< Holds flow meter id. */ 1006 uint32_t indirect_type:2; /**< Indirect action type. */ 1007 uint32_t rix_mreg_copy; 1008 /**< Index to metadata register copy table resource. */ 1009 uint32_t counter; /**< Holds flow counter. */ 1010 uint32_t tunnel_id; /**< Tunnel id */ 1011 union { 1012 uint32_t age; /**< Holds ASO age bit index. */ 1013 uint32_t ct; /**< Holds ASO CT index. */ 1014 }; 1015 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 1016 } __rte_packed; 1017 1018 /* 1019 * Define list of valid combinations of RX Hash fields 1020 * (see enum ibv_rx_hash_fields). 1021 */ 1022 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1023 #define MLX5_RSS_HASH_IPV4_TCP \ 1024 (MLX5_RSS_HASH_IPV4 | \ 1025 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1026 #define MLX5_RSS_HASH_IPV4_UDP \ 1027 (MLX5_RSS_HASH_IPV4 | \ 1028 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1029 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1030 #define MLX5_RSS_HASH_IPV6_TCP \ 1031 (MLX5_RSS_HASH_IPV6 | \ 1032 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1033 #define MLX5_RSS_HASH_IPV6_UDP \ 1034 (MLX5_RSS_HASH_IPV6 | \ 1035 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1036 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 1037 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 1038 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 1039 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1040 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1041 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1042 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1043 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1044 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1045 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1046 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1047 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1048 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1049 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1050 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1051 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1052 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1053 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1054 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1055 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1056 #define MLX5_RSS_HASH_NONE 0ULL 1057 1058 1059 /* extract next protocol type from Ethernet & VLAN headers */ 1060 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \ 1061 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \ 1062 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \ 1063 (_prt) = rte_be_to_cpu_16((_prt)); \ 1064 } while (0) 1065 1066 /* array of valid combinations of RX Hash fields for RSS */ 1067 static const uint64_t mlx5_rss_hash_fields[] = { 1068 MLX5_RSS_HASH_IPV4, 1069 MLX5_RSS_HASH_IPV4_TCP, 1070 MLX5_RSS_HASH_IPV4_UDP, 1071 MLX5_RSS_HASH_IPV6, 1072 MLX5_RSS_HASH_IPV6_TCP, 1073 MLX5_RSS_HASH_IPV6_UDP, 1074 MLX5_RSS_HASH_NONE, 1075 }; 1076 1077 /* Shared RSS action structure */ 1078 struct mlx5_shared_action_rss { 1079 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1080 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1081 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1082 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1083 struct mlx5_ind_table_obj *ind_tbl; 1084 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1085 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1086 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1087 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1088 }; 1089 1090 struct rte_flow_action_handle { 1091 uint32_t id; 1092 }; 1093 1094 /* Thread specific flow workspace intermediate data. */ 1095 struct mlx5_flow_workspace { 1096 /* If creating another flow in same thread, push new as stack. */ 1097 struct mlx5_flow_workspace *prev; 1098 struct mlx5_flow_workspace *next; 1099 uint32_t inuse; /* can't create new flow with current. */ 1100 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1101 struct mlx5_flow_rss_desc rss_desc; 1102 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1103 uint32_t flow_idx; /* Intermediate device flow index. */ 1104 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */ 1105 struct mlx5_flow_meter_policy *policy; 1106 /* The meter policy used by meter in flow. */ 1107 struct mlx5_flow_meter_policy *final_policy; 1108 /* The final policy when meter policy is hierarchy. */ 1109 uint32_t skip_matcher_reg:1; 1110 /* Indicates if need to skip matcher register in translate. */ 1111 }; 1112 1113 struct mlx5_flow_split_info { 1114 uint32_t external:1; 1115 /**< True if flow is created by request external to PMD. */ 1116 uint32_t prefix_mark:1; /**< Prefix subflow mark flag. */ 1117 uint32_t skip_scale:8; /**< Skip the scale the table with factor. */ 1118 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1119 uint32_t table_id; /**< Flow table identifier. */ 1120 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1121 }; 1122 1123 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1124 const struct rte_flow_attr *attr, 1125 const struct rte_flow_item items[], 1126 const struct rte_flow_action actions[], 1127 bool external, 1128 int hairpin, 1129 struct rte_flow_error *error); 1130 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1131 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1132 const struct rte_flow_item items[], 1133 const struct rte_flow_action actions[], struct rte_flow_error *error); 1134 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1135 struct mlx5_flow *dev_flow, 1136 const struct rte_flow_attr *attr, 1137 const struct rte_flow_item items[], 1138 const struct rte_flow_action actions[], 1139 struct rte_flow_error *error); 1140 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1141 struct rte_flow_error *error); 1142 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1143 struct rte_flow *flow); 1144 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1145 struct rte_flow *flow); 1146 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1147 struct rte_flow *flow, 1148 const struct rte_flow_action *actions, 1149 void *data, 1150 struct rte_flow_error *error); 1151 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev, 1152 struct mlx5_flow_meter_info *fm, 1153 uint32_t mtr_idx, 1154 uint8_t domain_bitmap); 1155 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1156 struct mlx5_flow_meter_info *fm); 1157 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev); 1158 typedef struct mlx5_flow_meter_sub_policy * 1159 (*mlx5_flow_meter_sub_policy_rss_prepare_t) 1160 (struct rte_eth_dev *dev, 1161 struct mlx5_flow_meter_policy *mtr_policy, 1162 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1163 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t) 1164 (struct rte_eth_dev *dev, 1165 struct mlx5_flow_meter_info *fm, 1166 int32_t src_port, 1167 const struct rte_flow_item *item, 1168 struct rte_flow_error *error); 1169 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t) 1170 (struct rte_eth_dev *dev, 1171 struct mlx5_flow_meter_policy *mtr_policy); 1172 typedef uint32_t (*mlx5_flow_mtr_alloc_t) 1173 (struct rte_eth_dev *dev); 1174 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev, 1175 uint32_t mtr_idx); 1176 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1177 (struct rte_eth_dev *dev); 1178 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1179 uint32_t cnt); 1180 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1181 uint32_t cnt, 1182 bool clear, uint64_t *pkts, 1183 uint64_t *bytes); 1184 typedef int (*mlx5_flow_get_aged_flows_t) 1185 (struct rte_eth_dev *dev, 1186 void **context, 1187 uint32_t nb_contexts, 1188 struct rte_flow_error *error); 1189 typedef int (*mlx5_flow_action_validate_t) 1190 (struct rte_eth_dev *dev, 1191 const struct rte_flow_indir_action_conf *conf, 1192 const struct rte_flow_action *action, 1193 struct rte_flow_error *error); 1194 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1195 (struct rte_eth_dev *dev, 1196 const struct rte_flow_indir_action_conf *conf, 1197 const struct rte_flow_action *action, 1198 struct rte_flow_error *error); 1199 typedef int (*mlx5_flow_action_destroy_t) 1200 (struct rte_eth_dev *dev, 1201 struct rte_flow_action_handle *action, 1202 struct rte_flow_error *error); 1203 typedef int (*mlx5_flow_action_update_t) 1204 (struct rte_eth_dev *dev, 1205 struct rte_flow_action_handle *action, 1206 const void *update, 1207 struct rte_flow_error *error); 1208 typedef int (*mlx5_flow_action_query_t) 1209 (struct rte_eth_dev *dev, 1210 const struct rte_flow_action_handle *action, 1211 void *data, 1212 struct rte_flow_error *error); 1213 typedef int (*mlx5_flow_sync_domain_t) 1214 (struct rte_eth_dev *dev, 1215 uint32_t domains, 1216 uint32_t flags); 1217 typedef int (*mlx5_flow_validate_mtr_acts_t) 1218 (struct rte_eth_dev *dev, 1219 const struct rte_flow_action *actions[RTE_COLORS], 1220 struct rte_flow_attr *attr, 1221 bool *is_rss, 1222 uint8_t *domain_bitmap, 1223 uint8_t *policy_mode, 1224 struct rte_mtr_error *error); 1225 typedef int (*mlx5_flow_create_mtr_acts_t) 1226 (struct rte_eth_dev *dev, 1227 struct mlx5_flow_meter_policy *mtr_policy, 1228 const struct rte_flow_action *actions[RTE_COLORS], 1229 struct rte_mtr_error *error); 1230 typedef void (*mlx5_flow_destroy_mtr_acts_t) 1231 (struct rte_eth_dev *dev, 1232 struct mlx5_flow_meter_policy *mtr_policy); 1233 typedef int (*mlx5_flow_create_policy_rules_t) 1234 (struct rte_eth_dev *dev, 1235 struct mlx5_flow_meter_policy *mtr_policy); 1236 typedef void (*mlx5_flow_destroy_policy_rules_t) 1237 (struct rte_eth_dev *dev, 1238 struct mlx5_flow_meter_policy *mtr_policy); 1239 typedef int (*mlx5_flow_create_def_policy_t) 1240 (struct rte_eth_dev *dev); 1241 typedef void (*mlx5_flow_destroy_def_policy_t) 1242 (struct rte_eth_dev *dev); 1243 typedef int (*mlx5_flow_discover_priorities_t) 1244 (struct rte_eth_dev *dev, 1245 const uint16_t *vprio, int vprio_n); 1246 typedef struct rte_flow_item_flex_handle *(*mlx5_flow_item_create_t) 1247 (struct rte_eth_dev *dev, 1248 const struct rte_flow_item_flex_conf *conf, 1249 struct rte_flow_error *error); 1250 typedef int (*mlx5_flow_item_release_t) 1251 (struct rte_eth_dev *dev, 1252 const struct rte_flow_item_flex_handle *handle, 1253 struct rte_flow_error *error); 1254 typedef int (*mlx5_flow_item_update_t) 1255 (struct rte_eth_dev *dev, 1256 const struct rte_flow_item_flex_handle *handle, 1257 const struct rte_flow_item_flex_conf *conf, 1258 struct rte_flow_error *error); 1259 1260 struct mlx5_flow_driver_ops { 1261 mlx5_flow_validate_t validate; 1262 mlx5_flow_prepare_t prepare; 1263 mlx5_flow_translate_t translate; 1264 mlx5_flow_apply_t apply; 1265 mlx5_flow_remove_t remove; 1266 mlx5_flow_destroy_t destroy; 1267 mlx5_flow_query_t query; 1268 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1269 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1270 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls; 1271 mlx5_flow_mtr_alloc_t create_meter; 1272 mlx5_flow_mtr_free_t free_meter; 1273 mlx5_flow_validate_mtr_acts_t validate_mtr_acts; 1274 mlx5_flow_create_mtr_acts_t create_mtr_acts; 1275 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts; 1276 mlx5_flow_create_policy_rules_t create_policy_rules; 1277 mlx5_flow_destroy_policy_rules_t destroy_policy_rules; 1278 mlx5_flow_create_def_policy_t create_def_policy; 1279 mlx5_flow_destroy_def_policy_t destroy_def_policy; 1280 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare; 1281 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create; 1282 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq; 1283 mlx5_flow_counter_alloc_t counter_alloc; 1284 mlx5_flow_counter_free_t counter_free; 1285 mlx5_flow_counter_query_t counter_query; 1286 mlx5_flow_get_aged_flows_t get_aged_flows; 1287 mlx5_flow_action_validate_t action_validate; 1288 mlx5_flow_action_create_t action_create; 1289 mlx5_flow_action_destroy_t action_destroy; 1290 mlx5_flow_action_update_t action_update; 1291 mlx5_flow_action_query_t action_query; 1292 mlx5_flow_sync_domain_t sync_domain; 1293 mlx5_flow_discover_priorities_t discover_priorities; 1294 mlx5_flow_item_create_t item_create; 1295 mlx5_flow_item_release_t item_release; 1296 mlx5_flow_item_update_t item_update; 1297 }; 1298 1299 /* mlx5_flow.c */ 1300 1301 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1302 __extension__ 1303 struct flow_grp_info { 1304 uint64_t external:1; 1305 uint64_t transfer:1; 1306 uint64_t fdb_def_rule:1; 1307 /* force standard group translation */ 1308 uint64_t std_tbl_fix:1; 1309 uint64_t skip_scale:2; 1310 }; 1311 1312 static inline bool 1313 tunnel_use_standard_attr_group_translate 1314 (const struct rte_eth_dev *dev, 1315 const struct rte_flow_attr *attr, 1316 const struct mlx5_flow_tunnel *tunnel, 1317 enum mlx5_tof_rule_type tof_rule_type) 1318 { 1319 bool verdict; 1320 1321 if (!is_tunnel_offload_active(dev)) 1322 /* no tunnel offload API */ 1323 verdict = true; 1324 else if (tunnel) { 1325 /* 1326 * OvS will use jump to group 0 in tunnel steer rule. 1327 * If tunnel steer rule starts from group 0 (attr.group == 0) 1328 * that 0 group must be translated with standard method. 1329 * attr.group == 0 in tunnel match rule translated with tunnel 1330 * method 1331 */ 1332 verdict = !attr->group && 1333 is_flow_tunnel_steer_rule(tof_rule_type); 1334 } else { 1335 /* 1336 * non-tunnel group translation uses standard method for 1337 * root group only: attr.group == 0 1338 */ 1339 verdict = !attr->group; 1340 } 1341 1342 return verdict; 1343 } 1344 1345 /** 1346 * Get DV flow aso meter by index. 1347 * 1348 * @param[in] dev 1349 * Pointer to the Ethernet device structure. 1350 * @param[in] idx 1351 * mlx5 flow aso meter index in the container. 1352 * @param[out] ppool 1353 * mlx5 flow aso meter pool in the container, 1354 * 1355 * @return 1356 * Pointer to the aso meter, NULL otherwise. 1357 */ 1358 static inline struct mlx5_aso_mtr * 1359 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) 1360 { 1361 struct mlx5_aso_mtr_pool *pool; 1362 struct mlx5_aso_mtr_pools_mng *pools_mng = 1363 &priv->sh->mtrmng->pools_mng; 1364 1365 /* Decrease to original index. */ 1366 idx--; 1367 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n); 1368 rte_rwlock_read_lock(&pools_mng->resize_mtrwl); 1369 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL]; 1370 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl); 1371 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; 1372 } 1373 1374 static __rte_always_inline const struct rte_flow_item * 1375 mlx5_find_end_item(const struct rte_flow_item *item) 1376 { 1377 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++); 1378 return item; 1379 } 1380 1381 static __rte_always_inline bool 1382 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) 1383 { 1384 struct rte_flow_item_integrity test = *item; 1385 test.l3_ok = 0; 1386 test.l4_ok = 0; 1387 test.ipv4_csum_ok = 0; 1388 test.l4_csum_ok = 0; 1389 return (test.value == 0); 1390 } 1391 1392 /* 1393 * Get ASO CT action by device and index. 1394 * 1395 * @param[in] dev 1396 * Pointer to the Ethernet device structure. 1397 * @param[in] idx 1398 * Index to the ASO CT action. 1399 * 1400 * @return 1401 * The specified ASO CT action pointer. 1402 */ 1403 static inline struct mlx5_aso_ct_action * 1404 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx) 1405 { 1406 struct mlx5_priv *priv = dev->data->dev_private; 1407 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng; 1408 struct mlx5_aso_ct_pool *pool; 1409 1410 idx--; 1411 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n); 1412 /* Bit operation AND could be used. */ 1413 rte_rwlock_read_lock(&mng->resize_rwl); 1414 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL]; 1415 rte_rwlock_read_unlock(&mng->resize_rwl); 1416 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL]; 1417 } 1418 1419 /* 1420 * Get ASO CT action by owner & index. 1421 * 1422 * @param[in] dev 1423 * Pointer to the Ethernet device structure. 1424 * @param[in] idx 1425 * Index to the ASO CT action and owner port combination. 1426 * 1427 * @return 1428 * The specified ASO CT action pointer. 1429 */ 1430 static inline struct mlx5_aso_ct_action * 1431 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx) 1432 { 1433 struct mlx5_priv *priv = dev->data->dev_private; 1434 struct mlx5_aso_ct_action *ct; 1435 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx); 1436 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx); 1437 1438 if (owner == PORT_ID(priv)) { 1439 ct = flow_aso_ct_get_by_dev_idx(dev, idx); 1440 } else { 1441 struct rte_eth_dev *owndev = &rte_eth_devices[owner]; 1442 1443 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS); 1444 if (dev->data->dev_started != 1) 1445 return NULL; 1446 ct = flow_aso_ct_get_by_dev_idx(owndev, idx); 1447 if (ct->peer != PORT_ID(priv)) 1448 return NULL; 1449 } 1450 return ct; 1451 } 1452 1453 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1454 const struct mlx5_flow_tunnel *tunnel, 1455 uint32_t group, uint32_t *table, 1456 const struct flow_grp_info *flags, 1457 struct rte_flow_error *error); 1458 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1459 int tunnel, uint64_t layer_types, 1460 uint64_t hash_fields); 1461 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1462 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1463 uint32_t subpriority); 1464 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1465 const struct rte_flow_attr *attr); 1466 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1467 const struct rte_flow_attr *attr, 1468 uint32_t subpriority, bool external); 1469 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1470 enum mlx5_feature_name feature, 1471 uint32_t id, 1472 struct rte_flow_error *error); 1473 const struct rte_flow_action *mlx5_flow_find_action 1474 (const struct rte_flow_action *actions, 1475 enum rte_flow_action_type action); 1476 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1477 const struct rte_flow_action *action, 1478 struct rte_flow_error *error); 1479 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1480 const struct rte_flow_attr *attr, 1481 struct rte_flow_error *error); 1482 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1483 const struct rte_flow_attr *attr, 1484 struct rte_flow_error *error); 1485 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1486 const struct rte_flow_attr *attr, 1487 struct rte_flow_error *error); 1488 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1489 uint64_t action_flags, 1490 const struct rte_flow_attr *attr, 1491 struct rte_flow_error *error); 1492 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1493 uint64_t action_flags, 1494 struct rte_eth_dev *dev, 1495 const struct rte_flow_attr *attr, 1496 struct rte_flow_error *error); 1497 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1498 uint64_t action_flags, 1499 struct rte_eth_dev *dev, 1500 const struct rte_flow_attr *attr, 1501 uint64_t item_flags, 1502 struct rte_flow_error *error); 1503 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1504 const struct rte_flow_attr *attr, 1505 struct rte_flow_error *error); 1506 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1507 const struct rte_flow_attr *attributes, 1508 struct rte_flow_error *error); 1509 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1510 const uint8_t *mask, 1511 const uint8_t *nic_mask, 1512 unsigned int size, 1513 bool range_accepted, 1514 struct rte_flow_error *error); 1515 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1516 uint64_t item_flags, bool ext_vlan_sup, 1517 struct rte_flow_error *error); 1518 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1519 uint64_t item_flags, 1520 uint8_t target_protocol, 1521 struct rte_flow_error *error); 1522 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1523 uint64_t item_flags, 1524 const struct rte_flow_item *gre_item, 1525 struct rte_flow_error *error); 1526 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1527 uint64_t item_flags, 1528 uint64_t last_item, 1529 uint16_t ether_type, 1530 const struct rte_flow_item_ipv4 *acc_mask, 1531 bool range_accepted, 1532 struct rte_flow_error *error); 1533 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1534 uint64_t item_flags, 1535 uint64_t last_item, 1536 uint16_t ether_type, 1537 const struct rte_flow_item_ipv6 *acc_mask, 1538 struct rte_flow_error *error); 1539 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1540 const struct rte_flow_item *item, 1541 uint64_t item_flags, 1542 uint64_t prev_layer, 1543 struct rte_flow_error *error); 1544 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1545 uint64_t item_flags, 1546 uint8_t target_protocol, 1547 const struct rte_flow_item_tcp *flow_mask, 1548 struct rte_flow_error *error); 1549 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1550 uint64_t item_flags, 1551 uint8_t target_protocol, 1552 struct rte_flow_error *error); 1553 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1554 uint64_t item_flags, 1555 struct rte_eth_dev *dev, 1556 struct rte_flow_error *error); 1557 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 1558 uint16_t udp_dport, 1559 const struct rte_flow_item *item, 1560 uint64_t item_flags, 1561 const struct rte_flow_attr *attr, 1562 struct rte_flow_error *error); 1563 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1564 uint64_t item_flags, 1565 struct rte_eth_dev *dev, 1566 struct rte_flow_error *error); 1567 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1568 uint64_t item_flags, 1569 uint8_t target_protocol, 1570 struct rte_flow_error *error); 1571 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1572 uint64_t item_flags, 1573 uint8_t target_protocol, 1574 struct rte_flow_error *error); 1575 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1576 uint64_t item_flags, 1577 uint8_t target_protocol, 1578 struct rte_flow_error *error); 1579 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1580 uint64_t item_flags, 1581 struct rte_eth_dev *dev, 1582 struct rte_flow_error *error); 1583 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1584 uint64_t last_item, 1585 const struct rte_flow_item *geneve_item, 1586 struct rte_eth_dev *dev, 1587 struct rte_flow_error *error); 1588 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1589 uint64_t item_flags, 1590 uint64_t last_item, 1591 uint16_t ether_type, 1592 const struct rte_flow_item_ecpri *acc_mask, 1593 struct rte_flow_error *error); 1594 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 1595 struct mlx5_flow_meter_info *fm, 1596 uint32_t mtr_idx, 1597 uint8_t domain_bitmap); 1598 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1599 struct mlx5_flow_meter_info *fm); 1600 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev); 1601 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare 1602 (struct rte_eth_dev *dev, 1603 struct mlx5_flow_meter_policy *mtr_policy, 1604 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1605 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 1606 struct mlx5_flow_meter_policy *mtr_policy); 1607 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1608 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev); 1609 int mlx5_action_handle_attach(struct rte_eth_dev *dev); 1610 int mlx5_action_handle_detach(struct rte_eth_dev *dev); 1611 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1612 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1613 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1614 1615 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx); 1616 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1617 void *cb_ctx); 1618 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1619 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx, 1620 struct mlx5_list_entry *oentry, 1621 void *entry_ctx); 1622 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1623 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1624 uint32_t table_level, uint8_t egress, uint8_t transfer, 1625 bool external, const struct mlx5_flow_tunnel *tunnel, 1626 uint32_t group_id, uint8_t dummy, 1627 uint32_t table_id, struct rte_flow_error *error); 1628 1629 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx); 1630 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1631 void *cb_ctx); 1632 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1633 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx, 1634 struct mlx5_list_entry *oentry, 1635 void *cb_ctx); 1636 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1637 1638 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1639 void *cb_ctx); 1640 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx); 1641 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1642 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx, 1643 struct mlx5_list_entry *oentry, 1644 void *ctx); 1645 void flow_dv_modify_clone_free_cb(void *tool_ctx, 1646 struct mlx5_list_entry *entry); 1647 1648 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx); 1649 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1650 void *cb_ctx); 1651 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1652 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx, 1653 struct mlx5_list_entry *entry, 1654 void *ctx); 1655 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1656 1657 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1658 void *cb_ctx); 1659 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx, 1660 void *cb_ctx); 1661 void flow_dv_encap_decap_remove_cb(void *tool_ctx, 1662 struct mlx5_list_entry *entry); 1663 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx, 1664 struct mlx5_list_entry *entry, 1665 void *cb_ctx); 1666 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx, 1667 struct mlx5_list_entry *entry); 1668 1669 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1670 void *ctx); 1671 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx); 1672 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1673 1674 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1675 void *cb_ctx); 1676 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx); 1677 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1678 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx, 1679 struct mlx5_list_entry *entry, void *cb_ctx); 1680 void flow_dv_port_id_clone_free_cb(void *tool_ctx, 1681 struct mlx5_list_entry *entry); 1682 1683 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1684 void *cb_ctx); 1685 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx, 1686 void *cb_ctx); 1687 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1688 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx, 1689 struct mlx5_list_entry *entry, void *cb_ctx); 1690 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx, 1691 struct mlx5_list_entry *entry); 1692 1693 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1694 void *cb_ctx); 1695 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx); 1696 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1697 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx, 1698 struct mlx5_list_entry *entry, void *cb_ctx); 1699 void flow_dv_sample_clone_free_cb(void *tool_ctx, 1700 struct mlx5_list_entry *entry); 1701 1702 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1703 void *cb_ctx); 1704 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx, 1705 void *cb_ctx); 1706 void flow_dv_dest_array_remove_cb(void *tool_ctx, 1707 struct mlx5_list_entry *entry); 1708 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx, 1709 struct mlx5_list_entry *entry, void *cb_ctx); 1710 void flow_dv_dest_array_clone_free_cb(void *tool_ctx, 1711 struct mlx5_list_entry *entry); 1712 int flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx, 1713 void **action, struct rte_flow_error *error); 1714 int 1715 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data, 1716 struct rte_flow_error *error); 1717 1718 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1719 uint32_t age_idx); 1720 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1721 const struct rte_flow_item *item, 1722 struct rte_flow_error *error); 1723 void flow_release_workspace(void *data); 1724 int mlx5_flow_os_init_workspace_once(void); 1725 void *mlx5_flow_os_get_specific_workspace(void); 1726 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1727 void mlx5_flow_os_release_workspace(void); 1728 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev); 1729 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx); 1730 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 1731 const struct rte_flow_action *actions[RTE_COLORS], 1732 struct rte_flow_attr *attr, 1733 bool *is_rss, 1734 uint8_t *domain_bitmap, 1735 uint8_t *policy_mode, 1736 struct rte_mtr_error *error); 1737 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 1738 struct mlx5_flow_meter_policy *mtr_policy); 1739 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 1740 struct mlx5_flow_meter_policy *mtr_policy, 1741 const struct rte_flow_action *actions[RTE_COLORS], 1742 struct rte_mtr_error *error); 1743 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 1744 struct mlx5_flow_meter_policy *mtr_policy); 1745 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 1746 struct mlx5_flow_meter_policy *mtr_policy); 1747 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev); 1748 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev); 1749 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1750 struct mlx5_flow_handle *dev_handle); 1751 const struct mlx5_flow_tunnel * 1752 mlx5_get_tof(const struct rte_flow_item *items, 1753 const struct rte_flow_action *actions, 1754 enum mlx5_tof_rule_type *rule_type); 1755 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1756