1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 #include <rte_alarm.h> 15 #include <rte_mtr.h> 16 17 #include <mlx5_glue.h> 18 #include <mlx5_prm.h> 19 20 #include "mlx5.h" 21 22 /* Private rte flow items. */ 23 enum mlx5_rte_flow_item_type { 24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 25 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 29 }; 30 31 /* Private (internal) rte flow actions. */ 32 enum mlx5_rte_flow_action_type { 33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 35 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 38 MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS, 39 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 40 }; 41 42 /* Matches on selected register. */ 43 struct mlx5_rte_flow_item_tag { 44 enum modify_reg id; 45 uint32_t data; 46 }; 47 48 /* Modify selected register. */ 49 struct mlx5_rte_flow_action_set_tag { 50 enum modify_reg id; 51 uint32_t data; 52 }; 53 54 struct mlx5_flow_action_copy_mreg { 55 enum modify_reg dst; 56 enum modify_reg src; 57 }; 58 59 /* Matches on source queue. */ 60 struct mlx5_rte_flow_item_tx_queue { 61 uint32_t queue; 62 }; 63 64 /* Feature name to allocate metadata register. */ 65 enum mlx5_feature_name { 66 MLX5_HAIRPIN_RX, 67 MLX5_HAIRPIN_TX, 68 MLX5_METADATA_RX, 69 MLX5_METADATA_TX, 70 MLX5_METADATA_FDB, 71 MLX5_FLOW_MARK, 72 MLX5_APP_TAG, 73 MLX5_COPY_MARK, 74 MLX5_MTR_COLOR, 75 MLX5_MTR_SFX, 76 }; 77 78 /* Default queue number. */ 79 #define MLX5_RSSQ_DEFAULT_NUM 16 80 81 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 82 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 83 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 84 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 85 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 86 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 87 88 /* Pattern inner Layer bits. */ 89 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 90 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 91 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 92 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 93 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 94 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 95 96 /* Pattern tunnel Layer bits. */ 97 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 98 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 99 #define MLX5_FLOW_LAYER_GRE (1u << 14) 100 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 101 /* List of tunnel Layer bits continued below. */ 102 103 /* General pattern items bits. */ 104 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 105 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 106 #define MLX5_FLOW_ITEM_TAG (1u << 18) 107 #define MLX5_FLOW_ITEM_MARK (1u << 19) 108 109 /* Pattern MISC bits. */ 110 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 111 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 112 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 113 114 /* Pattern tunnel Layer bits (continued). */ 115 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 116 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 117 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 118 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 119 120 /* Queue items. */ 121 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 122 123 /* Pattern tunnel Layer bits (continued). */ 124 #define MLX5_FLOW_LAYER_GTP (1u << 28) 125 126 /* Pattern eCPRI Layer bit. */ 127 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 128 129 /* IPv6 Fragment Extension Header bit. */ 130 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 131 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 132 133 /* Outer Masks. */ 134 #define MLX5_FLOW_LAYER_OUTER_L3 \ 135 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 136 #define MLX5_FLOW_LAYER_OUTER_L4 \ 137 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 138 #define MLX5_FLOW_LAYER_OUTER \ 139 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 140 MLX5_FLOW_LAYER_OUTER_L4) 141 142 /* Tunnel Masks. */ 143 #define MLX5_FLOW_LAYER_TUNNEL \ 144 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 145 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 146 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 147 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 148 149 /* Inner Masks. */ 150 #define MLX5_FLOW_LAYER_INNER_L3 \ 151 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 152 #define MLX5_FLOW_LAYER_INNER_L4 \ 153 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 154 #define MLX5_FLOW_LAYER_INNER \ 155 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 156 MLX5_FLOW_LAYER_INNER_L4) 157 158 /* Layer Masks. */ 159 #define MLX5_FLOW_LAYER_L2 \ 160 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 161 #define MLX5_FLOW_LAYER_L3_IPV4 \ 162 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 163 #define MLX5_FLOW_LAYER_L3_IPV6 \ 164 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 165 #define MLX5_FLOW_LAYER_L3 \ 166 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 167 #define MLX5_FLOW_LAYER_L4 \ 168 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 169 170 /* Actions */ 171 #define MLX5_FLOW_ACTION_DROP (1u << 0) 172 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 173 #define MLX5_FLOW_ACTION_RSS (1u << 2) 174 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 175 #define MLX5_FLOW_ACTION_MARK (1u << 4) 176 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 177 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 178 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 179 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 180 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 181 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 182 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 183 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 184 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 185 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 186 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 187 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 188 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 189 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 190 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 191 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 192 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 193 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 194 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 195 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 196 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 197 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 198 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 199 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 200 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 201 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 202 #define MLX5_FLOW_ACTION_METER (1ull << 31) 203 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 204 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 205 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 206 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 207 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 208 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 209 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 210 211 #define MLX5_FLOW_FATE_ACTIONS \ 212 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 213 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 214 MLX5_FLOW_ACTION_DEFAULT_MISS) 215 216 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 217 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 218 MLX5_FLOW_ACTION_JUMP) 219 220 221 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 222 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 223 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 224 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 225 MLX5_FLOW_ACTION_SET_TP_SRC | \ 226 MLX5_FLOW_ACTION_SET_TP_DST | \ 227 MLX5_FLOW_ACTION_SET_TTL | \ 228 MLX5_FLOW_ACTION_DEC_TTL | \ 229 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 230 MLX5_FLOW_ACTION_SET_MAC_DST | \ 231 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 232 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 233 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 234 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 235 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 236 MLX5_FLOW_ACTION_SET_TAG | \ 237 MLX5_FLOW_ACTION_MARK_EXT | \ 238 MLX5_FLOW_ACTION_SET_META | \ 239 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 240 MLX5_FLOW_ACTION_SET_IPV6_DSCP) 241 242 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 243 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 244 245 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 246 247 #ifndef IPPROTO_MPLS 248 #define IPPROTO_MPLS 137 249 #endif 250 251 /* UDP port number for MPLS */ 252 #define MLX5_UDP_PORT_MPLS 6635 253 254 /* UDP port numbers for VxLAN. */ 255 #define MLX5_UDP_PORT_VXLAN 4789 256 #define MLX5_UDP_PORT_VXLAN_GPE 4790 257 258 /* UDP port numbers for GENEVE. */ 259 #define MLX5_UDP_PORT_GENEVE 6081 260 261 /* Priority reserved for default flows. */ 262 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 263 264 /* 265 * Number of sub priorities. 266 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 267 * matching on the NIC (firmware dependent) L4 most have the higher priority 268 * followed by L3 and ending with L2. 269 */ 270 #define MLX5_PRIORITY_MAP_L2 2 271 #define MLX5_PRIORITY_MAP_L3 1 272 #define MLX5_PRIORITY_MAP_L4 0 273 #define MLX5_PRIORITY_MAP_MAX 3 274 275 /* Valid layer type for IPV4 RSS. */ 276 #define MLX5_IPV4_LAYER_TYPES \ 277 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 278 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 279 ETH_RSS_NONFRAG_IPV4_OTHER) 280 281 /* IBV hash source bits for IPV4. */ 282 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 283 284 /* Valid layer type for IPV6 RSS. */ 285 #define MLX5_IPV6_LAYER_TYPES \ 286 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 287 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 288 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 289 290 /* IBV hash source bits for IPV6. */ 291 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 292 293 /* IBV hash bits for L3 SRC. */ 294 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 295 296 /* IBV hash bits for L3 DST. */ 297 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 298 299 /* IBV hash bits for TCP. */ 300 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 301 IBV_RX_HASH_DST_PORT_TCP) 302 303 /* IBV hash bits for UDP. */ 304 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 305 IBV_RX_HASH_DST_PORT_UDP) 306 307 /* IBV hash bits for L4 SRC. */ 308 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 309 IBV_RX_HASH_SRC_PORT_UDP) 310 311 /* IBV hash bits for L4 DST. */ 312 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 313 IBV_RX_HASH_DST_PORT_UDP) 314 315 /* Geneve header first 16Bit */ 316 #define MLX5_GENEVE_VER_MASK 0x3 317 #define MLX5_GENEVE_VER_SHIFT 14 318 #define MLX5_GENEVE_VER_VAL(a) \ 319 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 320 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 321 #define MLX5_GENEVE_OPTLEN_SHIFT 7 322 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 323 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 324 #define MLX5_GENEVE_OAMF_MASK 0x1 325 #define MLX5_GENEVE_OAMF_SHIFT 7 326 #define MLX5_GENEVE_OAMF_VAL(a) \ 327 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 328 #define MLX5_GENEVE_CRITO_MASK 0x1 329 #define MLX5_GENEVE_CRITO_SHIFT 6 330 #define MLX5_GENEVE_CRITO_VAL(a) \ 331 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 332 #define MLX5_GENEVE_RSVD_MASK 0x3F 333 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 334 /* 335 * The length of the Geneve options fields, expressed in four byte multiples, 336 * not including the eight byte fixed tunnel. 337 */ 338 #define MLX5_GENEVE_OPT_LEN_0 14 339 #define MLX5_GENEVE_OPT_LEN_1 63 340 341 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \ 342 sizeof(struct rte_flow_item_ipv4)) 343 344 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 345 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 346 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 347 348 /* Specific item's fields can accept a range of values (using spec and last). */ 349 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 350 #define MLX5_ITEM_RANGE_ACCEPTED true 351 352 /* Software header modify action numbers of a flow. */ 353 #define MLX5_ACT_NUM_MDF_IPV4 1 354 #define MLX5_ACT_NUM_MDF_IPV6 4 355 #define MLX5_ACT_NUM_MDF_MAC 2 356 #define MLX5_ACT_NUM_MDF_VID 1 357 #define MLX5_ACT_NUM_MDF_PORT 2 358 #define MLX5_ACT_NUM_MDF_TTL 1 359 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 360 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 361 #define MLX5_ACT_NUM_MDF_TCPACK 1 362 #define MLX5_ACT_NUM_SET_REG 1 363 #define MLX5_ACT_NUM_SET_TAG 1 364 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 365 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 366 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 367 #define MLX5_ACT_NUM_SET_DSCP 1 368 369 enum mlx5_flow_drv_type { 370 MLX5_FLOW_TYPE_MIN, 371 MLX5_FLOW_TYPE_DV, 372 MLX5_FLOW_TYPE_VERBS, 373 MLX5_FLOW_TYPE_MAX, 374 }; 375 376 /* Fate action type. */ 377 enum mlx5_flow_fate_type { 378 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 379 MLX5_FLOW_FATE_QUEUE, 380 MLX5_FLOW_FATE_JUMP, 381 MLX5_FLOW_FATE_PORT_ID, 382 MLX5_FLOW_FATE_DROP, 383 MLX5_FLOW_FATE_DEFAULT_MISS, 384 MLX5_FLOW_FATE_MAX, 385 }; 386 387 /* Matcher PRM representation */ 388 struct mlx5_flow_dv_match_params { 389 size_t size; 390 /**< Size of match value. Do NOT split size and key! */ 391 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 392 /**< Matcher value. This value is used as the mask or as a key. */ 393 }; 394 395 /* Matcher structure. */ 396 struct mlx5_flow_dv_matcher { 397 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 398 struct mlx5_flow_tbl_resource *tbl; 399 /**< Pointer to the table(group) the matcher associated with. */ 400 void *matcher_object; /**< Pointer to DV matcher */ 401 uint16_t crc; /**< CRC of key. */ 402 uint16_t priority; /**< Priority of matcher. */ 403 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 404 }; 405 406 #define MLX5_ENCAP_MAX_LEN 132 407 408 /* Encap/decap resource key of the hash organization. */ 409 union mlx5_flow_encap_decap_key { 410 struct { 411 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 412 uint32_t refmt_type:8; /**< Header reformat type. */ 413 uint32_t buf_size:8; /**< Encap buf size. */ 414 uint32_t table_level:8; /**< Root table or not. */ 415 uint32_t cksum; /**< Encap buf check sum. */ 416 }; 417 uint64_t v64; /**< full 64bits value of key */ 418 }; 419 420 /* Encap/decap resource structure. */ 421 struct mlx5_flow_dv_encap_decap_resource { 422 struct mlx5_hlist_entry entry; 423 /* Pointer to next element. */ 424 uint32_t refcnt; /**< Reference counter. */ 425 void *action; 426 /**< Encap/decap action object. */ 427 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 428 size_t size; 429 uint8_t reformat_type; 430 uint8_t ft_type; 431 uint64_t flags; /**< Flags for RDMA API. */ 432 uint32_t idx; /**< Index for the index memory pool. */ 433 }; 434 435 /* Tag resource structure. */ 436 struct mlx5_flow_dv_tag_resource { 437 struct mlx5_hlist_entry entry; 438 /**< hash list entry for tag resource, tag value as the key. */ 439 void *action; 440 /**< Tag action object. */ 441 uint32_t refcnt; /**< Reference counter. */ 442 uint32_t idx; /**< Index for the index memory pool. */ 443 }; 444 445 /* 446 * Number of modification commands. 447 * The maximal actions amount in FW is some constant, and it is 16 in the 448 * latest releases. In some old releases, it will be limited to 8. 449 * Since there is no interface to query the capacity, the maximal value should 450 * be used to allow PMD to create the flow. The validation will be done in the 451 * lower driver layer or FW. A failure will be returned if exceeds the maximal 452 * supported actions number on the root table. 453 * On non-root tables, there is no limitation, but 32 is enough right now. 454 */ 455 #define MLX5_MAX_MODIFY_NUM 32 456 #define MLX5_ROOT_TBL_MODIFY_NUM 16 457 458 /* Modify resource structure */ 459 struct mlx5_flow_dv_modify_hdr_resource { 460 struct mlx5_hlist_entry entry; 461 void *action; /**< Modify header action object. */ 462 /* Key area for hash list matching: */ 463 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 464 uint32_t actions_num; /**< Number of modification actions. */ 465 uint64_t flags; /**< Flags for RDMA API. */ 466 struct mlx5_modification_cmd actions[]; 467 /**< Modification actions. */ 468 }; 469 470 /* Modify resource key of the hash organization. */ 471 union mlx5_flow_modify_hdr_key { 472 struct { 473 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 474 uint32_t actions_num:5; /**< Number of modification actions. */ 475 uint32_t group:19; /**< Flow group id. */ 476 uint32_t cksum; /**< Actions check sum. */ 477 }; 478 uint64_t v64; /**< full 64bits value of key */ 479 }; 480 481 /* Jump action resource structure. */ 482 struct mlx5_flow_dv_jump_tbl_resource { 483 void *action; /**< Pointer to the rdma core action. */ 484 }; 485 486 /* Port ID resource structure. */ 487 struct mlx5_flow_dv_port_id_action_resource { 488 struct mlx5_cache_entry entry; 489 void *action; /**< Action object. */ 490 uint32_t port_id; /**< Port ID value. */ 491 uint32_t idx; /**< Indexed pool memory index. */ 492 }; 493 494 /* Push VLAN action resource structure */ 495 struct mlx5_flow_dv_push_vlan_action_resource { 496 struct mlx5_cache_entry entry; /* Cache entry. */ 497 void *action; /**< Action object. */ 498 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 499 rte_be32_t vlan_tag; /**< VLAN tag value. */ 500 uint32_t idx; /**< Indexed pool memory index. */ 501 }; 502 503 /* Metadata register copy table entry. */ 504 struct mlx5_flow_mreg_copy_resource { 505 /* 506 * Hash list entry for copy table. 507 * - Key is 32/64-bit MARK action ID. 508 * - MUST be the first entry. 509 */ 510 struct mlx5_hlist_entry hlist_ent; 511 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 512 /* List entry for device flows. */ 513 uint32_t idx; 514 uint32_t rix_flow; /* Built flow for copy. */ 515 }; 516 517 /* Table tunnel parameter. */ 518 struct mlx5_flow_tbl_tunnel_prm { 519 const struct mlx5_flow_tunnel *tunnel; 520 uint32_t group_id; 521 bool external; 522 }; 523 524 /* Table data structure of the hash organization. */ 525 struct mlx5_flow_tbl_data_entry { 526 struct mlx5_hlist_entry entry; 527 /**< hash list entry, 64-bits key inside. */ 528 struct mlx5_flow_tbl_resource tbl; 529 /**< flow table resource. */ 530 struct mlx5_cache_list matchers; 531 /**< matchers' header associated with the flow table. */ 532 struct mlx5_flow_dv_jump_tbl_resource jump; 533 /**< jump resource, at most one for each table created. */ 534 uint32_t idx; /**< index for the indexed mempool. */ 535 /**< tunnel offload */ 536 const struct mlx5_flow_tunnel *tunnel; 537 uint32_t group_id; 538 bool external; 539 bool tunnel_offload; /* Tunnel offlod table or not. */ 540 bool is_egress; /**< Egress table. */ 541 }; 542 543 /* Sub rdma-core actions list. */ 544 struct mlx5_flow_sub_actions_list { 545 uint32_t actions_num; /**< Number of sample actions. */ 546 uint64_t action_flags; 547 void *dr_queue_action; 548 void *dr_tag_action; 549 void *dr_cnt_action; 550 void *dr_port_id_action; 551 void *dr_encap_action; 552 }; 553 554 /* Sample sub-actions resource list. */ 555 struct mlx5_flow_sub_actions_idx { 556 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 557 uint32_t rix_tag; /**< Index to the tag action. */ 558 uint32_t cnt; 559 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 560 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 561 }; 562 563 /* Sample action resource structure. */ 564 struct mlx5_flow_dv_sample_resource { 565 struct mlx5_cache_entry entry; /**< Cache entry. */ 566 union { 567 void *verbs_action; /**< Verbs sample action object. */ 568 void **sub_actions; /**< Sample sub-action array. */ 569 }; 570 uint32_t idx; /** Sample object index. */ 571 uint8_t ft_type; /** Flow Table Type */ 572 uint32_t ft_id; /** Flow Table Level */ 573 uint32_t ratio; /** Sample Ratio */ 574 uint64_t set_action; /** Restore reg_c0 value */ 575 void *normal_path_tbl; /** Flow Table pointer */ 576 void *default_miss; /** default_miss dr_action. */ 577 struct mlx5_flow_sub_actions_idx sample_idx; 578 /**< Action index resources. */ 579 struct mlx5_flow_sub_actions_list sample_act; 580 /**< Action resources. */ 581 }; 582 583 #define MLX5_MAX_DEST_NUM 2 584 585 /* Destination array action resource structure. */ 586 struct mlx5_flow_dv_dest_array_resource { 587 struct mlx5_cache_entry entry; /**< Cache entry. */ 588 uint32_t idx; /** Destination array action object index. */ 589 uint8_t ft_type; /** Flow Table Type */ 590 uint8_t num_of_dest; /**< Number of destination actions. */ 591 void *action; /**< Pointer to the rdma core action. */ 592 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 593 /**< Action index resources. */ 594 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 595 /**< Action resources. */ 596 }; 597 598 /* Verbs specification header. */ 599 struct ibv_spec_header { 600 enum ibv_flow_spec_type type; 601 uint16_t size; 602 }; 603 604 /* PMD flow priority for tunnel */ 605 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 606 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 607 608 609 /** Device flow handle structure for DV mode only. */ 610 struct mlx5_flow_handle_dv { 611 /* Flow DV api: */ 612 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 613 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 614 /**< Pointer to modify header resource in cache. */ 615 uint32_t rix_encap_decap; 616 /**< Index to encap/decap resource in cache. */ 617 uint32_t rix_push_vlan; 618 /**< Index to push VLAN action resource in cache. */ 619 uint32_t rix_tag; 620 /**< Index to the tag action. */ 621 uint32_t rix_sample; 622 /**< Index to sample action resource in cache. */ 623 uint32_t rix_dest_array; 624 /**< Index to destination array resource in cache. */ 625 } __rte_packed; 626 627 /** Device flow handle structure: used both for creating & destroying. */ 628 struct mlx5_flow_handle { 629 SILIST_ENTRY(uint32_t)next; 630 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 631 /**< Index to next device flow handle. */ 632 uint64_t layers; 633 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 634 void *drv_flow; /**< pointer to driver flow object. */ 635 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 636 uint32_t mark:1; /**< Metadate rxq mark flag. */ 637 uint32_t fate_action:3; /**< Fate action type. */ 638 union { 639 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 640 uint32_t rix_jump; /**< Index to the jump action resource. */ 641 uint32_t rix_port_id_action; 642 /**< Index to port ID action resource. */ 643 uint32_t rix_fate; 644 /**< Generic value indicates the fate action. */ 645 uint32_t rix_default_fate; 646 /**< Indicates default miss fate action. */ 647 }; 648 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 649 struct mlx5_flow_handle_dv dvh; 650 #endif 651 } __rte_packed; 652 653 /* 654 * Size for Verbs device flow handle structure only. Do not use the DV only 655 * structure in Verbs. No DV flows attributes will be accessed. 656 * Macro offsetof() could also be used here. 657 */ 658 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 659 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 660 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 661 #else 662 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 663 #endif 664 665 /* 666 * Max number of actions per DV flow. 667 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 668 * in rdma-core file providers/mlx5/verbs.c. 669 */ 670 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 671 672 /** Device flow structure only for DV flow creation. */ 673 struct mlx5_flow_dv_workspace { 674 uint32_t group; /**< The group index. */ 675 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 676 int actions_n; /**< number of actions. */ 677 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 678 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 679 /**< Pointer to encap/decap resource in cache. */ 680 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 681 /**< Pointer to push VLAN action resource in cache. */ 682 struct mlx5_flow_dv_tag_resource *tag_resource; 683 /**< pointer to the tag action. */ 684 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 685 /**< Pointer to port ID action resource. */ 686 struct mlx5_flow_dv_jump_tbl_resource *jump; 687 /**< Pointer to the jump action resource. */ 688 struct mlx5_flow_dv_match_params value; 689 /**< Holds the value that the packet is compared to. */ 690 struct mlx5_flow_dv_sample_resource *sample_res; 691 /**< Pointer to the sample action resource. */ 692 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 693 /**< Pointer to the destination array resource. */ 694 }; 695 696 /* 697 * Maximal Verbs flow specifications & actions size. 698 * Some elements are mutually exclusive, but enough space should be allocated. 699 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 700 * 2. One tunnel header (exception: GRE + MPLS), 701 * SPEC length: GRE == tunnel. 702 * Actions: 1. 1 Mark OR Flag. 703 * 2. 1 Drop (if any). 704 * 3. No limitation for counters, but it makes no sense to support too 705 * many counters in a single device flow. 706 */ 707 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 708 #define MLX5_VERBS_MAX_SPEC_SIZE \ 709 ( \ 710 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 711 sizeof(struct ibv_flow_spec_ipv6) + \ 712 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 713 sizeof(struct ibv_flow_spec_gre) + \ 714 sizeof(struct ibv_flow_spec_mpls)) \ 715 ) 716 #else 717 #define MLX5_VERBS_MAX_SPEC_SIZE \ 718 ( \ 719 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 720 sizeof(struct ibv_flow_spec_ipv6) + \ 721 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 722 sizeof(struct ibv_flow_spec_tunnel)) \ 723 ) 724 #endif 725 726 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 727 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 728 #define MLX5_VERBS_MAX_ACT_SIZE \ 729 ( \ 730 sizeof(struct ibv_flow_spec_action_tag) + \ 731 sizeof(struct ibv_flow_spec_action_drop) + \ 732 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 733 ) 734 #else 735 #define MLX5_VERBS_MAX_ACT_SIZE \ 736 ( \ 737 sizeof(struct ibv_flow_spec_action_tag) + \ 738 sizeof(struct ibv_flow_spec_action_drop) \ 739 ) 740 #endif 741 742 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 743 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 744 745 /** Device flow structure only for Verbs flow creation. */ 746 struct mlx5_flow_verbs_workspace { 747 unsigned int size; /**< Size of the attribute. */ 748 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 749 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 750 /**< Specifications & actions buffer of verbs flow. */ 751 }; 752 753 /** Maximal number of device sub-flows supported. */ 754 #define MLX5_NUM_MAX_DEV_FLOWS 32 755 756 /** Device flow structure. */ 757 struct mlx5_flow { 758 struct rte_flow *flow; /**< Pointer to the main flow. */ 759 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 760 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 761 uint64_t act_flags; 762 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 763 bool external; /**< true if the flow is created external to PMD. */ 764 uint8_t ingress; /**< 1 if the flow is ingress. */ 765 union { 766 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 767 struct mlx5_flow_dv_workspace dv; 768 #endif 769 struct mlx5_flow_verbs_workspace verbs; 770 }; 771 struct mlx5_flow_handle *handle; 772 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 773 const struct mlx5_flow_tunnel *tunnel; 774 }; 775 776 /* Flow meter state. */ 777 #define MLX5_FLOW_METER_DISABLE 0 778 #define MLX5_FLOW_METER_ENABLE 1 779 780 #define MLX5_MAN_WIDTH 8 781 /* Modify this value if enum rte_mtr_color changes. */ 782 #define RTE_MTR_DROPPED RTE_COLORS 783 784 /* Meter policer statistics */ 785 struct mlx5_flow_policer_stats { 786 uint32_t cnt[RTE_COLORS + 1]; 787 /**< Color counter, extra for drop. */ 788 uint64_t stats_mask; 789 /**< Statistics mask for the colors. */ 790 }; 791 792 /* Meter table structure. */ 793 struct mlx5_meter_domain_info { 794 struct mlx5_flow_tbl_resource *tbl; 795 /**< Meter table. */ 796 struct mlx5_flow_tbl_resource *sfx_tbl; 797 /**< Meter suffix table. */ 798 void *any_matcher; 799 /**< Meter color not match default criteria. */ 800 void *color_matcher; 801 /**< Meter color match criteria. */ 802 void *jump_actn; 803 /**< Meter match action. */ 804 void *policer_rules[RTE_MTR_DROPPED + 1]; 805 /**< Meter policer for the match. */ 806 }; 807 808 /* Meter table set for TX RX FDB. */ 809 struct mlx5_meter_domains_infos { 810 uint32_t ref_cnt; 811 /**< Table user count. */ 812 struct mlx5_meter_domain_info egress; 813 /**< TX meter table. */ 814 struct mlx5_meter_domain_info ingress; 815 /**< RX meter table. */ 816 struct mlx5_meter_domain_info transfer; 817 /**< FDB meter table. */ 818 void *drop_actn; 819 /**< Drop action as not matched. */ 820 void *count_actns[RTE_MTR_DROPPED + 1]; 821 /**< Counters for match and unmatched statistics. */ 822 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 823 /**< Flow meter parameter. */ 824 size_t fmp_size; 825 /**< Flow meter parameter size. */ 826 void *meter_action; 827 /**< Flow meter action. */ 828 }; 829 830 /* Meter parameter structure. */ 831 struct mlx5_flow_meter { 832 TAILQ_ENTRY(mlx5_flow_meter) next; 833 /**< Pointer to the next flow meter structure. */ 834 uint32_t idx; /* Index to meter object. */ 835 uint32_t meter_id; 836 /**< Meter id. */ 837 struct mlx5_flow_meter_profile *profile; 838 /**< Meter profile parameters. */ 839 840 rte_spinlock_t sl; /**< Meter action spinlock. */ 841 842 /** Policer actions (per meter output color). */ 843 enum rte_mtr_policer_action action[RTE_COLORS]; 844 845 /** Set of stats counters to be enabled. 846 * @see enum rte_mtr_stats_type 847 */ 848 uint64_t stats_mask; 849 850 /**< Rule applies to ingress traffic. */ 851 uint32_t ingress:1; 852 853 /**< Rule applies to egress traffic. */ 854 uint32_t egress:1; 855 /** 856 * Instead of simply matching the properties of traffic as it would 857 * appear on a given DPDK port ID, enabling this attribute transfers 858 * a flow rule to the lowest possible level of any device endpoints 859 * found in the pattern. 860 * 861 * When supported, this effectively enables an application to 862 * re-route traffic not necessarily intended for it (e.g. coming 863 * from or addressed to different physical ports, VFs or 864 * applications) at the device level. 865 * 866 * It complements the behavior of some pattern items such as 867 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 868 * 869 * When transferring flow rules, ingress and egress attributes keep 870 * their original meaning, as if processing traffic emitted or 871 * received by the application. 872 */ 873 uint32_t transfer:1; 874 struct mlx5_meter_domains_infos *mfts; 875 /**< Flow table created for this meter. */ 876 struct mlx5_flow_policer_stats policer_stats; 877 /**< Meter policer statistics. */ 878 uint32_t ref_cnt; 879 /**< Use count. */ 880 uint32_t active_state:1; 881 /**< Meter state. */ 882 uint32_t shared:1; 883 /**< Meter shared or not. */ 884 }; 885 886 /* RFC2697 parameter structure. */ 887 struct mlx5_flow_meter_srtcm_rfc2697_prm { 888 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 889 uint32_t cbs_exponent:5; 890 uint32_t cbs_mantissa:8; 891 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 892 uint32_t cir_exponent:5; 893 uint32_t cir_mantissa:8; 894 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 895 uint32_t ebs_exponent:5; 896 uint32_t ebs_mantissa:8; 897 }; 898 899 /* Flow meter profile structure. */ 900 struct mlx5_flow_meter_profile { 901 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 902 /**< Pointer to the next flow meter structure. */ 903 uint32_t meter_profile_id; /**< Profile id. */ 904 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 905 union { 906 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 907 /**< srtcm_rfc2697 struct. */ 908 }; 909 uint32_t ref_cnt; /**< Use count. */ 910 }; 911 912 /* Fdir flow structure */ 913 struct mlx5_fdir_flow { 914 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */ 915 struct mlx5_fdir *fdir; /* Pointer to fdir. */ 916 uint32_t rix_flow; /* Index to flow. */ 917 }; 918 919 #define MLX5_MAX_TUNNELS 256 920 #define MLX5_TNL_MISS_RULE_PRIORITY 3 921 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 922 923 /* 924 * When tunnel offload is active, all JUMP group ids are converted 925 * using the same method. That conversion is applied both to tunnel and 926 * regular rule types. 927 * Group ids used in tunnel rules are relative to it's tunnel (!). 928 * Application can create number of steer rules, using the same 929 * tunnel, with different group id in each rule. 930 * Each tunnel stores its groups internally in PMD tunnel object. 931 * Groups used in regular rules do not belong to any tunnel and are stored 932 * in tunnel hub. 933 */ 934 935 struct mlx5_flow_tunnel { 936 LIST_ENTRY(mlx5_flow_tunnel) chain; 937 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 938 uint32_t tunnel_id; /** unique tunnel ID */ 939 uint32_t refctn; 940 struct rte_flow_action action; 941 struct rte_flow_item item; 942 struct mlx5_hlist *groups; /** tunnel groups */ 943 }; 944 945 /** PMD tunnel related context */ 946 struct mlx5_flow_tunnel_hub { 947 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 948 rte_spinlock_t sl; /* Tunnel list spinlock. */ 949 struct mlx5_hlist *groups; /** non tunnel groups */ 950 }; 951 952 /* convert jump group to flow table ID in tunnel rules */ 953 struct tunnel_tbl_entry { 954 struct mlx5_hlist_entry hash; 955 uint32_t flow_table; 956 }; 957 958 static inline uint32_t 959 tunnel_id_to_flow_tbl(uint32_t id) 960 { 961 return id | (1u << 16); 962 } 963 964 static inline uint32_t 965 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 966 { 967 return flow_tbl & ~(1u << 16); 968 } 969 970 union tunnel_tbl_key { 971 uint64_t val; 972 struct { 973 uint32_t tunnel_id; 974 uint32_t group; 975 }; 976 }; 977 978 static inline struct mlx5_flow_tunnel_hub * 979 mlx5_tunnel_hub(struct rte_eth_dev *dev) 980 { 981 struct mlx5_priv *priv = dev->data->dev_private; 982 return priv->sh->tunnel_hub; 983 } 984 985 static inline bool 986 is_tunnel_offload_active(struct rte_eth_dev *dev) 987 { 988 struct mlx5_priv *priv = dev->data->dev_private; 989 return !!priv->config.dv_miss_info; 990 } 991 992 static inline bool 993 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev, 994 __rte_unused const struct rte_flow_attr *attr, 995 __rte_unused const struct rte_flow_item items[], 996 __rte_unused const struct rte_flow_action actions[]) 997 { 998 return (items[0].type == (typeof(items[0].type)) 999 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL); 1000 } 1001 1002 static inline bool 1003 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev, 1004 __rte_unused const struct rte_flow_attr *attr, 1005 __rte_unused const struct rte_flow_item items[], 1006 __rte_unused const struct rte_flow_action actions[]) 1007 { 1008 return (actions[0].type == (typeof(actions[0].type)) 1009 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET); 1010 } 1011 1012 static inline const struct mlx5_flow_tunnel * 1013 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 1014 { 1015 return actions[0].conf; 1016 } 1017 1018 static inline const struct mlx5_flow_tunnel * 1019 flow_items_to_tunnel(const struct rte_flow_item items[]) 1020 { 1021 return items[0].spec; 1022 } 1023 1024 /* Flow structure. */ 1025 struct rte_flow { 1026 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 1027 struct mlx5_shared_action_rss *shared_rss; /** < Shred RSS action. */ 1028 uint32_t dev_handles; 1029 /**< Device flow handles that are part of the flow. */ 1030 uint32_t drv_type:2; /**< Driver type. */ 1031 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */ 1032 uint32_t tunnel:1; 1033 uint32_t meter:16; /**< Holds flow meter id. */ 1034 uint32_t rix_mreg_copy; 1035 /**< Index to metadata register copy table resource. */ 1036 uint32_t counter; /**< Holds flow counter. */ 1037 uint32_t tunnel_id; /**< Tunnel id */ 1038 } __rte_packed; 1039 1040 /* 1041 * Define list of valid combinations of RX Hash fields 1042 * (see enum ibv_rx_hash_fields). 1043 */ 1044 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1045 #define MLX5_RSS_HASH_IPV4_TCP \ 1046 (MLX5_RSS_HASH_IPV4 | \ 1047 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP) 1048 #define MLX5_RSS_HASH_IPV4_UDP \ 1049 (MLX5_RSS_HASH_IPV4 | \ 1050 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP) 1051 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1052 #define MLX5_RSS_HASH_IPV6_TCP \ 1053 (MLX5_RSS_HASH_IPV6 | \ 1054 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP) 1055 #define MLX5_RSS_HASH_IPV6_UDP \ 1056 (MLX5_RSS_HASH_IPV6 | \ 1057 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP) 1058 #define MLX5_RSS_HASH_NONE 0ULL 1059 1060 /* array of valid combinations of RX Hash fields for RSS */ 1061 static const uint64_t mlx5_rss_hash_fields[] = { 1062 MLX5_RSS_HASH_IPV4, 1063 MLX5_RSS_HASH_IPV4_TCP, 1064 MLX5_RSS_HASH_IPV4_UDP, 1065 MLX5_RSS_HASH_IPV6, 1066 MLX5_RSS_HASH_IPV6_TCP, 1067 MLX5_RSS_HASH_IPV6_UDP, 1068 MLX5_RSS_HASH_NONE, 1069 }; 1070 1071 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1072 1073 /* Shared RSS action structure */ 1074 struct mlx5_shared_action_rss { 1075 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1076 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1077 uint16_t *queue; /**< Queue indices to use. */ 1078 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1079 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1080 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN]; 1081 /**< Hash RX queue indexes for tunneled RSS */ 1082 }; 1083 1084 struct rte_flow_shared_action { 1085 LIST_ENTRY(rte_flow_shared_action) next; 1086 /**< Pointer to the next element. */ 1087 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1088 uint64_t type; 1089 /**< Shared action type (see MLX5_FLOW_ACTION_SHARED_*). */ 1090 union { 1091 struct mlx5_shared_action_rss rss; 1092 /**< Shared RSS action. */ 1093 }; 1094 }; 1095 1096 /* Thread specific flow workspace intermediate data. */ 1097 struct mlx5_flow_workspace { 1098 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1099 struct mlx5_flow_rss_desc rss_desc[2]; 1100 uint32_t rssq_num[2]; /* Allocated queue num in rss_desc. */ 1101 int flow_idx; /* Intermediate device flow index. */ 1102 int flow_nested_idx; /* Intermediate device flow index, nested. */ 1103 }; 1104 1105 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1106 const struct rte_flow_attr *attr, 1107 const struct rte_flow_item items[], 1108 const struct rte_flow_action actions[], 1109 bool external, 1110 int hairpin, 1111 struct rte_flow_error *error); 1112 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1113 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1114 const struct rte_flow_item items[], 1115 const struct rte_flow_action actions[], struct rte_flow_error *error); 1116 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1117 struct mlx5_flow *dev_flow, 1118 const struct rte_flow_attr *attr, 1119 const struct rte_flow_item items[], 1120 const struct rte_flow_action actions[], 1121 struct rte_flow_error *error); 1122 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1123 struct rte_flow_error *error); 1124 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1125 struct rte_flow *flow); 1126 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1127 struct rte_flow *flow); 1128 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1129 struct rte_flow *flow, 1130 const struct rte_flow_action *actions, 1131 void *data, 1132 struct rte_flow_error *error); 1133 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 1134 (struct rte_eth_dev *dev, 1135 const struct mlx5_flow_meter *fm); 1136 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1137 struct mlx5_meter_domains_infos *tbls); 1138 typedef int (*mlx5_flow_create_policer_rules_t) 1139 (struct rte_eth_dev *dev, 1140 struct mlx5_flow_meter *fm, 1141 const struct rte_flow_attr *attr); 1142 typedef int (*mlx5_flow_destroy_policer_rules_t) 1143 (struct rte_eth_dev *dev, 1144 const struct mlx5_flow_meter *fm, 1145 const struct rte_flow_attr *attr); 1146 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1147 (struct rte_eth_dev *dev); 1148 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1149 uint32_t cnt); 1150 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1151 uint32_t cnt, 1152 bool clear, uint64_t *pkts, 1153 uint64_t *bytes); 1154 typedef int (*mlx5_flow_get_aged_flows_t) 1155 (struct rte_eth_dev *dev, 1156 void **context, 1157 uint32_t nb_contexts, 1158 struct rte_flow_error *error); 1159 typedef int (*mlx5_flow_action_validate_t) 1160 (struct rte_eth_dev *dev, 1161 const struct rte_flow_shared_action_conf *conf, 1162 const struct rte_flow_action *action, 1163 struct rte_flow_error *error); 1164 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t) 1165 (struct rte_eth_dev *dev, 1166 const struct rte_flow_shared_action_conf *conf, 1167 const struct rte_flow_action *action, 1168 struct rte_flow_error *error); 1169 typedef int (*mlx5_flow_action_destroy_t) 1170 (struct rte_eth_dev *dev, 1171 struct rte_flow_shared_action *action, 1172 struct rte_flow_error *error); 1173 typedef int (*mlx5_flow_action_update_t) 1174 (struct rte_eth_dev *dev, 1175 struct rte_flow_shared_action *action, 1176 const void *action_conf, 1177 struct rte_flow_error *error); 1178 typedef int (*mlx5_flow_sync_domain_t) 1179 (struct rte_eth_dev *dev, 1180 uint32_t domains, 1181 uint32_t flags); 1182 struct mlx5_flow_driver_ops { 1183 mlx5_flow_validate_t validate; 1184 mlx5_flow_prepare_t prepare; 1185 mlx5_flow_translate_t translate; 1186 mlx5_flow_apply_t apply; 1187 mlx5_flow_remove_t remove; 1188 mlx5_flow_destroy_t destroy; 1189 mlx5_flow_query_t query; 1190 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1191 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1192 mlx5_flow_create_policer_rules_t create_policer_rules; 1193 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 1194 mlx5_flow_counter_alloc_t counter_alloc; 1195 mlx5_flow_counter_free_t counter_free; 1196 mlx5_flow_counter_query_t counter_query; 1197 mlx5_flow_get_aged_flows_t get_aged_flows; 1198 mlx5_flow_action_validate_t action_validate; 1199 mlx5_flow_action_create_t action_create; 1200 mlx5_flow_action_destroy_t action_destroy; 1201 mlx5_flow_action_update_t action_update; 1202 mlx5_flow_sync_domain_t sync_domain; 1203 }; 1204 1205 /* mlx5_flow.c */ 1206 1207 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1208 __extension__ 1209 struct flow_grp_info { 1210 uint64_t external:1; 1211 uint64_t transfer:1; 1212 uint64_t fdb_def_rule:1; 1213 /* force standard group translation */ 1214 uint64_t std_tbl_fix:1; 1215 }; 1216 1217 static inline bool 1218 tunnel_use_standard_attr_group_translate 1219 (struct rte_eth_dev *dev, 1220 const struct mlx5_flow_tunnel *tunnel, 1221 const struct rte_flow_attr *attr, 1222 const struct rte_flow_item items[], 1223 const struct rte_flow_action actions[]) 1224 { 1225 bool verdict; 1226 1227 if (!is_tunnel_offload_active(dev)) 1228 /* no tunnel offload API */ 1229 verdict = true; 1230 else if (tunnel) { 1231 /* 1232 * OvS will use jump to group 0 in tunnel steer rule. 1233 * If tunnel steer rule starts from group 0 (attr.group == 0) 1234 * that 0 group must be translated with standard method. 1235 * attr.group == 0 in tunnel match rule translated with tunnel 1236 * method 1237 */ 1238 verdict = !attr->group && 1239 is_flow_tunnel_steer_rule(dev, attr, items, actions); 1240 } else { 1241 /* 1242 * non-tunnel group translation uses standard method for 1243 * root group only: attr.group == 0 1244 */ 1245 verdict = !attr->group; 1246 } 1247 1248 return verdict; 1249 } 1250 1251 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1252 const struct mlx5_flow_tunnel *tunnel, 1253 uint32_t group, uint32_t *table, 1254 struct flow_grp_info flags, 1255 struct rte_flow_error *error); 1256 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1257 int tunnel, uint64_t layer_types, 1258 uint64_t hash_fields); 1259 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1260 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1261 uint32_t subpriority); 1262 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1263 enum mlx5_feature_name feature, 1264 uint32_t id, 1265 struct rte_flow_error *error); 1266 const struct rte_flow_action *mlx5_flow_find_action 1267 (const struct rte_flow_action *actions, 1268 enum rte_flow_action_type action); 1269 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1270 const struct rte_flow_action *action, 1271 struct rte_flow_error *error); 1272 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1273 const struct rte_flow_attr *attr, 1274 struct rte_flow_error *error); 1275 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1276 const struct rte_flow_attr *attr, 1277 struct rte_flow_error *error); 1278 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1279 const struct rte_flow_attr *attr, 1280 struct rte_flow_error *error); 1281 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1282 uint64_t action_flags, 1283 const struct rte_flow_attr *attr, 1284 struct rte_flow_error *error); 1285 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1286 uint64_t action_flags, 1287 struct rte_eth_dev *dev, 1288 const struct rte_flow_attr *attr, 1289 struct rte_flow_error *error); 1290 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1291 uint64_t action_flags, 1292 struct rte_eth_dev *dev, 1293 const struct rte_flow_attr *attr, 1294 uint64_t item_flags, 1295 struct rte_flow_error *error); 1296 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1297 const struct rte_flow_attr *attr, 1298 struct rte_flow_error *error); 1299 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1300 const struct rte_flow_attr *attributes, 1301 struct rte_flow_error *error); 1302 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1303 const uint8_t *mask, 1304 const uint8_t *nic_mask, 1305 unsigned int size, 1306 bool range_accepted, 1307 struct rte_flow_error *error); 1308 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1309 uint64_t item_flags, bool ext_vlan_sup, 1310 struct rte_flow_error *error); 1311 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1312 uint64_t item_flags, 1313 uint8_t target_protocol, 1314 struct rte_flow_error *error); 1315 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1316 uint64_t item_flags, 1317 const struct rte_flow_item *gre_item, 1318 struct rte_flow_error *error); 1319 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1320 uint64_t item_flags, 1321 uint64_t last_item, 1322 uint16_t ether_type, 1323 const struct rte_flow_item_ipv4 *acc_mask, 1324 bool range_accepted, 1325 struct rte_flow_error *error); 1326 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1327 uint64_t item_flags, 1328 uint64_t last_item, 1329 uint16_t ether_type, 1330 const struct rte_flow_item_ipv6 *acc_mask, 1331 struct rte_flow_error *error); 1332 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1333 const struct rte_flow_item *item, 1334 uint64_t item_flags, 1335 uint64_t prev_layer, 1336 struct rte_flow_error *error); 1337 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1338 uint64_t item_flags, 1339 uint8_t target_protocol, 1340 const struct rte_flow_item_tcp *flow_mask, 1341 struct rte_flow_error *error); 1342 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1343 uint64_t item_flags, 1344 uint8_t target_protocol, 1345 struct rte_flow_error *error); 1346 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1347 uint64_t item_flags, 1348 struct rte_eth_dev *dev, 1349 struct rte_flow_error *error); 1350 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1351 uint64_t item_flags, 1352 struct rte_flow_error *error); 1353 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1354 uint64_t item_flags, 1355 struct rte_eth_dev *dev, 1356 struct rte_flow_error *error); 1357 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1358 uint64_t item_flags, 1359 uint8_t target_protocol, 1360 struct rte_flow_error *error); 1361 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1362 uint64_t item_flags, 1363 uint8_t target_protocol, 1364 struct rte_flow_error *error); 1365 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1366 uint64_t item_flags, 1367 uint8_t target_protocol, 1368 struct rte_flow_error *error); 1369 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1370 uint64_t item_flags, 1371 struct rte_eth_dev *dev, 1372 struct rte_flow_error *error); 1373 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1374 uint64_t item_flags, 1375 uint64_t last_item, 1376 uint16_t ether_type, 1377 const struct rte_flow_item_ecpri *acc_mask, 1378 struct rte_flow_error *error); 1379 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1380 (struct rte_eth_dev *dev, 1381 const struct mlx5_flow_meter *fm); 1382 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1383 struct mlx5_meter_domains_infos *tbl); 1384 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1385 struct mlx5_flow_meter *fm, 1386 const struct rte_flow_attr *attr); 1387 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1388 struct mlx5_flow_meter *fm, 1389 const struct rte_flow_attr *attr); 1390 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1391 struct rte_mtr_error *error); 1392 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1393 struct rte_flow_shared_action *mlx5_flow_get_shared_rss(struct rte_flow *flow); 1394 int mlx5_shared_action_flush(struct rte_eth_dev *dev); 1395 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1396 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1397 1398 /* Hash list callbacks for flow tables: */ 1399 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1400 uint64_t key, void *entry_ctx); 1401 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1402 struct mlx5_hlist_entry *entry); 1403 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1404 uint32_t table_id, uint8_t egress, uint8_t transfer, 1405 bool external, const struct mlx5_flow_tunnel *tunnel, 1406 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error); 1407 1408 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1409 uint64_t key, void *cb_ctx); 1410 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1411 struct mlx5_hlist_entry *entry); 1412 1413 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1414 struct mlx5_hlist_entry *entry, 1415 uint64_t key, void *cb_ctx); 1416 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1417 uint64_t key, void *ctx); 1418 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1419 struct mlx5_hlist_entry *entry); 1420 1421 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1422 uint64_t key, void *ctx); 1423 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1424 struct mlx5_hlist_entry *entry); 1425 1426 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1427 struct mlx5_hlist_entry *entry, 1428 uint64_t key, void *cb_ctx); 1429 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1430 uint64_t key, void *cb_ctx); 1431 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1432 struct mlx5_hlist_entry *entry); 1433 1434 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1435 struct mlx5_cache_entry *entry, void *ctx); 1436 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1437 struct mlx5_cache_entry *entry, void *ctx); 1438 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1439 struct mlx5_cache_entry *entry); 1440 1441 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1442 struct mlx5_cache_entry *entry, void *cb_ctx); 1443 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1444 struct mlx5_cache_entry *entry, void *cb_ctx); 1445 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1446 struct mlx5_cache_entry *entry); 1447 1448 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1449 struct mlx5_cache_entry *entry, void *cb_ctx); 1450 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1451 (struct mlx5_cache_list *list, 1452 struct mlx5_cache_entry *entry, void *cb_ctx); 1453 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1454 struct mlx5_cache_entry *entry); 1455 1456 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1457 struct mlx5_cache_entry *entry, void *cb_ctx); 1458 struct mlx5_cache_entry *flow_dv_sample_create_cb 1459 (struct mlx5_cache_list *list, 1460 struct mlx5_cache_entry *entry, void *cb_ctx); 1461 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1462 struct mlx5_cache_entry *entry); 1463 1464 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1465 struct mlx5_cache_entry *entry, void *cb_ctx); 1466 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1467 (struct mlx5_cache_list *list, 1468 struct mlx5_cache_entry *entry, void *cb_ctx); 1469 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1470 struct mlx5_cache_entry *entry); 1471 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1472