1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* Private rte flow items. */ 22 enum mlx5_rte_flow_item_type { 23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 24 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 28 }; 29 30 /* Private (internal) rte flow actions. */ 31 enum mlx5_rte_flow_action_type { 32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 33 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 34 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 38 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT, 40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP, 41 }; 42 43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 44 45 enum { 46 MLX5_INDIRECT_ACTION_TYPE_RSS, 47 MLX5_INDIRECT_ACTION_TYPE_AGE, 48 MLX5_INDIRECT_ACTION_TYPE_COUNT, 49 }; 50 51 /* Matches on selected register. */ 52 struct mlx5_rte_flow_item_tag { 53 enum modify_reg id; 54 uint32_t data; 55 }; 56 57 /* Modify selected register. */ 58 struct mlx5_rte_flow_action_set_tag { 59 enum modify_reg id; 60 uint8_t offset; 61 uint8_t length; 62 uint32_t data; 63 }; 64 65 struct mlx5_flow_action_copy_mreg { 66 enum modify_reg dst; 67 enum modify_reg src; 68 }; 69 70 /* Matches on source queue. */ 71 struct mlx5_rte_flow_item_tx_queue { 72 uint32_t queue; 73 }; 74 75 /* Feature name to allocate metadata register. */ 76 enum mlx5_feature_name { 77 MLX5_HAIRPIN_RX, 78 MLX5_HAIRPIN_TX, 79 MLX5_METADATA_RX, 80 MLX5_METADATA_TX, 81 MLX5_METADATA_FDB, 82 MLX5_FLOW_MARK, 83 MLX5_APP_TAG, 84 MLX5_COPY_MARK, 85 MLX5_MTR_COLOR, 86 MLX5_MTR_ID, 87 MLX5_ASO_FLOW_HIT, 88 }; 89 90 /* Default queue number. */ 91 #define MLX5_RSSQ_DEFAULT_NUM 16 92 93 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 94 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 95 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 96 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 97 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 98 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 99 100 /* Pattern inner Layer bits. */ 101 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 102 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 103 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 104 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 105 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 106 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 107 108 /* Pattern tunnel Layer bits. */ 109 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 110 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 111 #define MLX5_FLOW_LAYER_GRE (1u << 14) 112 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 113 /* List of tunnel Layer bits continued below. */ 114 115 /* General pattern items bits. */ 116 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 117 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 118 #define MLX5_FLOW_ITEM_TAG (1u << 18) 119 #define MLX5_FLOW_ITEM_MARK (1u << 19) 120 121 /* Pattern MISC bits. */ 122 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 123 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 124 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 125 126 /* Pattern tunnel Layer bits (continued). */ 127 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 128 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 129 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 130 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 131 132 /* Queue items. */ 133 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 134 135 /* Pattern tunnel Layer bits (continued). */ 136 #define MLX5_FLOW_LAYER_GTP (1u << 28) 137 138 /* Pattern eCPRI Layer bit. */ 139 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 140 141 /* IPv6 Fragment Extension Header bit. */ 142 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 143 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 144 145 /* Pattern tunnel Layer bits (continued). */ 146 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 147 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 148 149 /* INTEGRITY item bit */ 150 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34) 151 152 /* Outer Masks. */ 153 #define MLX5_FLOW_LAYER_OUTER_L3 \ 154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 155 #define MLX5_FLOW_LAYER_OUTER_L4 \ 156 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 157 #define MLX5_FLOW_LAYER_OUTER \ 158 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 159 MLX5_FLOW_LAYER_OUTER_L4) 160 161 /* Tunnel Masks. */ 162 #define MLX5_FLOW_LAYER_TUNNEL \ 163 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 164 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 165 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 166 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 167 168 /* Inner Masks. */ 169 #define MLX5_FLOW_LAYER_INNER_L3 \ 170 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 171 #define MLX5_FLOW_LAYER_INNER_L4 \ 172 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 173 #define MLX5_FLOW_LAYER_INNER \ 174 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 175 MLX5_FLOW_LAYER_INNER_L4) 176 177 /* Layer Masks. */ 178 #define MLX5_FLOW_LAYER_L2 \ 179 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 180 #define MLX5_FLOW_LAYER_L3_IPV4 \ 181 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 182 #define MLX5_FLOW_LAYER_L3_IPV6 \ 183 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 184 #define MLX5_FLOW_LAYER_L3 \ 185 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 186 #define MLX5_FLOW_LAYER_L4 \ 187 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 188 189 /* Actions */ 190 #define MLX5_FLOW_ACTION_DROP (1u << 0) 191 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 192 #define MLX5_FLOW_ACTION_RSS (1u << 2) 193 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 194 #define MLX5_FLOW_ACTION_MARK (1u << 4) 195 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 196 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 197 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 198 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 199 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 200 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 201 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 202 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 203 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 204 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 205 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 206 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 207 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 208 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 209 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 210 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 211 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 212 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 213 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 214 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 215 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 216 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 217 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 218 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 219 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 220 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 221 #define MLX5_FLOW_ACTION_METER (1ull << 31) 222 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 223 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 224 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 225 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 226 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 227 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 228 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 229 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 230 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40) 231 232 #define MLX5_FLOW_FATE_ACTIONS \ 233 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 234 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 235 MLX5_FLOW_ACTION_DEFAULT_MISS | \ 236 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 237 238 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 239 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 240 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 241 242 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 243 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 244 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 245 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 246 MLX5_FLOW_ACTION_SET_TP_SRC | \ 247 MLX5_FLOW_ACTION_SET_TP_DST | \ 248 MLX5_FLOW_ACTION_SET_TTL | \ 249 MLX5_FLOW_ACTION_DEC_TTL | \ 250 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 251 MLX5_FLOW_ACTION_SET_MAC_DST | \ 252 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 253 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 254 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 255 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 256 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 257 MLX5_FLOW_ACTION_SET_TAG | \ 258 MLX5_FLOW_ACTION_MARK_EXT | \ 259 MLX5_FLOW_ACTION_SET_META | \ 260 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 261 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 262 MLX5_FLOW_ACTION_MODIFY_FIELD) 263 264 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 265 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 266 267 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 268 269 #ifndef IPPROTO_MPLS 270 #define IPPROTO_MPLS 137 271 #endif 272 273 /* UDP port number for MPLS */ 274 #define MLX5_UDP_PORT_MPLS 6635 275 276 /* UDP port numbers for VxLAN. */ 277 #define MLX5_UDP_PORT_VXLAN 4789 278 #define MLX5_UDP_PORT_VXLAN_GPE 4790 279 280 /* UDP port numbers for GENEVE. */ 281 #define MLX5_UDP_PORT_GENEVE 6081 282 283 /* Lowest priority indicator. */ 284 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 285 286 /* 287 * Max priority for ingress\egress flow groups 288 * greater than 0 and for any transfer flow group. 289 * From user configation: 0 - 21843. 290 */ 291 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 292 293 /* 294 * Number of sub priorities. 295 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 296 * matching on the NIC (firmware dependent) L4 most have the higher priority 297 * followed by L3 and ending with L2. 298 */ 299 #define MLX5_PRIORITY_MAP_L2 2 300 #define MLX5_PRIORITY_MAP_L3 1 301 #define MLX5_PRIORITY_MAP_L4 0 302 #define MLX5_PRIORITY_MAP_MAX 3 303 304 /* Valid layer type for IPV4 RSS. */ 305 #define MLX5_IPV4_LAYER_TYPES \ 306 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 307 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 308 ETH_RSS_NONFRAG_IPV4_OTHER) 309 310 /* IBV hash source bits for IPV4. */ 311 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 312 313 /* Valid layer type for IPV6 RSS. */ 314 #define MLX5_IPV6_LAYER_TYPES \ 315 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 316 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 317 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 318 319 /* IBV hash source bits for IPV6. */ 320 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 321 322 /* IBV hash bits for L3 SRC. */ 323 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 324 325 /* IBV hash bits for L3 DST. */ 326 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 327 328 /* IBV hash bits for TCP. */ 329 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 330 IBV_RX_HASH_DST_PORT_TCP) 331 332 /* IBV hash bits for UDP. */ 333 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 334 IBV_RX_HASH_DST_PORT_UDP) 335 336 /* IBV hash bits for L4 SRC. */ 337 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 338 IBV_RX_HASH_SRC_PORT_UDP) 339 340 /* IBV hash bits for L4 DST. */ 341 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 342 IBV_RX_HASH_DST_PORT_UDP) 343 344 /* Geneve header first 16Bit */ 345 #define MLX5_GENEVE_VER_MASK 0x3 346 #define MLX5_GENEVE_VER_SHIFT 14 347 #define MLX5_GENEVE_VER_VAL(a) \ 348 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 349 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 350 #define MLX5_GENEVE_OPTLEN_SHIFT 8 351 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 352 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 353 #define MLX5_GENEVE_OAMF_MASK 0x1 354 #define MLX5_GENEVE_OAMF_SHIFT 7 355 #define MLX5_GENEVE_OAMF_VAL(a) \ 356 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 357 #define MLX5_GENEVE_CRITO_MASK 0x1 358 #define MLX5_GENEVE_CRITO_SHIFT 6 359 #define MLX5_GENEVE_CRITO_VAL(a) \ 360 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 361 #define MLX5_GENEVE_RSVD_MASK 0x3F 362 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 363 /* 364 * The length of the Geneve options fields, expressed in four byte multiples, 365 * not including the eight byte fixed tunnel. 366 */ 367 #define MLX5_GENEVE_OPT_LEN_0 14 368 #define MLX5_GENEVE_OPT_LEN_1 63 369 370 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 371 sizeof(struct rte_ipv4_hdr)) 372 /* GTP extension header flag. */ 373 #define MLX5_GTP_EXT_HEADER_FLAG 4 374 375 /* GTP extension header max PDU type value. */ 376 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 377 378 /* GTP extension header PDU type shift. */ 379 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 380 381 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 382 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 383 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 384 385 /* Specific item's fields can accept a range of values (using spec and last). */ 386 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 387 #define MLX5_ITEM_RANGE_ACCEPTED true 388 389 /* Software header modify action numbers of a flow. */ 390 #define MLX5_ACT_NUM_MDF_IPV4 1 391 #define MLX5_ACT_NUM_MDF_IPV6 4 392 #define MLX5_ACT_NUM_MDF_MAC 2 393 #define MLX5_ACT_NUM_MDF_VID 1 394 #define MLX5_ACT_NUM_MDF_PORT 2 395 #define MLX5_ACT_NUM_MDF_TTL 1 396 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 397 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 398 #define MLX5_ACT_NUM_MDF_TCPACK 1 399 #define MLX5_ACT_NUM_SET_REG 1 400 #define MLX5_ACT_NUM_SET_TAG 1 401 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 402 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 403 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 404 #define MLX5_ACT_NUM_SET_DSCP 1 405 406 /* Maximum number of fields to modify in MODIFY_FIELD */ 407 #define MLX5_ACT_MAX_MOD_FIELDS 5 408 409 enum mlx5_flow_drv_type { 410 MLX5_FLOW_TYPE_MIN, 411 MLX5_FLOW_TYPE_DV, 412 MLX5_FLOW_TYPE_VERBS, 413 MLX5_FLOW_TYPE_MAX, 414 }; 415 416 /* Fate action type. */ 417 enum mlx5_flow_fate_type { 418 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 419 MLX5_FLOW_FATE_QUEUE, 420 MLX5_FLOW_FATE_JUMP, 421 MLX5_FLOW_FATE_PORT_ID, 422 MLX5_FLOW_FATE_DROP, 423 MLX5_FLOW_FATE_DEFAULT_MISS, 424 MLX5_FLOW_FATE_SHARED_RSS, 425 MLX5_FLOW_FATE_MAX, 426 }; 427 428 /* Matcher PRM representation */ 429 struct mlx5_flow_dv_match_params { 430 size_t size; 431 /**< Size of match value. Do NOT split size and key! */ 432 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 433 /**< Matcher value. This value is used as the mask or as a key. */ 434 }; 435 436 /* Matcher structure. */ 437 struct mlx5_flow_dv_matcher { 438 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 439 struct mlx5_flow_tbl_resource *tbl; 440 /**< Pointer to the table(group) the matcher associated with. */ 441 void *matcher_object; /**< Pointer to DV matcher */ 442 uint16_t crc; /**< CRC of key. */ 443 uint16_t priority; /**< Priority of matcher. */ 444 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 445 }; 446 447 #define MLX5_ENCAP_MAX_LEN 132 448 449 /* Encap/decap resource structure. */ 450 struct mlx5_flow_dv_encap_decap_resource { 451 struct mlx5_hlist_entry entry; 452 /* Pointer to next element. */ 453 uint32_t refcnt; /**< Reference counter. */ 454 void *action; 455 /**< Encap/decap action object. */ 456 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 457 size_t size; 458 uint8_t reformat_type; 459 uint8_t ft_type; 460 uint64_t flags; /**< Flags for RDMA API. */ 461 uint32_t idx; /**< Index for the index memory pool. */ 462 }; 463 464 /* Tag resource structure. */ 465 struct mlx5_flow_dv_tag_resource { 466 struct mlx5_hlist_entry entry; 467 /**< hash list entry for tag resource, tag value as the key. */ 468 void *action; 469 /**< Tag action object. */ 470 uint32_t refcnt; /**< Reference counter. */ 471 uint32_t idx; /**< Index for the index memory pool. */ 472 uint32_t tag_id; /**< Tag ID. */ 473 }; 474 475 /* 476 * Number of modification commands. 477 * The maximal actions amount in FW is some constant, and it is 16 in the 478 * latest releases. In some old releases, it will be limited to 8. 479 * Since there is no interface to query the capacity, the maximal value should 480 * be used to allow PMD to create the flow. The validation will be done in the 481 * lower driver layer or FW. A failure will be returned if exceeds the maximal 482 * supported actions number on the root table. 483 * On non-root tables, there is no limitation, but 32 is enough right now. 484 */ 485 #define MLX5_MAX_MODIFY_NUM 32 486 #define MLX5_ROOT_TBL_MODIFY_NUM 16 487 488 /* Modify resource structure */ 489 struct mlx5_flow_dv_modify_hdr_resource { 490 struct mlx5_hlist_entry entry; 491 void *action; /**< Modify header action object. */ 492 /* Key area for hash list matching: */ 493 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 494 uint32_t actions_num; /**< Number of modification actions. */ 495 uint64_t flags; /**< Flags for RDMA API. */ 496 struct mlx5_modification_cmd actions[]; 497 /**< Modification actions. */ 498 }; 499 500 /* Modify resource key of the hash organization. */ 501 union mlx5_flow_modify_hdr_key { 502 struct { 503 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 504 uint32_t actions_num:5; /**< Number of modification actions. */ 505 uint32_t group:19; /**< Flow group id. */ 506 uint32_t cksum; /**< Actions check sum. */ 507 }; 508 uint64_t v64; /**< full 64bits value of key */ 509 }; 510 511 /* Jump action resource structure. */ 512 struct mlx5_flow_dv_jump_tbl_resource { 513 void *action; /**< Pointer to the rdma core action. */ 514 }; 515 516 /* Port ID resource structure. */ 517 struct mlx5_flow_dv_port_id_action_resource { 518 struct mlx5_cache_entry entry; 519 void *action; /**< Action object. */ 520 uint32_t port_id; /**< Port ID value. */ 521 uint32_t idx; /**< Indexed pool memory index. */ 522 }; 523 524 /* Push VLAN action resource structure */ 525 struct mlx5_flow_dv_push_vlan_action_resource { 526 struct mlx5_cache_entry entry; /* Cache entry. */ 527 void *action; /**< Action object. */ 528 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 529 rte_be32_t vlan_tag; /**< VLAN tag value. */ 530 uint32_t idx; /**< Indexed pool memory index. */ 531 }; 532 533 /* Metadata register copy table entry. */ 534 struct mlx5_flow_mreg_copy_resource { 535 /* 536 * Hash list entry for copy table. 537 * - Key is 32/64-bit MARK action ID. 538 * - MUST be the first entry. 539 */ 540 struct mlx5_hlist_entry hlist_ent; 541 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 542 /* List entry for device flows. */ 543 uint32_t idx; 544 uint32_t rix_flow; /* Built flow for copy. */ 545 uint32_t mark_id; 546 }; 547 548 /* Table tunnel parameter. */ 549 struct mlx5_flow_tbl_tunnel_prm { 550 const struct mlx5_flow_tunnel *tunnel; 551 uint32_t group_id; 552 bool external; 553 }; 554 555 /* Table data structure of the hash organization. */ 556 struct mlx5_flow_tbl_data_entry { 557 struct mlx5_hlist_entry entry; 558 /**< hash list entry, 64-bits key inside. */ 559 struct mlx5_flow_tbl_resource tbl; 560 /**< flow table resource. */ 561 struct mlx5_cache_list matchers; 562 /**< matchers' header associated with the flow table. */ 563 struct mlx5_flow_dv_jump_tbl_resource jump; 564 /**< jump resource, at most one for each table created. */ 565 uint32_t idx; /**< index for the indexed mempool. */ 566 /**< tunnel offload */ 567 const struct mlx5_flow_tunnel *tunnel; 568 uint32_t group_id; 569 uint32_t external:1; 570 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 571 uint32_t is_egress:1; /**< Egress table. */ 572 uint32_t is_transfer:1; /**< Transfer table. */ 573 uint32_t dummy:1; /**< DR table. */ 574 uint32_t id:22; /**< Table ID. */ 575 uint32_t reserve:5; /**< Reserved to future using. */ 576 uint32_t level; /**< Table level. */ 577 }; 578 579 /* Sub rdma-core actions list. */ 580 struct mlx5_flow_sub_actions_list { 581 uint32_t actions_num; /**< Number of sample actions. */ 582 uint64_t action_flags; 583 void *dr_queue_action; 584 void *dr_tag_action; 585 void *dr_cnt_action; 586 void *dr_port_id_action; 587 void *dr_encap_action; 588 void *dr_jump_action; 589 }; 590 591 /* Sample sub-actions resource list. */ 592 struct mlx5_flow_sub_actions_idx { 593 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 594 uint32_t rix_tag; /**< Index to the tag action. */ 595 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 596 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 597 uint32_t rix_jump; /**< Index to the jump action resource. */ 598 }; 599 600 /* Sample action resource structure. */ 601 struct mlx5_flow_dv_sample_resource { 602 struct mlx5_cache_entry entry; /**< Cache entry. */ 603 union { 604 void *verbs_action; /**< Verbs sample action object. */ 605 void **sub_actions; /**< Sample sub-action array. */ 606 }; 607 struct rte_eth_dev *dev; /**< Device registers the action. */ 608 uint32_t idx; /** Sample object index. */ 609 uint8_t ft_type; /** Flow Table Type */ 610 uint32_t ft_id; /** Flow Table Level */ 611 uint32_t ratio; /** Sample Ratio */ 612 uint64_t set_action; /** Restore reg_c0 value */ 613 void *normal_path_tbl; /** Flow Table pointer */ 614 struct mlx5_flow_sub_actions_idx sample_idx; 615 /**< Action index resources. */ 616 struct mlx5_flow_sub_actions_list sample_act; 617 /**< Action resources. */ 618 }; 619 620 #define MLX5_MAX_DEST_NUM 2 621 622 /* Destination array action resource structure. */ 623 struct mlx5_flow_dv_dest_array_resource { 624 struct mlx5_cache_entry entry; /**< Cache entry. */ 625 uint32_t idx; /** Destination array action object index. */ 626 uint8_t ft_type; /** Flow Table Type */ 627 uint8_t num_of_dest; /**< Number of destination actions. */ 628 struct rte_eth_dev *dev; /**< Device registers the action. */ 629 void *action; /**< Pointer to the rdma core action. */ 630 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 631 /**< Action index resources. */ 632 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 633 /**< Action resources. */ 634 }; 635 636 /* PMD flow priority for tunnel */ 637 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 638 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 639 640 641 /** Device flow handle structure for DV mode only. */ 642 struct mlx5_flow_handle_dv { 643 /* Flow DV api: */ 644 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 645 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 646 /**< Pointer to modify header resource in cache. */ 647 uint32_t rix_encap_decap; 648 /**< Index to encap/decap resource in cache. */ 649 uint32_t rix_push_vlan; 650 /**< Index to push VLAN action resource in cache. */ 651 uint32_t rix_tag; 652 /**< Index to the tag action. */ 653 uint32_t rix_sample; 654 /**< Index to sample action resource in cache. */ 655 uint32_t rix_dest_array; 656 /**< Index to destination array resource in cache. */ 657 } __rte_packed; 658 659 /** Device flow handle structure: used both for creating & destroying. */ 660 struct mlx5_flow_handle { 661 SILIST_ENTRY(uint32_t)next; 662 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 663 /**< Index to next device flow handle. */ 664 uint64_t layers; 665 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 666 void *drv_flow; /**< pointer to driver flow object. */ 667 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */ 668 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */ 669 uint32_t mark:1; /**< Metadate rxq mark flag. */ 670 uint32_t fate_action:3; /**< Fate action type. */ 671 union { 672 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 673 uint32_t rix_jump; /**< Index to the jump action resource. */ 674 uint32_t rix_port_id_action; 675 /**< Index to port ID action resource. */ 676 uint32_t rix_fate; 677 /**< Generic value indicates the fate action. */ 678 uint32_t rix_default_fate; 679 /**< Indicates default miss fate action. */ 680 uint32_t rix_srss; 681 /**< Indicates shared RSS fate action. */ 682 }; 683 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 684 struct mlx5_flow_handle_dv dvh; 685 #endif 686 } __rte_packed; 687 688 /* 689 * Size for Verbs device flow handle structure only. Do not use the DV only 690 * structure in Verbs. No DV flows attributes will be accessed. 691 * Macro offsetof() could also be used here. 692 */ 693 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 694 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 695 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 696 #else 697 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 698 #endif 699 700 /** Device flow structure only for DV flow creation. */ 701 struct mlx5_flow_dv_workspace { 702 uint32_t group; /**< The group index. */ 703 uint32_t table_id; /**< Flow table identifier. */ 704 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 705 int actions_n; /**< number of actions. */ 706 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 707 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 708 /**< Pointer to encap/decap resource in cache. */ 709 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 710 /**< Pointer to push VLAN action resource in cache. */ 711 struct mlx5_flow_dv_tag_resource *tag_resource; 712 /**< pointer to the tag action. */ 713 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 714 /**< Pointer to port ID action resource. */ 715 struct mlx5_flow_dv_jump_tbl_resource *jump; 716 /**< Pointer to the jump action resource. */ 717 struct mlx5_flow_dv_match_params value; 718 /**< Holds the value that the packet is compared to. */ 719 struct mlx5_flow_dv_sample_resource *sample_res; 720 /**< Pointer to the sample action resource. */ 721 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 722 /**< Pointer to the destination array resource. */ 723 }; 724 725 #ifdef HAVE_INFINIBAND_VERBS_H 726 /* 727 * Maximal Verbs flow specifications & actions size. 728 * Some elements are mutually exclusive, but enough space should be allocated. 729 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 730 * 2. One tunnel header (exception: GRE + MPLS), 731 * SPEC length: GRE == tunnel. 732 * Actions: 1. 1 Mark OR Flag. 733 * 2. 1 Drop (if any). 734 * 3. No limitation for counters, but it makes no sense to support too 735 * many counters in a single device flow. 736 */ 737 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 738 #define MLX5_VERBS_MAX_SPEC_SIZE \ 739 ( \ 740 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 741 sizeof(struct ibv_flow_spec_ipv6) + \ 742 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 743 sizeof(struct ibv_flow_spec_gre) + \ 744 sizeof(struct ibv_flow_spec_mpls)) \ 745 ) 746 #else 747 #define MLX5_VERBS_MAX_SPEC_SIZE \ 748 ( \ 749 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 750 sizeof(struct ibv_flow_spec_ipv6) + \ 751 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 752 sizeof(struct ibv_flow_spec_tunnel)) \ 753 ) 754 #endif 755 756 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 757 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 758 #define MLX5_VERBS_MAX_ACT_SIZE \ 759 ( \ 760 sizeof(struct ibv_flow_spec_action_tag) + \ 761 sizeof(struct ibv_flow_spec_action_drop) + \ 762 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 763 ) 764 #else 765 #define MLX5_VERBS_MAX_ACT_SIZE \ 766 ( \ 767 sizeof(struct ibv_flow_spec_action_tag) + \ 768 sizeof(struct ibv_flow_spec_action_drop) \ 769 ) 770 #endif 771 772 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 773 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 774 775 /** Device flow structure only for Verbs flow creation. */ 776 struct mlx5_flow_verbs_workspace { 777 unsigned int size; /**< Size of the attribute. */ 778 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 779 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 780 /**< Specifications & actions buffer of verbs flow. */ 781 }; 782 #endif /* HAVE_INFINIBAND_VERBS_H */ 783 784 #define MLX5_SCALE_FLOW_GROUP_BIT 0 785 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 786 787 /** Maximal number of device sub-flows supported. */ 788 #define MLX5_NUM_MAX_DEV_FLOWS 32 789 790 /** Device flow structure. */ 791 __extension__ 792 struct mlx5_flow { 793 struct rte_flow *flow; /**< Pointer to the main flow. */ 794 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 795 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 796 uint64_t act_flags; 797 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 798 bool external; /**< true if the flow is created external to PMD. */ 799 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 800 uint8_t skip_scale:2; 801 /** 802 * Each Bit be set to 1 if Skip the scale the flow group with factor. 803 * If bit0 be set to 1, then skip the scale the original flow group; 804 * If bit1 be set to 1, then skip the scale the jump flow group if 805 * having jump action. 806 * 00: Enable scale in a flow, default value. 807 * 01: Skip scale the flow group with factor, enable scale the group 808 * of jump action. 809 * 10: Enable scale the group with factor, skip scale the group of 810 * jump action. 811 * 11: Skip scale the table with factor both for flow group and jump 812 * group. 813 */ 814 union { 815 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 816 struct mlx5_flow_dv_workspace dv; 817 #endif 818 #ifdef HAVE_INFINIBAND_VERBS_H 819 struct mlx5_flow_verbs_workspace verbs; 820 #endif 821 }; 822 struct mlx5_flow_handle *handle; 823 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 824 const struct mlx5_flow_tunnel *tunnel; 825 }; 826 827 /* Flow meter state. */ 828 #define MLX5_FLOW_METER_DISABLE 0 829 #define MLX5_FLOW_METER_ENABLE 1 830 831 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u 832 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u 833 834 #define MLX5_MAN_WIDTH 8 835 /* Legacy Meter parameter structure. */ 836 struct mlx5_legacy_flow_meter { 837 struct mlx5_flow_meter_info fm; 838 /* Must be the first in struct. */ 839 TAILQ_ENTRY(mlx5_legacy_flow_meter) next; 840 /**< Pointer to the next flow meter structure. */ 841 uint32_t idx; 842 /* Index to meter object. */ 843 }; 844 845 #define MLX5_MAX_TUNNELS 256 846 #define MLX5_TNL_MISS_RULE_PRIORITY 3 847 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 848 849 /* 850 * When tunnel offload is active, all JUMP group ids are converted 851 * using the same method. That conversion is applied both to tunnel and 852 * regular rule types. 853 * Group ids used in tunnel rules are relative to it's tunnel (!). 854 * Application can create number of steer rules, using the same 855 * tunnel, with different group id in each rule. 856 * Each tunnel stores its groups internally in PMD tunnel object. 857 * Groups used in regular rules do not belong to any tunnel and are stored 858 * in tunnel hub. 859 */ 860 861 struct mlx5_flow_tunnel { 862 LIST_ENTRY(mlx5_flow_tunnel) chain; 863 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 864 uint32_t tunnel_id; /** unique tunnel ID */ 865 uint32_t refctn; 866 struct rte_flow_action action; 867 struct rte_flow_item item; 868 struct mlx5_hlist *groups; /** tunnel groups */ 869 }; 870 871 /** PMD tunnel related context */ 872 struct mlx5_flow_tunnel_hub { 873 /* Tunnels list 874 * Access to the list MUST be MT protected 875 */ 876 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 877 /* protect access to the tunnels list */ 878 rte_spinlock_t sl; 879 struct mlx5_hlist *groups; /** non tunnel groups */ 880 }; 881 882 /* convert jump group to flow table ID in tunnel rules */ 883 struct tunnel_tbl_entry { 884 struct mlx5_hlist_entry hash; 885 uint32_t flow_table; 886 uint32_t tunnel_id; 887 uint32_t group; 888 }; 889 890 static inline uint32_t 891 tunnel_id_to_flow_tbl(uint32_t id) 892 { 893 return id | (1u << 16); 894 } 895 896 static inline uint32_t 897 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 898 { 899 return flow_tbl & ~(1u << 16); 900 } 901 902 union tunnel_tbl_key { 903 uint64_t val; 904 struct { 905 uint32_t tunnel_id; 906 uint32_t group; 907 }; 908 }; 909 910 static inline struct mlx5_flow_tunnel_hub * 911 mlx5_tunnel_hub(struct rte_eth_dev *dev) 912 { 913 struct mlx5_priv *priv = dev->data->dev_private; 914 return priv->sh->tunnel_hub; 915 } 916 917 static inline bool 918 is_tunnel_offload_active(struct rte_eth_dev *dev) 919 { 920 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 921 struct mlx5_priv *priv = dev->data->dev_private; 922 return !!priv->config.dv_miss_info; 923 #else 924 RTE_SET_USED(dev); 925 return false; 926 #endif 927 } 928 929 static inline bool 930 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev, 931 __rte_unused const struct rte_flow_attr *attr, 932 __rte_unused const struct rte_flow_item items[], 933 __rte_unused const struct rte_flow_action actions[]) 934 { 935 return (items[0].type == (typeof(items[0].type)) 936 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL); 937 } 938 939 static inline bool 940 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev, 941 __rte_unused const struct rte_flow_attr *attr, 942 __rte_unused const struct rte_flow_item items[], 943 __rte_unused const struct rte_flow_action actions[]) 944 { 945 return (actions[0].type == (typeof(actions[0].type)) 946 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET); 947 } 948 949 static inline const struct mlx5_flow_tunnel * 950 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 951 { 952 return actions[0].conf; 953 } 954 955 static inline const struct mlx5_flow_tunnel * 956 flow_items_to_tunnel(const struct rte_flow_item items[]) 957 { 958 return items[0].spec; 959 } 960 961 /* Flow structure. */ 962 struct rte_flow { 963 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 964 uint32_t dev_handles; 965 /**< Device flow handles that are part of the flow. */ 966 uint32_t drv_type:2; /**< Driver type. */ 967 uint32_t tunnel:1; 968 uint32_t meter:24; /**< Holds flow meter id. */ 969 uint32_t rix_mreg_copy; 970 /**< Index to metadata register copy table resource. */ 971 uint32_t counter; /**< Holds flow counter. */ 972 uint32_t tunnel_id; /**< Tunnel id */ 973 uint32_t age; /**< Holds ASO age bit index. */ 974 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 975 } __rte_packed; 976 977 /* 978 * Define list of valid combinations of RX Hash fields 979 * (see enum ibv_rx_hash_fields). 980 */ 981 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 982 #define MLX5_RSS_HASH_IPV4_TCP \ 983 (MLX5_RSS_HASH_IPV4 | \ 984 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 985 #define MLX5_RSS_HASH_IPV4_UDP \ 986 (MLX5_RSS_HASH_IPV4 | \ 987 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 988 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 989 #define MLX5_RSS_HASH_IPV6_TCP \ 990 (MLX5_RSS_HASH_IPV6 | \ 991 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 992 #define MLX5_RSS_HASH_IPV6_UDP \ 993 (MLX5_RSS_HASH_IPV6 | \ 994 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 995 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 996 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 997 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 998 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 999 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1000 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1001 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1002 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1003 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1004 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1005 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1006 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1007 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1008 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1009 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1010 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1011 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1012 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1013 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1014 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1015 #define MLX5_RSS_HASH_NONE 0ULL 1016 1017 1018 /* extract next protocol type from Ethernet & VLAN headers */ 1019 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \ 1020 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \ 1021 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \ 1022 (_prt) = rte_be_to_cpu_16((_prt)); \ 1023 } while (0) 1024 1025 /* array of valid combinations of RX Hash fields for RSS */ 1026 static const uint64_t mlx5_rss_hash_fields[] = { 1027 MLX5_RSS_HASH_IPV4, 1028 MLX5_RSS_HASH_IPV4_TCP, 1029 MLX5_RSS_HASH_IPV4_UDP, 1030 MLX5_RSS_HASH_IPV6, 1031 MLX5_RSS_HASH_IPV6_TCP, 1032 MLX5_RSS_HASH_IPV6_UDP, 1033 MLX5_RSS_HASH_NONE, 1034 }; 1035 1036 /* Shared RSS action structure */ 1037 struct mlx5_shared_action_rss { 1038 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1039 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1040 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1041 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1042 struct mlx5_ind_table_obj *ind_tbl; 1043 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1044 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1045 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1046 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1047 }; 1048 1049 struct rte_flow_action_handle { 1050 uint32_t id; 1051 }; 1052 1053 /* Thread specific flow workspace intermediate data. */ 1054 struct mlx5_flow_workspace { 1055 /* If creating another flow in same thread, push new as stack. */ 1056 struct mlx5_flow_workspace *prev; 1057 struct mlx5_flow_workspace *next; 1058 uint32_t inuse; /* can't create new flow with current. */ 1059 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1060 struct mlx5_flow_rss_desc rss_desc; 1061 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1062 uint32_t flow_idx; /* Intermediate device flow index. */ 1063 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */ 1064 uint32_t skip_matcher_reg:1; 1065 /* Indicates if need to skip matcher register in translate. */ 1066 }; 1067 1068 struct mlx5_flow_split_info { 1069 bool external; 1070 /**< True if flow is created by request external to PMD. */ 1071 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1072 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1073 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1074 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1075 uint32_t table_id; /**< Flow table identifier. */ 1076 }; 1077 1078 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1079 const struct rte_flow_attr *attr, 1080 const struct rte_flow_item items[], 1081 const struct rte_flow_action actions[], 1082 bool external, 1083 int hairpin, 1084 struct rte_flow_error *error); 1085 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1086 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1087 const struct rte_flow_item items[], 1088 const struct rte_flow_action actions[], struct rte_flow_error *error); 1089 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1090 struct mlx5_flow *dev_flow, 1091 const struct rte_flow_attr *attr, 1092 const struct rte_flow_item items[], 1093 const struct rte_flow_action actions[], 1094 struct rte_flow_error *error); 1095 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1096 struct rte_flow_error *error); 1097 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1098 struct rte_flow *flow); 1099 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1100 struct rte_flow *flow); 1101 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1102 struct rte_flow *flow, 1103 const struct rte_flow_action *actions, 1104 void *data, 1105 struct rte_flow_error *error); 1106 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev, 1107 struct mlx5_flow_meter_info *fm, 1108 uint32_t mtr_idx, 1109 uint8_t domain_bitmap); 1110 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1111 struct mlx5_flow_meter_info *fm); 1112 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev); 1113 typedef struct mlx5_flow_meter_sub_policy * 1114 (*mlx5_flow_meter_sub_policy_rss_prepare_t) 1115 (struct rte_eth_dev *dev, 1116 struct mlx5_flow_meter_policy *mtr_policy, 1117 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1118 typedef uint32_t (*mlx5_flow_mtr_alloc_t) 1119 (struct rte_eth_dev *dev); 1120 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev, 1121 uint32_t mtr_idx); 1122 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1123 (struct rte_eth_dev *dev); 1124 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1125 uint32_t cnt); 1126 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1127 uint32_t cnt, 1128 bool clear, uint64_t *pkts, 1129 uint64_t *bytes); 1130 typedef int (*mlx5_flow_get_aged_flows_t) 1131 (struct rte_eth_dev *dev, 1132 void **context, 1133 uint32_t nb_contexts, 1134 struct rte_flow_error *error); 1135 typedef int (*mlx5_flow_action_validate_t) 1136 (struct rte_eth_dev *dev, 1137 const struct rte_flow_indir_action_conf *conf, 1138 const struct rte_flow_action *action, 1139 struct rte_flow_error *error); 1140 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1141 (struct rte_eth_dev *dev, 1142 const struct rte_flow_indir_action_conf *conf, 1143 const struct rte_flow_action *action, 1144 struct rte_flow_error *error); 1145 typedef int (*mlx5_flow_action_destroy_t) 1146 (struct rte_eth_dev *dev, 1147 struct rte_flow_action_handle *action, 1148 struct rte_flow_error *error); 1149 typedef int (*mlx5_flow_action_update_t) 1150 (struct rte_eth_dev *dev, 1151 struct rte_flow_action_handle *action, 1152 const void *update, 1153 struct rte_flow_error *error); 1154 typedef int (*mlx5_flow_action_query_t) 1155 (struct rte_eth_dev *dev, 1156 const struct rte_flow_action_handle *action, 1157 void *data, 1158 struct rte_flow_error *error); 1159 typedef int (*mlx5_flow_sync_domain_t) 1160 (struct rte_eth_dev *dev, 1161 uint32_t domains, 1162 uint32_t flags); 1163 typedef int (*mlx5_flow_validate_mtr_acts_t) 1164 (struct rte_eth_dev *dev, 1165 const struct rte_flow_action *actions[RTE_COLORS], 1166 struct rte_flow_attr *attr, 1167 bool *is_rss, 1168 uint8_t *domain_bitmap, 1169 bool *is_def_policy, 1170 struct rte_mtr_error *error); 1171 typedef int (*mlx5_flow_create_mtr_acts_t) 1172 (struct rte_eth_dev *dev, 1173 struct mlx5_flow_meter_policy *mtr_policy, 1174 const struct rte_flow_action *actions[RTE_COLORS], 1175 struct rte_mtr_error *error); 1176 typedef void (*mlx5_flow_destroy_mtr_acts_t) 1177 (struct rte_eth_dev *dev, 1178 struct mlx5_flow_meter_policy *mtr_policy); 1179 typedef int (*mlx5_flow_create_policy_rules_t) 1180 (struct rte_eth_dev *dev, 1181 struct mlx5_flow_meter_policy *mtr_policy); 1182 typedef void (*mlx5_flow_destroy_policy_rules_t) 1183 (struct rte_eth_dev *dev, 1184 struct mlx5_flow_meter_policy *mtr_policy); 1185 typedef int (*mlx5_flow_create_def_policy_t) 1186 (struct rte_eth_dev *dev); 1187 typedef void (*mlx5_flow_destroy_def_policy_t) 1188 (struct rte_eth_dev *dev); 1189 1190 struct mlx5_flow_driver_ops { 1191 mlx5_flow_validate_t validate; 1192 mlx5_flow_prepare_t prepare; 1193 mlx5_flow_translate_t translate; 1194 mlx5_flow_apply_t apply; 1195 mlx5_flow_remove_t remove; 1196 mlx5_flow_destroy_t destroy; 1197 mlx5_flow_query_t query; 1198 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1199 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1200 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls; 1201 mlx5_flow_mtr_alloc_t create_meter; 1202 mlx5_flow_mtr_free_t free_meter; 1203 mlx5_flow_validate_mtr_acts_t validate_mtr_acts; 1204 mlx5_flow_create_mtr_acts_t create_mtr_acts; 1205 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts; 1206 mlx5_flow_create_policy_rules_t create_policy_rules; 1207 mlx5_flow_destroy_policy_rules_t destroy_policy_rules; 1208 mlx5_flow_create_def_policy_t create_def_policy; 1209 mlx5_flow_destroy_def_policy_t destroy_def_policy; 1210 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare; 1211 mlx5_flow_counter_alloc_t counter_alloc; 1212 mlx5_flow_counter_free_t counter_free; 1213 mlx5_flow_counter_query_t counter_query; 1214 mlx5_flow_get_aged_flows_t get_aged_flows; 1215 mlx5_flow_action_validate_t action_validate; 1216 mlx5_flow_action_create_t action_create; 1217 mlx5_flow_action_destroy_t action_destroy; 1218 mlx5_flow_action_update_t action_update; 1219 mlx5_flow_action_query_t action_query; 1220 mlx5_flow_sync_domain_t sync_domain; 1221 }; 1222 1223 /* mlx5_flow.c */ 1224 1225 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1226 __extension__ 1227 struct flow_grp_info { 1228 uint64_t external:1; 1229 uint64_t transfer:1; 1230 uint64_t fdb_def_rule:1; 1231 /* force standard group translation */ 1232 uint64_t std_tbl_fix:1; 1233 uint64_t skip_scale:2; 1234 }; 1235 1236 static inline bool 1237 tunnel_use_standard_attr_group_translate 1238 (struct rte_eth_dev *dev, 1239 const struct mlx5_flow_tunnel *tunnel, 1240 const struct rte_flow_attr *attr, 1241 const struct rte_flow_item items[], 1242 const struct rte_flow_action actions[]) 1243 { 1244 bool verdict; 1245 1246 if (!is_tunnel_offload_active(dev)) 1247 /* no tunnel offload API */ 1248 verdict = true; 1249 else if (tunnel) { 1250 /* 1251 * OvS will use jump to group 0 in tunnel steer rule. 1252 * If tunnel steer rule starts from group 0 (attr.group == 0) 1253 * that 0 group must be translated with standard method. 1254 * attr.group == 0 in tunnel match rule translated with tunnel 1255 * method 1256 */ 1257 verdict = !attr->group && 1258 is_flow_tunnel_steer_rule(dev, attr, items, actions); 1259 } else { 1260 /* 1261 * non-tunnel group translation uses standard method for 1262 * root group only: attr.group == 0 1263 */ 1264 verdict = !attr->group; 1265 } 1266 1267 return verdict; 1268 } 1269 1270 /** 1271 * Get DV flow aso meter by index. 1272 * 1273 * @param[in] dev 1274 * Pointer to the Ethernet device structure. 1275 * @param[in] idx 1276 * mlx5 flow aso meter index in the container. 1277 * @param[out] ppool 1278 * mlx5 flow aso meter pool in the container, 1279 * 1280 * @return 1281 * Pointer to the aso meter, NULL otherwise. 1282 */ 1283 static inline struct mlx5_aso_mtr * 1284 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) 1285 { 1286 struct mlx5_aso_mtr_pool *pool; 1287 struct mlx5_aso_mtr_pools_mng *pools_mng = 1288 &priv->sh->mtrmng->pools_mng; 1289 1290 /* Decrease to original index. */ 1291 idx--; 1292 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n); 1293 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL]; 1294 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; 1295 } 1296 1297 static __rte_always_inline const struct rte_flow_item * 1298 mlx5_find_end_item(const struct rte_flow_item *item) 1299 { 1300 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++); 1301 return item; 1302 } 1303 1304 static __rte_always_inline bool 1305 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) 1306 { 1307 struct rte_flow_item_integrity test = *item; 1308 test.l3_ok = 0; 1309 test.l4_ok = 0; 1310 test.ipv4_csum_ok = 0; 1311 test.l4_csum_ok = 0; 1312 return (test.value == 0); 1313 } 1314 1315 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1316 const struct mlx5_flow_tunnel *tunnel, 1317 uint32_t group, uint32_t *table, 1318 const struct flow_grp_info *flags, 1319 struct rte_flow_error *error); 1320 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1321 int tunnel, uint64_t layer_types, 1322 uint64_t hash_fields); 1323 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1324 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1325 uint32_t subpriority); 1326 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1327 const struct rte_flow_attr *attr); 1328 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1329 const struct rte_flow_attr *attr, 1330 uint32_t subpriority); 1331 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1332 enum mlx5_feature_name feature, 1333 uint32_t id, 1334 struct rte_flow_error *error); 1335 const struct rte_flow_action *mlx5_flow_find_action 1336 (const struct rte_flow_action *actions, 1337 enum rte_flow_action_type action); 1338 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1339 const struct rte_flow_action *action, 1340 struct rte_flow_error *error); 1341 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1342 const struct rte_flow_attr *attr, 1343 struct rte_flow_error *error); 1344 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1345 const struct rte_flow_attr *attr, 1346 struct rte_flow_error *error); 1347 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1348 const struct rte_flow_attr *attr, 1349 struct rte_flow_error *error); 1350 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1351 uint64_t action_flags, 1352 const struct rte_flow_attr *attr, 1353 struct rte_flow_error *error); 1354 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1355 uint64_t action_flags, 1356 struct rte_eth_dev *dev, 1357 const struct rte_flow_attr *attr, 1358 struct rte_flow_error *error); 1359 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1360 uint64_t action_flags, 1361 struct rte_eth_dev *dev, 1362 const struct rte_flow_attr *attr, 1363 uint64_t item_flags, 1364 struct rte_flow_error *error); 1365 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1366 const struct rte_flow_attr *attr, 1367 struct rte_flow_error *error); 1368 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1369 const struct rte_flow_attr *attributes, 1370 struct rte_flow_error *error); 1371 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1372 const uint8_t *mask, 1373 const uint8_t *nic_mask, 1374 unsigned int size, 1375 bool range_accepted, 1376 struct rte_flow_error *error); 1377 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1378 uint64_t item_flags, bool ext_vlan_sup, 1379 struct rte_flow_error *error); 1380 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1381 uint64_t item_flags, 1382 uint8_t target_protocol, 1383 struct rte_flow_error *error); 1384 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1385 uint64_t item_flags, 1386 const struct rte_flow_item *gre_item, 1387 struct rte_flow_error *error); 1388 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1389 uint64_t item_flags, 1390 uint64_t last_item, 1391 uint16_t ether_type, 1392 const struct rte_flow_item_ipv4 *acc_mask, 1393 bool range_accepted, 1394 struct rte_flow_error *error); 1395 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1396 uint64_t item_flags, 1397 uint64_t last_item, 1398 uint16_t ether_type, 1399 const struct rte_flow_item_ipv6 *acc_mask, 1400 struct rte_flow_error *error); 1401 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1402 const struct rte_flow_item *item, 1403 uint64_t item_flags, 1404 uint64_t prev_layer, 1405 struct rte_flow_error *error); 1406 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1407 uint64_t item_flags, 1408 uint8_t target_protocol, 1409 const struct rte_flow_item_tcp *flow_mask, 1410 struct rte_flow_error *error); 1411 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1412 uint64_t item_flags, 1413 uint8_t target_protocol, 1414 struct rte_flow_error *error); 1415 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1416 uint64_t item_flags, 1417 struct rte_eth_dev *dev, 1418 struct rte_flow_error *error); 1419 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1420 uint64_t item_flags, 1421 struct rte_flow_error *error); 1422 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1423 uint64_t item_flags, 1424 struct rte_eth_dev *dev, 1425 struct rte_flow_error *error); 1426 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1427 uint64_t item_flags, 1428 uint8_t target_protocol, 1429 struct rte_flow_error *error); 1430 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1431 uint64_t item_flags, 1432 uint8_t target_protocol, 1433 struct rte_flow_error *error); 1434 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1435 uint64_t item_flags, 1436 uint8_t target_protocol, 1437 struct rte_flow_error *error); 1438 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1439 uint64_t item_flags, 1440 struct rte_eth_dev *dev, 1441 struct rte_flow_error *error); 1442 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1443 uint64_t last_item, 1444 const struct rte_flow_item *geneve_item, 1445 struct rte_eth_dev *dev, 1446 struct rte_flow_error *error); 1447 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1448 uint64_t item_flags, 1449 uint64_t last_item, 1450 uint16_t ether_type, 1451 const struct rte_flow_item_ecpri *acc_mask, 1452 struct rte_flow_error *error); 1453 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 1454 struct mlx5_flow_meter_info *fm, 1455 uint32_t mtr_idx, 1456 uint8_t domain_bitmap); 1457 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1458 struct mlx5_flow_meter_info *fm); 1459 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev); 1460 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare 1461 (struct rte_eth_dev *dev, 1462 struct mlx5_flow_meter_policy *mtr_policy, 1463 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1464 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1465 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1466 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1467 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1468 1469 /* Hash list callbacks for flow tables: */ 1470 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1471 uint64_t key, void *entry_ctx); 1472 int flow_dv_tbl_match_cb(struct mlx5_hlist *list, 1473 struct mlx5_hlist_entry *entry, uint64_t key, 1474 void *cb_ctx); 1475 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1476 struct mlx5_hlist_entry *entry); 1477 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1478 uint32_t table_level, uint8_t egress, uint8_t transfer, 1479 bool external, const struct mlx5_flow_tunnel *tunnel, 1480 uint32_t group_id, uint8_t dummy, 1481 uint32_t table_id, struct rte_flow_error *error); 1482 1483 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1484 uint64_t key, void *cb_ctx); 1485 int flow_dv_tag_match_cb(struct mlx5_hlist *list, 1486 struct mlx5_hlist_entry *entry, uint64_t key, 1487 void *cb_ctx); 1488 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1489 struct mlx5_hlist_entry *entry); 1490 1491 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1492 struct mlx5_hlist_entry *entry, 1493 uint64_t key, void *cb_ctx); 1494 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1495 uint64_t key, void *ctx); 1496 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1497 struct mlx5_hlist_entry *entry); 1498 1499 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1500 uint64_t key, void *ctx); 1501 int flow_dv_mreg_match_cb(struct mlx5_hlist *list, 1502 struct mlx5_hlist_entry *entry, uint64_t key, 1503 void *cb_ctx); 1504 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1505 struct mlx5_hlist_entry *entry); 1506 1507 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1508 struct mlx5_hlist_entry *entry, 1509 uint64_t key, void *cb_ctx); 1510 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1511 uint64_t key, void *cb_ctx); 1512 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1513 struct mlx5_hlist_entry *entry); 1514 1515 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1516 struct mlx5_cache_entry *entry, void *ctx); 1517 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1518 struct mlx5_cache_entry *entry, void *ctx); 1519 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1520 struct mlx5_cache_entry *entry); 1521 1522 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1523 struct mlx5_cache_entry *entry, void *cb_ctx); 1524 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1525 struct mlx5_cache_entry *entry, void *cb_ctx); 1526 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1527 struct mlx5_cache_entry *entry); 1528 1529 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1530 struct mlx5_cache_entry *entry, void *cb_ctx); 1531 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1532 (struct mlx5_cache_list *list, 1533 struct mlx5_cache_entry *entry, void *cb_ctx); 1534 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1535 struct mlx5_cache_entry *entry); 1536 1537 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1538 struct mlx5_cache_entry *entry, void *cb_ctx); 1539 struct mlx5_cache_entry *flow_dv_sample_create_cb 1540 (struct mlx5_cache_list *list, 1541 struct mlx5_cache_entry *entry, void *cb_ctx); 1542 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1543 struct mlx5_cache_entry *entry); 1544 1545 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1546 struct mlx5_cache_entry *entry, void *cb_ctx); 1547 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1548 (struct mlx5_cache_list *list, 1549 struct mlx5_cache_entry *entry, void *cb_ctx); 1550 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1551 struct mlx5_cache_entry *entry); 1552 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1553 uint32_t age_idx); 1554 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1555 const struct rte_flow_item *item, 1556 struct rte_flow_error *error); 1557 void flow_release_workspace(void *data); 1558 int mlx5_flow_os_init_workspace_once(void); 1559 void *mlx5_flow_os_get_specific_workspace(void); 1560 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1561 void mlx5_flow_os_release_workspace(void); 1562 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev); 1563 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx); 1564 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 1565 const struct rte_flow_action *actions[RTE_COLORS], 1566 struct rte_flow_attr *attr, 1567 bool *is_rss, 1568 uint8_t *domain_bitmap, 1569 bool *is_def_policy, 1570 struct rte_mtr_error *error); 1571 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 1572 struct mlx5_flow_meter_policy *mtr_policy); 1573 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 1574 struct mlx5_flow_meter_policy *mtr_policy, 1575 const struct rte_flow_action *actions[RTE_COLORS], 1576 struct rte_mtr_error *error); 1577 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 1578 struct mlx5_flow_meter_policy *mtr_policy); 1579 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 1580 struct mlx5_flow_meter_policy *mtr_policy); 1581 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev); 1582 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev); 1583 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1584 struct mlx5_flow_handle *dev_handle); 1585 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1586