1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 #include <rte_atomic.h> 15 #include <rte_alarm.h> 16 #include <rte_mtr.h> 17 18 #include <mlx5_glue.h> 19 #include <mlx5_prm.h> 20 21 #include "mlx5.h" 22 23 /* Private rte flow items. */ 24 enum mlx5_rte_flow_item_type { 25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 26 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 29 }; 30 31 /* Private (internal) rte flow actions. */ 32 enum mlx5_rte_flow_action_type { 33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 35 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 38 }; 39 40 /* Matches on selected register. */ 41 struct mlx5_rte_flow_item_tag { 42 enum modify_reg id; 43 uint32_t data; 44 }; 45 46 /* Modify selected register. */ 47 struct mlx5_rte_flow_action_set_tag { 48 enum modify_reg id; 49 uint32_t data; 50 }; 51 52 struct mlx5_flow_action_copy_mreg { 53 enum modify_reg dst; 54 enum modify_reg src; 55 }; 56 57 /* Matches on source queue. */ 58 struct mlx5_rte_flow_item_tx_queue { 59 uint32_t queue; 60 }; 61 62 /* Feature name to allocate metadata register. */ 63 enum mlx5_feature_name { 64 MLX5_HAIRPIN_RX, 65 MLX5_HAIRPIN_TX, 66 MLX5_METADATA_RX, 67 MLX5_METADATA_TX, 68 MLX5_METADATA_FDB, 69 MLX5_FLOW_MARK, 70 MLX5_APP_TAG, 71 MLX5_COPY_MARK, 72 MLX5_MTR_COLOR, 73 MLX5_MTR_SFX, 74 }; 75 76 /* Pattern outer Layer bits. */ 77 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 78 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 80 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 81 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 82 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 83 84 /* Pattern inner Layer bits. */ 85 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 86 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 87 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 88 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 89 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 90 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 91 92 /* Pattern tunnel Layer bits. */ 93 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 94 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 95 #define MLX5_FLOW_LAYER_GRE (1u << 14) 96 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 97 /* List of tunnel Layer bits continued below. */ 98 99 /* General pattern items bits. */ 100 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 101 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 102 #define MLX5_FLOW_ITEM_TAG (1u << 18) 103 #define MLX5_FLOW_ITEM_MARK (1u << 19) 104 105 /* Pattern MISC bits. */ 106 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 107 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 108 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 109 110 /* Pattern tunnel Layer bits (continued). */ 111 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 112 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 113 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 114 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 115 116 /* Queue items. */ 117 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 118 119 /* Pattern tunnel Layer bits (continued). */ 120 #define MLX5_FLOW_LAYER_GTP (1u << 28) 121 122 /* Pattern eCPRI Layer bit. */ 123 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 124 125 /* Outer Masks. */ 126 #define MLX5_FLOW_LAYER_OUTER_L3 \ 127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 128 #define MLX5_FLOW_LAYER_OUTER_L4 \ 129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 130 #define MLX5_FLOW_LAYER_OUTER \ 131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 132 MLX5_FLOW_LAYER_OUTER_L4) 133 134 /* Tunnel Masks. */ 135 #define MLX5_FLOW_LAYER_TUNNEL \ 136 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 137 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 138 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 139 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 140 141 /* Inner Masks. */ 142 #define MLX5_FLOW_LAYER_INNER_L3 \ 143 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 144 #define MLX5_FLOW_LAYER_INNER_L4 \ 145 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 146 #define MLX5_FLOW_LAYER_INNER \ 147 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 148 MLX5_FLOW_LAYER_INNER_L4) 149 150 /* Layer Masks. */ 151 #define MLX5_FLOW_LAYER_L2 \ 152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 153 #define MLX5_FLOW_LAYER_L3_IPV4 \ 154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 155 #define MLX5_FLOW_LAYER_L3_IPV6 \ 156 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 157 #define MLX5_FLOW_LAYER_L3 \ 158 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 159 #define MLX5_FLOW_LAYER_L4 \ 160 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 161 162 /* Actions */ 163 #define MLX5_FLOW_ACTION_DROP (1u << 0) 164 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 165 #define MLX5_FLOW_ACTION_RSS (1u << 2) 166 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 167 #define MLX5_FLOW_ACTION_MARK (1u << 4) 168 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 169 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 170 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 171 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 172 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 174 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 175 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 176 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 177 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 178 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 179 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 180 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 181 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 182 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 183 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 184 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 185 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 186 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 187 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 188 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 189 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 190 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 191 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 192 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 193 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 194 #define MLX5_FLOW_ACTION_METER (1ull << 31) 195 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 196 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 197 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 198 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 199 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 200 201 #define MLX5_FLOW_FATE_ACTIONS \ 202 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 203 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 204 MLX5_FLOW_ACTION_DEFAULT_MISS) 205 206 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 208 MLX5_FLOW_ACTION_JUMP) 209 210 211 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 212 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 213 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 214 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 215 MLX5_FLOW_ACTION_SET_TP_SRC | \ 216 MLX5_FLOW_ACTION_SET_TP_DST | \ 217 MLX5_FLOW_ACTION_SET_TTL | \ 218 MLX5_FLOW_ACTION_DEC_TTL | \ 219 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 220 MLX5_FLOW_ACTION_SET_MAC_DST | \ 221 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 222 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 223 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 224 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 225 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 226 MLX5_FLOW_ACTION_SET_TAG | \ 227 MLX5_FLOW_ACTION_MARK_EXT | \ 228 MLX5_FLOW_ACTION_SET_META | \ 229 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 230 MLX5_FLOW_ACTION_SET_IPV6_DSCP) 231 232 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 233 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 234 235 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 236 237 #ifndef IPPROTO_MPLS 238 #define IPPROTO_MPLS 137 239 #endif 240 241 /* UDP port number for MPLS */ 242 #define MLX5_UDP_PORT_MPLS 6635 243 244 /* UDP port numbers for VxLAN. */ 245 #define MLX5_UDP_PORT_VXLAN 4789 246 #define MLX5_UDP_PORT_VXLAN_GPE 4790 247 248 /* UDP port numbers for GENEVE. */ 249 #define MLX5_UDP_PORT_GENEVE 6081 250 251 /* Priority reserved for default flows. */ 252 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 253 254 /* 255 * Number of sub priorities. 256 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 257 * matching on the NIC (firmware dependent) L4 most have the higher priority 258 * followed by L3 and ending with L2. 259 */ 260 #define MLX5_PRIORITY_MAP_L2 2 261 #define MLX5_PRIORITY_MAP_L3 1 262 #define MLX5_PRIORITY_MAP_L4 0 263 #define MLX5_PRIORITY_MAP_MAX 3 264 265 /* Valid layer type for IPV4 RSS. */ 266 #define MLX5_IPV4_LAYER_TYPES \ 267 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 268 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 269 ETH_RSS_NONFRAG_IPV4_OTHER) 270 271 /* IBV hash source bits for IPV4. */ 272 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 273 274 /* Valid layer type for IPV6 RSS. */ 275 #define MLX5_IPV6_LAYER_TYPES \ 276 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 277 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 278 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 279 280 /* IBV hash source bits for IPV6. */ 281 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 282 283 /* IBV hash bits for L3 SRC. */ 284 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 285 286 /* IBV hash bits for L3 DST. */ 287 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 288 289 /* IBV hash bits for TCP. */ 290 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 291 IBV_RX_HASH_DST_PORT_TCP) 292 293 /* IBV hash bits for UDP. */ 294 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 295 IBV_RX_HASH_DST_PORT_UDP) 296 297 /* IBV hash bits for L4 SRC. */ 298 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 299 IBV_RX_HASH_SRC_PORT_UDP) 300 301 /* IBV hash bits for L4 DST. */ 302 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 303 IBV_RX_HASH_DST_PORT_UDP) 304 305 /* Geneve header first 16Bit */ 306 #define MLX5_GENEVE_VER_MASK 0x3 307 #define MLX5_GENEVE_VER_SHIFT 14 308 #define MLX5_GENEVE_VER_VAL(a) \ 309 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 310 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 311 #define MLX5_GENEVE_OPTLEN_SHIFT 7 312 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 313 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 314 #define MLX5_GENEVE_OAMF_MASK 0x1 315 #define MLX5_GENEVE_OAMF_SHIFT 7 316 #define MLX5_GENEVE_OAMF_VAL(a) \ 317 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 318 #define MLX5_GENEVE_CRITO_MASK 0x1 319 #define MLX5_GENEVE_CRITO_SHIFT 6 320 #define MLX5_GENEVE_CRITO_VAL(a) \ 321 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 322 #define MLX5_GENEVE_RSVD_MASK 0x3F 323 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 324 /* 325 * The length of the Geneve options fields, expressed in four byte multiples, 326 * not including the eight byte fixed tunnel. 327 */ 328 #define MLX5_GENEVE_OPT_LEN_0 14 329 #define MLX5_GENEVE_OPT_LEN_1 63 330 331 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \ 332 sizeof(struct rte_flow_item_ipv4)) 333 334 /* Software header modify action numbers of a flow. */ 335 #define MLX5_ACT_NUM_MDF_IPV4 1 336 #define MLX5_ACT_NUM_MDF_IPV6 4 337 #define MLX5_ACT_NUM_MDF_MAC 2 338 #define MLX5_ACT_NUM_MDF_VID 1 339 #define MLX5_ACT_NUM_MDF_PORT 2 340 #define MLX5_ACT_NUM_MDF_TTL 1 341 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 342 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 343 #define MLX5_ACT_NUM_MDF_TCPACK 1 344 #define MLX5_ACT_NUM_SET_REG 1 345 #define MLX5_ACT_NUM_SET_TAG 1 346 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 347 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 348 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 349 #define MLX5_ACT_NUM_SET_DSCP 1 350 351 enum mlx5_flow_drv_type { 352 MLX5_FLOW_TYPE_MIN, 353 MLX5_FLOW_TYPE_DV, 354 MLX5_FLOW_TYPE_VERBS, 355 MLX5_FLOW_TYPE_MAX, 356 }; 357 358 /* Fate action type. */ 359 enum mlx5_flow_fate_type { 360 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 361 MLX5_FLOW_FATE_QUEUE, 362 MLX5_FLOW_FATE_JUMP, 363 MLX5_FLOW_FATE_PORT_ID, 364 MLX5_FLOW_FATE_DROP, 365 MLX5_FLOW_FATE_DEFAULT_MISS, 366 MLX5_FLOW_FATE_MAX, 367 }; 368 369 /* Matcher PRM representation */ 370 struct mlx5_flow_dv_match_params { 371 size_t size; 372 /**< Size of match value. Do NOT split size and key! */ 373 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 374 /**< Matcher value. This value is used as the mask or as a key. */ 375 }; 376 377 /* Matcher structure. */ 378 struct mlx5_flow_dv_matcher { 379 LIST_ENTRY(mlx5_flow_dv_matcher) next; 380 /**< Pointer to the next element. */ 381 struct mlx5_flow_tbl_resource *tbl; 382 /**< Pointer to the table(group) the matcher associated with. */ 383 rte_atomic32_t refcnt; /**< Reference counter. */ 384 void *matcher_object; /**< Pointer to DV matcher */ 385 uint16_t crc; /**< CRC of key. */ 386 uint16_t priority; /**< Priority of matcher. */ 387 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 388 }; 389 390 #define MLX5_ENCAP_MAX_LEN 132 391 392 /* Encap/decap resource key of the hash organization. */ 393 union mlx5_flow_encap_decap_key { 394 struct { 395 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 396 uint32_t refmt_type:8; /**< Header reformat type. */ 397 uint32_t buf_size:8; /**< Encap buf size. */ 398 uint32_t table_level:8; /**< Root table or not. */ 399 uint32_t cksum; /**< Encap buf check sum. */ 400 }; 401 uint64_t v64; /**< full 64bits value of key */ 402 }; 403 404 /* Encap/decap resource structure. */ 405 struct mlx5_flow_dv_encap_decap_resource { 406 struct mlx5_hlist_entry entry; 407 /* Pointer to next element. */ 408 rte_atomic32_t refcnt; /**< Reference counter. */ 409 void *action; 410 /**< Encap/decap action object. */ 411 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 412 size_t size; 413 uint8_t reformat_type; 414 uint8_t ft_type; 415 uint64_t flags; /**< Flags for RDMA API. */ 416 uint32_t idx; /**< Index for the index memory pool. */ 417 }; 418 419 /* Tag resource structure. */ 420 struct mlx5_flow_dv_tag_resource { 421 struct mlx5_hlist_entry entry; 422 /**< hash list entry for tag resource, tag value as the key. */ 423 void *action; 424 /**< Tag action object. */ 425 rte_atomic32_t refcnt; /**< Reference counter. */ 426 uint32_t idx; /**< Index for the index memory pool. */ 427 }; 428 429 /* 430 * Number of modification commands. 431 * The maximal actions amount in FW is some constant, and it is 16 in the 432 * latest releases. In some old releases, it will be limited to 8. 433 * Since there is no interface to query the capacity, the maximal value should 434 * be used to allow PMD to create the flow. The validation will be done in the 435 * lower driver layer or FW. A failure will be returned if exceeds the maximal 436 * supported actions number on the root table. 437 * On non-root tables, there is no limitation, but 32 is enough right now. 438 */ 439 #define MLX5_MAX_MODIFY_NUM 32 440 #define MLX5_ROOT_TBL_MODIFY_NUM 16 441 442 /* Modify resource structure */ 443 struct mlx5_flow_dv_modify_hdr_resource { 444 struct mlx5_hlist_entry entry; 445 /* Pointer to next element. */ 446 rte_atomic32_t refcnt; /**< Reference counter. */ 447 void *action; 448 /**< Modify header action object. */ 449 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 450 uint32_t actions_num; /**< Number of modification actions. */ 451 uint64_t flags; /**< Flags for RDMA API. */ 452 struct mlx5_modification_cmd actions[]; 453 /**< Modification actions. */ 454 }; 455 456 /* Modify resource key of the hash organization. */ 457 union mlx5_flow_modify_hdr_key { 458 struct { 459 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 460 uint32_t actions_num:5; /**< Number of modification actions. */ 461 uint32_t group:19; /**< Flow group id. */ 462 uint32_t cksum; /**< Actions check sum. */ 463 }; 464 uint64_t v64; /**< full 64bits value of key */ 465 }; 466 467 /* Jump action resource structure. */ 468 struct mlx5_flow_dv_jump_tbl_resource { 469 rte_atomic32_t refcnt; /**< Reference counter. */ 470 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 471 void *action; /**< Pointer to the rdma core action. */ 472 }; 473 474 /* Port ID resource structure. */ 475 struct mlx5_flow_dv_port_id_action_resource { 476 ILIST_ENTRY(uint32_t)next; 477 /* Pointer to next element. */ 478 rte_atomic32_t refcnt; /**< Reference counter. */ 479 void *action; 480 /**< Action object. */ 481 uint32_t port_id; /**< Port ID value. */ 482 }; 483 484 /* Push VLAN action resource structure */ 485 struct mlx5_flow_dv_push_vlan_action_resource { 486 ILIST_ENTRY(uint32_t)next; 487 /* Pointer to next element. */ 488 rte_atomic32_t refcnt; /**< Reference counter. */ 489 void *action; /**< Action object. */ 490 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 491 rte_be32_t vlan_tag; /**< VLAN tag value. */ 492 }; 493 494 /* Metadata register copy table entry. */ 495 struct mlx5_flow_mreg_copy_resource { 496 /* 497 * Hash list entry for copy table. 498 * - Key is 32/64-bit MARK action ID. 499 * - MUST be the first entry. 500 */ 501 struct mlx5_hlist_entry hlist_ent; 502 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 503 /* List entry for device flows. */ 504 uint32_t refcnt; /* Reference counter. */ 505 uint32_t appcnt; /* Apply/Remove counter. */ 506 uint32_t idx; 507 uint32_t rix_flow; /* Built flow for copy. */ 508 }; 509 510 /* Table data structure of the hash organization. */ 511 struct mlx5_flow_tbl_data_entry { 512 struct mlx5_hlist_entry entry; 513 /**< hash list entry, 64-bits key inside. */ 514 struct mlx5_flow_tbl_resource tbl; 515 /**< flow table resource. */ 516 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 517 /**< matchers' header associated with the flow table. */ 518 struct mlx5_flow_dv_jump_tbl_resource jump; 519 /**< jump resource, at most one for each table created. */ 520 uint32_t idx; /**< index for the indexed mempool. */ 521 }; 522 523 /* Sub rdma-core actions list. */ 524 struct mlx5_flow_sub_actions_list { 525 uint32_t actions_num; /**< Number of sample actions. */ 526 uint64_t action_flags; 527 void *dr_queue_action; 528 void *dr_tag_action; 529 void *dr_cnt_action; 530 void *dr_port_id_action; 531 void *dr_encap_action; 532 }; 533 534 /* Sample sub-actions resource list. */ 535 struct mlx5_flow_sub_actions_idx { 536 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 537 uint32_t rix_tag; /**< Index to the tag action. */ 538 uint32_t cnt; 539 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 540 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 541 }; 542 543 /* Sample action resource structure. */ 544 struct mlx5_flow_dv_sample_resource { 545 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */ 546 uint32_t refcnt; /**< Reference counter. */ 547 void *verbs_action; /**< Verbs sample action object. */ 548 uint8_t ft_type; /** Flow Table Type */ 549 uint32_t ft_id; /** Flow Table Level */ 550 uint32_t ratio; /** Sample Ratio */ 551 uint64_t set_action; /** Restore reg_c0 value */ 552 void *normal_path_tbl; /** Flow Table pointer */ 553 void *default_miss; /** default_miss dr_action. */ 554 struct mlx5_flow_sub_actions_idx sample_idx; 555 /**< Action index resources. */ 556 struct mlx5_flow_sub_actions_list sample_act; 557 /**< Action resources. */ 558 }; 559 560 #define MLX5_MAX_DEST_NUM 2 561 562 /* Destination array action resource structure. */ 563 struct mlx5_flow_dv_dest_array_resource { 564 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */ 565 uint32_t refcnt; /**< Reference counter. */ 566 uint8_t ft_type; /** Flow Table Type */ 567 uint8_t num_of_dest; /**< Number of destination actions. */ 568 void *action; /**< Pointer to the rdma core action. */ 569 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 570 /**< Action index resources. */ 571 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 572 /**< Action resources. */ 573 }; 574 575 /* Verbs specification header. */ 576 struct ibv_spec_header { 577 enum ibv_flow_spec_type type; 578 uint16_t size; 579 }; 580 581 /* RSS description. */ 582 struct mlx5_flow_rss_desc { 583 uint32_t level; 584 uint32_t queue_num; /**< Number of entries in @p queue. */ 585 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 586 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 587 uint16_t queue[]; /**< Destination queues to redirect traffic to. */ 588 }; 589 590 /* PMD flow priority for tunnel */ 591 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 592 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 593 594 595 /** Device flow handle structure for DV mode only. */ 596 struct mlx5_flow_handle_dv { 597 /* Flow DV api: */ 598 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 599 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 600 /**< Pointer to modify header resource in cache. */ 601 uint32_t rix_encap_decap; 602 /**< Index to encap/decap resource in cache. */ 603 uint32_t rix_push_vlan; 604 /**< Index to push VLAN action resource in cache. */ 605 uint32_t rix_tag; 606 /**< Index to the tag action. */ 607 uint32_t rix_sample; 608 /**< Index to sample action resource in cache. */ 609 uint32_t rix_dest_array; 610 /**< Index to destination array resource in cache. */ 611 } __rte_packed; 612 613 /** Device flow handle structure: used both for creating & destroying. */ 614 struct mlx5_flow_handle { 615 SILIST_ENTRY(uint32_t)next; 616 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 617 /**< Index to next device flow handle. */ 618 uint64_t layers; 619 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 620 void *drv_flow; /**< pointer to driver flow object. */ 621 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 622 uint32_t mark:1; /**< Metadate rxq mark flag. */ 623 uint32_t fate_action:3; /**< Fate action type. */ 624 union { 625 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 626 uint32_t rix_jump; /**< Index to the jump action resource. */ 627 uint32_t rix_port_id_action; 628 /**< Index to port ID action resource. */ 629 uint32_t rix_fate; 630 /**< Generic value indicates the fate action. */ 631 uint32_t rix_default_fate; 632 /**< Indicates default miss fate action. */ 633 }; 634 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 635 struct mlx5_flow_handle_dv dvh; 636 #endif 637 } __rte_packed; 638 639 /* 640 * Size for Verbs device flow handle structure only. Do not use the DV only 641 * structure in Verbs. No DV flows attributes will be accessed. 642 * Macro offsetof() could also be used here. 643 */ 644 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 645 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 646 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 647 #else 648 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 649 #endif 650 651 /* 652 * Max number of actions per DV flow. 653 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 654 * in rdma-core file providers/mlx5/verbs.c. 655 */ 656 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 657 658 /** Device flow structure only for DV flow creation. */ 659 struct mlx5_flow_dv_workspace { 660 uint32_t group; /**< The group index. */ 661 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 662 int actions_n; /**< number of actions. */ 663 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 664 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 665 /**< Pointer to encap/decap resource in cache. */ 666 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 667 /**< Pointer to push VLAN action resource in cache. */ 668 struct mlx5_flow_dv_tag_resource *tag_resource; 669 /**< pointer to the tag action. */ 670 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 671 /**< Pointer to port ID action resource. */ 672 struct mlx5_flow_dv_jump_tbl_resource *jump; 673 /**< Pointer to the jump action resource. */ 674 struct mlx5_flow_dv_match_params value; 675 /**< Holds the value that the packet is compared to. */ 676 struct mlx5_flow_dv_sample_resource *sample_res; 677 /**< Pointer to the sample action resource. */ 678 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 679 /**< Pointer to the destination array resource. */ 680 }; 681 682 /* 683 * Maximal Verbs flow specifications & actions size. 684 * Some elements are mutually exclusive, but enough space should be allocated. 685 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 686 * 2. One tunnel header (exception: GRE + MPLS), 687 * SPEC length: GRE == tunnel. 688 * Actions: 1. 1 Mark OR Flag. 689 * 2. 1 Drop (if any). 690 * 3. No limitation for counters, but it makes no sense to support too 691 * many counters in a single device flow. 692 */ 693 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 694 #define MLX5_VERBS_MAX_SPEC_SIZE \ 695 ( \ 696 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 697 sizeof(struct ibv_flow_spec_ipv6) + \ 698 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 699 sizeof(struct ibv_flow_spec_gre) + \ 700 sizeof(struct ibv_flow_spec_mpls)) \ 701 ) 702 #else 703 #define MLX5_VERBS_MAX_SPEC_SIZE \ 704 ( \ 705 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 706 sizeof(struct ibv_flow_spec_ipv6) + \ 707 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 708 sizeof(struct ibv_flow_spec_tunnel)) \ 709 ) 710 #endif 711 712 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 713 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 714 #define MLX5_VERBS_MAX_ACT_SIZE \ 715 ( \ 716 sizeof(struct ibv_flow_spec_action_tag) + \ 717 sizeof(struct ibv_flow_spec_action_drop) + \ 718 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 719 ) 720 #else 721 #define MLX5_VERBS_MAX_ACT_SIZE \ 722 ( \ 723 sizeof(struct ibv_flow_spec_action_tag) + \ 724 sizeof(struct ibv_flow_spec_action_drop) \ 725 ) 726 #endif 727 728 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 729 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 730 731 /** Device flow structure only for Verbs flow creation. */ 732 struct mlx5_flow_verbs_workspace { 733 unsigned int size; /**< Size of the attribute. */ 734 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 735 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 736 /**< Specifications & actions buffer of verbs flow. */ 737 }; 738 739 /** Maximal number of device sub-flows supported. */ 740 #define MLX5_NUM_MAX_DEV_FLOWS 32 741 742 /** Device flow structure. */ 743 struct mlx5_flow { 744 struct rte_flow *flow; /**< Pointer to the main flow. */ 745 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 746 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 747 uint64_t act_flags; 748 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 749 bool external; /**< true if the flow is created external to PMD. */ 750 uint8_t ingress; /**< 1 if the flow is ingress. */ 751 union { 752 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 753 struct mlx5_flow_dv_workspace dv; 754 #endif 755 struct mlx5_flow_verbs_workspace verbs; 756 }; 757 struct mlx5_flow_handle *handle; 758 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 759 }; 760 761 /* Flow meter state. */ 762 #define MLX5_FLOW_METER_DISABLE 0 763 #define MLX5_FLOW_METER_ENABLE 1 764 765 #define MLX5_MAN_WIDTH 8 766 /* Modify this value if enum rte_mtr_color changes. */ 767 #define RTE_MTR_DROPPED RTE_COLORS 768 769 /* Meter policer statistics */ 770 struct mlx5_flow_policer_stats { 771 uint32_t cnt[RTE_COLORS + 1]; 772 /**< Color counter, extra for drop. */ 773 uint64_t stats_mask; 774 /**< Statistics mask for the colors. */ 775 }; 776 777 /* Meter table structure. */ 778 struct mlx5_meter_domain_info { 779 struct mlx5_flow_tbl_resource *tbl; 780 /**< Meter table. */ 781 struct mlx5_flow_tbl_resource *sfx_tbl; 782 /**< Meter suffix table. */ 783 void *any_matcher; 784 /**< Meter color not match default criteria. */ 785 void *color_matcher; 786 /**< Meter color match criteria. */ 787 void *jump_actn; 788 /**< Meter match action. */ 789 void *policer_rules[RTE_MTR_DROPPED + 1]; 790 /**< Meter policer for the match. */ 791 }; 792 793 /* Meter table set for TX RX FDB. */ 794 struct mlx5_meter_domains_infos { 795 uint32_t ref_cnt; 796 /**< Table user count. */ 797 struct mlx5_meter_domain_info egress; 798 /**< TX meter table. */ 799 struct mlx5_meter_domain_info ingress; 800 /**< RX meter table. */ 801 struct mlx5_meter_domain_info transfer; 802 /**< FDB meter table. */ 803 void *drop_actn; 804 /**< Drop action as not matched. */ 805 void *count_actns[RTE_MTR_DROPPED + 1]; 806 /**< Counters for match and unmatched statistics. */ 807 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 808 /**< Flow meter parameter. */ 809 size_t fmp_size; 810 /**< Flow meter parameter size. */ 811 void *meter_action; 812 /**< Flow meter action. */ 813 }; 814 815 /* Meter parameter structure. */ 816 struct mlx5_flow_meter { 817 TAILQ_ENTRY(mlx5_flow_meter) next; 818 /**< Pointer to the next flow meter structure. */ 819 uint32_t idx; /* Index to meter object. */ 820 uint32_t meter_id; 821 /**< Meter id. */ 822 struct mlx5_flow_meter_profile *profile; 823 /**< Meter profile parameters. */ 824 825 /** Policer actions (per meter output color). */ 826 enum rte_mtr_policer_action action[RTE_COLORS]; 827 828 /** Set of stats counters to be enabled. 829 * @see enum rte_mtr_stats_type 830 */ 831 uint64_t stats_mask; 832 833 /**< Rule applies to ingress traffic. */ 834 uint32_t ingress:1; 835 836 /**< Rule applies to egress traffic. */ 837 uint32_t egress:1; 838 /** 839 * Instead of simply matching the properties of traffic as it would 840 * appear on a given DPDK port ID, enabling this attribute transfers 841 * a flow rule to the lowest possible level of any device endpoints 842 * found in the pattern. 843 * 844 * When supported, this effectively enables an application to 845 * re-route traffic not necessarily intended for it (e.g. coming 846 * from or addressed to different physical ports, VFs or 847 * applications) at the device level. 848 * 849 * It complements the behavior of some pattern items such as 850 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 851 * 852 * When transferring flow rules, ingress and egress attributes keep 853 * their original meaning, as if processing traffic emitted or 854 * received by the application. 855 */ 856 uint32_t transfer:1; 857 struct mlx5_meter_domains_infos *mfts; 858 /**< Flow table created for this meter. */ 859 struct mlx5_flow_policer_stats policer_stats; 860 /**< Meter policer statistics. */ 861 uint32_t ref_cnt; 862 /**< Use count. */ 863 uint32_t active_state:1; 864 /**< Meter state. */ 865 uint32_t shared:1; 866 /**< Meter shared or not. */ 867 }; 868 869 /* RFC2697 parameter structure. */ 870 struct mlx5_flow_meter_srtcm_rfc2697_prm { 871 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 872 uint32_t cbs_exponent:5; 873 uint32_t cbs_mantissa:8; 874 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 875 uint32_t cir_exponent:5; 876 uint32_t cir_mantissa:8; 877 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 878 uint32_t ebs_exponent:5; 879 uint32_t ebs_mantissa:8; 880 }; 881 882 /* Flow meter profile structure. */ 883 struct mlx5_flow_meter_profile { 884 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 885 /**< Pointer to the next flow meter structure. */ 886 uint32_t meter_profile_id; /**< Profile id. */ 887 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 888 union { 889 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 890 /**< srtcm_rfc2697 struct. */ 891 }; 892 uint32_t ref_cnt; /**< Use count. */ 893 }; 894 895 /* Fdir flow structure */ 896 struct mlx5_fdir_flow { 897 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */ 898 struct mlx5_fdir *fdir; /* Pointer to fdir. */ 899 uint32_t rix_flow; /* Index to flow. */ 900 }; 901 902 #define HAIRPIN_FLOW_ID_BITS 28 903 904 /* Flow structure. */ 905 struct rte_flow { 906 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 907 uint32_t dev_handles; 908 /**< Device flow handles that are part of the flow. */ 909 uint32_t drv_type:2; /**< Driver type. */ 910 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */ 911 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS; 912 /**< The flow id used for hairpin. */ 913 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */ 914 uint32_t rix_mreg_copy; 915 /**< Index to metadata register copy table resource. */ 916 uint32_t counter; /**< Holds flow counter. */ 917 uint16_t meter; /**< Holds flow meter id. */ 918 } __rte_packed; 919 920 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 921 const struct rte_flow_attr *attr, 922 const struct rte_flow_item items[], 923 const struct rte_flow_action actions[], 924 bool external, 925 int hairpin, 926 struct rte_flow_error *error); 927 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 928 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 929 const struct rte_flow_item items[], 930 const struct rte_flow_action actions[], struct rte_flow_error *error); 931 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 932 struct mlx5_flow *dev_flow, 933 const struct rte_flow_attr *attr, 934 const struct rte_flow_item items[], 935 const struct rte_flow_action actions[], 936 struct rte_flow_error *error); 937 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 938 struct rte_flow_error *error); 939 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 940 struct rte_flow *flow); 941 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 942 struct rte_flow *flow); 943 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 944 struct rte_flow *flow, 945 const struct rte_flow_action *actions, 946 void *data, 947 struct rte_flow_error *error); 948 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 949 (struct rte_eth_dev *dev, 950 const struct mlx5_flow_meter *fm); 951 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 952 struct mlx5_meter_domains_infos *tbls); 953 typedef int (*mlx5_flow_create_policer_rules_t) 954 (struct rte_eth_dev *dev, 955 struct mlx5_flow_meter *fm, 956 const struct rte_flow_attr *attr); 957 typedef int (*mlx5_flow_destroy_policer_rules_t) 958 (struct rte_eth_dev *dev, 959 const struct mlx5_flow_meter *fm, 960 const struct rte_flow_attr *attr); 961 typedef uint32_t (*mlx5_flow_counter_alloc_t) 962 (struct rte_eth_dev *dev); 963 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 964 uint32_t cnt); 965 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 966 uint32_t cnt, 967 bool clear, uint64_t *pkts, 968 uint64_t *bytes); 969 typedef int (*mlx5_flow_get_aged_flows_t) 970 (struct rte_eth_dev *dev, 971 void **context, 972 uint32_t nb_contexts, 973 struct rte_flow_error *error); 974 struct mlx5_flow_driver_ops { 975 mlx5_flow_validate_t validate; 976 mlx5_flow_prepare_t prepare; 977 mlx5_flow_translate_t translate; 978 mlx5_flow_apply_t apply; 979 mlx5_flow_remove_t remove; 980 mlx5_flow_destroy_t destroy; 981 mlx5_flow_query_t query; 982 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 983 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 984 mlx5_flow_create_policer_rules_t create_policer_rules; 985 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 986 mlx5_flow_counter_alloc_t counter_alloc; 987 mlx5_flow_counter_free_t counter_free; 988 mlx5_flow_counter_query_t counter_query; 989 mlx5_flow_get_aged_flows_t get_aged_flows; 990 }; 991 992 /* mlx5_flow.c */ 993 994 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id); 995 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool); 996 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id); 997 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, 998 uint32_t id); 999 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, 1000 bool external, uint32_t group, bool fdb_def_rule, 1001 uint32_t *table, struct rte_flow_error *error); 1002 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1003 int tunnel, uint64_t layer_types, 1004 uint64_t hash_fields); 1005 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1006 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1007 uint32_t subpriority); 1008 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1009 enum mlx5_feature_name feature, 1010 uint32_t id, 1011 struct rte_flow_error *error); 1012 const struct rte_flow_action *mlx5_flow_find_action 1013 (const struct rte_flow_action *actions, 1014 enum rte_flow_action_type action); 1015 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1016 const struct rte_flow_attr *attr, 1017 struct rte_flow_error *error); 1018 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1019 const struct rte_flow_attr *attr, 1020 struct rte_flow_error *error); 1021 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1022 const struct rte_flow_attr *attr, 1023 struct rte_flow_error *error); 1024 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1025 uint64_t action_flags, 1026 const struct rte_flow_attr *attr, 1027 struct rte_flow_error *error); 1028 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1029 uint64_t action_flags, 1030 struct rte_eth_dev *dev, 1031 const struct rte_flow_attr *attr, 1032 struct rte_flow_error *error); 1033 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1034 uint64_t action_flags, 1035 struct rte_eth_dev *dev, 1036 const struct rte_flow_attr *attr, 1037 uint64_t item_flags, 1038 struct rte_flow_error *error); 1039 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1040 const struct rte_flow_attr *attr, 1041 struct rte_flow_error *error); 1042 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1043 const struct rte_flow_attr *attributes, 1044 struct rte_flow_error *error); 1045 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1046 const uint8_t *mask, 1047 const uint8_t *nic_mask, 1048 unsigned int size, 1049 struct rte_flow_error *error); 1050 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1051 uint64_t item_flags, 1052 struct rte_flow_error *error); 1053 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1054 uint64_t item_flags, 1055 uint8_t target_protocol, 1056 struct rte_flow_error *error); 1057 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1058 uint64_t item_flags, 1059 const struct rte_flow_item *gre_item, 1060 struct rte_flow_error *error); 1061 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1062 uint64_t item_flags, 1063 uint64_t last_item, 1064 uint16_t ether_type, 1065 const struct rte_flow_item_ipv4 *acc_mask, 1066 struct rte_flow_error *error); 1067 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1068 uint64_t item_flags, 1069 uint64_t last_item, 1070 uint16_t ether_type, 1071 const struct rte_flow_item_ipv6 *acc_mask, 1072 struct rte_flow_error *error); 1073 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1074 const struct rte_flow_item *item, 1075 uint64_t item_flags, 1076 uint64_t prev_layer, 1077 struct rte_flow_error *error); 1078 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1079 uint64_t item_flags, 1080 uint8_t target_protocol, 1081 const struct rte_flow_item_tcp *flow_mask, 1082 struct rte_flow_error *error); 1083 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1084 uint64_t item_flags, 1085 uint8_t target_protocol, 1086 struct rte_flow_error *error); 1087 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1088 uint64_t item_flags, 1089 struct rte_eth_dev *dev, 1090 struct rte_flow_error *error); 1091 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1092 uint64_t item_flags, 1093 struct rte_flow_error *error); 1094 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1095 uint64_t item_flags, 1096 struct rte_eth_dev *dev, 1097 struct rte_flow_error *error); 1098 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1099 uint64_t item_flags, 1100 uint8_t target_protocol, 1101 struct rte_flow_error *error); 1102 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1103 uint64_t item_flags, 1104 uint8_t target_protocol, 1105 struct rte_flow_error *error); 1106 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1107 uint64_t item_flags, 1108 uint8_t target_protocol, 1109 struct rte_flow_error *error); 1110 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1111 uint64_t item_flags, 1112 struct rte_eth_dev *dev, 1113 struct rte_flow_error *error); 1114 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1115 uint64_t item_flags, 1116 uint64_t last_item, 1117 uint16_t ether_type, 1118 const struct rte_flow_item_ecpri *acc_mask, 1119 struct rte_flow_error *error); 1120 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1121 (struct rte_eth_dev *dev, 1122 const struct mlx5_flow_meter *fm); 1123 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1124 struct mlx5_meter_domains_infos *tbl); 1125 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1126 struct mlx5_flow_meter *fm, 1127 const struct rte_flow_attr *attr); 1128 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1129 struct mlx5_flow_meter *fm, 1130 const struct rte_flow_attr *attr); 1131 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1132 struct rte_mtr_error *error); 1133 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1134