1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include "mlx5.h" 25 #include "mlx5_prm.h" 26 27 /* Pattern outer Layer bits. */ 28 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 29 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 30 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 31 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 32 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 33 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 34 35 /* Pattern inner Layer bits. */ 36 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 37 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 38 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 39 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 40 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 41 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 42 43 /* Pattern tunnel Layer bits. */ 44 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 45 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 46 #define MLX5_FLOW_LAYER_GRE (1u << 14) 47 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 48 49 /* General pattern items bits. */ 50 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 51 52 /* Outer Masks. */ 53 #define MLX5_FLOW_LAYER_OUTER_L3 \ 54 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 55 #define MLX5_FLOW_LAYER_OUTER_L4 \ 56 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 57 #define MLX5_FLOW_LAYER_OUTER \ 58 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 59 MLX5_FLOW_LAYER_OUTER_L4) 60 61 /* Tunnel Masks. */ 62 #define MLX5_FLOW_LAYER_TUNNEL \ 63 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 64 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS) 65 66 /* Inner Masks. */ 67 #define MLX5_FLOW_LAYER_INNER_L3 \ 68 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 69 #define MLX5_FLOW_LAYER_INNER_L4 \ 70 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 71 #define MLX5_FLOW_LAYER_INNER \ 72 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 73 MLX5_FLOW_LAYER_INNER_L4) 74 75 /* Layer Masks. */ 76 #define MLX5_FLOW_LAYER_L2 \ 77 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 78 #define MLX5_FLOW_LAYER_L3_IPV4 \ 79 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 80 #define MLX5_FLOW_LAYER_L3_IPV6 \ 81 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 82 #define MLX5_FLOW_LAYER_L3 \ 83 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 84 #define MLX5_FLOW_LAYER_L4 \ 85 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 86 87 /* Actions */ 88 #define MLX5_FLOW_ACTION_DROP (1u << 0) 89 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 90 #define MLX5_FLOW_ACTION_RSS (1u << 2) 91 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 92 #define MLX5_FLOW_ACTION_MARK (1u << 4) 93 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 94 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 95 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 96 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 97 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 98 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 99 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 100 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 101 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 102 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 103 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 104 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 105 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 106 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 107 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 108 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 109 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 110 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 111 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 112 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 113 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 114 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 115 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 116 117 #define MLX5_FLOW_FATE_ACTIONS \ 118 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 119 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) 120 121 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 122 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 123 MLX5_FLOW_ACTION_RAW_ENCAP) 124 125 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 126 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 127 MLX5_FLOW_ACTION_RAW_DECAP) 128 129 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 130 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 131 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 132 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 133 MLX5_FLOW_ACTION_SET_TP_SRC | \ 134 MLX5_FLOW_ACTION_SET_TP_DST | \ 135 MLX5_FLOW_ACTION_SET_TTL | \ 136 MLX5_FLOW_ACTION_DEC_TTL | \ 137 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 138 MLX5_FLOW_ACTION_SET_MAC_DST) 139 140 #ifndef IPPROTO_MPLS 141 #define IPPROTO_MPLS 137 142 #endif 143 144 /* UDP port number for MPLS */ 145 #define MLX5_UDP_PORT_MPLS 6635 146 147 /* UDP port numbers for VxLAN. */ 148 #define MLX5_UDP_PORT_VXLAN 4789 149 #define MLX5_UDP_PORT_VXLAN_GPE 4790 150 151 /* Priority reserved for default flows. */ 152 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 153 154 /* 155 * Number of sub priorities. 156 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 157 * matching on the NIC (firmware dependent) L4 most have the higher priority 158 * followed by L3 and ending with L2. 159 */ 160 #define MLX5_PRIORITY_MAP_L2 2 161 #define MLX5_PRIORITY_MAP_L3 1 162 #define MLX5_PRIORITY_MAP_L4 0 163 #define MLX5_PRIORITY_MAP_MAX 3 164 165 /* Valid layer type for IPV4 RSS. */ 166 #define MLX5_IPV4_LAYER_TYPES \ 167 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 168 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 169 ETH_RSS_NONFRAG_IPV4_OTHER) 170 171 /* IBV hash source bits for IPV4. */ 172 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 173 174 /* Valid layer type for IPV6 RSS. */ 175 #define MLX5_IPV6_LAYER_TYPES \ 176 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 177 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 178 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 179 180 /* IBV hash source bits for IPV6. */ 181 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 182 183 enum mlx5_flow_drv_type { 184 MLX5_FLOW_TYPE_MIN, 185 MLX5_FLOW_TYPE_DV, 186 MLX5_FLOW_TYPE_TCF, 187 MLX5_FLOW_TYPE_VERBS, 188 MLX5_FLOW_TYPE_MAX, 189 }; 190 191 /* Matcher PRM representation */ 192 struct mlx5_flow_dv_match_params { 193 size_t size; 194 /**< Size of match value. Do NOT split size and key! */ 195 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 196 /**< Matcher value. This value is used as the mask or as a key. */ 197 }; 198 199 /* Matcher structure. */ 200 struct mlx5_flow_dv_matcher { 201 LIST_ENTRY(mlx5_flow_dv_matcher) next; 202 /* Pointer to the next element. */ 203 rte_atomic32_t refcnt; /**< Reference counter. */ 204 void *matcher_object; /**< Pointer to DV matcher */ 205 uint16_t crc; /**< CRC of key. */ 206 uint16_t priority; /**< Priority of matcher. */ 207 uint8_t egress; /**< Egress matcher. */ 208 uint32_t group; /**< The matcher group. */ 209 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 210 }; 211 212 #define MLX5_ENCAP_MAX_LEN 132 213 214 /* Encap/decap resource structure. */ 215 struct mlx5_flow_dv_encap_decap_resource { 216 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 217 /* Pointer to next element. */ 218 rte_atomic32_t refcnt; /**< Reference counter. */ 219 void *verbs_action; 220 /**< Verbs encap/decap action object. */ 221 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 222 size_t size; 223 uint8_t reformat_type; 224 uint8_t ft_type; 225 uint64_t flags; /**< Flags for RDMA API. */ 226 }; 227 228 /* Tag resource structure. */ 229 struct mlx5_flow_dv_tag_resource { 230 LIST_ENTRY(mlx5_flow_dv_tag_resource) next; 231 /* Pointer to next element. */ 232 rte_atomic32_t refcnt; /**< Reference counter. */ 233 void *action; 234 /**< Verbs tag action object. */ 235 uint32_t tag; /**< the tag value. */ 236 }; 237 238 /* Number of modification commands. */ 239 #define MLX5_MODIFY_NUM 8 240 241 /* Modify resource structure */ 242 struct mlx5_flow_dv_modify_hdr_resource { 243 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 244 /* Pointer to next element. */ 245 rte_atomic32_t refcnt; /**< Reference counter. */ 246 struct ibv_flow_action *verbs_action; 247 /**< Verbs modify header action object. */ 248 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 249 uint32_t actions_num; /**< Number of modification actions. */ 250 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM]; 251 /**< Modification actions. */ 252 }; 253 254 /* Jump action resource structure. */ 255 struct mlx5_flow_dv_jump_tbl_resource { 256 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next; 257 /* Pointer to next element. */ 258 rte_atomic32_t refcnt; /**< Reference counter. */ 259 void *action; /**< Pointer to the rdma core action. */ 260 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 261 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */ 262 }; 263 264 /* 265 * Max number of actions per DV flow. 266 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 267 * In rdma-core file providers/mlx5/verbs.c 268 */ 269 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 270 271 /* DV flows structure. */ 272 struct mlx5_flow_dv { 273 uint64_t hash_fields; /**< Fields that participate in the hash. */ 274 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 275 /* Flow DV api: */ 276 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 277 struct mlx5_flow_dv_match_params value; 278 /**< Holds the value that the packet is compared to. */ 279 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 280 /**< Pointer to encap/decap resource in cache. */ 281 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 282 /**< Pointer to modify header resource in cache. */ 283 struct ibv_flow *flow; /**< Installed flow. */ 284 struct mlx5_flow_dv_jump_tbl_resource *jump; 285 /**< Pointer to the jump action resource. */ 286 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 287 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 288 /**< Action list. */ 289 #endif 290 int actions_n; /**< number of actions. */ 291 }; 292 293 /** Linux TC flower driver for E-Switch flow. */ 294 struct mlx5_flow_tcf { 295 struct nlmsghdr *nlh; 296 struct tcmsg *tcm; 297 uint32_t *ptc_flags; /**< tc rule applied flags. */ 298 union { /**< Tunnel encap/decap descriptor. */ 299 struct flow_tcf_tunnel_hdr *tunnel; 300 struct flow_tcf_vxlan_decap *vxlan_decap; 301 struct flow_tcf_vxlan_encap *vxlan_encap; 302 }; 303 uint32_t applied:1; /**< Whether rule is currently applied. */ 304 #ifndef NDEBUG 305 uint32_t nlsize; /**< Size of NL message buffer for debug check. */ 306 #endif 307 }; 308 309 /* Verbs specification header. */ 310 struct ibv_spec_header { 311 enum ibv_flow_spec_type type; 312 uint16_t size; 313 }; 314 315 /** Handles information leading to a drop fate. */ 316 struct mlx5_flow_verbs { 317 LIST_ENTRY(mlx5_flow_verbs) next; 318 unsigned int size; /**< Size of the attribute. */ 319 struct { 320 struct ibv_flow_attr *attr; 321 /**< Pointer to the Specification buffer. */ 322 uint8_t *specs; /**< Pointer to the specifications. */ 323 }; 324 struct ibv_flow *flow; /**< Verbs flow pointer. */ 325 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 326 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 327 }; 328 329 /** Device flow structure. */ 330 struct mlx5_flow { 331 LIST_ENTRY(mlx5_flow) next; 332 struct rte_flow *flow; /**< Pointer to the main flow. */ 333 uint64_t layers; 334 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 335 union { 336 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 337 struct mlx5_flow_dv dv; 338 #endif 339 struct mlx5_flow_tcf tcf; 340 struct mlx5_flow_verbs verbs; 341 }; 342 }; 343 344 /* Counters information. */ 345 struct mlx5_flow_counter { 346 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */ 347 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 348 uint32_t ref_cnt:31; /**< Reference counter. */ 349 uint32_t id; /**< Counter ID. */ 350 union { /**< Holds the counters for the rule. */ 351 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 352 struct ibv_counter_set *cs; 353 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 354 struct ibv_counters *cs; 355 #endif 356 struct mlx5_devx_counter_set *dcs; 357 }; 358 uint64_t hits; /**< Number of packets matched by the rule. */ 359 uint64_t bytes; /**< Number of bytes matched by the rule. */ 360 void *action; /**< Pointer to the dv action. */ 361 }; 362 363 /* Flow structure. */ 364 struct rte_flow { 365 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 366 enum mlx5_flow_drv_type drv_type; /**< Driver type. */ 367 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 368 struct mlx5_flow_dv_tag_resource *tag_resource; 369 /**< pointer to the tag action. */ 370 struct rte_flow_action_rss rss;/**< RSS context. */ 371 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 372 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 373 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 374 /**< Device flows that are part of the flow. */ 375 uint64_t actions; 376 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 377 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 378 uint8_t ingress; /**< 1 if the flow is ingress. */ 379 uint32_t group; /**< The group index. */ 380 }; 381 382 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 383 const struct rte_flow_attr *attr, 384 const struct rte_flow_item items[], 385 const struct rte_flow_action actions[], 386 struct rte_flow_error *error); 387 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 388 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 389 const struct rte_flow_action actions[], struct rte_flow_error *error); 390 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 391 struct mlx5_flow *dev_flow, 392 const struct rte_flow_attr *attr, 393 const struct rte_flow_item items[], 394 const struct rte_flow_action actions[], 395 struct rte_flow_error *error); 396 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 397 struct rte_flow_error *error); 398 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 399 struct rte_flow *flow); 400 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 401 struct rte_flow *flow); 402 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 403 struct rte_flow *flow, 404 const struct rte_flow_action *actions, 405 void *data, 406 struct rte_flow_error *error); 407 struct mlx5_flow_driver_ops { 408 mlx5_flow_validate_t validate; 409 mlx5_flow_prepare_t prepare; 410 mlx5_flow_translate_t translate; 411 mlx5_flow_apply_t apply; 412 mlx5_flow_remove_t remove; 413 mlx5_flow_destroy_t destroy; 414 mlx5_flow_query_t query; 415 }; 416 417 /* mlx5_flow.c */ 418 419 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 420 uint64_t layer_types, 421 uint64_t hash_fields); 422 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 423 uint32_t subpriority); 424 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 425 const struct rte_flow_attr *attr, 426 struct rte_flow_error *error); 427 int mlx5_flow_validate_action_drop(uint64_t action_flags, 428 const struct rte_flow_attr *attr, 429 struct rte_flow_error *error); 430 int mlx5_flow_validate_action_flag(uint64_t action_flags, 431 const struct rte_flow_attr *attr, 432 struct rte_flow_error *error); 433 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 434 uint64_t action_flags, 435 const struct rte_flow_attr *attr, 436 struct rte_flow_error *error); 437 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 438 uint64_t action_flags, 439 struct rte_eth_dev *dev, 440 const struct rte_flow_attr *attr, 441 struct rte_flow_error *error); 442 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 443 uint64_t action_flags, 444 struct rte_eth_dev *dev, 445 const struct rte_flow_attr *attr, 446 struct rte_flow_error *error); 447 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 448 const struct rte_flow_attr *attributes, 449 struct rte_flow_error *error); 450 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 451 const uint8_t *mask, 452 const uint8_t *nic_mask, 453 unsigned int size, 454 struct rte_flow_error *error); 455 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 456 uint64_t item_flags, 457 struct rte_flow_error *error); 458 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 459 uint64_t item_flags, 460 uint8_t target_protocol, 461 struct rte_flow_error *error); 462 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 463 uint64_t item_flags, 464 const struct rte_flow_item_ipv4 *acc_mask, 465 struct rte_flow_error *error); 466 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 467 uint64_t item_flags, 468 const struct rte_flow_item_ipv6 *acc_mask, 469 struct rte_flow_error *error); 470 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 471 const struct rte_flow_item *item, 472 uint64_t item_flags, 473 uint64_t prev_layer, 474 struct rte_flow_error *error); 475 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 476 uint64_t item_flags, 477 uint8_t target_protocol, 478 const struct rte_flow_item_tcp *flow_mask, 479 struct rte_flow_error *error); 480 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 481 uint64_t item_flags, 482 uint8_t target_protocol, 483 struct rte_flow_error *error); 484 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 485 uint64_t item_flags, 486 struct rte_flow_error *error); 487 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 488 uint64_t item_flags, 489 struct rte_flow_error *error); 490 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 491 uint64_t item_flags, 492 struct rte_eth_dev *dev, 493 struct rte_flow_error *error); 494 495 /* mlx5_flow_tcf.c */ 496 497 int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx, 498 unsigned int ifindex, struct rte_flow_error *error); 499 struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void); 500 void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx); 501 502 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 503