1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* Private rte flow items. */ 22 enum mlx5_rte_flow_item_type { 23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 24 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 28 }; 29 30 /* Private (internal) rte flow actions. */ 31 enum mlx5_rte_flow_action_type { 32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 33 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 34 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 38 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 39 }; 40 41 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 42 43 enum { 44 MLX5_INDIRECT_ACTION_TYPE_RSS, 45 MLX5_INDIRECT_ACTION_TYPE_AGE, 46 }; 47 48 /* Matches on selected register. */ 49 struct mlx5_rte_flow_item_tag { 50 enum modify_reg id; 51 uint32_t data; 52 }; 53 54 /* Modify selected register. */ 55 struct mlx5_rte_flow_action_set_tag { 56 enum modify_reg id; 57 uint32_t data; 58 }; 59 60 struct mlx5_flow_action_copy_mreg { 61 enum modify_reg dst; 62 enum modify_reg src; 63 }; 64 65 /* Matches on source queue. */ 66 struct mlx5_rte_flow_item_tx_queue { 67 uint32_t queue; 68 }; 69 70 /* Feature name to allocate metadata register. */ 71 enum mlx5_feature_name { 72 MLX5_HAIRPIN_RX, 73 MLX5_HAIRPIN_TX, 74 MLX5_METADATA_RX, 75 MLX5_METADATA_TX, 76 MLX5_METADATA_FDB, 77 MLX5_FLOW_MARK, 78 MLX5_APP_TAG, 79 MLX5_COPY_MARK, 80 MLX5_MTR_COLOR, 81 MLX5_MTR_SFX, 82 MLX5_ASO_FLOW_HIT, 83 }; 84 85 /* Default queue number. */ 86 #define MLX5_RSSQ_DEFAULT_NUM 16 87 88 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 89 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 91 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 92 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 93 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 94 95 /* Pattern inner Layer bits. */ 96 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 97 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 98 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 99 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 100 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 101 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 102 103 /* Pattern tunnel Layer bits. */ 104 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 105 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 106 #define MLX5_FLOW_LAYER_GRE (1u << 14) 107 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 108 /* List of tunnel Layer bits continued below. */ 109 110 /* General pattern items bits. */ 111 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 112 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 113 #define MLX5_FLOW_ITEM_TAG (1u << 18) 114 #define MLX5_FLOW_ITEM_MARK (1u << 19) 115 116 /* Pattern MISC bits. */ 117 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 118 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 119 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 120 121 /* Pattern tunnel Layer bits (continued). */ 122 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 123 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 124 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 125 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 126 127 /* Queue items. */ 128 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 129 130 /* Pattern tunnel Layer bits (continued). */ 131 #define MLX5_FLOW_LAYER_GTP (1u << 28) 132 133 /* Pattern eCPRI Layer bit. */ 134 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 135 136 /* IPv6 Fragment Extension Header bit. */ 137 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 138 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 139 140 /* Pattern tunnel Layer bits (continued). */ 141 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 142 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 143 144 /* Outer Masks. */ 145 #define MLX5_FLOW_LAYER_OUTER_L3 \ 146 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 147 #define MLX5_FLOW_LAYER_OUTER_L4 \ 148 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 149 #define MLX5_FLOW_LAYER_OUTER \ 150 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 151 MLX5_FLOW_LAYER_OUTER_L4) 152 153 /* Tunnel Masks. */ 154 #define MLX5_FLOW_LAYER_TUNNEL \ 155 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 156 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 157 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 158 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 159 160 /* Inner Masks. */ 161 #define MLX5_FLOW_LAYER_INNER_L3 \ 162 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 163 #define MLX5_FLOW_LAYER_INNER_L4 \ 164 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 165 #define MLX5_FLOW_LAYER_INNER \ 166 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 167 MLX5_FLOW_LAYER_INNER_L4) 168 169 /* Layer Masks. */ 170 #define MLX5_FLOW_LAYER_L2 \ 171 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 172 #define MLX5_FLOW_LAYER_L3_IPV4 \ 173 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 174 #define MLX5_FLOW_LAYER_L3_IPV6 \ 175 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 176 #define MLX5_FLOW_LAYER_L3 \ 177 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 178 #define MLX5_FLOW_LAYER_L4 \ 179 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 180 181 /* Actions */ 182 #define MLX5_FLOW_ACTION_DROP (1u << 0) 183 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 184 #define MLX5_FLOW_ACTION_RSS (1u << 2) 185 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 186 #define MLX5_FLOW_ACTION_MARK (1u << 4) 187 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 188 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 189 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 190 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 191 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 192 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 193 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 194 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 195 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 196 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 197 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 198 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 199 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 200 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 201 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 202 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 203 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 204 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 205 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 206 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 207 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 208 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 209 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 210 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 211 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 212 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 213 #define MLX5_FLOW_ACTION_METER (1ull << 31) 214 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 215 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 216 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 217 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 218 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 219 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 220 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 221 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 222 223 #define MLX5_FLOW_FATE_ACTIONS \ 224 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 225 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 226 MLX5_FLOW_ACTION_DEFAULT_MISS) 227 228 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 229 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 230 MLX5_FLOW_ACTION_JUMP) 231 232 233 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 234 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 235 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 236 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 237 MLX5_FLOW_ACTION_SET_TP_SRC | \ 238 MLX5_FLOW_ACTION_SET_TP_DST | \ 239 MLX5_FLOW_ACTION_SET_TTL | \ 240 MLX5_FLOW_ACTION_DEC_TTL | \ 241 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 242 MLX5_FLOW_ACTION_SET_MAC_DST | \ 243 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 244 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 245 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 246 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 247 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 248 MLX5_FLOW_ACTION_SET_TAG | \ 249 MLX5_FLOW_ACTION_MARK_EXT | \ 250 MLX5_FLOW_ACTION_SET_META | \ 251 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 252 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 253 MLX5_FLOW_ACTION_MODIFY_FIELD) 254 255 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 256 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 257 258 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 259 260 #ifndef IPPROTO_MPLS 261 #define IPPROTO_MPLS 137 262 #endif 263 264 /* UDP port number for MPLS */ 265 #define MLX5_UDP_PORT_MPLS 6635 266 267 /* UDP port numbers for VxLAN. */ 268 #define MLX5_UDP_PORT_VXLAN 4789 269 #define MLX5_UDP_PORT_VXLAN_GPE 4790 270 271 /* UDP port numbers for GENEVE. */ 272 #define MLX5_UDP_PORT_GENEVE 6081 273 274 /* Lowest priority indicator. */ 275 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 276 277 /* 278 * Max priority for ingress\egress flow groups 279 * greater than 0 and for any transfer flow group. 280 * From user configation: 0 - 21843. 281 */ 282 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 283 284 /* 285 * Number of sub priorities. 286 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 287 * matching on the NIC (firmware dependent) L4 most have the higher priority 288 * followed by L3 and ending with L2. 289 */ 290 #define MLX5_PRIORITY_MAP_L2 2 291 #define MLX5_PRIORITY_MAP_L3 1 292 #define MLX5_PRIORITY_MAP_L4 0 293 #define MLX5_PRIORITY_MAP_MAX 3 294 295 /* Valid layer type for IPV4 RSS. */ 296 #define MLX5_IPV4_LAYER_TYPES \ 297 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 298 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 299 ETH_RSS_NONFRAG_IPV4_OTHER) 300 301 /* IBV hash source bits for IPV4. */ 302 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 303 304 /* Valid layer type for IPV6 RSS. */ 305 #define MLX5_IPV6_LAYER_TYPES \ 306 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 307 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 308 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 309 310 /* IBV hash source bits for IPV6. */ 311 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 312 313 /* IBV hash bits for L3 SRC. */ 314 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 315 316 /* IBV hash bits for L3 DST. */ 317 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 318 319 /* IBV hash bits for TCP. */ 320 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 321 IBV_RX_HASH_DST_PORT_TCP) 322 323 /* IBV hash bits for UDP. */ 324 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 325 IBV_RX_HASH_DST_PORT_UDP) 326 327 /* IBV hash bits for L4 SRC. */ 328 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 329 IBV_RX_HASH_SRC_PORT_UDP) 330 331 /* IBV hash bits for L4 DST. */ 332 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 333 IBV_RX_HASH_DST_PORT_UDP) 334 335 /* Geneve header first 16Bit */ 336 #define MLX5_GENEVE_VER_MASK 0x3 337 #define MLX5_GENEVE_VER_SHIFT 14 338 #define MLX5_GENEVE_VER_VAL(a) \ 339 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 340 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 341 #define MLX5_GENEVE_OPTLEN_SHIFT 8 342 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 343 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 344 #define MLX5_GENEVE_OAMF_MASK 0x1 345 #define MLX5_GENEVE_OAMF_SHIFT 7 346 #define MLX5_GENEVE_OAMF_VAL(a) \ 347 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 348 #define MLX5_GENEVE_CRITO_MASK 0x1 349 #define MLX5_GENEVE_CRITO_SHIFT 6 350 #define MLX5_GENEVE_CRITO_VAL(a) \ 351 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 352 #define MLX5_GENEVE_RSVD_MASK 0x3F 353 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 354 /* 355 * The length of the Geneve options fields, expressed in four byte multiples, 356 * not including the eight byte fixed tunnel. 357 */ 358 #define MLX5_GENEVE_OPT_LEN_0 14 359 #define MLX5_GENEVE_OPT_LEN_1 63 360 361 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 362 sizeof(struct rte_ipv4_hdr)) 363 /* GTP extension header flag. */ 364 #define MLX5_GTP_EXT_HEADER_FLAG 4 365 366 /* GTP extension header max PDU type value. */ 367 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 368 369 /* GTP extension header PDU type shift. */ 370 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 371 372 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 373 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 374 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 375 376 /* Specific item's fields can accept a range of values (using spec and last). */ 377 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 378 #define MLX5_ITEM_RANGE_ACCEPTED true 379 380 /* Software header modify action numbers of a flow. */ 381 #define MLX5_ACT_NUM_MDF_IPV4 1 382 #define MLX5_ACT_NUM_MDF_IPV6 4 383 #define MLX5_ACT_NUM_MDF_MAC 2 384 #define MLX5_ACT_NUM_MDF_VID 1 385 #define MLX5_ACT_NUM_MDF_PORT 2 386 #define MLX5_ACT_NUM_MDF_TTL 1 387 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 388 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 389 #define MLX5_ACT_NUM_MDF_TCPACK 1 390 #define MLX5_ACT_NUM_SET_REG 1 391 #define MLX5_ACT_NUM_SET_TAG 1 392 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 393 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 394 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 395 #define MLX5_ACT_NUM_SET_DSCP 1 396 397 /* Maximum number of fields to modify in MODIFY_FIELD */ 398 #define MLX5_ACT_MAX_MOD_FIELDS 5 399 400 enum mlx5_flow_drv_type { 401 MLX5_FLOW_TYPE_MIN, 402 MLX5_FLOW_TYPE_DV, 403 MLX5_FLOW_TYPE_VERBS, 404 MLX5_FLOW_TYPE_MAX, 405 }; 406 407 /* Fate action type. */ 408 enum mlx5_flow_fate_type { 409 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 410 MLX5_FLOW_FATE_QUEUE, 411 MLX5_FLOW_FATE_JUMP, 412 MLX5_FLOW_FATE_PORT_ID, 413 MLX5_FLOW_FATE_DROP, 414 MLX5_FLOW_FATE_DEFAULT_MISS, 415 MLX5_FLOW_FATE_SHARED_RSS, 416 MLX5_FLOW_FATE_MAX, 417 }; 418 419 /* Matcher PRM representation */ 420 struct mlx5_flow_dv_match_params { 421 size_t size; 422 /**< Size of match value. Do NOT split size and key! */ 423 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 424 /**< Matcher value. This value is used as the mask or as a key. */ 425 }; 426 427 /* Matcher structure. */ 428 struct mlx5_flow_dv_matcher { 429 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 430 struct mlx5_flow_tbl_resource *tbl; 431 /**< Pointer to the table(group) the matcher associated with. */ 432 void *matcher_object; /**< Pointer to DV matcher */ 433 uint16_t crc; /**< CRC of key. */ 434 uint16_t priority; /**< Priority of matcher. */ 435 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 436 }; 437 438 #define MLX5_ENCAP_MAX_LEN 132 439 440 /* Encap/decap resource structure. */ 441 struct mlx5_flow_dv_encap_decap_resource { 442 struct mlx5_hlist_entry entry; 443 /* Pointer to next element. */ 444 uint32_t refcnt; /**< Reference counter. */ 445 void *action; 446 /**< Encap/decap action object. */ 447 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 448 size_t size; 449 uint8_t reformat_type; 450 uint8_t ft_type; 451 uint64_t flags; /**< Flags for RDMA API. */ 452 uint32_t idx; /**< Index for the index memory pool. */ 453 }; 454 455 /* Tag resource structure. */ 456 struct mlx5_flow_dv_tag_resource { 457 struct mlx5_hlist_entry entry; 458 /**< hash list entry for tag resource, tag value as the key. */ 459 void *action; 460 /**< Tag action object. */ 461 uint32_t refcnt; /**< Reference counter. */ 462 uint32_t idx; /**< Index for the index memory pool. */ 463 uint32_t tag_id; /**< Tag ID. */ 464 }; 465 466 /* 467 * Number of modification commands. 468 * The maximal actions amount in FW is some constant, and it is 16 in the 469 * latest releases. In some old releases, it will be limited to 8. 470 * Since there is no interface to query the capacity, the maximal value should 471 * be used to allow PMD to create the flow. The validation will be done in the 472 * lower driver layer or FW. A failure will be returned if exceeds the maximal 473 * supported actions number on the root table. 474 * On non-root tables, there is no limitation, but 32 is enough right now. 475 */ 476 #define MLX5_MAX_MODIFY_NUM 32 477 #define MLX5_ROOT_TBL_MODIFY_NUM 16 478 479 /* Modify resource structure */ 480 struct mlx5_flow_dv_modify_hdr_resource { 481 struct mlx5_hlist_entry entry; 482 void *action; /**< Modify header action object. */ 483 /* Key area for hash list matching: */ 484 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 485 uint32_t actions_num; /**< Number of modification actions. */ 486 uint64_t flags; /**< Flags for RDMA API. */ 487 struct mlx5_modification_cmd actions[]; 488 /**< Modification actions. */ 489 }; 490 491 /* Modify resource key of the hash organization. */ 492 union mlx5_flow_modify_hdr_key { 493 struct { 494 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 495 uint32_t actions_num:5; /**< Number of modification actions. */ 496 uint32_t group:19; /**< Flow group id. */ 497 uint32_t cksum; /**< Actions check sum. */ 498 }; 499 uint64_t v64; /**< full 64bits value of key */ 500 }; 501 502 /* Jump action resource structure. */ 503 struct mlx5_flow_dv_jump_tbl_resource { 504 void *action; /**< Pointer to the rdma core action. */ 505 }; 506 507 /* Port ID resource structure. */ 508 struct mlx5_flow_dv_port_id_action_resource { 509 struct mlx5_cache_entry entry; 510 void *action; /**< Action object. */ 511 uint32_t port_id; /**< Port ID value. */ 512 uint32_t idx; /**< Indexed pool memory index. */ 513 }; 514 515 /* Push VLAN action resource structure */ 516 struct mlx5_flow_dv_push_vlan_action_resource { 517 struct mlx5_cache_entry entry; /* Cache entry. */ 518 void *action; /**< Action object. */ 519 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 520 rte_be32_t vlan_tag; /**< VLAN tag value. */ 521 uint32_t idx; /**< Indexed pool memory index. */ 522 }; 523 524 /* Metadata register copy table entry. */ 525 struct mlx5_flow_mreg_copy_resource { 526 /* 527 * Hash list entry for copy table. 528 * - Key is 32/64-bit MARK action ID. 529 * - MUST be the first entry. 530 */ 531 struct mlx5_hlist_entry hlist_ent; 532 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 533 /* List entry for device flows. */ 534 uint32_t idx; 535 uint32_t rix_flow; /* Built flow for copy. */ 536 uint32_t mark_id; 537 }; 538 539 /* Table tunnel parameter. */ 540 struct mlx5_flow_tbl_tunnel_prm { 541 const struct mlx5_flow_tunnel *tunnel; 542 uint32_t group_id; 543 bool external; 544 }; 545 546 /* Table data structure of the hash organization. */ 547 struct mlx5_flow_tbl_data_entry { 548 struct mlx5_hlist_entry entry; 549 /**< hash list entry, 64-bits key inside. */ 550 struct mlx5_flow_tbl_resource tbl; 551 /**< flow table resource. */ 552 struct mlx5_cache_list matchers; 553 /**< matchers' header associated with the flow table. */ 554 struct mlx5_flow_dv_jump_tbl_resource jump; 555 /**< jump resource, at most one for each table created. */ 556 uint32_t idx; /**< index for the indexed mempool. */ 557 /**< tunnel offload */ 558 const struct mlx5_flow_tunnel *tunnel; 559 uint32_t group_id; 560 uint32_t external:1; 561 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 562 uint32_t is_egress:1; /**< Egress table. */ 563 uint32_t is_transfer:1; /**< Transfer table. */ 564 uint32_t dummy:1; /**< DR table. */ 565 uint32_t reserve:27; /**< Reserved to future using. */ 566 uint32_t table_id; /**< Table ID. */ 567 }; 568 569 /* Sub rdma-core actions list. */ 570 struct mlx5_flow_sub_actions_list { 571 uint32_t actions_num; /**< Number of sample actions. */ 572 uint64_t action_flags; 573 void *dr_queue_action; 574 void *dr_tag_action; 575 void *dr_cnt_action; 576 void *dr_port_id_action; 577 void *dr_encap_action; 578 void *dr_jump_action; 579 }; 580 581 /* Sample sub-actions resource list. */ 582 struct mlx5_flow_sub_actions_idx { 583 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 584 uint32_t rix_tag; /**< Index to the tag action. */ 585 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 586 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 587 uint32_t rix_jump; /**< Index to the jump action resource. */ 588 }; 589 590 /* Sample action resource structure. */ 591 struct mlx5_flow_dv_sample_resource { 592 struct mlx5_cache_entry entry; /**< Cache entry. */ 593 union { 594 void *verbs_action; /**< Verbs sample action object. */ 595 void **sub_actions; /**< Sample sub-action array. */ 596 }; 597 struct rte_eth_dev *dev; /**< Device registers the action. */ 598 uint32_t idx; /** Sample object index. */ 599 uint8_t ft_type; /** Flow Table Type */ 600 uint32_t ft_id; /** Flow Table Level */ 601 uint32_t ratio; /** Sample Ratio */ 602 uint64_t set_action; /** Restore reg_c0 value */ 603 void *normal_path_tbl; /** Flow Table pointer */ 604 struct mlx5_flow_sub_actions_idx sample_idx; 605 /**< Action index resources. */ 606 struct mlx5_flow_sub_actions_list sample_act; 607 /**< Action resources. */ 608 }; 609 610 #define MLX5_MAX_DEST_NUM 2 611 612 /* Destination array action resource structure. */ 613 struct mlx5_flow_dv_dest_array_resource { 614 struct mlx5_cache_entry entry; /**< Cache entry. */ 615 uint32_t idx; /** Destination array action object index. */ 616 uint8_t ft_type; /** Flow Table Type */ 617 uint8_t num_of_dest; /**< Number of destination actions. */ 618 struct rte_eth_dev *dev; /**< Device registers the action. */ 619 void *action; /**< Pointer to the rdma core action. */ 620 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 621 /**< Action index resources. */ 622 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 623 /**< Action resources. */ 624 }; 625 626 /* PMD flow priority for tunnel */ 627 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 628 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 629 630 631 /** Device flow handle structure for DV mode only. */ 632 struct mlx5_flow_handle_dv { 633 /* Flow DV api: */ 634 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 635 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 636 /**< Pointer to modify header resource in cache. */ 637 uint32_t rix_encap_decap; 638 /**< Index to encap/decap resource in cache. */ 639 uint32_t rix_push_vlan; 640 /**< Index to push VLAN action resource in cache. */ 641 uint32_t rix_tag; 642 /**< Index to the tag action. */ 643 uint32_t rix_sample; 644 /**< Index to sample action resource in cache. */ 645 uint32_t rix_dest_array; 646 /**< Index to destination array resource in cache. */ 647 } __rte_packed; 648 649 /** Device flow handle structure: used both for creating & destroying. */ 650 struct mlx5_flow_handle { 651 SILIST_ENTRY(uint32_t)next; 652 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 653 /**< Index to next device flow handle. */ 654 uint64_t layers; 655 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 656 void *drv_flow; /**< pointer to driver flow object. */ 657 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 658 uint32_t mark:1; /**< Metadate rxq mark flag. */ 659 uint32_t fate_action:3; /**< Fate action type. */ 660 union { 661 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 662 uint32_t rix_jump; /**< Index to the jump action resource. */ 663 uint32_t rix_port_id_action; 664 /**< Index to port ID action resource. */ 665 uint32_t rix_fate; 666 /**< Generic value indicates the fate action. */ 667 uint32_t rix_default_fate; 668 /**< Indicates default miss fate action. */ 669 uint32_t rix_srss; 670 /**< Indicates shared RSS fate action. */ 671 }; 672 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 673 struct mlx5_flow_handle_dv dvh; 674 #endif 675 } __rte_packed; 676 677 /* 678 * Size for Verbs device flow handle structure only. Do not use the DV only 679 * structure in Verbs. No DV flows attributes will be accessed. 680 * Macro offsetof() could also be used here. 681 */ 682 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 683 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 684 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 685 #else 686 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 687 #endif 688 689 /* 690 * Max number of actions per DV flow. 691 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 692 * in rdma-core file providers/mlx5/verbs.c. 693 */ 694 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 695 696 /** Device flow structure only for DV flow creation. */ 697 struct mlx5_flow_dv_workspace { 698 uint32_t group; /**< The group index. */ 699 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 700 int actions_n; /**< number of actions. */ 701 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 702 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 703 /**< Pointer to encap/decap resource in cache. */ 704 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 705 /**< Pointer to push VLAN action resource in cache. */ 706 struct mlx5_flow_dv_tag_resource *tag_resource; 707 /**< pointer to the tag action. */ 708 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 709 /**< Pointer to port ID action resource. */ 710 struct mlx5_flow_dv_jump_tbl_resource *jump; 711 /**< Pointer to the jump action resource. */ 712 struct mlx5_flow_dv_match_params value; 713 /**< Holds the value that the packet is compared to. */ 714 struct mlx5_flow_dv_sample_resource *sample_res; 715 /**< Pointer to the sample action resource. */ 716 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 717 /**< Pointer to the destination array resource. */ 718 }; 719 720 #ifdef HAVE_INFINIBAND_VERBS_H 721 /* 722 * Maximal Verbs flow specifications & actions size. 723 * Some elements are mutually exclusive, but enough space should be allocated. 724 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 725 * 2. One tunnel header (exception: GRE + MPLS), 726 * SPEC length: GRE == tunnel. 727 * Actions: 1. 1 Mark OR Flag. 728 * 2. 1 Drop (if any). 729 * 3. No limitation for counters, but it makes no sense to support too 730 * many counters in a single device flow. 731 */ 732 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 733 #define MLX5_VERBS_MAX_SPEC_SIZE \ 734 ( \ 735 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 736 sizeof(struct ibv_flow_spec_ipv6) + \ 737 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 738 sizeof(struct ibv_flow_spec_gre) + \ 739 sizeof(struct ibv_flow_spec_mpls)) \ 740 ) 741 #else 742 #define MLX5_VERBS_MAX_SPEC_SIZE \ 743 ( \ 744 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 745 sizeof(struct ibv_flow_spec_ipv6) + \ 746 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 747 sizeof(struct ibv_flow_spec_tunnel)) \ 748 ) 749 #endif 750 751 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 752 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 753 #define MLX5_VERBS_MAX_ACT_SIZE \ 754 ( \ 755 sizeof(struct ibv_flow_spec_action_tag) + \ 756 sizeof(struct ibv_flow_spec_action_drop) + \ 757 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 758 ) 759 #else 760 #define MLX5_VERBS_MAX_ACT_SIZE \ 761 ( \ 762 sizeof(struct ibv_flow_spec_action_tag) + \ 763 sizeof(struct ibv_flow_spec_action_drop) \ 764 ) 765 #endif 766 767 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 768 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 769 770 /** Device flow structure only for Verbs flow creation. */ 771 struct mlx5_flow_verbs_workspace { 772 unsigned int size; /**< Size of the attribute. */ 773 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 774 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 775 /**< Specifications & actions buffer of verbs flow. */ 776 }; 777 #endif /* HAVE_INFINIBAND_VERBS_H */ 778 779 #define MLX5_SCALE_FLOW_GROUP_BIT 0 780 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 781 782 /** Maximal number of device sub-flows supported. */ 783 #define MLX5_NUM_MAX_DEV_FLOWS 32 784 785 /** Device flow structure. */ 786 __extension__ 787 struct mlx5_flow { 788 struct rte_flow *flow; /**< Pointer to the main flow. */ 789 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 790 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 791 uint64_t act_flags; 792 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 793 bool external; /**< true if the flow is created external to PMD. */ 794 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 795 uint8_t skip_scale:2; 796 /** 797 * Each Bit be set to 1 if Skip the scale the flow group with factor. 798 * If bit0 be set to 1, then skip the scale the original flow group; 799 * If bit1 be set to 1, then skip the scale the jump flow group if 800 * having jump action. 801 * 00: Enable scale in a flow, default value. 802 * 01: Skip scale the flow group with factor, enable scale the group 803 * of jump action. 804 * 10: Enable scale the group with factor, skip scale the group of 805 * jump action. 806 * 11: Skip scale the table with factor both for flow group and jump 807 * group. 808 */ 809 union { 810 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 811 struct mlx5_flow_dv_workspace dv; 812 #endif 813 #ifdef HAVE_INFINIBAND_VERBS_H 814 struct mlx5_flow_verbs_workspace verbs; 815 #endif 816 }; 817 struct mlx5_flow_handle *handle; 818 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 819 const struct mlx5_flow_tunnel *tunnel; 820 }; 821 822 /* Flow meter state. */ 823 #define MLX5_FLOW_METER_DISABLE 0 824 #define MLX5_FLOW_METER_ENABLE 1 825 826 #define MLX5_MAN_WIDTH 8 827 /* Modify this value if enum rte_mtr_color changes. */ 828 #define RTE_MTR_DROPPED RTE_COLORS 829 830 /* Meter policer statistics */ 831 struct mlx5_flow_policer_stats { 832 uint32_t cnt[RTE_COLORS + 1]; 833 /**< Color counter, extra for drop. */ 834 uint64_t stats_mask; 835 /**< Statistics mask for the colors. */ 836 }; 837 838 /* Meter table structure. */ 839 struct mlx5_meter_domain_info { 840 struct mlx5_flow_tbl_resource *tbl; 841 /**< Meter table. */ 842 struct mlx5_flow_tbl_resource *sfx_tbl; 843 /**< Meter suffix table. */ 844 void *any_matcher; 845 /**< Meter color not match default criteria. */ 846 void *color_matcher; 847 /**< Meter color match criteria. */ 848 void *jump_actn; 849 /**< Meter match action. */ 850 void *policer_rules[RTE_MTR_DROPPED + 1]; 851 /**< Meter policer for the match. */ 852 }; 853 854 /* Meter table set for TX RX FDB. */ 855 struct mlx5_meter_domains_infos { 856 uint32_t ref_cnt; 857 /**< Table user count. */ 858 struct mlx5_meter_domain_info egress; 859 /**< TX meter table. */ 860 struct mlx5_meter_domain_info ingress; 861 /**< RX meter table. */ 862 struct mlx5_meter_domain_info transfer; 863 /**< FDB meter table. */ 864 void *drop_actn; 865 /**< Drop action as not matched. */ 866 void *count_actns[RTE_MTR_DROPPED + 1]; 867 /**< Counters for match and unmatched statistics. */ 868 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 869 /**< Flow meter parameter. */ 870 size_t fmp_size; 871 /**< Flow meter parameter size. */ 872 void *meter_action; 873 /**< Flow meter action. */ 874 }; 875 876 /* Meter parameter structure. */ 877 struct mlx5_flow_meter { 878 TAILQ_ENTRY(mlx5_flow_meter) next; 879 /**< Pointer to the next flow meter structure. */ 880 uint32_t idx; /* Index to meter object. */ 881 uint32_t meter_id; 882 /**< Meter id. */ 883 struct mlx5_flow_meter_profile *profile; 884 /**< Meter profile parameters. */ 885 886 rte_spinlock_t sl; /**< Meter action spinlock. */ 887 888 /** Policer actions (per meter output color). */ 889 enum rte_mtr_policer_action action[RTE_COLORS]; 890 891 /** Set of stats counters to be enabled. 892 * @see enum rte_mtr_stats_type 893 */ 894 uint64_t stats_mask; 895 896 /**< Rule applies to ingress traffic. */ 897 uint32_t ingress:1; 898 899 /**< Rule applies to egress traffic. */ 900 uint32_t egress:1; 901 /** 902 * Instead of simply matching the properties of traffic as it would 903 * appear on a given DPDK port ID, enabling this attribute transfers 904 * a flow rule to the lowest possible level of any device endpoints 905 * found in the pattern. 906 * 907 * When supported, this effectively enables an application to 908 * re-route traffic not necessarily intended for it (e.g. coming 909 * from or addressed to different physical ports, VFs or 910 * applications) at the device level. 911 * 912 * It complements the behavior of some pattern items such as 913 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 914 * 915 * When transferring flow rules, ingress and egress attributes keep 916 * their original meaning, as if processing traffic emitted or 917 * received by the application. 918 */ 919 uint32_t transfer:1; 920 struct mlx5_meter_domains_infos *mfts; 921 /**< Flow table created for this meter. */ 922 struct mlx5_flow_policer_stats policer_stats; 923 /**< Meter policer statistics. */ 924 uint32_t ref_cnt; 925 /**< Use count. */ 926 uint32_t active_state:1; 927 /**< Meter state. */ 928 uint32_t shared:1; 929 /**< Meter shared or not. */ 930 }; 931 932 /* RFC2697 parameter structure. */ 933 struct mlx5_flow_meter_srtcm_rfc2697_prm { 934 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 935 uint32_t cbs_exponent:5; 936 uint32_t cbs_mantissa:8; 937 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 938 uint32_t cir_exponent:5; 939 uint32_t cir_mantissa:8; 940 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 941 uint32_t ebs_exponent:5; 942 uint32_t ebs_mantissa:8; 943 }; 944 945 /* Flow meter profile structure. */ 946 struct mlx5_flow_meter_profile { 947 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 948 /**< Pointer to the next flow meter structure. */ 949 uint32_t meter_profile_id; /**< Profile id. */ 950 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 951 union { 952 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 953 /**< srtcm_rfc2697 struct. */ 954 }; 955 uint32_t ref_cnt; /**< Use count. */ 956 }; 957 958 #define MLX5_MAX_TUNNELS 256 959 #define MLX5_TNL_MISS_RULE_PRIORITY 3 960 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 961 962 /* 963 * When tunnel offload is active, all JUMP group ids are converted 964 * using the same method. That conversion is applied both to tunnel and 965 * regular rule types. 966 * Group ids used in tunnel rules are relative to it's tunnel (!). 967 * Application can create number of steer rules, using the same 968 * tunnel, with different group id in each rule. 969 * Each tunnel stores its groups internally in PMD tunnel object. 970 * Groups used in regular rules do not belong to any tunnel and are stored 971 * in tunnel hub. 972 */ 973 974 struct mlx5_flow_tunnel { 975 LIST_ENTRY(mlx5_flow_tunnel) chain; 976 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 977 uint32_t tunnel_id; /** unique tunnel ID */ 978 uint32_t refctn; 979 struct rte_flow_action action; 980 struct rte_flow_item item; 981 struct mlx5_hlist *groups; /** tunnel groups */ 982 }; 983 984 /** PMD tunnel related context */ 985 struct mlx5_flow_tunnel_hub { 986 /* Tunnels list 987 * Access to the list MUST be MT protected 988 */ 989 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 990 /* protect access to the tunnels list */ 991 rte_spinlock_t sl; 992 struct mlx5_hlist *groups; /** non tunnel groups */ 993 }; 994 995 /* convert jump group to flow table ID in tunnel rules */ 996 struct tunnel_tbl_entry { 997 struct mlx5_hlist_entry hash; 998 uint32_t flow_table; 999 uint32_t tunnel_id; 1000 uint32_t group; 1001 }; 1002 1003 static inline uint32_t 1004 tunnel_id_to_flow_tbl(uint32_t id) 1005 { 1006 return id | (1u << 16); 1007 } 1008 1009 static inline uint32_t 1010 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 1011 { 1012 return flow_tbl & ~(1u << 16); 1013 } 1014 1015 union tunnel_tbl_key { 1016 uint64_t val; 1017 struct { 1018 uint32_t tunnel_id; 1019 uint32_t group; 1020 }; 1021 }; 1022 1023 static inline struct mlx5_flow_tunnel_hub * 1024 mlx5_tunnel_hub(struct rte_eth_dev *dev) 1025 { 1026 struct mlx5_priv *priv = dev->data->dev_private; 1027 return priv->sh->tunnel_hub; 1028 } 1029 1030 static inline bool 1031 is_tunnel_offload_active(struct rte_eth_dev *dev) 1032 { 1033 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1034 struct mlx5_priv *priv = dev->data->dev_private; 1035 return !!priv->config.dv_miss_info; 1036 #else 1037 RTE_SET_USED(dev); 1038 return false; 1039 #endif 1040 } 1041 1042 static inline bool 1043 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev, 1044 __rte_unused const struct rte_flow_attr *attr, 1045 __rte_unused const struct rte_flow_item items[], 1046 __rte_unused const struct rte_flow_action actions[]) 1047 { 1048 return (items[0].type == (typeof(items[0].type)) 1049 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL); 1050 } 1051 1052 static inline bool 1053 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev, 1054 __rte_unused const struct rte_flow_attr *attr, 1055 __rte_unused const struct rte_flow_item items[], 1056 __rte_unused const struct rte_flow_action actions[]) 1057 { 1058 return (actions[0].type == (typeof(actions[0].type)) 1059 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET); 1060 } 1061 1062 static inline const struct mlx5_flow_tunnel * 1063 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 1064 { 1065 return actions[0].conf; 1066 } 1067 1068 static inline const struct mlx5_flow_tunnel * 1069 flow_items_to_tunnel(const struct rte_flow_item items[]) 1070 { 1071 return items[0].spec; 1072 } 1073 1074 /* Flow structure. */ 1075 struct rte_flow { 1076 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 1077 uint32_t dev_handles; 1078 /**< Device flow handles that are part of the flow. */ 1079 uint32_t drv_type:2; /**< Driver type. */ 1080 uint32_t tunnel:1; 1081 uint32_t meter:16; /**< Holds flow meter id. */ 1082 uint32_t rix_mreg_copy; 1083 /**< Index to metadata register copy table resource. */ 1084 uint32_t counter; /**< Holds flow counter. */ 1085 uint32_t tunnel_id; /**< Tunnel id */ 1086 uint32_t age; /**< Holds ASO age bit index. */ 1087 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 1088 } __rte_packed; 1089 1090 /* 1091 * Define list of valid combinations of RX Hash fields 1092 * (see enum ibv_rx_hash_fields). 1093 */ 1094 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1095 #define MLX5_RSS_HASH_IPV4_TCP \ 1096 (MLX5_RSS_HASH_IPV4 | \ 1097 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1098 #define MLX5_RSS_HASH_IPV4_UDP \ 1099 (MLX5_RSS_HASH_IPV4 | \ 1100 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1101 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1102 #define MLX5_RSS_HASH_IPV6_TCP \ 1103 (MLX5_RSS_HASH_IPV6 | \ 1104 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1105 #define MLX5_RSS_HASH_IPV6_UDP \ 1106 (MLX5_RSS_HASH_IPV6 | \ 1107 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1108 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 1109 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 1110 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 1111 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1112 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1113 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1114 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1115 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1116 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1117 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1118 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1119 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1120 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1121 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1122 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1123 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1124 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1125 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1126 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1127 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1128 #define MLX5_RSS_HASH_NONE 0ULL 1129 1130 /* array of valid combinations of RX Hash fields for RSS */ 1131 static const uint64_t mlx5_rss_hash_fields[] = { 1132 MLX5_RSS_HASH_IPV4, 1133 MLX5_RSS_HASH_IPV4_TCP, 1134 MLX5_RSS_HASH_IPV4_UDP, 1135 MLX5_RSS_HASH_IPV6, 1136 MLX5_RSS_HASH_IPV6_TCP, 1137 MLX5_RSS_HASH_IPV6_UDP, 1138 MLX5_RSS_HASH_NONE, 1139 }; 1140 1141 /* Shared RSS action structure */ 1142 struct mlx5_shared_action_rss { 1143 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1144 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1145 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1146 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1147 struct mlx5_ind_table_obj *ind_tbl; 1148 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1149 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1150 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1151 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1152 }; 1153 1154 struct rte_flow_action_handle { 1155 uint32_t id; 1156 }; 1157 1158 /* Thread specific flow workspace intermediate data. */ 1159 struct mlx5_flow_workspace { 1160 /* If creating another flow in same thread, push new as stack. */ 1161 struct mlx5_flow_workspace *prev; 1162 struct mlx5_flow_workspace *next; 1163 uint32_t inuse; /* can't create new flow with current. */ 1164 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1165 struct mlx5_flow_rss_desc rss_desc; 1166 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1167 uint32_t flow_idx; /* Intermediate device flow index. */ 1168 }; 1169 1170 struct mlx5_flow_split_info { 1171 bool external; 1172 /**< True if flow is created by request external to PMD. */ 1173 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1174 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1175 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1176 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1177 }; 1178 1179 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1180 const struct rte_flow_attr *attr, 1181 const struct rte_flow_item items[], 1182 const struct rte_flow_action actions[], 1183 bool external, 1184 int hairpin, 1185 struct rte_flow_error *error); 1186 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1187 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1188 const struct rte_flow_item items[], 1189 const struct rte_flow_action actions[], struct rte_flow_error *error); 1190 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1191 struct mlx5_flow *dev_flow, 1192 const struct rte_flow_attr *attr, 1193 const struct rte_flow_item items[], 1194 const struct rte_flow_action actions[], 1195 struct rte_flow_error *error); 1196 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1197 struct rte_flow_error *error); 1198 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1199 struct rte_flow *flow); 1200 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1201 struct rte_flow *flow); 1202 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1203 struct rte_flow *flow, 1204 const struct rte_flow_action *actions, 1205 void *data, 1206 struct rte_flow_error *error); 1207 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 1208 (struct rte_eth_dev *dev, 1209 const struct mlx5_flow_meter *fm); 1210 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1211 struct mlx5_meter_domains_infos *tbls); 1212 typedef int (*mlx5_flow_create_policer_rules_t) 1213 (struct rte_eth_dev *dev, 1214 struct mlx5_flow_meter *fm, 1215 const struct rte_flow_attr *attr); 1216 typedef int (*mlx5_flow_destroy_policer_rules_t) 1217 (struct rte_eth_dev *dev, 1218 const struct mlx5_flow_meter *fm, 1219 const struct rte_flow_attr *attr); 1220 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1221 (struct rte_eth_dev *dev); 1222 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1223 uint32_t cnt); 1224 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1225 uint32_t cnt, 1226 bool clear, uint64_t *pkts, 1227 uint64_t *bytes); 1228 typedef int (*mlx5_flow_get_aged_flows_t) 1229 (struct rte_eth_dev *dev, 1230 void **context, 1231 uint32_t nb_contexts, 1232 struct rte_flow_error *error); 1233 typedef int (*mlx5_flow_action_validate_t) 1234 (struct rte_eth_dev *dev, 1235 const struct rte_flow_indir_action_conf *conf, 1236 const struct rte_flow_action *action, 1237 struct rte_flow_error *error); 1238 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1239 (struct rte_eth_dev *dev, 1240 const struct rte_flow_indir_action_conf *conf, 1241 const struct rte_flow_action *action, 1242 struct rte_flow_error *error); 1243 typedef int (*mlx5_flow_action_destroy_t) 1244 (struct rte_eth_dev *dev, 1245 struct rte_flow_action_handle *action, 1246 struct rte_flow_error *error); 1247 typedef int (*mlx5_flow_action_update_t) 1248 (struct rte_eth_dev *dev, 1249 struct rte_flow_action_handle *action, 1250 const void *update, 1251 struct rte_flow_error *error); 1252 typedef int (*mlx5_flow_action_query_t) 1253 (struct rte_eth_dev *dev, 1254 const struct rte_flow_action_handle *action, 1255 void *data, 1256 struct rte_flow_error *error); 1257 typedef int (*mlx5_flow_sync_domain_t) 1258 (struct rte_eth_dev *dev, 1259 uint32_t domains, 1260 uint32_t flags); 1261 1262 struct mlx5_flow_driver_ops { 1263 mlx5_flow_validate_t validate; 1264 mlx5_flow_prepare_t prepare; 1265 mlx5_flow_translate_t translate; 1266 mlx5_flow_apply_t apply; 1267 mlx5_flow_remove_t remove; 1268 mlx5_flow_destroy_t destroy; 1269 mlx5_flow_query_t query; 1270 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1271 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1272 mlx5_flow_create_policer_rules_t create_policer_rules; 1273 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 1274 mlx5_flow_counter_alloc_t counter_alloc; 1275 mlx5_flow_counter_free_t counter_free; 1276 mlx5_flow_counter_query_t counter_query; 1277 mlx5_flow_get_aged_flows_t get_aged_flows; 1278 mlx5_flow_action_validate_t action_validate; 1279 mlx5_flow_action_create_t action_create; 1280 mlx5_flow_action_destroy_t action_destroy; 1281 mlx5_flow_action_update_t action_update; 1282 mlx5_flow_action_query_t action_query; 1283 mlx5_flow_sync_domain_t sync_domain; 1284 }; 1285 1286 /* mlx5_flow.c */ 1287 1288 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1289 __extension__ 1290 struct flow_grp_info { 1291 uint64_t external:1; 1292 uint64_t transfer:1; 1293 uint64_t fdb_def_rule:1; 1294 /* force standard group translation */ 1295 uint64_t std_tbl_fix:1; 1296 uint64_t skip_scale:2; 1297 }; 1298 1299 static inline bool 1300 tunnel_use_standard_attr_group_translate 1301 (struct rte_eth_dev *dev, 1302 const struct mlx5_flow_tunnel *tunnel, 1303 const struct rte_flow_attr *attr, 1304 const struct rte_flow_item items[], 1305 const struct rte_flow_action actions[]) 1306 { 1307 bool verdict; 1308 1309 if (!is_tunnel_offload_active(dev)) 1310 /* no tunnel offload API */ 1311 verdict = true; 1312 else if (tunnel) { 1313 /* 1314 * OvS will use jump to group 0 in tunnel steer rule. 1315 * If tunnel steer rule starts from group 0 (attr.group == 0) 1316 * that 0 group must be translated with standard method. 1317 * attr.group == 0 in tunnel match rule translated with tunnel 1318 * method 1319 */ 1320 verdict = !attr->group && 1321 is_flow_tunnel_steer_rule(dev, attr, items, actions); 1322 } else { 1323 /* 1324 * non-tunnel group translation uses standard method for 1325 * root group only: attr.group == 0 1326 */ 1327 verdict = !attr->group; 1328 } 1329 1330 return verdict; 1331 } 1332 1333 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1334 const struct mlx5_flow_tunnel *tunnel, 1335 uint32_t group, uint32_t *table, 1336 const struct flow_grp_info *flags, 1337 struct rte_flow_error *error); 1338 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1339 int tunnel, uint64_t layer_types, 1340 uint64_t hash_fields); 1341 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1342 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1343 uint32_t subpriority); 1344 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1345 const struct rte_flow_attr *attr); 1346 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1347 const struct rte_flow_attr *attr, 1348 uint32_t subpriority); 1349 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1350 enum mlx5_feature_name feature, 1351 uint32_t id, 1352 struct rte_flow_error *error); 1353 const struct rte_flow_action *mlx5_flow_find_action 1354 (const struct rte_flow_action *actions, 1355 enum rte_flow_action_type action); 1356 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1357 const struct rte_flow_action *action, 1358 struct rte_flow_error *error); 1359 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1360 const struct rte_flow_attr *attr, 1361 struct rte_flow_error *error); 1362 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1363 const struct rte_flow_attr *attr, 1364 struct rte_flow_error *error); 1365 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1366 const struct rte_flow_attr *attr, 1367 struct rte_flow_error *error); 1368 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1369 uint64_t action_flags, 1370 const struct rte_flow_attr *attr, 1371 struct rte_flow_error *error); 1372 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1373 uint64_t action_flags, 1374 struct rte_eth_dev *dev, 1375 const struct rte_flow_attr *attr, 1376 struct rte_flow_error *error); 1377 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1378 uint64_t action_flags, 1379 struct rte_eth_dev *dev, 1380 const struct rte_flow_attr *attr, 1381 uint64_t item_flags, 1382 struct rte_flow_error *error); 1383 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1384 const struct rte_flow_attr *attr, 1385 struct rte_flow_error *error); 1386 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1387 const struct rte_flow_attr *attributes, 1388 struct rte_flow_error *error); 1389 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1390 const uint8_t *mask, 1391 const uint8_t *nic_mask, 1392 unsigned int size, 1393 bool range_accepted, 1394 struct rte_flow_error *error); 1395 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1396 uint64_t item_flags, bool ext_vlan_sup, 1397 struct rte_flow_error *error); 1398 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1399 uint64_t item_flags, 1400 uint8_t target_protocol, 1401 struct rte_flow_error *error); 1402 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1403 uint64_t item_flags, 1404 const struct rte_flow_item *gre_item, 1405 struct rte_flow_error *error); 1406 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1407 uint64_t item_flags, 1408 uint64_t last_item, 1409 uint16_t ether_type, 1410 const struct rte_flow_item_ipv4 *acc_mask, 1411 bool range_accepted, 1412 struct rte_flow_error *error); 1413 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1414 uint64_t item_flags, 1415 uint64_t last_item, 1416 uint16_t ether_type, 1417 const struct rte_flow_item_ipv6 *acc_mask, 1418 struct rte_flow_error *error); 1419 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1420 const struct rte_flow_item *item, 1421 uint64_t item_flags, 1422 uint64_t prev_layer, 1423 struct rte_flow_error *error); 1424 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1425 uint64_t item_flags, 1426 uint8_t target_protocol, 1427 const struct rte_flow_item_tcp *flow_mask, 1428 struct rte_flow_error *error); 1429 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1430 uint64_t item_flags, 1431 uint8_t target_protocol, 1432 struct rte_flow_error *error); 1433 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1434 uint64_t item_flags, 1435 struct rte_eth_dev *dev, 1436 struct rte_flow_error *error); 1437 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1438 uint64_t item_flags, 1439 struct rte_flow_error *error); 1440 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1441 uint64_t item_flags, 1442 struct rte_eth_dev *dev, 1443 struct rte_flow_error *error); 1444 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1445 uint64_t item_flags, 1446 uint8_t target_protocol, 1447 struct rte_flow_error *error); 1448 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1449 uint64_t item_flags, 1450 uint8_t target_protocol, 1451 struct rte_flow_error *error); 1452 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1453 uint64_t item_flags, 1454 uint8_t target_protocol, 1455 struct rte_flow_error *error); 1456 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1457 uint64_t item_flags, 1458 struct rte_eth_dev *dev, 1459 struct rte_flow_error *error); 1460 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1461 uint64_t last_item, 1462 const struct rte_flow_item *geneve_item, 1463 struct rte_eth_dev *dev, 1464 struct rte_flow_error *error); 1465 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1466 uint64_t item_flags, 1467 uint64_t last_item, 1468 uint16_t ether_type, 1469 const struct rte_flow_item_ecpri *acc_mask, 1470 struct rte_flow_error *error); 1471 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1472 (struct rte_eth_dev *dev, 1473 const struct mlx5_flow_meter *fm); 1474 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1475 struct mlx5_meter_domains_infos *tbl); 1476 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1477 struct mlx5_flow_meter *fm, 1478 const struct rte_flow_attr *attr); 1479 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1480 struct mlx5_flow_meter *fm, 1481 const struct rte_flow_attr *attr); 1482 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1483 struct rte_mtr_error *error); 1484 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1485 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1486 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1487 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1488 1489 /* Hash list callbacks for flow tables: */ 1490 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1491 uint64_t key, void *entry_ctx); 1492 int flow_dv_tbl_match_cb(struct mlx5_hlist *list, 1493 struct mlx5_hlist_entry *entry, uint64_t key, 1494 void *cb_ctx); 1495 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1496 struct mlx5_hlist_entry *entry); 1497 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1498 uint32_t table_id, uint8_t egress, uint8_t transfer, 1499 bool external, const struct mlx5_flow_tunnel *tunnel, 1500 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error); 1501 1502 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1503 uint64_t key, void *cb_ctx); 1504 int flow_dv_tag_match_cb(struct mlx5_hlist *list, 1505 struct mlx5_hlist_entry *entry, uint64_t key, 1506 void *cb_ctx); 1507 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1508 struct mlx5_hlist_entry *entry); 1509 1510 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1511 struct mlx5_hlist_entry *entry, 1512 uint64_t key, void *cb_ctx); 1513 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1514 uint64_t key, void *ctx); 1515 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1516 struct mlx5_hlist_entry *entry); 1517 1518 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1519 uint64_t key, void *ctx); 1520 int flow_dv_mreg_match_cb(struct mlx5_hlist *list, 1521 struct mlx5_hlist_entry *entry, uint64_t key, 1522 void *cb_ctx); 1523 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1524 struct mlx5_hlist_entry *entry); 1525 1526 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1527 struct mlx5_hlist_entry *entry, 1528 uint64_t key, void *cb_ctx); 1529 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1530 uint64_t key, void *cb_ctx); 1531 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1532 struct mlx5_hlist_entry *entry); 1533 1534 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1535 struct mlx5_cache_entry *entry, void *ctx); 1536 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1537 struct mlx5_cache_entry *entry, void *ctx); 1538 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1539 struct mlx5_cache_entry *entry); 1540 1541 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1542 struct mlx5_cache_entry *entry, void *cb_ctx); 1543 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1544 struct mlx5_cache_entry *entry, void *cb_ctx); 1545 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1546 struct mlx5_cache_entry *entry); 1547 1548 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1549 struct mlx5_cache_entry *entry, void *cb_ctx); 1550 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1551 (struct mlx5_cache_list *list, 1552 struct mlx5_cache_entry *entry, void *cb_ctx); 1553 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1554 struct mlx5_cache_entry *entry); 1555 1556 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1557 struct mlx5_cache_entry *entry, void *cb_ctx); 1558 struct mlx5_cache_entry *flow_dv_sample_create_cb 1559 (struct mlx5_cache_list *list, 1560 struct mlx5_cache_entry *entry, void *cb_ctx); 1561 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1562 struct mlx5_cache_entry *entry); 1563 1564 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1565 struct mlx5_cache_entry *entry, void *cb_ctx); 1566 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1567 (struct mlx5_cache_list *list, 1568 struct mlx5_cache_entry *entry, void *cb_ctx); 1569 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1570 struct mlx5_cache_entry *entry); 1571 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1572 uint32_t age_idx); 1573 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1574 const struct rte_flow_item *item, 1575 struct rte_flow_error *error); 1576 1577 void flow_release_workspace(void *data); 1578 int mlx5_flow_os_init_workspace_once(void); 1579 void *mlx5_flow_os_get_specific_workspace(void); 1580 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1581 void mlx5_flow_os_release_workspace(void); 1582 1583 1584 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1585