1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include "mlx5.h" 25 #include "mlx5_prm.h" 26 27 /* Pattern outer Layer bits. */ 28 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 29 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 30 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 31 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 32 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 33 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 34 35 /* Pattern inner Layer bits. */ 36 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 37 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 38 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 39 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 40 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 41 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 42 43 /* Pattern tunnel Layer bits. */ 44 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 45 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 46 #define MLX5_FLOW_LAYER_GRE (1u << 14) 47 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 48 49 /* General pattern items bits. */ 50 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 51 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 52 53 /* Outer Masks. */ 54 #define MLX5_FLOW_LAYER_OUTER_L3 \ 55 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 56 #define MLX5_FLOW_LAYER_OUTER_L4 \ 57 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 58 #define MLX5_FLOW_LAYER_OUTER \ 59 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 60 MLX5_FLOW_LAYER_OUTER_L4) 61 62 /* Tunnel Masks. */ 63 #define MLX5_FLOW_LAYER_TUNNEL \ 64 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 65 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS) 66 67 /* Inner Masks. */ 68 #define MLX5_FLOW_LAYER_INNER_L3 \ 69 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 70 #define MLX5_FLOW_LAYER_INNER_L4 \ 71 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 72 #define MLX5_FLOW_LAYER_INNER \ 73 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 74 MLX5_FLOW_LAYER_INNER_L4) 75 76 /* Layer Masks. */ 77 #define MLX5_FLOW_LAYER_L2 \ 78 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 79 #define MLX5_FLOW_LAYER_L3_IPV4 \ 80 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 81 #define MLX5_FLOW_LAYER_L3_IPV6 \ 82 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 83 #define MLX5_FLOW_LAYER_L3 \ 84 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 85 #define MLX5_FLOW_LAYER_L4 \ 86 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 87 88 /* Actions */ 89 #define MLX5_FLOW_ACTION_DROP (1u << 0) 90 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 91 #define MLX5_FLOW_ACTION_RSS (1u << 2) 92 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 93 #define MLX5_FLOW_ACTION_MARK (1u << 4) 94 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 95 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 96 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 97 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 98 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 99 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 100 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 101 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 102 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 103 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 104 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 105 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 106 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 107 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 108 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 109 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 110 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 111 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 112 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 113 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 114 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 115 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 116 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 117 118 #define MLX5_FLOW_FATE_ACTIONS \ 119 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 120 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) 121 122 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 123 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 124 MLX5_FLOW_ACTION_JUMP) 125 126 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 127 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 128 MLX5_FLOW_ACTION_RAW_ENCAP) 129 130 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 131 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 132 MLX5_FLOW_ACTION_RAW_DECAP) 133 134 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 135 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 136 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 137 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 138 MLX5_FLOW_ACTION_SET_TP_SRC | \ 139 MLX5_FLOW_ACTION_SET_TP_DST | \ 140 MLX5_FLOW_ACTION_SET_TTL | \ 141 MLX5_FLOW_ACTION_DEC_TTL | \ 142 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 143 MLX5_FLOW_ACTION_SET_MAC_DST) 144 145 #ifndef IPPROTO_MPLS 146 #define IPPROTO_MPLS 137 147 #endif 148 149 /* UDP port number for MPLS */ 150 #define MLX5_UDP_PORT_MPLS 6635 151 152 /* UDP port numbers for VxLAN. */ 153 #define MLX5_UDP_PORT_VXLAN 4789 154 #define MLX5_UDP_PORT_VXLAN_GPE 4790 155 156 /* Priority reserved for default flows. */ 157 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 158 159 /* 160 * Number of sub priorities. 161 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 162 * matching on the NIC (firmware dependent) L4 most have the higher priority 163 * followed by L3 and ending with L2. 164 */ 165 #define MLX5_PRIORITY_MAP_L2 2 166 #define MLX5_PRIORITY_MAP_L3 1 167 #define MLX5_PRIORITY_MAP_L4 0 168 #define MLX5_PRIORITY_MAP_MAX 3 169 170 /* Valid layer type for IPV4 RSS. */ 171 #define MLX5_IPV4_LAYER_TYPES \ 172 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 173 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 174 ETH_RSS_NONFRAG_IPV4_OTHER) 175 176 /* IBV hash source bits for IPV4. */ 177 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 178 179 /* Valid layer type for IPV6 RSS. */ 180 #define MLX5_IPV6_LAYER_TYPES \ 181 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 182 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 183 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 184 185 /* IBV hash source bits for IPV6. */ 186 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 187 188 enum mlx5_flow_drv_type { 189 MLX5_FLOW_TYPE_MIN, 190 MLX5_FLOW_TYPE_DV, 191 MLX5_FLOW_TYPE_TCF, 192 MLX5_FLOW_TYPE_VERBS, 193 MLX5_FLOW_TYPE_MAX, 194 }; 195 196 /* Matcher PRM representation */ 197 struct mlx5_flow_dv_match_params { 198 size_t size; 199 /**< Size of match value. Do NOT split size and key! */ 200 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 201 /**< Matcher value. This value is used as the mask or as a key. */ 202 }; 203 204 /* Matcher structure. */ 205 struct mlx5_flow_dv_matcher { 206 LIST_ENTRY(mlx5_flow_dv_matcher) next; 207 /* Pointer to the next element. */ 208 rte_atomic32_t refcnt; /**< Reference counter. */ 209 void *matcher_object; /**< Pointer to DV matcher */ 210 uint16_t crc; /**< CRC of key. */ 211 uint16_t priority; /**< Priority of matcher. */ 212 uint8_t egress; /**< Egress matcher. */ 213 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 214 uint32_t group; /**< The matcher group. */ 215 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 216 }; 217 218 #define MLX5_ENCAP_MAX_LEN 132 219 220 /* Encap/decap resource structure. */ 221 struct mlx5_flow_dv_encap_decap_resource { 222 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 223 /* Pointer to next element. */ 224 rte_atomic32_t refcnt; /**< Reference counter. */ 225 void *verbs_action; 226 /**< Verbs encap/decap action object. */ 227 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 228 size_t size; 229 uint8_t reformat_type; 230 uint8_t ft_type; 231 uint64_t flags; /**< Flags for RDMA API. */ 232 }; 233 234 /* Tag resource structure. */ 235 struct mlx5_flow_dv_tag_resource { 236 LIST_ENTRY(mlx5_flow_dv_tag_resource) next; 237 /* Pointer to next element. */ 238 rte_atomic32_t refcnt; /**< Reference counter. */ 239 void *action; 240 /**< Verbs tag action object. */ 241 uint32_t tag; /**< the tag value. */ 242 }; 243 244 /* Number of modification commands. */ 245 #define MLX5_MODIFY_NUM 8 246 247 /* Modify resource structure */ 248 struct mlx5_flow_dv_modify_hdr_resource { 249 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 250 /* Pointer to next element. */ 251 rte_atomic32_t refcnt; /**< Reference counter. */ 252 struct ibv_flow_action *verbs_action; 253 /**< Verbs modify header action object. */ 254 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 255 uint32_t actions_num; /**< Number of modification actions. */ 256 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM]; 257 /**< Modification actions. */ 258 uint64_t flags; /**< Flags for RDMA API. */ 259 }; 260 261 /* Jump action resource structure. */ 262 struct mlx5_flow_dv_jump_tbl_resource { 263 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next; 264 /* Pointer to next element. */ 265 rte_atomic32_t refcnt; /**< Reference counter. */ 266 void *action; /**< Pointer to the rdma core action. */ 267 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 268 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */ 269 }; 270 271 /* Port ID resource structure. */ 272 struct mlx5_flow_dv_port_id_action_resource { 273 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next; 274 /* Pointer to next element. */ 275 rte_atomic32_t refcnt; /**< Reference counter. */ 276 void *action; 277 /**< Verbs tag action object. */ 278 uint32_t port_id; /**< Port ID value. */ 279 }; 280 281 /* 282 * Max number of actions per DV flow. 283 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 284 * In rdma-core file providers/mlx5/verbs.c 285 */ 286 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 287 288 /* DV flows structure. */ 289 struct mlx5_flow_dv { 290 uint64_t hash_fields; /**< Fields that participate in the hash. */ 291 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 292 /* Flow DV api: */ 293 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 294 struct mlx5_flow_dv_match_params value; 295 /**< Holds the value that the packet is compared to. */ 296 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 297 /**< Pointer to encap/decap resource in cache. */ 298 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 299 /**< Pointer to modify header resource in cache. */ 300 struct ibv_flow *flow; /**< Installed flow. */ 301 struct mlx5_flow_dv_jump_tbl_resource *jump; 302 /**< Pointer to the jump action resource. */ 303 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 304 /**< Pointer to port ID action resource. */ 305 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 306 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 307 /**< Action list. */ 308 #endif 309 int actions_n; /**< number of actions. */ 310 }; 311 312 /** Linux TC flower driver for E-Switch flow. */ 313 struct mlx5_flow_tcf { 314 struct nlmsghdr *nlh; 315 struct tcmsg *tcm; 316 uint32_t *ptc_flags; /**< tc rule applied flags. */ 317 union { /**< Tunnel encap/decap descriptor. */ 318 struct flow_tcf_tunnel_hdr *tunnel; 319 struct flow_tcf_vxlan_decap *vxlan_decap; 320 struct flow_tcf_vxlan_encap *vxlan_encap; 321 }; 322 uint32_t applied:1; /**< Whether rule is currently applied. */ 323 #ifndef NDEBUG 324 uint32_t nlsize; /**< Size of NL message buffer for debug check. */ 325 #endif 326 }; 327 328 /* Verbs specification header. */ 329 struct ibv_spec_header { 330 enum ibv_flow_spec_type type; 331 uint16_t size; 332 }; 333 334 /** Handles information leading to a drop fate. */ 335 struct mlx5_flow_verbs { 336 LIST_ENTRY(mlx5_flow_verbs) next; 337 unsigned int size; /**< Size of the attribute. */ 338 struct { 339 struct ibv_flow_attr *attr; 340 /**< Pointer to the Specification buffer. */ 341 uint8_t *specs; /**< Pointer to the specifications. */ 342 }; 343 struct ibv_flow *flow; /**< Verbs flow pointer. */ 344 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 345 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 346 }; 347 348 /** Device flow structure. */ 349 struct mlx5_flow { 350 LIST_ENTRY(mlx5_flow) next; 351 struct rte_flow *flow; /**< Pointer to the main flow. */ 352 uint64_t layers; 353 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 354 union { 355 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 356 struct mlx5_flow_dv dv; 357 #endif 358 struct mlx5_flow_tcf tcf; 359 struct mlx5_flow_verbs verbs; 360 }; 361 }; 362 363 /* Counters information. */ 364 struct mlx5_flow_counter { 365 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */ 366 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 367 uint32_t ref_cnt:31; /**< Reference counter. */ 368 uint32_t id; /**< Counter ID. */ 369 union { /**< Holds the counters for the rule. */ 370 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 371 struct ibv_counter_set *cs; 372 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 373 struct ibv_counters *cs; 374 #endif 375 struct mlx5_devx_counter_set *dcs; 376 }; 377 uint64_t hits; /**< Number of packets matched by the rule. */ 378 uint64_t bytes; /**< Number of bytes matched by the rule. */ 379 void *action; /**< Pointer to the dv action. */ 380 }; 381 382 /* Flow structure. */ 383 struct rte_flow { 384 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 385 enum mlx5_flow_drv_type drv_type; /**< Driver type. */ 386 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 387 struct mlx5_flow_dv_tag_resource *tag_resource; 388 /**< pointer to the tag action. */ 389 struct rte_flow_action_rss rss;/**< RSS context. */ 390 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 391 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 392 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 393 /**< Device flows that are part of the flow. */ 394 uint64_t actions; 395 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 396 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 397 uint8_t ingress; /**< 1 if the flow is ingress. */ 398 uint32_t group; /**< The group index. */ 399 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 400 }; 401 402 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 403 const struct rte_flow_attr *attr, 404 const struct rte_flow_item items[], 405 const struct rte_flow_action actions[], 406 struct rte_flow_error *error); 407 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 408 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 409 const struct rte_flow_action actions[], struct rte_flow_error *error); 410 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 411 struct mlx5_flow *dev_flow, 412 const struct rte_flow_attr *attr, 413 const struct rte_flow_item items[], 414 const struct rte_flow_action actions[], 415 struct rte_flow_error *error); 416 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 417 struct rte_flow_error *error); 418 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 419 struct rte_flow *flow); 420 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 421 struct rte_flow *flow); 422 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 423 struct rte_flow *flow, 424 const struct rte_flow_action *actions, 425 void *data, 426 struct rte_flow_error *error); 427 struct mlx5_flow_driver_ops { 428 mlx5_flow_validate_t validate; 429 mlx5_flow_prepare_t prepare; 430 mlx5_flow_translate_t translate; 431 mlx5_flow_apply_t apply; 432 mlx5_flow_remove_t remove; 433 mlx5_flow_destroy_t destroy; 434 mlx5_flow_query_t query; 435 }; 436 437 /* mlx5_flow.c */ 438 439 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 440 uint64_t layer_types, 441 uint64_t hash_fields); 442 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 443 uint32_t subpriority); 444 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 445 const struct rte_flow_attr *attr, 446 struct rte_flow_error *error); 447 int mlx5_flow_validate_action_drop(uint64_t action_flags, 448 const struct rte_flow_attr *attr, 449 struct rte_flow_error *error); 450 int mlx5_flow_validate_action_flag(uint64_t action_flags, 451 const struct rte_flow_attr *attr, 452 struct rte_flow_error *error); 453 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 454 uint64_t action_flags, 455 const struct rte_flow_attr *attr, 456 struct rte_flow_error *error); 457 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 458 uint64_t action_flags, 459 struct rte_eth_dev *dev, 460 const struct rte_flow_attr *attr, 461 struct rte_flow_error *error); 462 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 463 uint64_t action_flags, 464 struct rte_eth_dev *dev, 465 const struct rte_flow_attr *attr, 466 uint64_t item_flags, 467 struct rte_flow_error *error); 468 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 469 const struct rte_flow_attr *attributes, 470 struct rte_flow_error *error); 471 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 472 const uint8_t *mask, 473 const uint8_t *nic_mask, 474 unsigned int size, 475 struct rte_flow_error *error); 476 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 477 uint64_t item_flags, 478 struct rte_flow_error *error); 479 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 480 uint64_t item_flags, 481 uint8_t target_protocol, 482 struct rte_flow_error *error); 483 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 484 uint64_t item_flags, 485 const struct rte_flow_item_ipv4 *acc_mask, 486 struct rte_flow_error *error); 487 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 488 uint64_t item_flags, 489 const struct rte_flow_item_ipv6 *acc_mask, 490 struct rte_flow_error *error); 491 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 492 const struct rte_flow_item *item, 493 uint64_t item_flags, 494 uint64_t prev_layer, 495 struct rte_flow_error *error); 496 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 497 uint64_t item_flags, 498 uint8_t target_protocol, 499 const struct rte_flow_item_tcp *flow_mask, 500 struct rte_flow_error *error); 501 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 502 uint64_t item_flags, 503 uint8_t target_protocol, 504 struct rte_flow_error *error); 505 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 506 uint64_t item_flags, 507 struct rte_flow_error *error); 508 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 509 uint64_t item_flags, 510 struct rte_flow_error *error); 511 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 512 uint64_t item_flags, 513 struct rte_eth_dev *dev, 514 struct rte_flow_error *error); 515 516 /* mlx5_flow_tcf.c */ 517 518 int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx, 519 unsigned int ifindex, struct rte_flow_error *error); 520 struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void); 521 void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx); 522 523 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 524