1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 /* Verbs header. */ 15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 16 #ifdef PEDANTIC 17 #pragma GCC diagnostic ignored "-Wpedantic" 18 #endif 19 #include <infiniband/verbs.h> 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic error "-Wpedantic" 22 #endif 23 24 #include <rte_atomic.h> 25 #include <rte_alarm.h> 26 27 #include "mlx5.h" 28 #include "mlx5_prm.h" 29 30 /* Pattern outer Layer bits. */ 31 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 32 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 33 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 34 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 35 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 36 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 37 38 /* Pattern inner Layer bits. */ 39 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 40 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 41 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 42 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 43 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 44 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 45 46 /* Pattern tunnel Layer bits. */ 47 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 48 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 49 #define MLX5_FLOW_LAYER_GRE (1u << 14) 50 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 51 /* List of tunnel Layer bits continued below. */ 52 53 /* General pattern items bits. */ 54 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 55 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 56 57 /* Pattern MISC bits. */ 58 #define MLX5_FLOW_LAYER_ICMP (1u << 18) 59 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19) 60 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20) 61 62 /* Pattern tunnel Layer bits (continued). */ 63 #define MLX5_FLOW_LAYER_IPIP (1u << 21) 64 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22) 65 #define MLX5_FLOW_LAYER_NVGRE (1u << 23) 66 67 /* Outer Masks. */ 68 #define MLX5_FLOW_LAYER_OUTER_L3 \ 69 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 70 #define MLX5_FLOW_LAYER_OUTER_L4 \ 71 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 72 #define MLX5_FLOW_LAYER_OUTER \ 73 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 74 MLX5_FLOW_LAYER_OUTER_L4) 75 76 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */ 77 #define MLX5_FLOW_LAYER_IPV4_LRO \ 78 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP) 79 #define MLX5_FLOW_LAYER_IPV6_LRO \ 80 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP) 81 82 /* Tunnel Masks. */ 83 #define MLX5_FLOW_LAYER_TUNNEL \ 84 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 85 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 86 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP) 87 88 /* Inner Masks. */ 89 #define MLX5_FLOW_LAYER_INNER_L3 \ 90 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 91 #define MLX5_FLOW_LAYER_INNER_L4 \ 92 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 93 #define MLX5_FLOW_LAYER_INNER \ 94 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 95 MLX5_FLOW_LAYER_INNER_L4) 96 97 /* Layer Masks. */ 98 #define MLX5_FLOW_LAYER_L2 \ 99 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 100 #define MLX5_FLOW_LAYER_L3_IPV4 \ 101 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 102 #define MLX5_FLOW_LAYER_L3_IPV6 \ 103 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 104 #define MLX5_FLOW_LAYER_L3 \ 105 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 106 #define MLX5_FLOW_LAYER_L4 \ 107 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 108 109 /* Actions */ 110 #define MLX5_FLOW_ACTION_DROP (1u << 0) 111 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 112 #define MLX5_FLOW_ACTION_RSS (1u << 2) 113 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 114 #define MLX5_FLOW_ACTION_MARK (1u << 4) 115 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 116 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 117 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 118 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 119 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 120 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 121 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 122 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 123 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 124 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 125 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 126 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 127 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 128 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 129 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 130 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 131 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 132 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 133 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 134 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 135 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 136 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 137 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 138 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28) 139 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29) 140 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30) 141 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31) 142 143 #define MLX5_FLOW_FATE_ACTIONS \ 144 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 145 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) 146 147 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 148 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 149 MLX5_FLOW_ACTION_JUMP) 150 151 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 152 MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 153 MLX5_FLOW_ACTION_RAW_ENCAP | \ 154 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 155 156 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 157 MLX5_FLOW_ACTION_NVGRE_DECAP | \ 158 MLX5_FLOW_ACTION_RAW_DECAP | \ 159 MLX5_FLOW_ACTION_OF_POP_VLAN) 160 161 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 162 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 163 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 164 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 165 MLX5_FLOW_ACTION_SET_TP_SRC | \ 166 MLX5_FLOW_ACTION_SET_TP_DST | \ 167 MLX5_FLOW_ACTION_SET_TTL | \ 168 MLX5_FLOW_ACTION_DEC_TTL | \ 169 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 170 MLX5_FLOW_ACTION_SET_MAC_DST | \ 171 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 172 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 173 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 174 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 175 MLX5_FLOW_ACTION_OF_SET_VLAN_VID) 176 177 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 178 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 179 180 #ifndef IPPROTO_MPLS 181 #define IPPROTO_MPLS 137 182 #endif 183 184 /* UDP port number for MPLS */ 185 #define MLX5_UDP_PORT_MPLS 6635 186 187 /* UDP port numbers for VxLAN. */ 188 #define MLX5_UDP_PORT_VXLAN 4789 189 #define MLX5_UDP_PORT_VXLAN_GPE 4790 190 191 /* Priority reserved for default flows. */ 192 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 193 194 /* 195 * Number of sub priorities. 196 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 197 * matching on the NIC (firmware dependent) L4 most have the higher priority 198 * followed by L3 and ending with L2. 199 */ 200 #define MLX5_PRIORITY_MAP_L2 2 201 #define MLX5_PRIORITY_MAP_L3 1 202 #define MLX5_PRIORITY_MAP_L4 0 203 #define MLX5_PRIORITY_MAP_MAX 3 204 205 /* Valid layer type for IPV4 RSS. */ 206 #define MLX5_IPV4_LAYER_TYPES \ 207 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 208 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 209 ETH_RSS_NONFRAG_IPV4_OTHER) 210 211 /* IBV hash source bits for IPV4. */ 212 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 213 214 /* Valid layer type for IPV6 RSS. */ 215 #define MLX5_IPV6_LAYER_TYPES \ 216 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 217 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 218 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 219 220 /* IBV hash source bits for IPV6. */ 221 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 222 223 enum mlx5_flow_drv_type { 224 MLX5_FLOW_TYPE_MIN, 225 MLX5_FLOW_TYPE_DV, 226 MLX5_FLOW_TYPE_VERBS, 227 MLX5_FLOW_TYPE_MAX, 228 }; 229 230 /* Matcher PRM representation */ 231 struct mlx5_flow_dv_match_params { 232 size_t size; 233 /**< Size of match value. Do NOT split size and key! */ 234 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 235 /**< Matcher value. This value is used as the mask or as a key. */ 236 }; 237 238 /* Matcher structure. */ 239 struct mlx5_flow_dv_matcher { 240 LIST_ENTRY(mlx5_flow_dv_matcher) next; 241 /* Pointer to the next element. */ 242 rte_atomic32_t refcnt; /**< Reference counter. */ 243 void *matcher_object; /**< Pointer to DV matcher */ 244 uint16_t crc; /**< CRC of key. */ 245 uint16_t priority; /**< Priority of matcher. */ 246 uint8_t egress; /**< Egress matcher. */ 247 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 248 uint32_t group; /**< The matcher group. */ 249 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 250 }; 251 252 #define MLX5_ENCAP_MAX_LEN 132 253 254 /* Encap/decap resource structure. */ 255 struct mlx5_flow_dv_encap_decap_resource { 256 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 257 /* Pointer to next element. */ 258 rte_atomic32_t refcnt; /**< Reference counter. */ 259 void *verbs_action; 260 /**< Verbs encap/decap action object. */ 261 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 262 size_t size; 263 uint8_t reformat_type; 264 uint8_t ft_type; 265 uint64_t flags; /**< Flags for RDMA API. */ 266 }; 267 268 /* Tag resource structure. */ 269 struct mlx5_flow_dv_tag_resource { 270 LIST_ENTRY(mlx5_flow_dv_tag_resource) next; 271 /* Pointer to next element. */ 272 rte_atomic32_t refcnt; /**< Reference counter. */ 273 void *action; 274 /**< Verbs tag action object. */ 275 uint32_t tag; /**< the tag value. */ 276 }; 277 278 /* Number of modification commands. */ 279 #define MLX5_MODIFY_NUM 8 280 281 /* Modify resource structure */ 282 struct mlx5_flow_dv_modify_hdr_resource { 283 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 284 /* Pointer to next element. */ 285 rte_atomic32_t refcnt; /**< Reference counter. */ 286 struct ibv_flow_action *verbs_action; 287 /**< Verbs modify header action object. */ 288 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 289 uint32_t actions_num; /**< Number of modification actions. */ 290 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM]; 291 /**< Modification actions. */ 292 uint64_t flags; /**< Flags for RDMA API. */ 293 }; 294 295 /* Jump action resource structure. */ 296 struct mlx5_flow_dv_jump_tbl_resource { 297 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next; 298 /* Pointer to next element. */ 299 rte_atomic32_t refcnt; /**< Reference counter. */ 300 void *action; /**< Pointer to the rdma core action. */ 301 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 302 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */ 303 }; 304 305 /* Port ID resource structure. */ 306 struct mlx5_flow_dv_port_id_action_resource { 307 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next; 308 /* Pointer to next element. */ 309 rte_atomic32_t refcnt; /**< Reference counter. */ 310 void *action; 311 /**< Verbs tag action object. */ 312 uint32_t port_id; /**< Port ID value. */ 313 }; 314 315 /* Push VLAN action resource structure */ 316 struct mlx5_flow_dv_push_vlan_action_resource { 317 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next; 318 /* Pointer to next element. */ 319 rte_atomic32_t refcnt; /**< Reference counter. */ 320 void *action; /**< Direct verbs action object. */ 321 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 322 rte_be32_t vlan_tag; /**< VLAN tag value. */ 323 }; 324 325 /* 326 * Max number of actions per DV flow. 327 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 328 * In rdma-core file providers/mlx5/verbs.c 329 */ 330 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 331 332 /* DV flows structure. */ 333 struct mlx5_flow_dv { 334 uint64_t hash_fields; /**< Fields that participate in the hash. */ 335 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 336 /* Flow DV api: */ 337 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 338 struct mlx5_flow_dv_match_params value; 339 /**< Holds the value that the packet is compared to. */ 340 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 341 /**< Pointer to encap/decap resource in cache. */ 342 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 343 /**< Pointer to modify header resource in cache. */ 344 struct ibv_flow *flow; /**< Installed flow. */ 345 struct mlx5_flow_dv_jump_tbl_resource *jump; 346 /**< Pointer to the jump action resource. */ 347 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 348 /**< Pointer to port ID action resource. */ 349 struct mlx5_vf_vlan vf_vlan; 350 /**< Structure for VF VLAN workaround. */ 351 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 352 /**< Pointer to push VLAN action resource in cache. */ 353 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 354 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 355 /**< Action list. */ 356 #endif 357 int actions_n; /**< number of actions. */ 358 }; 359 360 /* Verbs specification header. */ 361 struct ibv_spec_header { 362 enum ibv_flow_spec_type type; 363 uint16_t size; 364 }; 365 366 /** Handles information leading to a drop fate. */ 367 struct mlx5_flow_verbs { 368 LIST_ENTRY(mlx5_flow_verbs) next; 369 unsigned int size; /**< Size of the attribute. */ 370 struct { 371 struct ibv_flow_attr *attr; 372 /**< Pointer to the Specification buffer. */ 373 uint8_t *specs; /**< Pointer to the specifications. */ 374 }; 375 struct ibv_flow *flow; /**< Verbs flow pointer. */ 376 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 377 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 378 struct mlx5_vf_vlan vf_vlan; 379 /**< Structure for VF VLAN workaround. */ 380 }; 381 382 /** Device flow structure. */ 383 struct mlx5_flow { 384 LIST_ENTRY(mlx5_flow) next; 385 struct rte_flow *flow; /**< Pointer to the main flow. */ 386 uint64_t layers; 387 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 388 union { 389 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 390 struct mlx5_flow_dv dv; 391 #endif 392 struct mlx5_flow_verbs verbs; 393 }; 394 bool external; /**< true if the flow is created external to PMD. */ 395 }; 396 397 /* Flow structure. */ 398 struct rte_flow { 399 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 400 enum mlx5_flow_drv_type drv_type; /**< Driver type. */ 401 struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 402 struct mlx5_flow_dv_tag_resource *tag_resource; 403 /**< pointer to the tag action. */ 404 struct rte_flow_action_rss rss;/**< RSS context. */ 405 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 406 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 407 LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 408 /**< Device flows that are part of the flow. */ 409 uint64_t actions; 410 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 411 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 412 uint8_t ingress; /**< 1 if the flow is ingress. */ 413 uint32_t group; /**< The group index. */ 414 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 415 }; 416 417 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 418 const struct rte_flow_attr *attr, 419 const struct rte_flow_item items[], 420 const struct rte_flow_action actions[], 421 bool external, 422 struct rte_flow_error *error); 423 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 424 (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 425 const struct rte_flow_action actions[], struct rte_flow_error *error); 426 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 427 struct mlx5_flow *dev_flow, 428 const struct rte_flow_attr *attr, 429 const struct rte_flow_item items[], 430 const struct rte_flow_action actions[], 431 struct rte_flow_error *error); 432 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 433 struct rte_flow_error *error); 434 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 435 struct rte_flow *flow); 436 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 437 struct rte_flow *flow); 438 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 439 struct rte_flow *flow, 440 const struct rte_flow_action *actions, 441 void *data, 442 struct rte_flow_error *error); 443 struct mlx5_flow_driver_ops { 444 mlx5_flow_validate_t validate; 445 mlx5_flow_prepare_t prepare; 446 mlx5_flow_translate_t translate; 447 mlx5_flow_apply_t apply; 448 mlx5_flow_remove_t remove; 449 mlx5_flow_destroy_t destroy; 450 mlx5_flow_query_t query; 451 }; 452 453 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \ 454 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) 455 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \ 456 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) 457 458 /* mlx5_flow.c */ 459 460 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, 461 bool external, uint32_t group, uint32_t *table, 462 struct rte_flow_error *error); 463 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 464 uint64_t layer_types, 465 uint64_t hash_fields); 466 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 467 uint32_t subpriority); 468 const struct rte_flow_action *mlx5_flow_find_action 469 (const struct rte_flow_action *actions, 470 enum rte_flow_action_type action); 471 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 472 const struct rte_flow_attr *attr, 473 struct rte_flow_error *error); 474 int mlx5_flow_validate_action_drop(uint64_t action_flags, 475 const struct rte_flow_attr *attr, 476 struct rte_flow_error *error); 477 int mlx5_flow_validate_action_flag(uint64_t action_flags, 478 const struct rte_flow_attr *attr, 479 struct rte_flow_error *error); 480 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 481 uint64_t action_flags, 482 const struct rte_flow_attr *attr, 483 struct rte_flow_error *error); 484 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 485 uint64_t action_flags, 486 struct rte_eth_dev *dev, 487 const struct rte_flow_attr *attr, 488 struct rte_flow_error *error); 489 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 490 uint64_t action_flags, 491 struct rte_eth_dev *dev, 492 const struct rte_flow_attr *attr, 493 uint64_t item_flags, 494 struct rte_flow_error *error); 495 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 496 const struct rte_flow_attr *attributes, 497 struct rte_flow_error *error); 498 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 499 const uint8_t *mask, 500 const uint8_t *nic_mask, 501 unsigned int size, 502 struct rte_flow_error *error); 503 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 504 uint64_t item_flags, 505 struct rte_flow_error *error); 506 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 507 uint64_t item_flags, 508 uint8_t target_protocol, 509 struct rte_flow_error *error); 510 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 511 uint64_t item_flags, 512 const struct rte_flow_item *gre_item, 513 struct rte_flow_error *error); 514 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 515 uint64_t item_flags, 516 const struct rte_flow_item_ipv4 *acc_mask, 517 struct rte_flow_error *error); 518 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 519 uint64_t item_flags, 520 const struct rte_flow_item_ipv6 *acc_mask, 521 struct rte_flow_error *error); 522 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 523 const struct rte_flow_item *item, 524 uint64_t item_flags, 525 uint64_t prev_layer, 526 struct rte_flow_error *error); 527 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 528 uint64_t item_flags, 529 uint8_t target_protocol, 530 const struct rte_flow_item_tcp *flow_mask, 531 struct rte_flow_error *error); 532 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 533 uint64_t item_flags, 534 uint8_t target_protocol, 535 struct rte_flow_error *error); 536 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 537 uint64_t item_flags, 538 struct rte_eth_dev *dev, 539 struct rte_flow_error *error); 540 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 541 uint64_t item_flags, 542 struct rte_flow_error *error); 543 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 544 uint64_t item_flags, 545 struct rte_eth_dev *dev, 546 struct rte_flow_error *error); 547 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 548 uint64_t item_flags, 549 uint8_t target_protocol, 550 struct rte_flow_error *error); 551 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 552 uint64_t item_flags, 553 uint8_t target_protocol, 554 struct rte_flow_error *error); 555 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 556 uint64_t item_flags, 557 uint8_t target_protocol, 558 struct rte_flow_error *error); 559 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 560