1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 #include <rte_atomic.h> 15 #include <rte_alarm.h> 16 #include <rte_mtr.h> 17 18 #include <mlx5_glue.h> 19 #include <mlx5_prm.h> 20 21 #include "mlx5.h" 22 23 /* Private rte flow items. */ 24 enum mlx5_rte_flow_item_type { 25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 26 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 29 }; 30 31 /* Private (internal) rte flow actions. */ 32 enum mlx5_rte_flow_action_type { 33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 35 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 38 }; 39 40 /* Matches on selected register. */ 41 struct mlx5_rte_flow_item_tag { 42 enum modify_reg id; 43 uint32_t data; 44 }; 45 46 /* Modify selected register. */ 47 struct mlx5_rte_flow_action_set_tag { 48 enum modify_reg id; 49 uint32_t data; 50 }; 51 52 struct mlx5_flow_action_copy_mreg { 53 enum modify_reg dst; 54 enum modify_reg src; 55 }; 56 57 /* Matches on source queue. */ 58 struct mlx5_rte_flow_item_tx_queue { 59 uint32_t queue; 60 }; 61 62 /* Feature name to allocate metadata register. */ 63 enum mlx5_feature_name { 64 MLX5_HAIRPIN_RX, 65 MLX5_HAIRPIN_TX, 66 MLX5_METADATA_RX, 67 MLX5_METADATA_TX, 68 MLX5_METADATA_FDB, 69 MLX5_FLOW_MARK, 70 MLX5_APP_TAG, 71 MLX5_COPY_MARK, 72 MLX5_MTR_COLOR, 73 MLX5_MTR_SFX, 74 }; 75 76 /* Pattern outer Layer bits. */ 77 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 78 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 80 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 81 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 82 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 83 84 /* Pattern inner Layer bits. */ 85 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 86 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 87 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 88 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 89 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 90 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 91 92 /* Pattern tunnel Layer bits. */ 93 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 94 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 95 #define MLX5_FLOW_LAYER_GRE (1u << 14) 96 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 97 /* List of tunnel Layer bits continued below. */ 98 99 /* General pattern items bits. */ 100 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 101 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 102 #define MLX5_FLOW_ITEM_TAG (1u << 18) 103 #define MLX5_FLOW_ITEM_MARK (1u << 19) 104 105 /* Pattern MISC bits. */ 106 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 107 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 108 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 109 110 /* Pattern tunnel Layer bits (continued). */ 111 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 112 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 113 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 114 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 115 116 /* Queue items. */ 117 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 118 119 /* Pattern tunnel Layer bits (continued). */ 120 #define MLX5_FLOW_LAYER_GTP (1u << 28) 121 122 /* Pattern eCPRI Layer bit. */ 123 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 124 125 /* Outer Masks. */ 126 #define MLX5_FLOW_LAYER_OUTER_L3 \ 127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 128 #define MLX5_FLOW_LAYER_OUTER_L4 \ 129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 130 #define MLX5_FLOW_LAYER_OUTER \ 131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 132 MLX5_FLOW_LAYER_OUTER_L4) 133 134 /* Tunnel Masks. */ 135 #define MLX5_FLOW_LAYER_TUNNEL \ 136 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 137 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 138 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 139 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 140 141 /* Inner Masks. */ 142 #define MLX5_FLOW_LAYER_INNER_L3 \ 143 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 144 #define MLX5_FLOW_LAYER_INNER_L4 \ 145 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 146 #define MLX5_FLOW_LAYER_INNER \ 147 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 148 MLX5_FLOW_LAYER_INNER_L4) 149 150 /* Layer Masks. */ 151 #define MLX5_FLOW_LAYER_L2 \ 152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 153 #define MLX5_FLOW_LAYER_L3_IPV4 \ 154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 155 #define MLX5_FLOW_LAYER_L3_IPV6 \ 156 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 157 #define MLX5_FLOW_LAYER_L3 \ 158 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 159 #define MLX5_FLOW_LAYER_L4 \ 160 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 161 162 /* Actions */ 163 #define MLX5_FLOW_ACTION_DROP (1u << 0) 164 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 165 #define MLX5_FLOW_ACTION_RSS (1u << 2) 166 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 167 #define MLX5_FLOW_ACTION_MARK (1u << 4) 168 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 169 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 170 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 171 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 172 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 174 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 175 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 176 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 177 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 178 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 179 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 180 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 181 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 182 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 183 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 184 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 185 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 186 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 187 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 188 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 189 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 190 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 191 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 192 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 193 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 194 #define MLX5_FLOW_ACTION_METER (1ull << 31) 195 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 196 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 197 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 198 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 199 200 #define MLX5_FLOW_FATE_ACTIONS \ 201 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 202 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 203 MLX5_FLOW_ACTION_DEFAULT_MISS) 204 205 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 207 MLX5_FLOW_ACTION_JUMP) 208 209 210 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 211 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 212 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 213 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 214 MLX5_FLOW_ACTION_SET_TP_SRC | \ 215 MLX5_FLOW_ACTION_SET_TP_DST | \ 216 MLX5_FLOW_ACTION_SET_TTL | \ 217 MLX5_FLOW_ACTION_DEC_TTL | \ 218 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 219 MLX5_FLOW_ACTION_SET_MAC_DST | \ 220 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 221 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 222 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 223 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 224 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 225 MLX5_FLOW_ACTION_SET_TAG | \ 226 MLX5_FLOW_ACTION_MARK_EXT | \ 227 MLX5_FLOW_ACTION_SET_META | \ 228 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 229 MLX5_FLOW_ACTION_SET_IPV6_DSCP) 230 231 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 232 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 233 234 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 235 236 #ifndef IPPROTO_MPLS 237 #define IPPROTO_MPLS 137 238 #endif 239 240 /* UDP port number for MPLS */ 241 #define MLX5_UDP_PORT_MPLS 6635 242 243 /* UDP port numbers for VxLAN. */ 244 #define MLX5_UDP_PORT_VXLAN 4789 245 #define MLX5_UDP_PORT_VXLAN_GPE 4790 246 247 /* UDP port numbers for GENEVE. */ 248 #define MLX5_UDP_PORT_GENEVE 6081 249 250 /* Priority reserved for default flows. */ 251 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 252 253 /* 254 * Number of sub priorities. 255 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 256 * matching on the NIC (firmware dependent) L4 most have the higher priority 257 * followed by L3 and ending with L2. 258 */ 259 #define MLX5_PRIORITY_MAP_L2 2 260 #define MLX5_PRIORITY_MAP_L3 1 261 #define MLX5_PRIORITY_MAP_L4 0 262 #define MLX5_PRIORITY_MAP_MAX 3 263 264 /* Valid layer type for IPV4 RSS. */ 265 #define MLX5_IPV4_LAYER_TYPES \ 266 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 267 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 268 ETH_RSS_NONFRAG_IPV4_OTHER) 269 270 /* IBV hash source bits for IPV4. */ 271 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 272 273 /* Valid layer type for IPV6 RSS. */ 274 #define MLX5_IPV6_LAYER_TYPES \ 275 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 276 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 277 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 278 279 /* IBV hash source bits for IPV6. */ 280 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 281 282 /* IBV hash bits for L3 SRC. */ 283 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 284 285 /* IBV hash bits for L3 DST. */ 286 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 287 288 /* IBV hash bits for TCP. */ 289 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 290 IBV_RX_HASH_DST_PORT_TCP) 291 292 /* IBV hash bits for UDP. */ 293 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 294 IBV_RX_HASH_DST_PORT_UDP) 295 296 /* IBV hash bits for L4 SRC. */ 297 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 298 IBV_RX_HASH_SRC_PORT_UDP) 299 300 /* IBV hash bits for L4 DST. */ 301 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 302 IBV_RX_HASH_DST_PORT_UDP) 303 304 /* Geneve header first 16Bit */ 305 #define MLX5_GENEVE_VER_MASK 0x3 306 #define MLX5_GENEVE_VER_SHIFT 14 307 #define MLX5_GENEVE_VER_VAL(a) \ 308 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 309 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 310 #define MLX5_GENEVE_OPTLEN_SHIFT 7 311 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 312 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 313 #define MLX5_GENEVE_OAMF_MASK 0x1 314 #define MLX5_GENEVE_OAMF_SHIFT 7 315 #define MLX5_GENEVE_OAMF_VAL(a) \ 316 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 317 #define MLX5_GENEVE_CRITO_MASK 0x1 318 #define MLX5_GENEVE_CRITO_SHIFT 6 319 #define MLX5_GENEVE_CRITO_VAL(a) \ 320 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 321 #define MLX5_GENEVE_RSVD_MASK 0x3F 322 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 323 /* 324 * The length of the Geneve options fields, expressed in four byte multiples, 325 * not including the eight byte fixed tunnel. 326 */ 327 #define MLX5_GENEVE_OPT_LEN_0 14 328 #define MLX5_GENEVE_OPT_LEN_1 63 329 330 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \ 331 sizeof(struct rte_flow_item_ipv4)) 332 333 /* Software header modify action numbers of a flow. */ 334 #define MLX5_ACT_NUM_MDF_IPV4 1 335 #define MLX5_ACT_NUM_MDF_IPV6 4 336 #define MLX5_ACT_NUM_MDF_MAC 2 337 #define MLX5_ACT_NUM_MDF_VID 1 338 #define MLX5_ACT_NUM_MDF_PORT 2 339 #define MLX5_ACT_NUM_MDF_TTL 1 340 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 341 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 342 #define MLX5_ACT_NUM_MDF_TCPACK 1 343 #define MLX5_ACT_NUM_SET_REG 1 344 #define MLX5_ACT_NUM_SET_TAG 1 345 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 346 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 347 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 348 #define MLX5_ACT_NUM_SET_DSCP 1 349 350 enum mlx5_flow_drv_type { 351 MLX5_FLOW_TYPE_MIN, 352 MLX5_FLOW_TYPE_DV, 353 MLX5_FLOW_TYPE_VERBS, 354 MLX5_FLOW_TYPE_MAX, 355 }; 356 357 /* Fate action type. */ 358 enum mlx5_flow_fate_type { 359 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 360 MLX5_FLOW_FATE_QUEUE, 361 MLX5_FLOW_FATE_JUMP, 362 MLX5_FLOW_FATE_PORT_ID, 363 MLX5_FLOW_FATE_DROP, 364 MLX5_FLOW_FATE_DEFAULT_MISS, 365 MLX5_FLOW_FATE_MAX, 366 }; 367 368 /* Matcher PRM representation */ 369 struct mlx5_flow_dv_match_params { 370 size_t size; 371 /**< Size of match value. Do NOT split size and key! */ 372 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 373 /**< Matcher value. This value is used as the mask or as a key. */ 374 }; 375 376 /* Matcher structure. */ 377 struct mlx5_flow_dv_matcher { 378 LIST_ENTRY(mlx5_flow_dv_matcher) next; 379 /**< Pointer to the next element. */ 380 struct mlx5_flow_tbl_resource *tbl; 381 /**< Pointer to the table(group) the matcher associated with. */ 382 rte_atomic32_t refcnt; /**< Reference counter. */ 383 void *matcher_object; /**< Pointer to DV matcher */ 384 uint16_t crc; /**< CRC of key. */ 385 uint16_t priority; /**< Priority of matcher. */ 386 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 387 }; 388 389 #define MLX5_ENCAP_MAX_LEN 132 390 391 /* Encap/decap resource structure. */ 392 struct mlx5_flow_dv_encap_decap_resource { 393 ILIST_ENTRY(uint32_t)next; 394 /* Pointer to next element. */ 395 rte_atomic32_t refcnt; /**< Reference counter. */ 396 void *action; 397 /**< Encap/decap action object. */ 398 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 399 size_t size; 400 uint8_t reformat_type; 401 uint8_t ft_type; 402 uint64_t flags; /**< Flags for RDMA API. */ 403 }; 404 405 /* Tag resource structure. */ 406 struct mlx5_flow_dv_tag_resource { 407 struct mlx5_hlist_entry entry; 408 /**< hash list entry for tag resource, tag value as the key. */ 409 void *action; 410 /**< Tag action object. */ 411 rte_atomic32_t refcnt; /**< Reference counter. */ 412 uint32_t idx; /**< Index for the index memory pool. */ 413 }; 414 415 /* 416 * Number of modification commands. 417 * The maximal actions amount in FW is some constant, and it is 16 in the 418 * latest releases. In some old releases, it will be limited to 8. 419 * Since there is no interface to query the capacity, the maximal value should 420 * be used to allow PMD to create the flow. The validation will be done in the 421 * lower driver layer or FW. A failure will be returned if exceeds the maximal 422 * supported actions number on the root table. 423 * On non-root tables, there is no limitation, but 32 is enough right now. 424 */ 425 #define MLX5_MAX_MODIFY_NUM 32 426 #define MLX5_ROOT_TBL_MODIFY_NUM 16 427 428 /* Modify resource structure */ 429 struct mlx5_flow_dv_modify_hdr_resource { 430 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next; 431 /* Pointer to next element. */ 432 rte_atomic32_t refcnt; /**< Reference counter. */ 433 void *action; 434 /**< Modify header action object. */ 435 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 436 uint32_t actions_num; /**< Number of modification actions. */ 437 uint64_t flags; /**< Flags for RDMA API. */ 438 struct mlx5_modification_cmd actions[]; 439 /**< Modification actions. */ 440 }; 441 442 /* Jump action resource structure. */ 443 struct mlx5_flow_dv_jump_tbl_resource { 444 rte_atomic32_t refcnt; /**< Reference counter. */ 445 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 446 void *action; /**< Pointer to the rdma core action. */ 447 }; 448 449 /* Port ID resource structure. */ 450 struct mlx5_flow_dv_port_id_action_resource { 451 ILIST_ENTRY(uint32_t)next; 452 /* Pointer to next element. */ 453 rte_atomic32_t refcnt; /**< Reference counter. */ 454 void *action; 455 /**< Action object. */ 456 uint32_t port_id; /**< Port ID value. */ 457 }; 458 459 /* Push VLAN action resource structure */ 460 struct mlx5_flow_dv_push_vlan_action_resource { 461 ILIST_ENTRY(uint32_t)next; 462 /* Pointer to next element. */ 463 rte_atomic32_t refcnt; /**< Reference counter. */ 464 void *action; /**< Action object. */ 465 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 466 rte_be32_t vlan_tag; /**< VLAN tag value. */ 467 }; 468 469 /* Metadata register copy table entry. */ 470 struct mlx5_flow_mreg_copy_resource { 471 /* 472 * Hash list entry for copy table. 473 * - Key is 32/64-bit MARK action ID. 474 * - MUST be the first entry. 475 */ 476 struct mlx5_hlist_entry hlist_ent; 477 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 478 /* List entry for device flows. */ 479 uint32_t refcnt; /* Reference counter. */ 480 uint32_t appcnt; /* Apply/Remove counter. */ 481 uint32_t idx; 482 uint32_t rix_flow; /* Built flow for copy. */ 483 }; 484 485 /* Table data structure of the hash organization. */ 486 struct mlx5_flow_tbl_data_entry { 487 struct mlx5_hlist_entry entry; 488 /**< hash list entry, 64-bits key inside. */ 489 struct mlx5_flow_tbl_resource tbl; 490 /**< flow table resource. */ 491 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 492 /**< matchers' header associated with the flow table. */ 493 struct mlx5_flow_dv_jump_tbl_resource jump; 494 /**< jump resource, at most one for each table created. */ 495 uint32_t idx; /**< index for the indexed mempool. */ 496 }; 497 498 /* Verbs specification header. */ 499 struct ibv_spec_header { 500 enum ibv_flow_spec_type type; 501 uint16_t size; 502 }; 503 504 /* RSS description. */ 505 struct mlx5_flow_rss_desc { 506 uint32_t level; 507 uint32_t queue_num; /**< Number of entries in @p queue. */ 508 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 509 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 510 uint16_t queue[]; /**< Destination queues to redirect traffic to. */ 511 }; 512 513 /* PMD flow priority for tunnel */ 514 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 515 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 516 517 518 /** Device flow handle structure for DV mode only. */ 519 struct mlx5_flow_handle_dv { 520 /* Flow DV api: */ 521 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 522 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 523 /**< Pointer to modify header resource in cache. */ 524 uint32_t rix_encap_decap; 525 /**< Index to encap/decap resource in cache. */ 526 uint32_t rix_push_vlan; 527 /**< Index to push VLAN action resource in cache. */ 528 uint32_t rix_tag; 529 /**< Index to the tag action. */ 530 } __rte_packed; 531 532 /** Device flow handle structure: used both for creating & destroying. */ 533 struct mlx5_flow_handle { 534 SILIST_ENTRY(uint32_t)next; 535 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 536 /**< Index to next device flow handle. */ 537 uint64_t layers; 538 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 539 void *drv_flow; /**< pointer to driver flow object. */ 540 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 541 uint32_t mark:1; /**< Metadate rxq mark flag. */ 542 uint32_t fate_action:3; /**< Fate action type. */ 543 union { 544 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 545 uint32_t rix_jump; /**< Index to the jump action resource. */ 546 uint32_t rix_port_id_action; 547 /**< Index to port ID action resource. */ 548 uint32_t rix_fate; 549 /**< Generic value indicates the fate action. */ 550 uint32_t rix_default_fate; 551 /**< Indicates default miss fate action. */ 552 }; 553 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 554 struct mlx5_flow_handle_dv dvh; 555 #endif 556 } __rte_packed; 557 558 /* 559 * Size for Verbs device flow handle structure only. Do not use the DV only 560 * structure in Verbs. No DV flows attributes will be accessed. 561 * Macro offsetof() could also be used here. 562 */ 563 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 564 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 565 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 566 #else 567 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 568 #endif 569 570 /* 571 * Max number of actions per DV flow. 572 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 573 * in rdma-core file providers/mlx5/verbs.c. 574 */ 575 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 576 577 /** Device flow structure only for DV flow creation. */ 578 struct mlx5_flow_dv_workspace { 579 uint32_t group; /**< The group index. */ 580 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 581 int actions_n; /**< number of actions. */ 582 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 583 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 584 /**< Pointer to encap/decap resource in cache. */ 585 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 586 /**< Pointer to push VLAN action resource in cache. */ 587 struct mlx5_flow_dv_tag_resource *tag_resource; 588 /**< pointer to the tag action. */ 589 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 590 /**< Pointer to port ID action resource. */ 591 struct mlx5_flow_dv_jump_tbl_resource *jump; 592 /**< Pointer to the jump action resource. */ 593 struct mlx5_flow_dv_match_params value; 594 /**< Holds the value that the packet is compared to. */ 595 }; 596 597 /* 598 * Maximal Verbs flow specifications & actions size. 599 * Some elements are mutually exclusive, but enough space should be allocated. 600 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 601 * 2. One tunnel header (exception: GRE + MPLS), 602 * SPEC length: GRE == tunnel. 603 * Actions: 1. 1 Mark OR Flag. 604 * 2. 1 Drop (if any). 605 * 3. No limitation for counters, but it makes no sense to support too 606 * many counters in a single device flow. 607 */ 608 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 609 #define MLX5_VERBS_MAX_SPEC_SIZE \ 610 ( \ 611 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 612 sizeof(struct ibv_flow_spec_ipv6) + \ 613 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 614 sizeof(struct ibv_flow_spec_gre) + \ 615 sizeof(struct ibv_flow_spec_mpls)) \ 616 ) 617 #else 618 #define MLX5_VERBS_MAX_SPEC_SIZE \ 619 ( \ 620 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 621 sizeof(struct ibv_flow_spec_ipv6) + \ 622 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 623 sizeof(struct ibv_flow_spec_tunnel)) \ 624 ) 625 #endif 626 627 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 628 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 629 #define MLX5_VERBS_MAX_ACT_SIZE \ 630 ( \ 631 sizeof(struct ibv_flow_spec_action_tag) + \ 632 sizeof(struct ibv_flow_spec_action_drop) + \ 633 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 634 ) 635 #else 636 #define MLX5_VERBS_MAX_ACT_SIZE \ 637 ( \ 638 sizeof(struct ibv_flow_spec_action_tag) + \ 639 sizeof(struct ibv_flow_spec_action_drop) \ 640 ) 641 #endif 642 643 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 644 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 645 646 /** Device flow structure only for Verbs flow creation. */ 647 struct mlx5_flow_verbs_workspace { 648 unsigned int size; /**< Size of the attribute. */ 649 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 650 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 651 /**< Specifications & actions buffer of verbs flow. */ 652 }; 653 654 /** Maximal number of device sub-flows supported. */ 655 #define MLX5_NUM_MAX_DEV_FLOWS 32 656 657 /** Device flow structure. */ 658 struct mlx5_flow { 659 struct rte_flow *flow; /**< Pointer to the main flow. */ 660 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 661 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 662 uint64_t act_flags; 663 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 664 bool external; /**< true if the flow is created external to PMD. */ 665 uint8_t ingress; /**< 1 if the flow is ingress. */ 666 union { 667 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 668 struct mlx5_flow_dv_workspace dv; 669 #endif 670 struct mlx5_flow_verbs_workspace verbs; 671 }; 672 struct mlx5_flow_handle *handle; 673 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 674 }; 675 676 /* Flow meter state. */ 677 #define MLX5_FLOW_METER_DISABLE 0 678 #define MLX5_FLOW_METER_ENABLE 1 679 680 #define MLX5_MAN_WIDTH 8 681 /* Modify this value if enum rte_mtr_color changes. */ 682 #define RTE_MTR_DROPPED RTE_COLORS 683 684 /* Meter policer statistics */ 685 struct mlx5_flow_policer_stats { 686 uint32_t cnt[RTE_COLORS + 1]; 687 /**< Color counter, extra for drop. */ 688 uint64_t stats_mask; 689 /**< Statistics mask for the colors. */ 690 }; 691 692 /* Meter table structure. */ 693 struct mlx5_meter_domain_info { 694 struct mlx5_flow_tbl_resource *tbl; 695 /**< Meter table. */ 696 struct mlx5_flow_tbl_resource *sfx_tbl; 697 /**< Meter suffix table. */ 698 void *any_matcher; 699 /**< Meter color not match default criteria. */ 700 void *color_matcher; 701 /**< Meter color match criteria. */ 702 void *jump_actn; 703 /**< Meter match action. */ 704 void *policer_rules[RTE_MTR_DROPPED + 1]; 705 /**< Meter policer for the match. */ 706 }; 707 708 /* Meter table set for TX RX FDB. */ 709 struct mlx5_meter_domains_infos { 710 uint32_t ref_cnt; 711 /**< Table user count. */ 712 struct mlx5_meter_domain_info egress; 713 /**< TX meter table. */ 714 struct mlx5_meter_domain_info ingress; 715 /**< RX meter table. */ 716 struct mlx5_meter_domain_info transfer; 717 /**< FDB meter table. */ 718 void *drop_actn; 719 /**< Drop action as not matched. */ 720 void *count_actns[RTE_MTR_DROPPED + 1]; 721 /**< Counters for match and unmatched statistics. */ 722 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 723 /**< Flow meter parameter. */ 724 size_t fmp_size; 725 /**< Flow meter parameter size. */ 726 void *meter_action; 727 /**< Flow meter action. */ 728 }; 729 730 /* Meter parameter structure. */ 731 struct mlx5_flow_meter { 732 TAILQ_ENTRY(mlx5_flow_meter) next; 733 /**< Pointer to the next flow meter structure. */ 734 uint32_t idx; /* Index to meter object. */ 735 uint32_t meter_id; 736 /**< Meter id. */ 737 struct mlx5_flow_meter_profile *profile; 738 /**< Meter profile parameters. */ 739 740 /** Policer actions (per meter output color). */ 741 enum rte_mtr_policer_action action[RTE_COLORS]; 742 743 /** Set of stats counters to be enabled. 744 * @see enum rte_mtr_stats_type 745 */ 746 uint64_t stats_mask; 747 748 /**< Rule applies to ingress traffic. */ 749 uint32_t ingress:1; 750 751 /**< Rule applies to egress traffic. */ 752 uint32_t egress:1; 753 /** 754 * Instead of simply matching the properties of traffic as it would 755 * appear on a given DPDK port ID, enabling this attribute transfers 756 * a flow rule to the lowest possible level of any device endpoints 757 * found in the pattern. 758 * 759 * When supported, this effectively enables an application to 760 * re-route traffic not necessarily intended for it (e.g. coming 761 * from or addressed to different physical ports, VFs or 762 * applications) at the device level. 763 * 764 * It complements the behavior of some pattern items such as 765 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 766 * 767 * When transferring flow rules, ingress and egress attributes keep 768 * their original meaning, as if processing traffic emitted or 769 * received by the application. 770 */ 771 uint32_t transfer:1; 772 struct mlx5_meter_domains_infos *mfts; 773 /**< Flow table created for this meter. */ 774 struct mlx5_flow_policer_stats policer_stats; 775 /**< Meter policer statistics. */ 776 uint32_t ref_cnt; 777 /**< Use count. */ 778 uint32_t active_state:1; 779 /**< Meter state. */ 780 uint32_t shared:1; 781 /**< Meter shared or not. */ 782 }; 783 784 /* RFC2697 parameter structure. */ 785 struct mlx5_flow_meter_srtcm_rfc2697_prm { 786 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 787 uint32_t cbs_exponent:5; 788 uint32_t cbs_mantissa:8; 789 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 790 uint32_t cir_exponent:5; 791 uint32_t cir_mantissa:8; 792 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 793 uint32_t ebs_exponent:5; 794 uint32_t ebs_mantissa:8; 795 }; 796 797 /* Flow meter profile structure. */ 798 struct mlx5_flow_meter_profile { 799 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 800 /**< Pointer to the next flow meter structure. */ 801 uint32_t meter_profile_id; /**< Profile id. */ 802 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 803 union { 804 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 805 /**< srtcm_rfc2697 struct. */ 806 }; 807 uint32_t ref_cnt; /**< Use count. */ 808 }; 809 810 /* Fdir flow structure */ 811 struct mlx5_fdir_flow { 812 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */ 813 struct mlx5_fdir *fdir; /* Pointer to fdir. */ 814 uint32_t rix_flow; /* Index to flow. */ 815 }; 816 817 #define HAIRPIN_FLOW_ID_BITS 28 818 819 /* Flow structure. */ 820 struct rte_flow { 821 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 822 uint32_t dev_handles; 823 /**< Device flow handles that are part of the flow. */ 824 uint32_t drv_type:2; /**< Driver type. */ 825 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */ 826 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS; 827 /**< The flow id used for hairpin. */ 828 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */ 829 uint32_t rix_mreg_copy; 830 /**< Index to metadata register copy table resource. */ 831 uint32_t counter; /**< Holds flow counter. */ 832 uint16_t meter; /**< Holds flow meter id. */ 833 } __rte_packed; 834 835 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 836 const struct rte_flow_attr *attr, 837 const struct rte_flow_item items[], 838 const struct rte_flow_action actions[], 839 bool external, 840 int hairpin, 841 struct rte_flow_error *error); 842 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 843 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 844 const struct rte_flow_item items[], 845 const struct rte_flow_action actions[], struct rte_flow_error *error); 846 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 847 struct mlx5_flow *dev_flow, 848 const struct rte_flow_attr *attr, 849 const struct rte_flow_item items[], 850 const struct rte_flow_action actions[], 851 struct rte_flow_error *error); 852 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 853 struct rte_flow_error *error); 854 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 855 struct rte_flow *flow); 856 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 857 struct rte_flow *flow); 858 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 859 struct rte_flow *flow, 860 const struct rte_flow_action *actions, 861 void *data, 862 struct rte_flow_error *error); 863 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 864 (struct rte_eth_dev *dev, 865 const struct mlx5_flow_meter *fm); 866 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 867 struct mlx5_meter_domains_infos *tbls); 868 typedef int (*mlx5_flow_create_policer_rules_t) 869 (struct rte_eth_dev *dev, 870 struct mlx5_flow_meter *fm, 871 const struct rte_flow_attr *attr); 872 typedef int (*mlx5_flow_destroy_policer_rules_t) 873 (struct rte_eth_dev *dev, 874 const struct mlx5_flow_meter *fm, 875 const struct rte_flow_attr *attr); 876 typedef uint32_t (*mlx5_flow_counter_alloc_t) 877 (struct rte_eth_dev *dev); 878 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 879 uint32_t cnt); 880 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 881 uint32_t cnt, 882 bool clear, uint64_t *pkts, 883 uint64_t *bytes); 884 typedef int (*mlx5_flow_get_aged_flows_t) 885 (struct rte_eth_dev *dev, 886 void **context, 887 uint32_t nb_contexts, 888 struct rte_flow_error *error); 889 struct mlx5_flow_driver_ops { 890 mlx5_flow_validate_t validate; 891 mlx5_flow_prepare_t prepare; 892 mlx5_flow_translate_t translate; 893 mlx5_flow_apply_t apply; 894 mlx5_flow_remove_t remove; 895 mlx5_flow_destroy_t destroy; 896 mlx5_flow_query_t query; 897 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 898 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 899 mlx5_flow_create_policer_rules_t create_policer_rules; 900 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 901 mlx5_flow_counter_alloc_t counter_alloc; 902 mlx5_flow_counter_free_t counter_free; 903 mlx5_flow_counter_query_t counter_query; 904 mlx5_flow_get_aged_flows_t get_aged_flows; 905 }; 906 907 /* mlx5_flow.c */ 908 909 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id); 910 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool); 911 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id); 912 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, 913 uint32_t id); 914 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, 915 bool external, uint32_t group, bool fdb_def_rule, 916 uint32_t *table, struct rte_flow_error *error); 917 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 918 int tunnel, uint64_t layer_types, 919 uint64_t hash_fields); 920 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 921 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 922 uint32_t subpriority); 923 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 924 enum mlx5_feature_name feature, 925 uint32_t id, 926 struct rte_flow_error *error); 927 const struct rte_flow_action *mlx5_flow_find_action 928 (const struct rte_flow_action *actions, 929 enum rte_flow_action_type action); 930 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 931 const struct rte_flow_attr *attr, 932 struct rte_flow_error *error); 933 int mlx5_flow_validate_action_drop(uint64_t action_flags, 934 const struct rte_flow_attr *attr, 935 struct rte_flow_error *error); 936 int mlx5_flow_validate_action_flag(uint64_t action_flags, 937 const struct rte_flow_attr *attr, 938 struct rte_flow_error *error); 939 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 940 uint64_t action_flags, 941 const struct rte_flow_attr *attr, 942 struct rte_flow_error *error); 943 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 944 uint64_t action_flags, 945 struct rte_eth_dev *dev, 946 const struct rte_flow_attr *attr, 947 struct rte_flow_error *error); 948 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 949 uint64_t action_flags, 950 struct rte_eth_dev *dev, 951 const struct rte_flow_attr *attr, 952 uint64_t item_flags, 953 struct rte_flow_error *error); 954 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 955 const struct rte_flow_attr *attr, 956 struct rte_flow_error *error); 957 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 958 const struct rte_flow_attr *attributes, 959 struct rte_flow_error *error); 960 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 961 const uint8_t *mask, 962 const uint8_t *nic_mask, 963 unsigned int size, 964 struct rte_flow_error *error); 965 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 966 uint64_t item_flags, 967 struct rte_flow_error *error); 968 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 969 uint64_t item_flags, 970 uint8_t target_protocol, 971 struct rte_flow_error *error); 972 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 973 uint64_t item_flags, 974 const struct rte_flow_item *gre_item, 975 struct rte_flow_error *error); 976 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 977 uint64_t item_flags, 978 uint64_t last_item, 979 uint16_t ether_type, 980 const struct rte_flow_item_ipv4 *acc_mask, 981 struct rte_flow_error *error); 982 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 983 uint64_t item_flags, 984 uint64_t last_item, 985 uint16_t ether_type, 986 const struct rte_flow_item_ipv6 *acc_mask, 987 struct rte_flow_error *error); 988 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 989 const struct rte_flow_item *item, 990 uint64_t item_flags, 991 uint64_t prev_layer, 992 struct rte_flow_error *error); 993 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 994 uint64_t item_flags, 995 uint8_t target_protocol, 996 const struct rte_flow_item_tcp *flow_mask, 997 struct rte_flow_error *error); 998 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 999 uint64_t item_flags, 1000 uint8_t target_protocol, 1001 struct rte_flow_error *error); 1002 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1003 uint64_t item_flags, 1004 struct rte_eth_dev *dev, 1005 struct rte_flow_error *error); 1006 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1007 uint64_t item_flags, 1008 struct rte_flow_error *error); 1009 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1010 uint64_t item_flags, 1011 struct rte_eth_dev *dev, 1012 struct rte_flow_error *error); 1013 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1014 uint64_t item_flags, 1015 uint8_t target_protocol, 1016 struct rte_flow_error *error); 1017 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1018 uint64_t item_flags, 1019 uint8_t target_protocol, 1020 struct rte_flow_error *error); 1021 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1022 uint64_t item_flags, 1023 uint8_t target_protocol, 1024 struct rte_flow_error *error); 1025 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1026 uint64_t item_flags, 1027 struct rte_eth_dev *dev, 1028 struct rte_flow_error *error); 1029 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1030 uint64_t item_flags, 1031 uint64_t last_item, 1032 uint16_t ether_type, 1033 const struct rte_flow_item_ecpri *acc_mask, 1034 struct rte_flow_error *error); 1035 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1036 (struct rte_eth_dev *dev, 1037 const struct mlx5_flow_meter *fm); 1038 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1039 struct mlx5_meter_domains_infos *tbl); 1040 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1041 struct mlx5_flow_meter *fm, 1042 const struct rte_flow_attr *attr); 1043 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1044 struct mlx5_flow_meter *fm, 1045 const struct rte_flow_attr *attr); 1046 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1047 struct rte_mtr_error *error); 1048 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1049