1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* Private rte flow items. */ 22 enum mlx5_rte_flow_item_type { 23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 24 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 28 }; 29 30 /* Private (internal) rte flow actions. */ 31 enum mlx5_rte_flow_action_type { 32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 33 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 34 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 38 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT, 40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP, 41 }; 42 43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 44 45 enum { 46 MLX5_INDIRECT_ACTION_TYPE_RSS, 47 MLX5_INDIRECT_ACTION_TYPE_AGE, 48 MLX5_INDIRECT_ACTION_TYPE_COUNT, 49 MLX5_INDIRECT_ACTION_TYPE_CT, 50 }; 51 52 /* Now, the maximal ports will be supported is 256, action number is 4M. */ 53 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100 54 55 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22 56 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1) 57 58 /* 30-31: type, 22-29: owner port, 0-21: index. */ 59 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \ 60 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \ 61 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \ 62 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index)) 63 64 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \ 65 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \ 66 MLX5_INDIRECT_ACT_CT_OWNER_MASK) 67 68 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \ 69 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1)) 70 71 /* Matches on selected register. */ 72 struct mlx5_rte_flow_item_tag { 73 enum modify_reg id; 74 uint32_t data; 75 }; 76 77 /* Modify selected register. */ 78 struct mlx5_rte_flow_action_set_tag { 79 enum modify_reg id; 80 uint8_t offset; 81 uint8_t length; 82 uint32_t data; 83 }; 84 85 struct mlx5_flow_action_copy_mreg { 86 enum modify_reg dst; 87 enum modify_reg src; 88 }; 89 90 /* Matches on source queue. */ 91 struct mlx5_rte_flow_item_tx_queue { 92 uint32_t queue; 93 }; 94 95 /* Feature name to allocate metadata register. */ 96 enum mlx5_feature_name { 97 MLX5_HAIRPIN_RX, 98 MLX5_HAIRPIN_TX, 99 MLX5_METADATA_RX, 100 MLX5_METADATA_TX, 101 MLX5_METADATA_FDB, 102 MLX5_FLOW_MARK, 103 MLX5_APP_TAG, 104 MLX5_COPY_MARK, 105 MLX5_MTR_COLOR, 106 MLX5_MTR_ID, 107 MLX5_ASO_FLOW_HIT, 108 MLX5_ASO_CONNTRACK, 109 }; 110 111 /* Default queue number. */ 112 #define MLX5_RSSQ_DEFAULT_NUM 16 113 114 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 115 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 116 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 117 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 118 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 119 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 120 121 /* Pattern inner Layer bits. */ 122 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 123 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 124 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 125 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 126 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 127 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 128 129 /* Pattern tunnel Layer bits. */ 130 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 131 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 132 #define MLX5_FLOW_LAYER_GRE (1u << 14) 133 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 134 /* List of tunnel Layer bits continued below. */ 135 136 /* General pattern items bits. */ 137 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 138 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 139 #define MLX5_FLOW_ITEM_TAG (1u << 18) 140 #define MLX5_FLOW_ITEM_MARK (1u << 19) 141 142 /* Pattern MISC bits. */ 143 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 144 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 145 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 146 147 /* Pattern tunnel Layer bits (continued). */ 148 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 149 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 150 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 151 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 152 153 /* Queue items. */ 154 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 155 156 /* Pattern tunnel Layer bits (continued). */ 157 #define MLX5_FLOW_LAYER_GTP (1u << 28) 158 159 /* Pattern eCPRI Layer bit. */ 160 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 161 162 /* IPv6 Fragment Extension Header bit. */ 163 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 164 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 165 166 /* Pattern tunnel Layer bits (continued). */ 167 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 168 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 169 170 /* INTEGRITY item bit */ 171 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34) 172 173 /* Conntrack item. */ 174 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35) 175 176 /* Outer Masks. */ 177 #define MLX5_FLOW_LAYER_OUTER_L3 \ 178 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 179 #define MLX5_FLOW_LAYER_OUTER_L4 \ 180 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 181 #define MLX5_FLOW_LAYER_OUTER \ 182 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 183 MLX5_FLOW_LAYER_OUTER_L4) 184 185 /* Tunnel Masks. */ 186 #define MLX5_FLOW_LAYER_TUNNEL \ 187 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 188 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 189 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 190 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 191 192 /* Inner Masks. */ 193 #define MLX5_FLOW_LAYER_INNER_L3 \ 194 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 195 #define MLX5_FLOW_LAYER_INNER_L4 \ 196 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 197 #define MLX5_FLOW_LAYER_INNER \ 198 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 199 MLX5_FLOW_LAYER_INNER_L4) 200 201 /* Layer Masks. */ 202 #define MLX5_FLOW_LAYER_L2 \ 203 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 204 #define MLX5_FLOW_LAYER_L3_IPV4 \ 205 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 206 #define MLX5_FLOW_LAYER_L3_IPV6 \ 207 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 208 #define MLX5_FLOW_LAYER_L3 \ 209 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 210 #define MLX5_FLOW_LAYER_L4 \ 211 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 212 213 /* Actions */ 214 #define MLX5_FLOW_ACTION_DROP (1u << 0) 215 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 216 #define MLX5_FLOW_ACTION_RSS (1u << 2) 217 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 218 #define MLX5_FLOW_ACTION_MARK (1u << 4) 219 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 220 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 221 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 222 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 223 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 224 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 225 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 226 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 227 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 228 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 229 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 230 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 231 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 232 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 233 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 234 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 235 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 236 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 237 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 238 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 239 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 240 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 241 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 242 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 243 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 244 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 245 #define MLX5_FLOW_ACTION_METER (1ull << 31) 246 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 247 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 248 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 249 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 250 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 251 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 252 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 253 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 254 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40) 255 #define MLX5_FLOW_ACTION_CT (1ull << 41) 256 257 #define MLX5_FLOW_FATE_ACTIONS \ 258 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 259 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 260 MLX5_FLOW_ACTION_DEFAULT_MISS | \ 261 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 262 263 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 264 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 265 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) 266 267 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 268 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 269 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 270 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 271 MLX5_FLOW_ACTION_SET_TP_SRC | \ 272 MLX5_FLOW_ACTION_SET_TP_DST | \ 273 MLX5_FLOW_ACTION_SET_TTL | \ 274 MLX5_FLOW_ACTION_DEC_TTL | \ 275 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 276 MLX5_FLOW_ACTION_SET_MAC_DST | \ 277 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 278 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 279 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 280 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 281 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 282 MLX5_FLOW_ACTION_SET_TAG | \ 283 MLX5_FLOW_ACTION_MARK_EXT | \ 284 MLX5_FLOW_ACTION_SET_META | \ 285 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 286 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 287 MLX5_FLOW_ACTION_MODIFY_FIELD) 288 289 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 290 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 291 292 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 293 294 #ifndef IPPROTO_MPLS 295 #define IPPROTO_MPLS 137 296 #endif 297 298 /* UDP port number for MPLS */ 299 #define MLX5_UDP_PORT_MPLS 6635 300 301 /* UDP port numbers for VxLAN. */ 302 #define MLX5_UDP_PORT_VXLAN 4789 303 #define MLX5_UDP_PORT_VXLAN_GPE 4790 304 305 /* UDP port numbers for GENEVE. */ 306 #define MLX5_UDP_PORT_GENEVE 6081 307 308 /* Lowest priority indicator. */ 309 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 310 311 /* 312 * Max priority for ingress\egress flow groups 313 * greater than 0 and for any transfer flow group. 314 * From user configation: 0 - 21843. 315 */ 316 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 317 318 /* 319 * Number of sub priorities. 320 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 321 * matching on the NIC (firmware dependent) L4 most have the higher priority 322 * followed by L3 and ending with L2. 323 */ 324 #define MLX5_PRIORITY_MAP_L2 2 325 #define MLX5_PRIORITY_MAP_L3 1 326 #define MLX5_PRIORITY_MAP_L4 0 327 #define MLX5_PRIORITY_MAP_MAX 3 328 329 /* Valid layer type for IPV4 RSS. */ 330 #define MLX5_IPV4_LAYER_TYPES \ 331 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 332 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 333 ETH_RSS_NONFRAG_IPV4_OTHER) 334 335 /* IBV hash source bits for IPV4. */ 336 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 337 338 /* Valid layer type for IPV6 RSS. */ 339 #define MLX5_IPV6_LAYER_TYPES \ 340 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 341 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 342 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 343 344 /* IBV hash source bits for IPV6. */ 345 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 346 347 /* IBV hash bits for L3 SRC. */ 348 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 349 350 /* IBV hash bits for L3 DST. */ 351 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 352 353 /* IBV hash bits for TCP. */ 354 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 355 IBV_RX_HASH_DST_PORT_TCP) 356 357 /* IBV hash bits for UDP. */ 358 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 359 IBV_RX_HASH_DST_PORT_UDP) 360 361 /* IBV hash bits for L4 SRC. */ 362 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 363 IBV_RX_HASH_SRC_PORT_UDP) 364 365 /* IBV hash bits for L4 DST. */ 366 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 367 IBV_RX_HASH_DST_PORT_UDP) 368 369 /* Geneve header first 16Bit */ 370 #define MLX5_GENEVE_VER_MASK 0x3 371 #define MLX5_GENEVE_VER_SHIFT 14 372 #define MLX5_GENEVE_VER_VAL(a) \ 373 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 374 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 375 #define MLX5_GENEVE_OPTLEN_SHIFT 8 376 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 377 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 378 #define MLX5_GENEVE_OAMF_MASK 0x1 379 #define MLX5_GENEVE_OAMF_SHIFT 7 380 #define MLX5_GENEVE_OAMF_VAL(a) \ 381 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 382 #define MLX5_GENEVE_CRITO_MASK 0x1 383 #define MLX5_GENEVE_CRITO_SHIFT 6 384 #define MLX5_GENEVE_CRITO_VAL(a) \ 385 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 386 #define MLX5_GENEVE_RSVD_MASK 0x3F 387 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 388 /* 389 * The length of the Geneve options fields, expressed in four byte multiples, 390 * not including the eight byte fixed tunnel. 391 */ 392 #define MLX5_GENEVE_OPT_LEN_0 14 393 #define MLX5_GENEVE_OPT_LEN_1 63 394 395 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 396 sizeof(struct rte_ipv4_hdr)) 397 /* GTP extension header flag. */ 398 #define MLX5_GTP_EXT_HEADER_FLAG 4 399 400 /* GTP extension header PDU type shift. */ 401 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 402 403 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 404 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 405 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 406 407 /* Specific item's fields can accept a range of values (using spec and last). */ 408 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 409 #define MLX5_ITEM_RANGE_ACCEPTED true 410 411 /* Software header modify action numbers of a flow. */ 412 #define MLX5_ACT_NUM_MDF_IPV4 1 413 #define MLX5_ACT_NUM_MDF_IPV6 4 414 #define MLX5_ACT_NUM_MDF_MAC 2 415 #define MLX5_ACT_NUM_MDF_VID 1 416 #define MLX5_ACT_NUM_MDF_PORT 2 417 #define MLX5_ACT_NUM_MDF_TTL 1 418 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 419 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 420 #define MLX5_ACT_NUM_MDF_TCPACK 1 421 #define MLX5_ACT_NUM_SET_REG 1 422 #define MLX5_ACT_NUM_SET_TAG 1 423 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 424 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 425 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 426 #define MLX5_ACT_NUM_SET_DSCP 1 427 428 /* Maximum number of fields to modify in MODIFY_FIELD */ 429 #define MLX5_ACT_MAX_MOD_FIELDS 5 430 431 /* Syndrome bits definition for connection tracking. */ 432 #define MLX5_CT_SYNDROME_VALID (0x0 << 6) 433 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6) 434 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6) 435 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1) 436 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0) 437 438 enum mlx5_flow_drv_type { 439 MLX5_FLOW_TYPE_MIN, 440 MLX5_FLOW_TYPE_DV, 441 MLX5_FLOW_TYPE_VERBS, 442 MLX5_FLOW_TYPE_MAX, 443 }; 444 445 /* Fate action type. */ 446 enum mlx5_flow_fate_type { 447 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 448 MLX5_FLOW_FATE_QUEUE, 449 MLX5_FLOW_FATE_JUMP, 450 MLX5_FLOW_FATE_PORT_ID, 451 MLX5_FLOW_FATE_DROP, 452 MLX5_FLOW_FATE_DEFAULT_MISS, 453 MLX5_FLOW_FATE_SHARED_RSS, 454 MLX5_FLOW_FATE_MTR, 455 MLX5_FLOW_FATE_MAX, 456 }; 457 458 /* Matcher PRM representation */ 459 struct mlx5_flow_dv_match_params { 460 size_t size; 461 /**< Size of match value. Do NOT split size and key! */ 462 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 463 /**< Matcher value. This value is used as the mask or as a key. */ 464 }; 465 466 /* Matcher structure. */ 467 struct mlx5_flow_dv_matcher { 468 struct mlx5_list_entry entry; /**< Pointer to the next element. */ 469 struct mlx5_flow_tbl_resource *tbl; 470 /**< Pointer to the table(group) the matcher associated with. */ 471 void *matcher_object; /**< Pointer to DV matcher */ 472 uint16_t crc; /**< CRC of key. */ 473 uint16_t priority; /**< Priority of matcher. */ 474 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 475 }; 476 477 #define MLX5_ENCAP_MAX_LEN 132 478 479 /* Encap/decap resource structure. */ 480 struct mlx5_flow_dv_encap_decap_resource { 481 struct mlx5_list_entry entry; 482 /* Pointer to next element. */ 483 uint32_t refcnt; /**< Reference counter. */ 484 void *action; 485 /**< Encap/decap action object. */ 486 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 487 size_t size; 488 uint8_t reformat_type; 489 uint8_t ft_type; 490 uint64_t flags; /**< Flags for RDMA API. */ 491 uint32_t idx; /**< Index for the index memory pool. */ 492 }; 493 494 /* Tag resource structure. */ 495 struct mlx5_flow_dv_tag_resource { 496 struct mlx5_list_entry entry; 497 /**< hash list entry for tag resource, tag value as the key. */ 498 void *action; 499 /**< Tag action object. */ 500 uint32_t refcnt; /**< Reference counter. */ 501 uint32_t idx; /**< Index for the index memory pool. */ 502 uint32_t tag_id; /**< Tag ID. */ 503 }; 504 505 /* Modify resource structure */ 506 struct mlx5_flow_dv_modify_hdr_resource { 507 struct mlx5_list_entry entry; 508 void *action; /**< Modify header action object. */ 509 uint32_t idx; 510 /* Key area for hash list matching: */ 511 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 512 uint8_t actions_num; /**< Number of modification actions. */ 513 bool root; /**< Whether action is in root table. */ 514 struct mlx5_modification_cmd actions[]; 515 /**< Modification actions. */ 516 } __rte_packed; 517 518 /* Modify resource key of the hash organization. */ 519 union mlx5_flow_modify_hdr_key { 520 struct { 521 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 522 uint32_t actions_num:5; /**< Number of modification actions. */ 523 uint32_t group:19; /**< Flow group id. */ 524 uint32_t cksum; /**< Actions check sum. */ 525 }; 526 uint64_t v64; /**< full 64bits value of key */ 527 }; 528 529 /* Jump action resource structure. */ 530 struct mlx5_flow_dv_jump_tbl_resource { 531 void *action; /**< Pointer to the rdma core action. */ 532 }; 533 534 /* Port ID resource structure. */ 535 struct mlx5_flow_dv_port_id_action_resource { 536 struct mlx5_list_entry entry; 537 void *action; /**< Action object. */ 538 uint32_t port_id; /**< Port ID value. */ 539 uint32_t idx; /**< Indexed pool memory index. */ 540 }; 541 542 /* Push VLAN action resource structure */ 543 struct mlx5_flow_dv_push_vlan_action_resource { 544 struct mlx5_list_entry entry; /* Cache entry. */ 545 void *action; /**< Action object. */ 546 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 547 rte_be32_t vlan_tag; /**< VLAN tag value. */ 548 uint32_t idx; /**< Indexed pool memory index. */ 549 }; 550 551 /* Metadata register copy table entry. */ 552 struct mlx5_flow_mreg_copy_resource { 553 /* 554 * Hash list entry for copy table. 555 * - Key is 32/64-bit MARK action ID. 556 * - MUST be the first entry. 557 */ 558 struct mlx5_list_entry hlist_ent; 559 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 560 /* List entry for device flows. */ 561 uint32_t idx; 562 uint32_t rix_flow; /* Built flow for copy. */ 563 uint32_t mark_id; 564 }; 565 566 /* Table tunnel parameter. */ 567 struct mlx5_flow_tbl_tunnel_prm { 568 const struct mlx5_flow_tunnel *tunnel; 569 uint32_t group_id; 570 bool external; 571 }; 572 573 /* Table data structure of the hash organization. */ 574 struct mlx5_flow_tbl_data_entry { 575 struct mlx5_list_entry entry; 576 /**< hash list entry, 64-bits key inside. */ 577 struct mlx5_flow_tbl_resource tbl; 578 /**< flow table resource. */ 579 struct mlx5_list *matchers; 580 /**< matchers' header associated with the flow table. */ 581 struct mlx5_flow_dv_jump_tbl_resource jump; 582 /**< jump resource, at most one for each table created. */ 583 uint32_t idx; /**< index for the indexed mempool. */ 584 /**< tunnel offload */ 585 const struct mlx5_flow_tunnel *tunnel; 586 uint32_t group_id; 587 uint32_t external:1; 588 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 589 uint32_t is_egress:1; /**< Egress table. */ 590 uint32_t is_transfer:1; /**< Transfer table. */ 591 uint32_t dummy:1; /**< DR table. */ 592 uint32_t id:22; /**< Table ID. */ 593 uint32_t reserve:5; /**< Reserved to future using. */ 594 uint32_t level; /**< Table level. */ 595 }; 596 597 /* Sub rdma-core actions list. */ 598 struct mlx5_flow_sub_actions_list { 599 uint32_t actions_num; /**< Number of sample actions. */ 600 uint64_t action_flags; 601 void *dr_queue_action; 602 void *dr_tag_action; 603 void *dr_cnt_action; 604 void *dr_port_id_action; 605 void *dr_encap_action; 606 void *dr_jump_action; 607 }; 608 609 /* Sample sub-actions resource list. */ 610 struct mlx5_flow_sub_actions_idx { 611 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 612 uint32_t rix_tag; /**< Index to the tag action. */ 613 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 614 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 615 uint32_t rix_jump; /**< Index to the jump action resource. */ 616 }; 617 618 /* Sample action resource structure. */ 619 struct mlx5_flow_dv_sample_resource { 620 struct mlx5_list_entry entry; /**< Cache entry. */ 621 union { 622 void *verbs_action; /**< Verbs sample action object. */ 623 void **sub_actions; /**< Sample sub-action array. */ 624 }; 625 struct rte_eth_dev *dev; /**< Device registers the action. */ 626 uint32_t idx; /** Sample object index. */ 627 uint8_t ft_type; /** Flow Table Type */ 628 uint32_t ft_id; /** Flow Table Level */ 629 uint32_t ratio; /** Sample Ratio */ 630 uint64_t set_action; /** Restore reg_c0 value */ 631 void *normal_path_tbl; /** Flow Table pointer */ 632 struct mlx5_flow_sub_actions_idx sample_idx; 633 /**< Action index resources. */ 634 struct mlx5_flow_sub_actions_list sample_act; 635 /**< Action resources. */ 636 }; 637 638 #define MLX5_MAX_DEST_NUM 2 639 640 /* Destination array action resource structure. */ 641 struct mlx5_flow_dv_dest_array_resource { 642 struct mlx5_list_entry entry; /**< Cache entry. */ 643 uint32_t idx; /** Destination array action object index. */ 644 uint8_t ft_type; /** Flow Table Type */ 645 uint8_t num_of_dest; /**< Number of destination actions. */ 646 struct rte_eth_dev *dev; /**< Device registers the action. */ 647 void *action; /**< Pointer to the rdma core action. */ 648 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 649 /**< Action index resources. */ 650 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 651 /**< Action resources. */ 652 }; 653 654 /* PMD flow priority for tunnel */ 655 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 656 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 657 658 659 /** Device flow handle structure for DV mode only. */ 660 struct mlx5_flow_handle_dv { 661 /* Flow DV api: */ 662 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 663 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 664 /**< Pointer to modify header resource in cache. */ 665 uint32_t rix_encap_decap; 666 /**< Index to encap/decap resource in cache. */ 667 uint32_t rix_push_vlan; 668 /**< Index to push VLAN action resource in cache. */ 669 uint32_t rix_tag; 670 /**< Index to the tag action. */ 671 uint32_t rix_sample; 672 /**< Index to sample action resource in cache. */ 673 uint32_t rix_dest_array; 674 /**< Index to destination array resource in cache. */ 675 } __rte_packed; 676 677 /** Device flow handle structure: used both for creating & destroying. */ 678 struct mlx5_flow_handle { 679 SILIST_ENTRY(uint32_t)next; 680 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 681 /**< Index to next device flow handle. */ 682 uint64_t layers; 683 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 684 void *drv_flow; /**< pointer to driver flow object. */ 685 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */ 686 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */ 687 uint32_t mark:1; /**< Metadate rxq mark flag. */ 688 uint32_t fate_action:3; /**< Fate action type. */ 689 union { 690 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 691 uint32_t rix_jump; /**< Index to the jump action resource. */ 692 uint32_t rix_port_id_action; 693 /**< Index to port ID action resource. */ 694 uint32_t rix_fate; 695 /**< Generic value indicates the fate action. */ 696 uint32_t rix_default_fate; 697 /**< Indicates default miss fate action. */ 698 uint32_t rix_srss; 699 /**< Indicates shared RSS fate action. */ 700 }; 701 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 702 struct mlx5_flow_handle_dv dvh; 703 #endif 704 } __rte_packed; 705 706 /* 707 * Size for Verbs device flow handle structure only. Do not use the DV only 708 * structure in Verbs. No DV flows attributes will be accessed. 709 * Macro offsetof() could also be used here. 710 */ 711 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 712 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 713 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 714 #else 715 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 716 #endif 717 718 /** Device flow structure only for DV flow creation. */ 719 struct mlx5_flow_dv_workspace { 720 uint32_t group; /**< The group index. */ 721 uint32_t table_id; /**< Flow table identifier. */ 722 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 723 int actions_n; /**< number of actions. */ 724 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 725 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 726 /**< Pointer to encap/decap resource in cache. */ 727 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 728 /**< Pointer to push VLAN action resource in cache. */ 729 struct mlx5_flow_dv_tag_resource *tag_resource; 730 /**< pointer to the tag action. */ 731 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 732 /**< Pointer to port ID action resource. */ 733 struct mlx5_flow_dv_jump_tbl_resource *jump; 734 /**< Pointer to the jump action resource. */ 735 struct mlx5_flow_dv_match_params value; 736 /**< Holds the value that the packet is compared to. */ 737 struct mlx5_flow_dv_sample_resource *sample_res; 738 /**< Pointer to the sample action resource. */ 739 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 740 /**< Pointer to the destination array resource. */ 741 }; 742 743 #ifdef HAVE_INFINIBAND_VERBS_H 744 /* 745 * Maximal Verbs flow specifications & actions size. 746 * Some elements are mutually exclusive, but enough space should be allocated. 747 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 748 * 2. One tunnel header (exception: GRE + MPLS), 749 * SPEC length: GRE == tunnel. 750 * Actions: 1. 1 Mark OR Flag. 751 * 2. 1 Drop (if any). 752 * 3. No limitation for counters, but it makes no sense to support too 753 * many counters in a single device flow. 754 */ 755 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 756 #define MLX5_VERBS_MAX_SPEC_SIZE \ 757 ( \ 758 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 759 sizeof(struct ibv_flow_spec_ipv6) + \ 760 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 761 sizeof(struct ibv_flow_spec_gre) + \ 762 sizeof(struct ibv_flow_spec_mpls)) \ 763 ) 764 #else 765 #define MLX5_VERBS_MAX_SPEC_SIZE \ 766 ( \ 767 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 768 sizeof(struct ibv_flow_spec_ipv6) + \ 769 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 770 sizeof(struct ibv_flow_spec_tunnel)) \ 771 ) 772 #endif 773 774 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 775 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 776 #define MLX5_VERBS_MAX_ACT_SIZE \ 777 ( \ 778 sizeof(struct ibv_flow_spec_action_tag) + \ 779 sizeof(struct ibv_flow_spec_action_drop) + \ 780 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 781 ) 782 #else 783 #define MLX5_VERBS_MAX_ACT_SIZE \ 784 ( \ 785 sizeof(struct ibv_flow_spec_action_tag) + \ 786 sizeof(struct ibv_flow_spec_action_drop) \ 787 ) 788 #endif 789 790 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 791 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 792 793 /** Device flow structure only for Verbs flow creation. */ 794 struct mlx5_flow_verbs_workspace { 795 unsigned int size; /**< Size of the attribute. */ 796 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 797 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 798 /**< Specifications & actions buffer of verbs flow. */ 799 }; 800 #endif /* HAVE_INFINIBAND_VERBS_H */ 801 802 #define MLX5_SCALE_FLOW_GROUP_BIT 0 803 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 804 805 /** Maximal number of device sub-flows supported. */ 806 #define MLX5_NUM_MAX_DEV_FLOWS 32 807 808 /** 809 * tunnel offload rules type 810 */ 811 enum mlx5_tof_rule_type { 812 MLX5_TUNNEL_OFFLOAD_NONE = 0, 813 MLX5_TUNNEL_OFFLOAD_SET_RULE, 814 MLX5_TUNNEL_OFFLOAD_MATCH_RULE, 815 MLX5_TUNNEL_OFFLOAD_MISS_RULE, 816 }; 817 818 /** Device flow structure. */ 819 __extension__ 820 struct mlx5_flow { 821 struct rte_flow *flow; /**< Pointer to the main flow. */ 822 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 823 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 824 uint64_t act_flags; 825 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 826 bool external; /**< true if the flow is created external to PMD. */ 827 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 828 uint8_t skip_scale:2; 829 /** 830 * Each Bit be set to 1 if Skip the scale the flow group with factor. 831 * If bit0 be set to 1, then skip the scale the original flow group; 832 * If bit1 be set to 1, then skip the scale the jump flow group if 833 * having jump action. 834 * 00: Enable scale in a flow, default value. 835 * 01: Skip scale the flow group with factor, enable scale the group 836 * of jump action. 837 * 10: Enable scale the group with factor, skip scale the group of 838 * jump action. 839 * 11: Skip scale the table with factor both for flow group and jump 840 * group. 841 */ 842 union { 843 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 844 struct mlx5_flow_dv_workspace dv; 845 #endif 846 #ifdef HAVE_INFINIBAND_VERBS_H 847 struct mlx5_flow_verbs_workspace verbs; 848 #endif 849 }; 850 struct mlx5_flow_handle *handle; 851 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 852 const struct mlx5_flow_tunnel *tunnel; 853 enum mlx5_tof_rule_type tof_type; 854 }; 855 856 /* Flow meter state. */ 857 #define MLX5_FLOW_METER_DISABLE 0 858 #define MLX5_FLOW_METER_ENABLE 1 859 860 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u 861 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u 862 863 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES 864 865 #define MLX5_MAN_WIDTH 8 866 /* Legacy Meter parameter structure. */ 867 struct mlx5_legacy_flow_meter { 868 struct mlx5_flow_meter_info fm; 869 /* Must be the first in struct. */ 870 TAILQ_ENTRY(mlx5_legacy_flow_meter) next; 871 /**< Pointer to the next flow meter structure. */ 872 uint32_t idx; 873 /* Index to meter object. */ 874 }; 875 876 #define MLX5_MAX_TUNNELS 256 877 #define MLX5_TNL_MISS_RULE_PRIORITY 3 878 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 879 880 /* 881 * When tunnel offload is active, all JUMP group ids are converted 882 * using the same method. That conversion is applied both to tunnel and 883 * regular rule types. 884 * Group ids used in tunnel rules are relative to it's tunnel (!). 885 * Application can create number of steer rules, using the same 886 * tunnel, with different group id in each rule. 887 * Each tunnel stores its groups internally in PMD tunnel object. 888 * Groups used in regular rules do not belong to any tunnel and are stored 889 * in tunnel hub. 890 */ 891 892 struct mlx5_flow_tunnel { 893 LIST_ENTRY(mlx5_flow_tunnel) chain; 894 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 895 uint32_t tunnel_id; /** unique tunnel ID */ 896 uint32_t refctn; 897 struct rte_flow_action action; 898 struct rte_flow_item item; 899 struct mlx5_hlist *groups; /** tunnel groups */ 900 }; 901 902 /** PMD tunnel related context */ 903 struct mlx5_flow_tunnel_hub { 904 /* Tunnels list 905 * Access to the list MUST be MT protected 906 */ 907 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 908 /* protect access to the tunnels list */ 909 rte_spinlock_t sl; 910 struct mlx5_hlist *groups; /** non tunnel groups */ 911 }; 912 913 /* convert jump group to flow table ID in tunnel rules */ 914 struct tunnel_tbl_entry { 915 struct mlx5_list_entry hash; 916 uint32_t flow_table; 917 uint32_t tunnel_id; 918 uint32_t group; 919 }; 920 921 static inline uint32_t 922 tunnel_id_to_flow_tbl(uint32_t id) 923 { 924 return id | (1u << 16); 925 } 926 927 static inline uint32_t 928 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 929 { 930 return flow_tbl & ~(1u << 16); 931 } 932 933 union tunnel_tbl_key { 934 uint64_t val; 935 struct { 936 uint32_t tunnel_id; 937 uint32_t group; 938 }; 939 }; 940 941 static inline struct mlx5_flow_tunnel_hub * 942 mlx5_tunnel_hub(struct rte_eth_dev *dev) 943 { 944 struct mlx5_priv *priv = dev->data->dev_private; 945 return priv->sh->tunnel_hub; 946 } 947 948 static inline bool 949 is_tunnel_offload_active(const struct rte_eth_dev *dev) 950 { 951 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 952 const struct mlx5_priv *priv = dev->data->dev_private; 953 return !!priv->config.dv_miss_info; 954 #else 955 RTE_SET_USED(dev); 956 return false; 957 #endif 958 } 959 960 static inline bool 961 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type) 962 { 963 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 964 } 965 966 static inline bool 967 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type) 968 { 969 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE; 970 } 971 972 static inline const struct mlx5_flow_tunnel * 973 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 974 { 975 return actions[0].conf; 976 } 977 978 static inline const struct mlx5_flow_tunnel * 979 flow_items_to_tunnel(const struct rte_flow_item items[]) 980 { 981 return items[0].spec; 982 } 983 984 /* Flow structure. */ 985 struct rte_flow { 986 uint32_t dev_handles; 987 /**< Device flow handles that are part of the flow. */ 988 uint32_t type:2; 989 uint32_t drv_type:2; /**< Driver type. */ 990 uint32_t tunnel:1; 991 uint32_t meter:24; /**< Holds flow meter id. */ 992 uint32_t indirect_type:2; /**< Indirect action type. */ 993 uint32_t rix_mreg_copy; 994 /**< Index to metadata register copy table resource. */ 995 uint32_t counter; /**< Holds flow counter. */ 996 uint32_t tunnel_id; /**< Tunnel id */ 997 union { 998 uint32_t age; /**< Holds ASO age bit index. */ 999 uint32_t ct; /**< Holds ASO CT index. */ 1000 }; 1001 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 1002 } __rte_packed; 1003 1004 /* 1005 * Define list of valid combinations of RX Hash fields 1006 * (see enum ibv_rx_hash_fields). 1007 */ 1008 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1009 #define MLX5_RSS_HASH_IPV4_TCP \ 1010 (MLX5_RSS_HASH_IPV4 | \ 1011 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1012 #define MLX5_RSS_HASH_IPV4_UDP \ 1013 (MLX5_RSS_HASH_IPV4 | \ 1014 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1015 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1016 #define MLX5_RSS_HASH_IPV6_TCP \ 1017 (MLX5_RSS_HASH_IPV6 | \ 1018 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1019 #define MLX5_RSS_HASH_IPV6_UDP \ 1020 (MLX5_RSS_HASH_IPV6 | \ 1021 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1022 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 1023 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 1024 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 1025 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1026 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1027 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1028 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1029 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1030 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1031 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1032 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1033 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1034 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1035 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1036 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1037 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1038 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1039 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1040 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1041 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1042 #define MLX5_RSS_HASH_NONE 0ULL 1043 1044 1045 /* extract next protocol type from Ethernet & VLAN headers */ 1046 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \ 1047 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \ 1048 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \ 1049 (_prt) = rte_be_to_cpu_16((_prt)); \ 1050 } while (0) 1051 1052 /* array of valid combinations of RX Hash fields for RSS */ 1053 static const uint64_t mlx5_rss_hash_fields[] = { 1054 MLX5_RSS_HASH_IPV4, 1055 MLX5_RSS_HASH_IPV4_TCP, 1056 MLX5_RSS_HASH_IPV4_UDP, 1057 MLX5_RSS_HASH_IPV6, 1058 MLX5_RSS_HASH_IPV6_TCP, 1059 MLX5_RSS_HASH_IPV6_UDP, 1060 MLX5_RSS_HASH_NONE, 1061 }; 1062 1063 /* Shared RSS action structure */ 1064 struct mlx5_shared_action_rss { 1065 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1066 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1067 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1068 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1069 struct mlx5_ind_table_obj *ind_tbl; 1070 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1071 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1072 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1073 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1074 }; 1075 1076 struct rte_flow_action_handle { 1077 uint32_t id; 1078 }; 1079 1080 /* Thread specific flow workspace intermediate data. */ 1081 struct mlx5_flow_workspace { 1082 /* If creating another flow in same thread, push new as stack. */ 1083 struct mlx5_flow_workspace *prev; 1084 struct mlx5_flow_workspace *next; 1085 uint32_t inuse; /* can't create new flow with current. */ 1086 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1087 struct mlx5_flow_rss_desc rss_desc; 1088 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1089 uint32_t flow_idx; /* Intermediate device flow index. */ 1090 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */ 1091 struct mlx5_flow_meter_policy *policy; 1092 /* The meter policy used by meter in flow. */ 1093 struct mlx5_flow_meter_policy *final_policy; 1094 /* The final policy when meter policy is hierarchy. */ 1095 uint32_t skip_matcher_reg:1; 1096 /* Indicates if need to skip matcher register in translate. */ 1097 }; 1098 1099 struct mlx5_flow_split_info { 1100 bool external; 1101 /**< True if flow is created by request external to PMD. */ 1102 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1103 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1104 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1105 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1106 uint32_t table_id; /**< Flow table identifier. */ 1107 }; 1108 1109 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1110 const struct rte_flow_attr *attr, 1111 const struct rte_flow_item items[], 1112 const struct rte_flow_action actions[], 1113 bool external, 1114 int hairpin, 1115 struct rte_flow_error *error); 1116 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1117 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1118 const struct rte_flow_item items[], 1119 const struct rte_flow_action actions[], struct rte_flow_error *error); 1120 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1121 struct mlx5_flow *dev_flow, 1122 const struct rte_flow_attr *attr, 1123 const struct rte_flow_item items[], 1124 const struct rte_flow_action actions[], 1125 struct rte_flow_error *error); 1126 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1127 struct rte_flow_error *error); 1128 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1129 struct rte_flow *flow); 1130 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1131 struct rte_flow *flow); 1132 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1133 struct rte_flow *flow, 1134 const struct rte_flow_action *actions, 1135 void *data, 1136 struct rte_flow_error *error); 1137 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev, 1138 struct mlx5_flow_meter_info *fm, 1139 uint32_t mtr_idx, 1140 uint8_t domain_bitmap); 1141 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1142 struct mlx5_flow_meter_info *fm); 1143 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev); 1144 typedef struct mlx5_flow_meter_sub_policy * 1145 (*mlx5_flow_meter_sub_policy_rss_prepare_t) 1146 (struct rte_eth_dev *dev, 1147 struct mlx5_flow_meter_policy *mtr_policy, 1148 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1149 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t) 1150 (struct rte_eth_dev *dev, 1151 struct mlx5_flow_meter_info *fm, 1152 int32_t src_port, 1153 const struct rte_flow_item *item, 1154 struct rte_flow_error *error); 1155 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t) 1156 (struct rte_eth_dev *dev, 1157 struct mlx5_flow_meter_policy *mtr_policy); 1158 typedef uint32_t (*mlx5_flow_mtr_alloc_t) 1159 (struct rte_eth_dev *dev); 1160 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev, 1161 uint32_t mtr_idx); 1162 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1163 (struct rte_eth_dev *dev); 1164 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1165 uint32_t cnt); 1166 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1167 uint32_t cnt, 1168 bool clear, uint64_t *pkts, 1169 uint64_t *bytes); 1170 typedef int (*mlx5_flow_get_aged_flows_t) 1171 (struct rte_eth_dev *dev, 1172 void **context, 1173 uint32_t nb_contexts, 1174 struct rte_flow_error *error); 1175 typedef int (*mlx5_flow_action_validate_t) 1176 (struct rte_eth_dev *dev, 1177 const struct rte_flow_indir_action_conf *conf, 1178 const struct rte_flow_action *action, 1179 struct rte_flow_error *error); 1180 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1181 (struct rte_eth_dev *dev, 1182 const struct rte_flow_indir_action_conf *conf, 1183 const struct rte_flow_action *action, 1184 struct rte_flow_error *error); 1185 typedef int (*mlx5_flow_action_destroy_t) 1186 (struct rte_eth_dev *dev, 1187 struct rte_flow_action_handle *action, 1188 struct rte_flow_error *error); 1189 typedef int (*mlx5_flow_action_update_t) 1190 (struct rte_eth_dev *dev, 1191 struct rte_flow_action_handle *action, 1192 const void *update, 1193 struct rte_flow_error *error); 1194 typedef int (*mlx5_flow_action_query_t) 1195 (struct rte_eth_dev *dev, 1196 const struct rte_flow_action_handle *action, 1197 void *data, 1198 struct rte_flow_error *error); 1199 typedef int (*mlx5_flow_sync_domain_t) 1200 (struct rte_eth_dev *dev, 1201 uint32_t domains, 1202 uint32_t flags); 1203 typedef int (*mlx5_flow_validate_mtr_acts_t) 1204 (struct rte_eth_dev *dev, 1205 const struct rte_flow_action *actions[RTE_COLORS], 1206 struct rte_flow_attr *attr, 1207 bool *is_rss, 1208 uint8_t *domain_bitmap, 1209 uint8_t *policy_mode, 1210 struct rte_mtr_error *error); 1211 typedef int (*mlx5_flow_create_mtr_acts_t) 1212 (struct rte_eth_dev *dev, 1213 struct mlx5_flow_meter_policy *mtr_policy, 1214 const struct rte_flow_action *actions[RTE_COLORS], 1215 struct rte_mtr_error *error); 1216 typedef void (*mlx5_flow_destroy_mtr_acts_t) 1217 (struct rte_eth_dev *dev, 1218 struct mlx5_flow_meter_policy *mtr_policy); 1219 typedef int (*mlx5_flow_create_policy_rules_t) 1220 (struct rte_eth_dev *dev, 1221 struct mlx5_flow_meter_policy *mtr_policy); 1222 typedef void (*mlx5_flow_destroy_policy_rules_t) 1223 (struct rte_eth_dev *dev, 1224 struct mlx5_flow_meter_policy *mtr_policy); 1225 typedef int (*mlx5_flow_create_def_policy_t) 1226 (struct rte_eth_dev *dev); 1227 typedef void (*mlx5_flow_destroy_def_policy_t) 1228 (struct rte_eth_dev *dev); 1229 1230 struct mlx5_flow_driver_ops { 1231 mlx5_flow_validate_t validate; 1232 mlx5_flow_prepare_t prepare; 1233 mlx5_flow_translate_t translate; 1234 mlx5_flow_apply_t apply; 1235 mlx5_flow_remove_t remove; 1236 mlx5_flow_destroy_t destroy; 1237 mlx5_flow_query_t query; 1238 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1239 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1240 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls; 1241 mlx5_flow_mtr_alloc_t create_meter; 1242 mlx5_flow_mtr_free_t free_meter; 1243 mlx5_flow_validate_mtr_acts_t validate_mtr_acts; 1244 mlx5_flow_create_mtr_acts_t create_mtr_acts; 1245 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts; 1246 mlx5_flow_create_policy_rules_t create_policy_rules; 1247 mlx5_flow_destroy_policy_rules_t destroy_policy_rules; 1248 mlx5_flow_create_def_policy_t create_def_policy; 1249 mlx5_flow_destroy_def_policy_t destroy_def_policy; 1250 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare; 1251 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create; 1252 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq; 1253 mlx5_flow_counter_alloc_t counter_alloc; 1254 mlx5_flow_counter_free_t counter_free; 1255 mlx5_flow_counter_query_t counter_query; 1256 mlx5_flow_get_aged_flows_t get_aged_flows; 1257 mlx5_flow_action_validate_t action_validate; 1258 mlx5_flow_action_create_t action_create; 1259 mlx5_flow_action_destroy_t action_destroy; 1260 mlx5_flow_action_update_t action_update; 1261 mlx5_flow_action_query_t action_query; 1262 mlx5_flow_sync_domain_t sync_domain; 1263 }; 1264 1265 /* mlx5_flow.c */ 1266 1267 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1268 __extension__ 1269 struct flow_grp_info { 1270 uint64_t external:1; 1271 uint64_t transfer:1; 1272 uint64_t fdb_def_rule:1; 1273 /* force standard group translation */ 1274 uint64_t std_tbl_fix:1; 1275 uint64_t skip_scale:2; 1276 }; 1277 1278 static inline bool 1279 tunnel_use_standard_attr_group_translate 1280 (const struct rte_eth_dev *dev, 1281 const struct rte_flow_attr *attr, 1282 const struct mlx5_flow_tunnel *tunnel, 1283 enum mlx5_tof_rule_type tof_rule_type) 1284 { 1285 bool verdict; 1286 1287 if (!is_tunnel_offload_active(dev)) 1288 /* no tunnel offload API */ 1289 verdict = true; 1290 else if (tunnel) { 1291 /* 1292 * OvS will use jump to group 0 in tunnel steer rule. 1293 * If tunnel steer rule starts from group 0 (attr.group == 0) 1294 * that 0 group must be translated with standard method. 1295 * attr.group == 0 in tunnel match rule translated with tunnel 1296 * method 1297 */ 1298 verdict = !attr->group && 1299 is_flow_tunnel_steer_rule(tof_rule_type); 1300 } else { 1301 /* 1302 * non-tunnel group translation uses standard method for 1303 * root group only: attr.group == 0 1304 */ 1305 verdict = !attr->group; 1306 } 1307 1308 return verdict; 1309 } 1310 1311 /** 1312 * Get DV flow aso meter by index. 1313 * 1314 * @param[in] dev 1315 * Pointer to the Ethernet device structure. 1316 * @param[in] idx 1317 * mlx5 flow aso meter index in the container. 1318 * @param[out] ppool 1319 * mlx5 flow aso meter pool in the container, 1320 * 1321 * @return 1322 * Pointer to the aso meter, NULL otherwise. 1323 */ 1324 static inline struct mlx5_aso_mtr * 1325 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) 1326 { 1327 struct mlx5_aso_mtr_pool *pool; 1328 struct mlx5_aso_mtr_pools_mng *pools_mng = 1329 &priv->sh->mtrmng->pools_mng; 1330 1331 /* Decrease to original index. */ 1332 idx--; 1333 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n); 1334 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL]; 1335 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; 1336 } 1337 1338 static __rte_always_inline const struct rte_flow_item * 1339 mlx5_find_end_item(const struct rte_flow_item *item) 1340 { 1341 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++); 1342 return item; 1343 } 1344 1345 static __rte_always_inline bool 1346 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item) 1347 { 1348 struct rte_flow_item_integrity test = *item; 1349 test.l3_ok = 0; 1350 test.l4_ok = 0; 1351 test.ipv4_csum_ok = 0; 1352 test.l4_csum_ok = 0; 1353 return (test.value == 0); 1354 } 1355 1356 /* 1357 * Get ASO CT action by device and index. 1358 * 1359 * @param[in] dev 1360 * Pointer to the Ethernet device structure. 1361 * @param[in] idx 1362 * Index to the ASO CT action. 1363 * 1364 * @return 1365 * The specified ASO CT action pointer. 1366 */ 1367 static inline struct mlx5_aso_ct_action * 1368 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx) 1369 { 1370 struct mlx5_priv *priv = dev->data->dev_private; 1371 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng; 1372 struct mlx5_aso_ct_pool *pool; 1373 1374 idx--; 1375 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n); 1376 /* Bit operation AND could be used. */ 1377 rte_rwlock_read_lock(&mng->resize_rwl); 1378 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL]; 1379 rte_rwlock_read_unlock(&mng->resize_rwl); 1380 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL]; 1381 } 1382 1383 /* 1384 * Get ASO CT action by owner & index. 1385 * 1386 * @param[in] dev 1387 * Pointer to the Ethernet device structure. 1388 * @param[in] idx 1389 * Index to the ASO CT action and owner port combination. 1390 * 1391 * @return 1392 * The specified ASO CT action pointer. 1393 */ 1394 static inline struct mlx5_aso_ct_action * 1395 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx) 1396 { 1397 struct mlx5_priv *priv = dev->data->dev_private; 1398 struct mlx5_aso_ct_action *ct; 1399 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx); 1400 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx); 1401 1402 if (owner == PORT_ID(priv)) { 1403 ct = flow_aso_ct_get_by_dev_idx(dev, idx); 1404 } else { 1405 struct rte_eth_dev *owndev = &rte_eth_devices[owner]; 1406 1407 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS); 1408 if (dev->data->dev_started != 1) 1409 return NULL; 1410 ct = flow_aso_ct_get_by_dev_idx(owndev, idx); 1411 if (ct->peer != PORT_ID(priv)) 1412 return NULL; 1413 } 1414 return ct; 1415 } 1416 1417 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1418 const struct mlx5_flow_tunnel *tunnel, 1419 uint32_t group, uint32_t *table, 1420 const struct flow_grp_info *flags, 1421 struct rte_flow_error *error); 1422 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1423 int tunnel, uint64_t layer_types, 1424 uint64_t hash_fields); 1425 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1426 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1427 uint32_t subpriority); 1428 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1429 const struct rte_flow_attr *attr); 1430 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1431 const struct rte_flow_attr *attr, 1432 uint32_t subpriority); 1433 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1434 enum mlx5_feature_name feature, 1435 uint32_t id, 1436 struct rte_flow_error *error); 1437 const struct rte_flow_action *mlx5_flow_find_action 1438 (const struct rte_flow_action *actions, 1439 enum rte_flow_action_type action); 1440 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1441 const struct rte_flow_action *action, 1442 struct rte_flow_error *error); 1443 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1444 const struct rte_flow_attr *attr, 1445 struct rte_flow_error *error); 1446 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1447 const struct rte_flow_attr *attr, 1448 struct rte_flow_error *error); 1449 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1450 const struct rte_flow_attr *attr, 1451 struct rte_flow_error *error); 1452 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1453 uint64_t action_flags, 1454 const struct rte_flow_attr *attr, 1455 struct rte_flow_error *error); 1456 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1457 uint64_t action_flags, 1458 struct rte_eth_dev *dev, 1459 const struct rte_flow_attr *attr, 1460 struct rte_flow_error *error); 1461 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1462 uint64_t action_flags, 1463 struct rte_eth_dev *dev, 1464 const struct rte_flow_attr *attr, 1465 uint64_t item_flags, 1466 struct rte_flow_error *error); 1467 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1468 const struct rte_flow_attr *attr, 1469 struct rte_flow_error *error); 1470 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1471 const struct rte_flow_attr *attributes, 1472 struct rte_flow_error *error); 1473 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1474 const uint8_t *mask, 1475 const uint8_t *nic_mask, 1476 unsigned int size, 1477 bool range_accepted, 1478 struct rte_flow_error *error); 1479 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1480 uint64_t item_flags, bool ext_vlan_sup, 1481 struct rte_flow_error *error); 1482 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1483 uint64_t item_flags, 1484 uint8_t target_protocol, 1485 struct rte_flow_error *error); 1486 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1487 uint64_t item_flags, 1488 const struct rte_flow_item *gre_item, 1489 struct rte_flow_error *error); 1490 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1491 uint64_t item_flags, 1492 uint64_t last_item, 1493 uint16_t ether_type, 1494 const struct rte_flow_item_ipv4 *acc_mask, 1495 bool range_accepted, 1496 struct rte_flow_error *error); 1497 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1498 uint64_t item_flags, 1499 uint64_t last_item, 1500 uint16_t ether_type, 1501 const struct rte_flow_item_ipv6 *acc_mask, 1502 struct rte_flow_error *error); 1503 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1504 const struct rte_flow_item *item, 1505 uint64_t item_flags, 1506 uint64_t prev_layer, 1507 struct rte_flow_error *error); 1508 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1509 uint64_t item_flags, 1510 uint8_t target_protocol, 1511 const struct rte_flow_item_tcp *flow_mask, 1512 struct rte_flow_error *error); 1513 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1514 uint64_t item_flags, 1515 uint8_t target_protocol, 1516 struct rte_flow_error *error); 1517 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1518 uint64_t item_flags, 1519 struct rte_eth_dev *dev, 1520 struct rte_flow_error *error); 1521 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 1522 uint16_t udp_dport, 1523 const struct rte_flow_item *item, 1524 uint64_t item_flags, 1525 const struct rte_flow_attr *attr, 1526 struct rte_flow_error *error); 1527 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1528 uint64_t item_flags, 1529 struct rte_eth_dev *dev, 1530 struct rte_flow_error *error); 1531 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1532 uint64_t item_flags, 1533 uint8_t target_protocol, 1534 struct rte_flow_error *error); 1535 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1536 uint64_t item_flags, 1537 uint8_t target_protocol, 1538 struct rte_flow_error *error); 1539 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1540 uint64_t item_flags, 1541 uint8_t target_protocol, 1542 struct rte_flow_error *error); 1543 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1544 uint64_t item_flags, 1545 struct rte_eth_dev *dev, 1546 struct rte_flow_error *error); 1547 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1548 uint64_t last_item, 1549 const struct rte_flow_item *geneve_item, 1550 struct rte_eth_dev *dev, 1551 struct rte_flow_error *error); 1552 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1553 uint64_t item_flags, 1554 uint64_t last_item, 1555 uint16_t ether_type, 1556 const struct rte_flow_item_ecpri *acc_mask, 1557 struct rte_flow_error *error); 1558 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 1559 struct mlx5_flow_meter_info *fm, 1560 uint32_t mtr_idx, 1561 uint8_t domain_bitmap); 1562 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1563 struct mlx5_flow_meter_info *fm); 1564 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev); 1565 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare 1566 (struct rte_eth_dev *dev, 1567 struct mlx5_flow_meter_policy *mtr_policy, 1568 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); 1569 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 1570 struct mlx5_flow_meter_policy *mtr_policy); 1571 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1572 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev); 1573 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1574 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1575 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1576 1577 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx); 1578 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1579 void *cb_ctx); 1580 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1581 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx, 1582 struct mlx5_list_entry *oentry, 1583 void *entry_ctx); 1584 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1585 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1586 uint32_t table_level, uint8_t egress, uint8_t transfer, 1587 bool external, const struct mlx5_flow_tunnel *tunnel, 1588 uint32_t group_id, uint8_t dummy, 1589 uint32_t table_id, struct rte_flow_error *error); 1590 1591 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx); 1592 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1593 void *cb_ctx); 1594 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1595 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx, 1596 struct mlx5_list_entry *oentry, 1597 void *cb_ctx); 1598 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1599 1600 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1601 void *cb_ctx); 1602 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx); 1603 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1604 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx, 1605 struct mlx5_list_entry *oentry, 1606 void *ctx); 1607 void flow_dv_modify_clone_free_cb(void *tool_ctx, 1608 struct mlx5_list_entry *entry); 1609 1610 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx); 1611 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1612 void *cb_ctx); 1613 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1614 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx, 1615 struct mlx5_list_entry *entry, 1616 void *ctx); 1617 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1618 1619 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1620 void *cb_ctx); 1621 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx, 1622 void *cb_ctx); 1623 void flow_dv_encap_decap_remove_cb(void *tool_ctx, 1624 struct mlx5_list_entry *entry); 1625 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx, 1626 struct mlx5_list_entry *entry, 1627 void *cb_ctx); 1628 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx, 1629 struct mlx5_list_entry *entry); 1630 1631 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1632 void *ctx); 1633 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx); 1634 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1635 1636 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1637 void *cb_ctx); 1638 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx); 1639 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1640 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx, 1641 struct mlx5_list_entry *entry, void *cb_ctx); 1642 void flow_dv_port_id_clone_free_cb(void *tool_ctx, 1643 struct mlx5_list_entry *entry); 1644 1645 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1646 void *cb_ctx); 1647 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx, 1648 void *cb_ctx); 1649 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1650 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx, 1651 struct mlx5_list_entry *entry, void *cb_ctx); 1652 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx, 1653 struct mlx5_list_entry *entry); 1654 1655 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1656 void *cb_ctx); 1657 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx); 1658 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 1659 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx, 1660 struct mlx5_list_entry *entry, void *cb_ctx); 1661 void flow_dv_sample_clone_free_cb(void *tool_ctx, 1662 struct mlx5_list_entry *entry); 1663 1664 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 1665 void *cb_ctx); 1666 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx, 1667 void *cb_ctx); 1668 void flow_dv_dest_array_remove_cb(void *tool_ctx, 1669 struct mlx5_list_entry *entry); 1670 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx, 1671 struct mlx5_list_entry *entry, void *cb_ctx); 1672 void flow_dv_dest_array_clone_free_cb(void *tool_ctx, 1673 struct mlx5_list_entry *entry); 1674 1675 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1676 uint32_t age_idx); 1677 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1678 const struct rte_flow_item *item, 1679 struct rte_flow_error *error); 1680 void flow_release_workspace(void *data); 1681 int mlx5_flow_os_init_workspace_once(void); 1682 void *mlx5_flow_os_get_specific_workspace(void); 1683 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1684 void mlx5_flow_os_release_workspace(void); 1685 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev); 1686 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx); 1687 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 1688 const struct rte_flow_action *actions[RTE_COLORS], 1689 struct rte_flow_attr *attr, 1690 bool *is_rss, 1691 uint8_t *domain_bitmap, 1692 uint8_t *policy_mode, 1693 struct rte_mtr_error *error); 1694 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 1695 struct mlx5_flow_meter_policy *mtr_policy); 1696 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 1697 struct mlx5_flow_meter_policy *mtr_policy, 1698 const struct rte_flow_action *actions[RTE_COLORS], 1699 struct rte_mtr_error *error); 1700 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 1701 struct mlx5_flow_meter_policy *mtr_policy); 1702 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 1703 struct mlx5_flow_meter_policy *mtr_policy); 1704 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev); 1705 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev); 1706 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1707 struct mlx5_flow_handle *dev_handle); 1708 const struct mlx5_flow_tunnel * 1709 mlx5_get_tof(const struct rte_flow_item *items, 1710 const struct rte_flow_action *actions, 1711 enum mlx5_tof_rule_type *rule_type); 1712 1713 1714 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1715