184c406e7SOri Kam /* SPDX-License-Identifier: BSD-3-Clause 284c406e7SOri Kam * Copyright 2018 Mellanox Technologies, Ltd 384c406e7SOri Kam */ 484c406e7SOri Kam 584c406e7SOri Kam #ifndef RTE_PMD_MLX5_FLOW_H_ 684c406e7SOri Kam #define RTE_PMD_MLX5_FLOW_H_ 784c406e7SOri Kam 884c406e7SOri Kam #include <netinet/in.h> 984c406e7SOri Kam #include <sys/queue.h> 1084c406e7SOri Kam #include <stdalign.h> 1184c406e7SOri Kam #include <stdint.h> 1284c406e7SOri Kam #include <string.h> 1384c406e7SOri Kam 1484c406e7SOri Kam /* Verbs header. */ 1584c406e7SOri Kam /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 1684c406e7SOri Kam #ifdef PEDANTIC 1784c406e7SOri Kam #pragma GCC diagnostic ignored "-Wpedantic" 1884c406e7SOri Kam #endif 1984c406e7SOri Kam #include <infiniband/verbs.h> 2084c406e7SOri Kam #ifdef PEDANTIC 2184c406e7SOri Kam #pragma GCC diagnostic error "-Wpedantic" 2284c406e7SOri Kam #endif 2384c406e7SOri Kam 2484c406e7SOri Kam /* Pattern outer Layer bits. */ 2584c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 2684c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 2784c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 2884c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 2984c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 3084c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 3184c406e7SOri Kam 3284c406e7SOri Kam /* Pattern inner Layer bits. */ 3384c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 3484c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 3584c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 3684c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 3784c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 3884c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 3984c406e7SOri Kam 4084c406e7SOri Kam /* Pattern tunnel Layer bits. */ 4184c406e7SOri Kam #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 4284c406e7SOri Kam #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 4384c406e7SOri Kam #define MLX5_FLOW_LAYER_GRE (1u << 14) 4484c406e7SOri Kam #define MLX5_FLOW_LAYER_MPLS (1u << 15) 4584c406e7SOri Kam 466bd7fbd0SDekel Peled /* General pattern items bits. */ 476bd7fbd0SDekel Peled #define MLX5_FLOW_ITEM_METADATA (1u << 16) 486bd7fbd0SDekel Peled 4984c406e7SOri Kam /* Outer Masks. */ 5084c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L3 \ 5184c406e7SOri Kam (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 5284c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L4 \ 5384c406e7SOri Kam (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 5484c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER \ 5584c406e7SOri Kam (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 5684c406e7SOri Kam MLX5_FLOW_LAYER_OUTER_L4) 5784c406e7SOri Kam 5884c406e7SOri Kam /* Tunnel Masks. */ 5984c406e7SOri Kam #define MLX5_FLOW_LAYER_TUNNEL \ 6084c406e7SOri Kam (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 6184c406e7SOri Kam MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS) 6284c406e7SOri Kam 6384c406e7SOri Kam /* Inner Masks. */ 6484c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L3 \ 6584c406e7SOri Kam (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 6684c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L4 \ 6784c406e7SOri Kam (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 6884c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER \ 6984c406e7SOri Kam (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 7084c406e7SOri Kam MLX5_FLOW_LAYER_INNER_L4) 7184c406e7SOri Kam 7284c406e7SOri Kam /* Actions */ 7384c406e7SOri Kam #define MLX5_FLOW_ACTION_DROP (1u << 0) 7484c406e7SOri Kam #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 7584c406e7SOri Kam #define MLX5_FLOW_ACTION_RSS (1u << 2) 7684c406e7SOri Kam #define MLX5_FLOW_ACTION_FLAG (1u << 3) 7784c406e7SOri Kam #define MLX5_FLOW_ACTION_MARK (1u << 4) 7884c406e7SOri Kam #define MLX5_FLOW_ACTION_COUNT (1u << 5) 7957123c00SYongseok Koh #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 8057123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 8157123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 8257123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 8357123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 842ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 852ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 862ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 872ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 882ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 892ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 9031fda518SYongseok Koh #define MLX5_FLOW_ACTION_JUMP (1u << 17) 91a7cb5bcdSXiaoyu Min #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 92a7cb5bcdSXiaoyu Min #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 9376046778SXiaoyu Min #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 9476046778SXiaoyu Min #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 9534d41b7aSDekel Peled #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22) 9649d6465aSDekel Peled #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23) 97a124cff0SDekel Peled #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24) 984b8727f0SDekel Peled #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25) 998ba9eee4SDekel Peled #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26) 1008ba9eee4SDekel Peled #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27) 10184c406e7SOri Kam 10284c406e7SOri Kam #define MLX5_FLOW_FATE_ACTIONS \ 10384c406e7SOri Kam (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS) 10484c406e7SOri Kam 1058ba9eee4SDekel Peled #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ 1068ba9eee4SDekel Peled MLX5_FLOW_ACTION_NVGRE_ENCAP | \ 1078ba9eee4SDekel Peled MLX5_FLOW_ACTION_RAW_ENCAP) 108a124cff0SDekel Peled 1098ba9eee4SDekel Peled #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ 1108ba9eee4SDekel Peled MLX5_FLOW_ACTION_NVGRE_DECAP | \ 1118ba9eee4SDekel Peled MLX5_FLOW_ACTION_RAW_DECAP) 1124b8727f0SDekel Peled 11384c406e7SOri Kam #ifndef IPPROTO_MPLS 11484c406e7SOri Kam #define IPPROTO_MPLS 137 11584c406e7SOri Kam #endif 11684c406e7SOri Kam 117fc2c498cSOri Kam /* UDP port numbers for VxLAN. */ 118fc2c498cSOri Kam #define MLX5_UDP_PORT_VXLAN 4789 119fc2c498cSOri Kam #define MLX5_UDP_PORT_VXLAN_GPE 4790 120fc2c498cSOri Kam 12184c406e7SOri Kam /* Priority reserved for default flows. */ 12284c406e7SOri Kam #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) 12384c406e7SOri Kam 12484c406e7SOri Kam /* 12584c406e7SOri Kam * Number of sub priorities. 12684c406e7SOri Kam * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 12784c406e7SOri Kam * matching on the NIC (firmware dependent) L4 most have the higher priority 12884c406e7SOri Kam * followed by L3 and ending with L2. 12984c406e7SOri Kam */ 13084c406e7SOri Kam #define MLX5_PRIORITY_MAP_L2 2 13184c406e7SOri Kam #define MLX5_PRIORITY_MAP_L3 1 13284c406e7SOri Kam #define MLX5_PRIORITY_MAP_L4 0 13384c406e7SOri Kam #define MLX5_PRIORITY_MAP_MAX 3 13484c406e7SOri Kam 135fc2c498cSOri Kam /* Valid layer type for IPV4 RSS. */ 136fc2c498cSOri Kam #define MLX5_IPV4_LAYER_TYPES \ 137fc2c498cSOri Kam (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 138fc2c498cSOri Kam ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 139fc2c498cSOri Kam ETH_RSS_NONFRAG_IPV4_OTHER) 140fc2c498cSOri Kam 141fc2c498cSOri Kam /* IBV hash source bits for IPV4. */ 142fc2c498cSOri Kam #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 143fc2c498cSOri Kam 144fc2c498cSOri Kam /* Valid layer type for IPV6 RSS. */ 145fc2c498cSOri Kam #define MLX5_IPV6_LAYER_TYPES \ 146fc2c498cSOri Kam (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 147fc2c498cSOri Kam ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 148fc2c498cSOri Kam ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 149fc2c498cSOri Kam 150fc2c498cSOri Kam /* IBV hash source bits for IPV6. */ 151fc2c498cSOri Kam #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 152fc2c498cSOri Kam 1533d694341SOri Kam /* Max number of actions per DV flow. */ 1543d694341SOri Kam #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 1553d694341SOri Kam 1560c76d1c9SYongseok Koh enum mlx5_flow_drv_type { 1570c76d1c9SYongseok Koh MLX5_FLOW_TYPE_MIN, 1580c76d1c9SYongseok Koh MLX5_FLOW_TYPE_DV, 15957123c00SYongseok Koh MLX5_FLOW_TYPE_TCF, 1600c76d1c9SYongseok Koh MLX5_FLOW_TYPE_VERBS, 1610c76d1c9SYongseok Koh MLX5_FLOW_TYPE_MAX, 1620c76d1c9SYongseok Koh }; 1630c76d1c9SYongseok Koh 164865a0c15SOri Kam /* Matcher PRM representation */ 165865a0c15SOri Kam struct mlx5_flow_dv_match_params { 166865a0c15SOri Kam size_t size; 167865a0c15SOri Kam /**< Size of match value. Do NOT split size and key! */ 168865a0c15SOri Kam uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 169865a0c15SOri Kam /**< Matcher value. This value is used as the mask or as a key. */ 170865a0c15SOri Kam }; 171865a0c15SOri Kam 172d02cb069SOri Kam #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 173*c513f05cSDekel Peled #define MLX5_ENCAP_MAX_LEN 132 174d02cb069SOri Kam 175865a0c15SOri Kam /* Matcher structure. */ 176865a0c15SOri Kam struct mlx5_flow_dv_matcher { 177865a0c15SOri Kam LIST_ENTRY(mlx5_flow_dv_matcher) next; 178865a0c15SOri Kam /* Pointer to the next element. */ 179865a0c15SOri Kam rte_atomic32_t refcnt; /**< Reference counter. */ 180865a0c15SOri Kam void *matcher_object; /**< Pointer to DV matcher */ 181865a0c15SOri Kam uint16_t crc; /**< CRC of key. */ 182865a0c15SOri Kam uint16_t priority; /**< Priority of matcher. */ 183865a0c15SOri Kam uint8_t egress; /**< Egress matcher. */ 184865a0c15SOri Kam struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 185865a0c15SOri Kam }; 186865a0c15SOri Kam 187*c513f05cSDekel Peled /* Encap/decap resource structure. */ 188*c513f05cSDekel Peled struct mlx5_flow_dv_encap_decap_resource { 189*c513f05cSDekel Peled LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next; 190*c513f05cSDekel Peled /* Pointer to next element. */ 191*c513f05cSDekel Peled rte_atomic32_t refcnt; /**< Reference counter. */ 192*c513f05cSDekel Peled struct ibv_flow_action *verbs_action; 193*c513f05cSDekel Peled /**< Verbs encap/decap action object. */ 194*c513f05cSDekel Peled uint8_t buf[MLX5_ENCAP_MAX_LEN]; 195*c513f05cSDekel Peled size_t size; 196*c513f05cSDekel Peled uint8_t reformat_type; 197*c513f05cSDekel Peled uint8_t ft_type; 198*c513f05cSDekel Peled }; 199*c513f05cSDekel Peled 200865a0c15SOri Kam /* DV flows structure. */ 201865a0c15SOri Kam struct mlx5_flow_dv { 202865a0c15SOri Kam uint64_t hash_fields; /**< Fields that participate in the hash. */ 203865a0c15SOri Kam struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */ 204865a0c15SOri Kam /* Flow DV api: */ 205865a0c15SOri Kam struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 206865a0c15SOri Kam struct mlx5_flow_dv_match_params value; 207865a0c15SOri Kam /**< Holds the value that the packet is compared to. */ 208*c513f05cSDekel Peled struct mlx5_flow_dv_encap_decap_resource *encap_decap; 209*c513f05cSDekel Peled /**< Pointer to encap/decap resource in cache. */ 210865a0c15SOri Kam struct ibv_flow *flow; /**< Installed flow. */ 211d02cb069SOri Kam #ifdef HAVE_IBV_FLOW_DV_SUPPORT 212d02cb069SOri Kam struct mlx5dv_flow_action_attr actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 213d02cb069SOri Kam /**< Action list. */ 214d02cb069SOri Kam #endif 215d02cb069SOri Kam int actions_n; /**< number of actions. */ 216865a0c15SOri Kam }; 217865a0c15SOri Kam 21857123c00SYongseok Koh /** Linux TC flower driver for E-Switch flow. */ 21957123c00SYongseok Koh struct mlx5_flow_tcf { 22057123c00SYongseok Koh struct nlmsghdr *nlh; 22157123c00SYongseok Koh struct tcmsg *tcm; 22257123c00SYongseok Koh }; 22357123c00SYongseok Koh 22484c406e7SOri Kam /* Verbs specification header. */ 22584c406e7SOri Kam struct ibv_spec_header { 22684c406e7SOri Kam enum ibv_flow_spec_type type; 22784c406e7SOri Kam uint16_t size; 22884c406e7SOri Kam }; 22984c406e7SOri Kam 23084c406e7SOri Kam /** Handles information leading to a drop fate. */ 23184c406e7SOri Kam struct mlx5_flow_verbs { 23284c406e7SOri Kam LIST_ENTRY(mlx5_flow_verbs) next; 23384c406e7SOri Kam unsigned int size; /**< Size of the attribute. */ 23484c406e7SOri Kam struct { 23584c406e7SOri Kam struct ibv_flow_attr *attr; 23684c406e7SOri Kam /**< Pointer to the Specification buffer. */ 23784c406e7SOri Kam uint8_t *specs; /**< Pointer to the specifications. */ 23884c406e7SOri Kam }; 23984c406e7SOri Kam struct ibv_flow *flow; /**< Verbs flow pointer. */ 24084c406e7SOri Kam struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ 24184c406e7SOri Kam uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ 24284c406e7SOri Kam }; 24384c406e7SOri Kam 24484c406e7SOri Kam /** Device flow structure. */ 24584c406e7SOri Kam struct mlx5_flow { 24684c406e7SOri Kam LIST_ENTRY(mlx5_flow) next; 24784c406e7SOri Kam struct rte_flow *flow; /**< Pointer to the main flow. */ 2480ddd1143SYongseok Koh uint64_t layers; 24924663641SYongseok Koh /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 25084c406e7SOri Kam union { 251c4d9b9f7SOri Kam #ifdef HAVE_IBV_FLOW_DV_SUPPORT 252865a0c15SOri Kam struct mlx5_flow_dv dv; 253c4d9b9f7SOri Kam #endif 25457123c00SYongseok Koh struct mlx5_flow_tcf tcf; 255865a0c15SOri Kam struct mlx5_flow_verbs verbs; 25684c406e7SOri Kam }; 25784c406e7SOri Kam }; 25884c406e7SOri Kam 25984c406e7SOri Kam /* Counters information. */ 26084c406e7SOri Kam struct mlx5_flow_counter { 26184c406e7SOri Kam LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */ 26284c406e7SOri Kam uint32_t shared:1; /**< Share counter ID with other flow rules. */ 26384c406e7SOri Kam uint32_t ref_cnt:31; /**< Reference counter. */ 26484c406e7SOri Kam uint32_t id; /**< Counter ID. */ 265db48f9dbSViacheslav Ovsiienko #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 26684c406e7SOri Kam struct ibv_counter_set *cs; /**< Holds the counters for the rule. */ 267db48f9dbSViacheslav Ovsiienko #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 268db48f9dbSViacheslav Ovsiienko struct ibv_counters *cs; /**< Holds the counters for the rule. */ 269db48f9dbSViacheslav Ovsiienko #endif 27084c406e7SOri Kam uint64_t hits; /**< Number of packets matched by the rule. */ 27184c406e7SOri Kam uint64_t bytes; /**< Number of bytes matched by the rule. */ 27284c406e7SOri Kam }; 27384c406e7SOri Kam 27484c406e7SOri Kam /* Flow structure. */ 27584c406e7SOri Kam struct rte_flow { 27684c406e7SOri Kam TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */ 2770c76d1c9SYongseok Koh enum mlx5_flow_drv_type drv_type; /**< Drvier type. */ 27884c406e7SOri Kam struct mlx5_flow_counter *counter; /**< Holds flow counter. */ 27984c406e7SOri Kam struct rte_flow_action_rss rss;/**< RSS context. */ 28084c406e7SOri Kam uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 28184c406e7SOri Kam uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ 28284c406e7SOri Kam LIST_HEAD(dev_flows, mlx5_flow) dev_flows; 28384c406e7SOri Kam /**< Device flows that are part of the flow. */ 2840ddd1143SYongseok Koh uint64_t actions; 28524663641SYongseok Koh /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 2862720f833SYongseok Koh struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ 28784c406e7SOri Kam }; 2882720f833SYongseok Koh 28984c406e7SOri Kam typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 29084c406e7SOri Kam const struct rte_flow_attr *attr, 29184c406e7SOri Kam const struct rte_flow_item items[], 29284c406e7SOri Kam const struct rte_flow_action actions[], 29384c406e7SOri Kam struct rte_flow_error *error); 29484c406e7SOri Kam typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 29584c406e7SOri Kam (const struct rte_flow_attr *attr, const struct rte_flow_item items[], 29684c406e7SOri Kam const struct rte_flow_action actions[], uint64_t *item_flags, 29784c406e7SOri Kam uint64_t *action_flags, struct rte_flow_error *error); 29884c406e7SOri Kam typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 29984c406e7SOri Kam struct mlx5_flow *dev_flow, 30084c406e7SOri Kam const struct rte_flow_attr *attr, 30184c406e7SOri Kam const struct rte_flow_item items[], 30284c406e7SOri Kam const struct rte_flow_action actions[], 30384c406e7SOri Kam struct rte_flow_error *error); 30484c406e7SOri Kam typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 30584c406e7SOri Kam struct rte_flow_error *error); 30684c406e7SOri Kam typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 30784c406e7SOri Kam struct rte_flow *flow); 30884c406e7SOri Kam typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 30984c406e7SOri Kam struct rte_flow *flow); 310684dafe7SMoti Haimovsky typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 311684dafe7SMoti Haimovsky struct rte_flow *flow, 312684dafe7SMoti Haimovsky const struct rte_flow_action *actions, 313684dafe7SMoti Haimovsky void *data, 314684dafe7SMoti Haimovsky struct rte_flow_error *error); 31584c406e7SOri Kam struct mlx5_flow_driver_ops { 31684c406e7SOri Kam mlx5_flow_validate_t validate; 31784c406e7SOri Kam mlx5_flow_prepare_t prepare; 31884c406e7SOri Kam mlx5_flow_translate_t translate; 31984c406e7SOri Kam mlx5_flow_apply_t apply; 32084c406e7SOri Kam mlx5_flow_remove_t remove; 32184c406e7SOri Kam mlx5_flow_destroy_t destroy; 322684dafe7SMoti Haimovsky mlx5_flow_query_t query; 32384c406e7SOri Kam }; 32484c406e7SOri Kam 32584c406e7SOri Kam /* mlx5_flow.c */ 32684c406e7SOri Kam 327fc2c498cSOri Kam uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, 3280ddd1143SYongseok Koh uint64_t layer_types, 329fc2c498cSOri Kam uint64_t hash_fields); 33084c406e7SOri Kam uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 33184c406e7SOri Kam uint32_t subpriority); 33284c406e7SOri Kam int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 3333e9fa079SDekel Peled const struct rte_flow_attr *attr, 33484c406e7SOri Kam struct rte_flow_error *error); 33584c406e7SOri Kam int mlx5_flow_validate_action_drop(uint64_t action_flags, 3363e9fa079SDekel Peled const struct rte_flow_attr *attr, 33784c406e7SOri Kam struct rte_flow_error *error); 33884c406e7SOri Kam int mlx5_flow_validate_action_flag(uint64_t action_flags, 3393e9fa079SDekel Peled const struct rte_flow_attr *attr, 34084c406e7SOri Kam struct rte_flow_error *error); 34184c406e7SOri Kam int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 34284c406e7SOri Kam uint64_t action_flags, 3433e9fa079SDekel Peled const struct rte_flow_attr *attr, 34484c406e7SOri Kam struct rte_flow_error *error); 34584c406e7SOri Kam int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 34684c406e7SOri Kam uint64_t action_flags, 34784c406e7SOri Kam struct rte_eth_dev *dev, 3483e9fa079SDekel Peled const struct rte_flow_attr *attr, 34984c406e7SOri Kam struct rte_flow_error *error); 35084c406e7SOri Kam int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 35184c406e7SOri Kam uint64_t action_flags, 35284c406e7SOri Kam struct rte_eth_dev *dev, 3533e9fa079SDekel Peled const struct rte_flow_attr *attr, 35484c406e7SOri Kam struct rte_flow_error *error); 35584c406e7SOri Kam int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 35684c406e7SOri Kam const struct rte_flow_attr *attributes, 35784c406e7SOri Kam struct rte_flow_error *error); 3586bd7fbd0SDekel Peled int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 3596bd7fbd0SDekel Peled const uint8_t *mask, 3606bd7fbd0SDekel Peled const uint8_t *nic_mask, 3616bd7fbd0SDekel Peled unsigned int size, 3626bd7fbd0SDekel Peled struct rte_flow_error *error); 36384c406e7SOri Kam int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 36484c406e7SOri Kam uint64_t item_flags, 36584c406e7SOri Kam struct rte_flow_error *error); 36684c406e7SOri Kam int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 36784c406e7SOri Kam uint64_t item_flags, 36884c406e7SOri Kam uint8_t target_protocol, 36984c406e7SOri Kam struct rte_flow_error *error); 37084c406e7SOri Kam int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 371ed4c5247SShahaf Shuler uint64_t item_flags, 37284c406e7SOri Kam struct rte_flow_error *error); 37384c406e7SOri Kam int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 37484c406e7SOri Kam uint64_t item_flags, 37584c406e7SOri Kam struct rte_flow_error *error); 37684c406e7SOri Kam int mlx5_flow_validate_item_mpls(const struct rte_flow_item *item, 37784c406e7SOri Kam uint64_t item_flags, 37884c406e7SOri Kam uint8_t target_protocol, 37984c406e7SOri Kam struct rte_flow_error *error); 38084c406e7SOri Kam int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 38184c406e7SOri Kam uint64_t item_flags, 38284c406e7SOri Kam uint8_t target_protocol, 38392378c2bSMoti Haimovsky const struct rte_flow_item_tcp *flow_mask, 38484c406e7SOri Kam struct rte_flow_error *error); 38584c406e7SOri Kam int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 38684c406e7SOri Kam uint64_t item_flags, 38784c406e7SOri Kam uint8_t target_protocol, 38884c406e7SOri Kam struct rte_flow_error *error); 38984c406e7SOri Kam int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 390ed4c5247SShahaf Shuler uint64_t item_flags, 39184c406e7SOri Kam struct rte_flow_error *error); 39284c406e7SOri Kam int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 39384c406e7SOri Kam uint64_t item_flags, 39484c406e7SOri Kam struct rte_flow_error *error); 39584c406e7SOri Kam int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 39684c406e7SOri Kam uint64_t item_flags, 39784c406e7SOri Kam struct rte_eth_dev *dev, 39884c406e7SOri Kam struct rte_flow_error *error); 39984c406e7SOri Kam 40057123c00SYongseok Koh /* mlx5_flow_tcf.c */ 40157123c00SYongseok Koh 402d53180afSMoti Haimovsky int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx, 403d53180afSMoti Haimovsky unsigned int ifindex, struct rte_flow_error *error); 404d53180afSMoti Haimovsky struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void); 405d53180afSMoti Haimovsky void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx); 40657123c00SYongseok Koh 40784c406e7SOri Kam #endif /* RTE_PMD_MLX5_FLOW_H_ */ 408