xref: /dpdk/drivers/net/mlx5/mlx5_flow.h (revision 49d6465af3e15e257b87b6a7cf41cf474a74ca1a)
184c406e7SOri Kam /* SPDX-License-Identifier: BSD-3-Clause
284c406e7SOri Kam  * Copyright 2018 Mellanox Technologies, Ltd
384c406e7SOri Kam  */
484c406e7SOri Kam 
584c406e7SOri Kam #ifndef RTE_PMD_MLX5_FLOW_H_
684c406e7SOri Kam #define RTE_PMD_MLX5_FLOW_H_
784c406e7SOri Kam 
884c406e7SOri Kam #include <netinet/in.h>
984c406e7SOri Kam #include <sys/queue.h>
1084c406e7SOri Kam #include <stdalign.h>
1184c406e7SOri Kam #include <stdint.h>
1284c406e7SOri Kam #include <string.h>
1384c406e7SOri Kam 
1484c406e7SOri Kam /* Verbs header. */
1584c406e7SOri Kam /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
1684c406e7SOri Kam #ifdef PEDANTIC
1784c406e7SOri Kam #pragma GCC diagnostic ignored "-Wpedantic"
1884c406e7SOri Kam #endif
1984c406e7SOri Kam #include <infiniband/verbs.h>
2084c406e7SOri Kam #ifdef PEDANTIC
2184c406e7SOri Kam #pragma GCC diagnostic error "-Wpedantic"
2284c406e7SOri Kam #endif
2384c406e7SOri Kam 
2484c406e7SOri Kam /* Pattern outer Layer bits. */
2584c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
2684c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
2784c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
2884c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
2984c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
3084c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
3184c406e7SOri Kam 
3284c406e7SOri Kam /* Pattern inner Layer bits. */
3384c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
3484c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
3584c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
3684c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
3784c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
3884c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
3984c406e7SOri Kam 
4084c406e7SOri Kam /* Pattern tunnel Layer bits. */
4184c406e7SOri Kam #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
4284c406e7SOri Kam #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
4384c406e7SOri Kam #define MLX5_FLOW_LAYER_GRE (1u << 14)
4484c406e7SOri Kam #define MLX5_FLOW_LAYER_MPLS (1u << 15)
4584c406e7SOri Kam 
466bd7fbd0SDekel Peled /* General pattern items bits. */
476bd7fbd0SDekel Peled #define MLX5_FLOW_ITEM_METADATA (1u << 16)
486bd7fbd0SDekel Peled 
4984c406e7SOri Kam /* Outer Masks. */
5084c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L3 \
5184c406e7SOri Kam 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
5284c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER_L4 \
5384c406e7SOri Kam 	(MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
5484c406e7SOri Kam #define MLX5_FLOW_LAYER_OUTER \
5584c406e7SOri Kam 	(MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
5684c406e7SOri Kam 	 MLX5_FLOW_LAYER_OUTER_L4)
5784c406e7SOri Kam 
5884c406e7SOri Kam /* Tunnel Masks. */
5984c406e7SOri Kam #define MLX5_FLOW_LAYER_TUNNEL \
6084c406e7SOri Kam 	(MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
6184c406e7SOri Kam 	 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS)
6284c406e7SOri Kam 
6384c406e7SOri Kam /* Inner Masks. */
6484c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L3 \
6584c406e7SOri Kam 	(MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
6684c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER_L4 \
6784c406e7SOri Kam 	(MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
6884c406e7SOri Kam #define MLX5_FLOW_LAYER_INNER \
6984c406e7SOri Kam 	(MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
7084c406e7SOri Kam 	 MLX5_FLOW_LAYER_INNER_L4)
7184c406e7SOri Kam 
7284c406e7SOri Kam /* Actions */
7384c406e7SOri Kam #define MLX5_FLOW_ACTION_DROP (1u << 0)
7484c406e7SOri Kam #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
7584c406e7SOri Kam #define MLX5_FLOW_ACTION_RSS (1u << 2)
7684c406e7SOri Kam #define MLX5_FLOW_ACTION_FLAG (1u << 3)
7784c406e7SOri Kam #define MLX5_FLOW_ACTION_MARK (1u << 4)
7884c406e7SOri Kam #define MLX5_FLOW_ACTION_COUNT (1u << 5)
7957123c00SYongseok Koh #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
8057123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
8157123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
8257123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
8357123c00SYongseok Koh #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
842ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
852ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
862ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
872ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
882ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
892ed2fe5fSXiaoyu Min #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
9031fda518SYongseok Koh #define MLX5_FLOW_ACTION_JUMP (1u << 17)
91a7cb5bcdSXiaoyu Min #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
92a7cb5bcdSXiaoyu Min #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
9376046778SXiaoyu Min #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
9476046778SXiaoyu Min #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
9534d41b7aSDekel Peled #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
96*49d6465aSDekel Peled #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
9784c406e7SOri Kam 
9884c406e7SOri Kam #define MLX5_FLOW_FATE_ACTIONS \
9984c406e7SOri Kam 	(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)
10084c406e7SOri Kam 
10184c406e7SOri Kam #ifndef IPPROTO_MPLS
10284c406e7SOri Kam #define IPPROTO_MPLS 137
10384c406e7SOri Kam #endif
10484c406e7SOri Kam 
105fc2c498cSOri Kam /* UDP port numbers for VxLAN. */
106fc2c498cSOri Kam #define MLX5_UDP_PORT_VXLAN 4789
107fc2c498cSOri Kam #define MLX5_UDP_PORT_VXLAN_GPE 4790
108fc2c498cSOri Kam 
10984c406e7SOri Kam /* Priority reserved for default flows. */
11084c406e7SOri Kam #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
11184c406e7SOri Kam 
11284c406e7SOri Kam /*
11384c406e7SOri Kam  * Number of sub priorities.
11484c406e7SOri Kam  * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
11584c406e7SOri Kam  * matching on the NIC (firmware dependent) L4 most have the higher priority
11684c406e7SOri Kam  * followed by L3 and ending with L2.
11784c406e7SOri Kam  */
11884c406e7SOri Kam #define MLX5_PRIORITY_MAP_L2 2
11984c406e7SOri Kam #define MLX5_PRIORITY_MAP_L3 1
12084c406e7SOri Kam #define MLX5_PRIORITY_MAP_L4 0
12184c406e7SOri Kam #define MLX5_PRIORITY_MAP_MAX 3
12284c406e7SOri Kam 
123fc2c498cSOri Kam /* Valid layer type for IPV4 RSS. */
124fc2c498cSOri Kam #define MLX5_IPV4_LAYER_TYPES \
125fc2c498cSOri Kam 	(ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
126fc2c498cSOri Kam 	 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
127fc2c498cSOri Kam 	 ETH_RSS_NONFRAG_IPV4_OTHER)
128fc2c498cSOri Kam 
129fc2c498cSOri Kam /* IBV hash source bits  for IPV4. */
130fc2c498cSOri Kam #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
131fc2c498cSOri Kam 
132fc2c498cSOri Kam /* Valid layer type for IPV6 RSS. */
133fc2c498cSOri Kam #define MLX5_IPV6_LAYER_TYPES \
134fc2c498cSOri Kam 	(ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
135fc2c498cSOri Kam 	 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX  | ETH_RSS_IPV6_TCP_EX | \
136fc2c498cSOri Kam 	 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
137fc2c498cSOri Kam 
138fc2c498cSOri Kam /* IBV hash source bits  for IPV6. */
139fc2c498cSOri Kam #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
140fc2c498cSOri Kam 
1413d694341SOri Kam /* Max number of actions per DV flow. */
1423d694341SOri Kam #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
1433d694341SOri Kam 
1440c76d1c9SYongseok Koh enum mlx5_flow_drv_type {
1450c76d1c9SYongseok Koh 	MLX5_FLOW_TYPE_MIN,
1460c76d1c9SYongseok Koh 	MLX5_FLOW_TYPE_DV,
14757123c00SYongseok Koh 	MLX5_FLOW_TYPE_TCF,
1480c76d1c9SYongseok Koh 	MLX5_FLOW_TYPE_VERBS,
1490c76d1c9SYongseok Koh 	MLX5_FLOW_TYPE_MAX,
1500c76d1c9SYongseok Koh };
1510c76d1c9SYongseok Koh 
152865a0c15SOri Kam /* Matcher PRM representation */
153865a0c15SOri Kam struct mlx5_flow_dv_match_params {
154865a0c15SOri Kam 	size_t size;
155865a0c15SOri Kam 	/**< Size of match value. Do NOT split size and key! */
156865a0c15SOri Kam 	uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
157865a0c15SOri Kam 	/**< Matcher value. This value is used as the mask or as a key. */
158865a0c15SOri Kam };
159865a0c15SOri Kam 
160d02cb069SOri Kam #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
161d02cb069SOri Kam 
162865a0c15SOri Kam /* Matcher structure. */
163865a0c15SOri Kam struct mlx5_flow_dv_matcher {
164865a0c15SOri Kam 	LIST_ENTRY(mlx5_flow_dv_matcher) next;
165865a0c15SOri Kam 	/* Pointer to the next element. */
166865a0c15SOri Kam 	rte_atomic32_t refcnt; /**< Reference counter. */
167865a0c15SOri Kam 	void *matcher_object; /**< Pointer to DV matcher */
168865a0c15SOri Kam 	uint16_t crc; /**< CRC of key. */
169865a0c15SOri Kam 	uint16_t priority; /**< Priority of matcher. */
170865a0c15SOri Kam 	uint8_t egress; /**< Egress matcher. */
171865a0c15SOri Kam 	struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
172865a0c15SOri Kam };
173865a0c15SOri Kam 
174865a0c15SOri Kam /* DV flows structure. */
175865a0c15SOri Kam struct mlx5_flow_dv {
176865a0c15SOri Kam 	uint64_t hash_fields; /**< Fields that participate in the hash. */
177865a0c15SOri Kam 	struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
178865a0c15SOri Kam 	/* Flow DV api: */
179865a0c15SOri Kam 	struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
180865a0c15SOri Kam 	struct mlx5_flow_dv_match_params value;
181865a0c15SOri Kam 	/**< Holds the value that the packet is compared to. */
182865a0c15SOri Kam 	struct ibv_flow *flow; /**< Installed flow. */
183d02cb069SOri Kam #ifdef HAVE_IBV_FLOW_DV_SUPPORT
184d02cb069SOri Kam 	struct mlx5dv_flow_action_attr actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
185d02cb069SOri Kam 	/**< Action list. */
18634d41b7aSDekel Peled 	struct ibv_flow_action *encap_decap_verbs_action;
18734d41b7aSDekel Peled 	/**< Verbs encap/decap object. */
188d02cb069SOri Kam #endif
189d02cb069SOri Kam 	int actions_n; /**< number of actions. */
190865a0c15SOri Kam };
191865a0c15SOri Kam 
19257123c00SYongseok Koh /** Linux TC flower driver for E-Switch flow. */
19357123c00SYongseok Koh struct mlx5_flow_tcf {
19457123c00SYongseok Koh 	struct nlmsghdr *nlh;
19557123c00SYongseok Koh 	struct tcmsg *tcm;
19657123c00SYongseok Koh };
19757123c00SYongseok Koh 
19884c406e7SOri Kam /* Verbs specification header. */
19984c406e7SOri Kam struct ibv_spec_header {
20084c406e7SOri Kam 	enum ibv_flow_spec_type type;
20184c406e7SOri Kam 	uint16_t size;
20284c406e7SOri Kam };
20384c406e7SOri Kam 
20484c406e7SOri Kam /** Handles information leading to a drop fate. */
20584c406e7SOri Kam struct mlx5_flow_verbs {
20684c406e7SOri Kam 	LIST_ENTRY(mlx5_flow_verbs) next;
20784c406e7SOri Kam 	unsigned int size; /**< Size of the attribute. */
20884c406e7SOri Kam 	struct {
20984c406e7SOri Kam 		struct ibv_flow_attr *attr;
21084c406e7SOri Kam 		/**< Pointer to the Specification buffer. */
21184c406e7SOri Kam 		uint8_t *specs; /**< Pointer to the specifications. */
21284c406e7SOri Kam 	};
21384c406e7SOri Kam 	struct ibv_flow *flow; /**< Verbs flow pointer. */
21484c406e7SOri Kam 	struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
21584c406e7SOri Kam 	uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
21684c406e7SOri Kam };
21784c406e7SOri Kam 
21884c406e7SOri Kam /** Device flow structure. */
21984c406e7SOri Kam struct mlx5_flow {
22084c406e7SOri Kam 	LIST_ENTRY(mlx5_flow) next;
22184c406e7SOri Kam 	struct rte_flow *flow; /**< Pointer to the main flow. */
2220ddd1143SYongseok Koh 	uint64_t layers;
22324663641SYongseok Koh 	/**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
22484c406e7SOri Kam 	union {
225c4d9b9f7SOri Kam #ifdef HAVE_IBV_FLOW_DV_SUPPORT
226865a0c15SOri Kam 		struct mlx5_flow_dv dv;
227c4d9b9f7SOri Kam #endif
22857123c00SYongseok Koh 		struct mlx5_flow_tcf tcf;
229865a0c15SOri Kam 		struct mlx5_flow_verbs verbs;
23084c406e7SOri Kam 	};
23184c406e7SOri Kam };
23284c406e7SOri Kam 
23384c406e7SOri Kam /* Counters information. */
23484c406e7SOri Kam struct mlx5_flow_counter {
23584c406e7SOri Kam 	LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */
23684c406e7SOri Kam 	uint32_t shared:1; /**< Share counter ID with other flow rules. */
23784c406e7SOri Kam 	uint32_t ref_cnt:31; /**< Reference counter. */
23884c406e7SOri Kam 	uint32_t id; /**< Counter ID. */
239db48f9dbSViacheslav Ovsiienko #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
24084c406e7SOri Kam 	struct ibv_counter_set *cs; /**< Holds the counters for the rule. */
241db48f9dbSViacheslav Ovsiienko #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
242db48f9dbSViacheslav Ovsiienko 	struct ibv_counters *cs; /**< Holds the counters for the rule. */
243db48f9dbSViacheslav Ovsiienko #endif
24484c406e7SOri Kam 	uint64_t hits; /**< Number of packets matched by the rule. */
24584c406e7SOri Kam 	uint64_t bytes; /**< Number of bytes matched by the rule. */
24684c406e7SOri Kam };
24784c406e7SOri Kam 
24884c406e7SOri Kam /* Flow structure. */
24984c406e7SOri Kam struct rte_flow {
25084c406e7SOri Kam 	TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
2510c76d1c9SYongseok Koh 	enum mlx5_flow_drv_type drv_type; /**< Drvier type. */
25284c406e7SOri Kam 	struct mlx5_flow_counter *counter; /**< Holds flow counter. */
25384c406e7SOri Kam 	struct rte_flow_action_rss rss;/**< RSS context. */
25484c406e7SOri Kam 	uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
25584c406e7SOri Kam 	uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
25684c406e7SOri Kam 	LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
25784c406e7SOri Kam 	/**< Device flows that are part of the flow. */
2580ddd1143SYongseok Koh 	uint64_t actions;
25924663641SYongseok Koh 	/**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
2602720f833SYongseok Koh 	struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
26184c406e7SOri Kam };
2622720f833SYongseok Koh 
26384c406e7SOri Kam typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
26484c406e7SOri Kam 				    const struct rte_flow_attr *attr,
26584c406e7SOri Kam 				    const struct rte_flow_item items[],
26684c406e7SOri Kam 				    const struct rte_flow_action actions[],
26784c406e7SOri Kam 				    struct rte_flow_error *error);
26884c406e7SOri Kam typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
26984c406e7SOri Kam 	(const struct rte_flow_attr *attr, const struct rte_flow_item items[],
27084c406e7SOri Kam 	 const struct rte_flow_action actions[], uint64_t *item_flags,
27184c406e7SOri Kam 	 uint64_t *action_flags, struct rte_flow_error *error);
27284c406e7SOri Kam typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
27384c406e7SOri Kam 				     struct mlx5_flow *dev_flow,
27484c406e7SOri Kam 				     const struct rte_flow_attr *attr,
27584c406e7SOri Kam 				     const struct rte_flow_item items[],
27684c406e7SOri Kam 				     const struct rte_flow_action actions[],
27784c406e7SOri Kam 				     struct rte_flow_error *error);
27884c406e7SOri Kam typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
27984c406e7SOri Kam 				 struct rte_flow_error *error);
28084c406e7SOri Kam typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
28184c406e7SOri Kam 				   struct rte_flow *flow);
28284c406e7SOri Kam typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
28384c406e7SOri Kam 				    struct rte_flow *flow);
284684dafe7SMoti Haimovsky typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
285684dafe7SMoti Haimovsky 				 struct rte_flow *flow,
286684dafe7SMoti Haimovsky 				 const struct rte_flow_action *actions,
287684dafe7SMoti Haimovsky 				 void *data,
288684dafe7SMoti Haimovsky 				 struct rte_flow_error *error);
28984c406e7SOri Kam struct mlx5_flow_driver_ops {
29084c406e7SOri Kam 	mlx5_flow_validate_t validate;
29184c406e7SOri Kam 	mlx5_flow_prepare_t prepare;
29284c406e7SOri Kam 	mlx5_flow_translate_t translate;
29384c406e7SOri Kam 	mlx5_flow_apply_t apply;
29484c406e7SOri Kam 	mlx5_flow_remove_t remove;
29584c406e7SOri Kam 	mlx5_flow_destroy_t destroy;
296684dafe7SMoti Haimovsky 	mlx5_flow_query_t query;
29784c406e7SOri Kam };
29884c406e7SOri Kam 
29984c406e7SOri Kam /* mlx5_flow.c */
30084c406e7SOri Kam 
301fc2c498cSOri Kam uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
3020ddd1143SYongseok Koh 				     uint64_t layer_types,
303fc2c498cSOri Kam 				     uint64_t hash_fields);
30484c406e7SOri Kam uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
30584c406e7SOri Kam 				   uint32_t subpriority);
30684c406e7SOri Kam int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
3073e9fa079SDekel Peled 				    const struct rte_flow_attr *attr,
30884c406e7SOri Kam 				    struct rte_flow_error *error);
30984c406e7SOri Kam int mlx5_flow_validate_action_drop(uint64_t action_flags,
3103e9fa079SDekel Peled 				   const struct rte_flow_attr *attr,
31184c406e7SOri Kam 				   struct rte_flow_error *error);
31284c406e7SOri Kam int mlx5_flow_validate_action_flag(uint64_t action_flags,
3133e9fa079SDekel Peled 				   const struct rte_flow_attr *attr,
31484c406e7SOri Kam 				   struct rte_flow_error *error);
31584c406e7SOri Kam int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
31684c406e7SOri Kam 				   uint64_t action_flags,
3173e9fa079SDekel Peled 				   const struct rte_flow_attr *attr,
31884c406e7SOri Kam 				   struct rte_flow_error *error);
31984c406e7SOri Kam int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
32084c406e7SOri Kam 				    uint64_t action_flags,
32184c406e7SOri Kam 				    struct rte_eth_dev *dev,
3223e9fa079SDekel Peled 				    const struct rte_flow_attr *attr,
32384c406e7SOri Kam 				    struct rte_flow_error *error);
32484c406e7SOri Kam int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
32584c406e7SOri Kam 				  uint64_t action_flags,
32684c406e7SOri Kam 				  struct rte_eth_dev *dev,
3273e9fa079SDekel Peled 				  const struct rte_flow_attr *attr,
32884c406e7SOri Kam 				  struct rte_flow_error *error);
32984c406e7SOri Kam int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
33084c406e7SOri Kam 				  const struct rte_flow_attr *attributes,
33184c406e7SOri Kam 				  struct rte_flow_error *error);
3326bd7fbd0SDekel Peled int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
3336bd7fbd0SDekel Peled 			      const uint8_t *mask,
3346bd7fbd0SDekel Peled 			      const uint8_t *nic_mask,
3356bd7fbd0SDekel Peled 			      unsigned int size,
3366bd7fbd0SDekel Peled 			      struct rte_flow_error *error);
33784c406e7SOri Kam int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
33884c406e7SOri Kam 				uint64_t item_flags,
33984c406e7SOri Kam 				struct rte_flow_error *error);
34084c406e7SOri Kam int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
34184c406e7SOri Kam 				uint64_t item_flags,
34284c406e7SOri Kam 				uint8_t target_protocol,
34384c406e7SOri Kam 				struct rte_flow_error *error);
34484c406e7SOri Kam int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
345ed4c5247SShahaf Shuler 				 uint64_t item_flags,
34684c406e7SOri Kam 				 struct rte_flow_error *error);
34784c406e7SOri Kam int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
34884c406e7SOri Kam 				 uint64_t item_flags,
34984c406e7SOri Kam 				 struct rte_flow_error *error);
35084c406e7SOri Kam int mlx5_flow_validate_item_mpls(const struct rte_flow_item *item,
35184c406e7SOri Kam 				 uint64_t item_flags,
35284c406e7SOri Kam 				 uint8_t target_protocol,
35384c406e7SOri Kam 				 struct rte_flow_error *error);
35484c406e7SOri Kam int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
35584c406e7SOri Kam 				uint64_t item_flags,
35684c406e7SOri Kam 				uint8_t target_protocol,
35792378c2bSMoti Haimovsky 				const struct rte_flow_item_tcp *flow_mask,
35884c406e7SOri Kam 				struct rte_flow_error *error);
35984c406e7SOri Kam int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
36084c406e7SOri Kam 				uint64_t item_flags,
36184c406e7SOri Kam 				uint8_t target_protocol,
36284c406e7SOri Kam 				struct rte_flow_error *error);
36384c406e7SOri Kam int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
364ed4c5247SShahaf Shuler 				 uint64_t item_flags,
36584c406e7SOri Kam 				 struct rte_flow_error *error);
36684c406e7SOri Kam int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
36784c406e7SOri Kam 				  uint64_t item_flags,
36884c406e7SOri Kam 				  struct rte_flow_error *error);
36984c406e7SOri Kam int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
37084c406e7SOri Kam 				      uint64_t item_flags,
37184c406e7SOri Kam 				      struct rte_eth_dev *dev,
37284c406e7SOri Kam 				      struct rte_flow_error *error);
37384c406e7SOri Kam 
37457123c00SYongseok Koh /* mlx5_flow_tcf.c */
37557123c00SYongseok Koh 
376d53180afSMoti Haimovsky int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx,
377d53180afSMoti Haimovsky 		       unsigned int ifindex, struct rte_flow_error *error);
378d53180afSMoti Haimovsky struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void);
379d53180afSMoti Haimovsky void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx);
38057123c00SYongseok Koh 
38184c406e7SOri Kam #endif /* RTE_PMD_MLX5_FLOW_H_ */
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