1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 13 #include <ethdev_driver.h> 14 #include <rte_bus_pci.h> 15 #include <rte_mbuf.h> 16 #include <rte_common.h> 17 #include <rte_interrupts.h> 18 #include <rte_malloc.h> 19 #include <rte_string_fns.h> 20 #include <rte_rwlock.h> 21 #include <rte_cycles.h> 22 23 #include <mlx5_malloc.h> 24 25 #include "mlx5_rxtx.h" 26 #include "mlx5_autoconf.h" 27 28 /** 29 * Get the interface index from device name. 30 * 31 * @param[in] dev 32 * Pointer to Ethernet device. 33 * 34 * @return 35 * Nonzero interface index on success, zero otherwise and rte_errno is set. 36 */ 37 unsigned int 38 mlx5_ifindex(const struct rte_eth_dev *dev) 39 { 40 struct mlx5_priv *priv = dev->data->dev_private; 41 unsigned int ifindex; 42 43 MLX5_ASSERT(priv); 44 MLX5_ASSERT(priv->if_index); 45 if (priv->master && priv->sh->bond.ifindex > 0) 46 ifindex = priv->sh->bond.ifindex; 47 else 48 ifindex = priv->if_index; 49 if (!ifindex) 50 rte_errno = ENXIO; 51 return ifindex; 52 } 53 54 /** 55 * DPDK callback for Ethernet device configuration. 56 * 57 * @param dev 58 * Pointer to Ethernet device structure. 59 * 60 * @return 61 * 0 on success, a negative errno value otherwise and rte_errno is set. 62 */ 63 int 64 mlx5_dev_configure(struct rte_eth_dev *dev) 65 { 66 struct mlx5_priv *priv = dev->data->dev_private; 67 unsigned int rxqs_n = dev->data->nb_rx_queues; 68 unsigned int txqs_n = dev->data->nb_tx_queues; 69 const uint8_t use_app_rss_key = 70 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; 71 int ret = 0; 72 73 if (use_app_rss_key && 74 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len != 75 MLX5_RSS_HASH_KEY_LEN)) { 76 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long", 77 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN)); 78 rte_errno = EINVAL; 79 return -rte_errno; 80 } 81 priv->rss_conf.rss_key = 82 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE, 83 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY); 84 if (!priv->rss_conf.rss_key) { 85 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)", 86 dev->data->port_id, rxqs_n); 87 rte_errno = ENOMEM; 88 return -rte_errno; 89 } 90 91 if ((dev->data->dev_conf.txmode.offloads & 92 DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP) && 93 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) { 94 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag", 95 dev->data->port_id); 96 return -rte_errno; 97 } 98 memcpy(priv->rss_conf.rss_key, 99 use_app_rss_key ? 100 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key : 101 rss_hash_default_key, 102 MLX5_RSS_HASH_KEY_LEN); 103 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN; 104 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf; 105 priv->rxqs = (void *)dev->data->rx_queues; 106 priv->txqs = (void *)dev->data->tx_queues; 107 if (txqs_n != priv->txqs_n) { 108 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u", 109 dev->data->port_id, priv->txqs_n, txqs_n); 110 priv->txqs_n = txqs_n; 111 } 112 if (rxqs_n > priv->config.ind_table_max_size) { 113 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 114 dev->data->port_id, rxqs_n); 115 rte_errno = EINVAL; 116 return -rte_errno; 117 } 118 if (rxqs_n != priv->rxqs_n) { 119 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 120 dev->data->port_id, priv->rxqs_n, rxqs_n); 121 priv->rxqs_n = rxqs_n; 122 } 123 priv->skip_default_rss_reta = 0; 124 ret = mlx5_proc_priv_init(dev); 125 if (ret) 126 return ret; 127 return 0; 128 } 129 130 /** 131 * Configure default RSS reta. 132 * 133 * @param dev 134 * Pointer to Ethernet device structure. 135 * 136 * @return 137 * 0 on success, a negative errno value otherwise and rte_errno is set. 138 */ 139 int 140 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev) 141 { 142 struct mlx5_priv *priv = dev->data->dev_private; 143 unsigned int rxqs_n = dev->data->nb_rx_queues; 144 unsigned int i; 145 unsigned int j; 146 unsigned int reta_idx_n; 147 int ret = 0; 148 unsigned int *rss_queue_arr = NULL; 149 unsigned int rss_queue_n = 0; 150 151 if (priv->skip_default_rss_reta) 152 return ret; 153 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0, 154 SOCKET_ID_ANY); 155 if (!rss_queue_arr) { 156 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)", 157 dev->data->port_id, rxqs_n); 158 rte_errno = ENOMEM; 159 return -rte_errno; 160 } 161 for (i = 0, j = 0; i < rxqs_n; i++) { 162 struct mlx5_rxq_data *rxq_data; 163 struct mlx5_rxq_ctrl *rxq_ctrl; 164 165 rxq_data = (*priv->rxqs)[i]; 166 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); 167 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) 168 rss_queue_arr[j++] = i; 169 } 170 rss_queue_n = j; 171 if (rss_queue_n > priv->config.ind_table_max_size) { 172 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 173 dev->data->port_id, rss_queue_n); 174 rte_errno = EINVAL; 175 mlx5_free(rss_queue_arr); 176 return -rte_errno; 177 } 178 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 179 dev->data->port_id, priv->rxqs_n, rxqs_n); 180 priv->rxqs_n = rxqs_n; 181 /* 182 * If the requested number of RX queues is not a power of two, 183 * use the maximum indirection table size for better balancing. 184 * The result is always rounded to the next power of two. 185 */ 186 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ? 187 priv->config.ind_table_max_size : 188 rss_queue_n)); 189 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n); 190 if (ret) { 191 mlx5_free(rss_queue_arr); 192 return ret; 193 } 194 /* 195 * When the number of RX queues is not a power of two, 196 * the remaining table entries are padded with reused WQs 197 * and hashes are not spread uniformly. 198 */ 199 for (i = 0, j = 0; (i != reta_idx_n); ++i) { 200 (*priv->reta_idx)[i] = rss_queue_arr[j]; 201 if (++j == rss_queue_n) 202 j = 0; 203 } 204 mlx5_free(rss_queue_arr); 205 return ret; 206 } 207 208 /** 209 * Sets default tuning parameters. 210 * 211 * @param dev 212 * Pointer to Ethernet device. 213 * @param[out] info 214 * Info structure output buffer. 215 */ 216 static void 217 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 218 { 219 struct mlx5_priv *priv = dev->data->dev_private; 220 221 /* Minimum CPU utilization. */ 222 info->default_rxportconf.ring_size = 256; 223 info->default_txportconf.ring_size = 256; 224 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; 225 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; 226 if ((priv->link_speed_capa & ETH_LINK_SPEED_200G) | 227 (priv->link_speed_capa & ETH_LINK_SPEED_100G)) { 228 info->default_rxportconf.nb_queues = 16; 229 info->default_txportconf.nb_queues = 16; 230 if (dev->data->nb_rx_queues > 2 || 231 dev->data->nb_tx_queues > 2) { 232 /* Max Throughput. */ 233 info->default_rxportconf.ring_size = 2048; 234 info->default_txportconf.ring_size = 2048; 235 } 236 } else { 237 info->default_rxportconf.nb_queues = 8; 238 info->default_txportconf.nb_queues = 8; 239 if (dev->data->nb_rx_queues > 2 || 240 dev->data->nb_tx_queues > 2) { 241 /* Max Throughput. */ 242 info->default_rxportconf.ring_size = 4096; 243 info->default_txportconf.ring_size = 4096; 244 } 245 } 246 } 247 248 /** 249 * Sets tx mbuf limiting parameters. 250 * 251 * @param dev 252 * Pointer to Ethernet device. 253 * @param[out] info 254 * Info structure output buffer. 255 */ 256 static void 257 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 258 { 259 struct mlx5_priv *priv = dev->data->dev_private; 260 struct mlx5_dev_config *config = &priv->config; 261 unsigned int inlen; 262 uint16_t nb_max; 263 264 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ? 265 MLX5_SEND_DEF_INLINE_LEN : 266 (unsigned int)config->txq_inline_max; 267 MLX5_ASSERT(config->txq_inline_min >= 0); 268 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min); 269 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX + 270 MLX5_ESEG_MIN_INLINE_SIZE - 271 MLX5_WQE_CSEG_SIZE - 272 MLX5_WQE_ESEG_SIZE - 273 MLX5_WQE_DSEG_SIZE * 2); 274 nb_max = (MLX5_WQE_SIZE_MAX + 275 MLX5_ESEG_MIN_INLINE_SIZE - 276 MLX5_WQE_CSEG_SIZE - 277 MLX5_WQE_ESEG_SIZE - 278 MLX5_WQE_DSEG_SIZE - 279 inlen) / MLX5_WSEG_SIZE; 280 info->tx_desc_lim.nb_seg_max = nb_max; 281 info->tx_desc_lim.nb_mtu_seg_max = nb_max; 282 } 283 284 /** 285 * DPDK callback to get information about the device. 286 * 287 * @param dev 288 * Pointer to Ethernet device structure. 289 * @param[out] info 290 * Info structure output buffer. 291 */ 292 int 293 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 294 { 295 struct mlx5_priv *priv = dev->data->dev_private; 296 struct mlx5_dev_config *config = &priv->config; 297 unsigned int max; 298 299 /* FIXME: we should ask the device for these values. */ 300 info->min_rx_bufsize = 32; 301 info->max_rx_pktlen = 65536; 302 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; 303 /* 304 * Since we need one CQ per QP, the limit is the minimum number 305 * between the two values. 306 */ 307 max = RTE_MIN(priv->sh->device_attr.max_cq, 308 priv->sh->device_attr.max_qp); 309 /* max_rx_queues is uint16_t. */ 310 max = RTE_MIN(max, (unsigned int)UINT16_MAX); 311 info->max_rx_queues = max; 312 info->max_tx_queues = max; 313 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; 314 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); 315 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; 316 info->rx_seg_capa.multi_pools = !config->mprq.enabled; 317 info->rx_seg_capa.offset_allowed = !config->mprq.enabled; 318 info->rx_seg_capa.offset_align_log2 = 0; 319 info->rx_offload_capa = (mlx5_get_rx_port_offloads() | 320 info->rx_queue_offload_capa); 321 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); 322 info->if_index = mlx5_ifindex(dev); 323 info->reta_size = priv->reta_idx_n ? 324 priv->reta_idx_n : config->ind_table_max_size; 325 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; 326 info->speed_capa = priv->link_speed_capa; 327 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; 328 mlx5_set_default_params(dev, info); 329 mlx5_set_txlimit_params(dev, info); 330 info->switch_info.name = dev->data->name; 331 info->switch_info.domain_id = priv->domain_id; 332 info->switch_info.port_id = priv->representor_id; 333 if (priv->representor) { 334 uint16_t port_id; 335 336 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 337 struct mlx5_priv *opriv = 338 rte_eth_devices[port_id].data->dev_private; 339 340 if (!opriv || 341 opriv->representor || 342 opriv->sh != priv->sh || 343 opriv->domain_id != priv->domain_id) 344 continue; 345 /* 346 * Override switch name with that of the master 347 * device. 348 */ 349 info->switch_info.name = opriv->dev_data->name; 350 break; 351 } 352 } 353 return 0; 354 } 355 356 /** 357 * Calculate representor ID from port switch info. 358 * 359 * Uint16 representor ID bits definition: 360 * pf: 2 361 * type: 2 362 * vf/sf: 12 363 * 364 * @param info 365 * Port switch info. 366 * 367 * @return 368 * Encoded representor ID. 369 */ 370 uint16_t 371 mlx5_representor_id_encode(const struct mlx5_switch_info *info) 372 { 373 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF; 374 uint16_t repr = info->port_name; 375 376 if (info->representor == 0) 377 return UINT16_MAX; 378 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF) 379 type = RTE_ETH_REPRESENTOR_SF; 380 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) 381 repr = UINT16_MAX; 382 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr); 383 } 384 385 /** 386 * DPDK callback to get information about representor. 387 * 388 * Representor ID bits definition: 389 * vf/sf: 12 390 * type: 2 391 * pf: 2 392 * 393 * @param dev 394 * Pointer to Ethernet device structure. 395 * @param[out] info 396 * Nullable info structure output buffer. 397 * 398 * @return 399 * negative on error, or the number of representor ranges. 400 */ 401 int 402 mlx5_representor_info_get(struct rte_eth_dev *dev, 403 struct rte_eth_representor_info *info) 404 { 405 struct mlx5_priv *priv = dev->data->dev_private; 406 int n_type = 3; /* Number of representor types, VF, HPF and SF. */ 407 int n_pf = 2; /* Number of PFs. */ 408 int i = 0, pf; 409 410 if (info == NULL) 411 goto out; 412 info->controller = 0; 413 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0; 414 for (pf = 0; pf < n_pf; ++pf) { 415 /* VF range. */ 416 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 417 info->ranges[i].controller = 0; 418 info->ranges[i].pf = pf; 419 info->ranges[i].vf = 0; 420 info->ranges[i].id_base = 421 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 422 info->ranges[i].id_end = 423 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 424 snprintf(info->ranges[i].name, 425 sizeof(info->ranges[i].name), "pf%dvf", pf); 426 i++; 427 /* HPF range. */ 428 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 429 info->ranges[i].controller = 0; 430 info->ranges[i].pf = pf; 431 info->ranges[i].vf = UINT16_MAX; 432 info->ranges[i].id_base = 433 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 434 info->ranges[i].id_end = 435 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 436 snprintf(info->ranges[i].name, 437 sizeof(info->ranges[i].name), "pf%dvf", pf); 438 i++; 439 /* SF range. */ 440 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 441 info->ranges[i].controller = 0; 442 info->ranges[i].pf = pf; 443 info->ranges[i].vf = 0; 444 info->ranges[i].id_base = 445 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 446 info->ranges[i].id_end = 447 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 448 snprintf(info->ranges[i].name, 449 sizeof(info->ranges[i].name), "pf%dsf", pf); 450 i++; 451 } 452 out: 453 return n_type * n_pf; 454 } 455 456 /** 457 * Get firmware version of a device. 458 * 459 * @param dev 460 * Ethernet device port. 461 * @param fw_ver 462 * String output allocated by caller. 463 * @param fw_size 464 * Size of the output string, including terminating null byte. 465 * 466 * @return 467 * 0 on success, or the size of the non truncated string if too big. 468 */ 469 int 470 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) 471 { 472 struct mlx5_priv *priv = dev->data->dev_private; 473 struct mlx5_dev_attr *attr = &priv->sh->device_attr; 474 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1; 475 476 if (fw_size < size) 477 return size; 478 if (fw_ver != NULL) 479 strlcpy(fw_ver, attr->fw_ver, fw_size); 480 return 0; 481 } 482 483 /** 484 * Get supported packet types. 485 * 486 * @param dev 487 * Pointer to Ethernet device structure. 488 * 489 * @return 490 * A pointer to the supported Packet types array. 491 */ 492 const uint32_t * 493 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev) 494 { 495 static const uint32_t ptypes[] = { 496 /* refers to rxq_cq_to_pkt_type() */ 497 RTE_PTYPE_L2_ETHER, 498 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 499 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 500 RTE_PTYPE_L4_NONFRAG, 501 RTE_PTYPE_L4_FRAG, 502 RTE_PTYPE_L4_TCP, 503 RTE_PTYPE_L4_UDP, 504 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 505 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 506 RTE_PTYPE_INNER_L4_NONFRAG, 507 RTE_PTYPE_INNER_L4_FRAG, 508 RTE_PTYPE_INNER_L4_TCP, 509 RTE_PTYPE_INNER_L4_UDP, 510 RTE_PTYPE_UNKNOWN 511 }; 512 513 if (dev->rx_pkt_burst == mlx5_rx_burst || 514 dev->rx_pkt_burst == mlx5_rx_burst_mprq || 515 dev->rx_pkt_burst == mlx5_rx_burst_vec || 516 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec) 517 return ptypes; 518 return NULL; 519 } 520 521 /** 522 * DPDK callback to change the MTU. 523 * 524 * @param dev 525 * Pointer to Ethernet device structure. 526 * @param in_mtu 527 * New MTU. 528 * 529 * @return 530 * 0 on success, a negative errno value otherwise and rte_errno is set. 531 */ 532 int 533 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 534 { 535 struct mlx5_priv *priv = dev->data->dev_private; 536 uint16_t kern_mtu = 0; 537 int ret; 538 539 ret = mlx5_get_mtu(dev, &kern_mtu); 540 if (ret) 541 return ret; 542 /* Set kernel interface MTU first. */ 543 ret = mlx5_set_mtu(dev, mtu); 544 if (ret) 545 return ret; 546 ret = mlx5_get_mtu(dev, &kern_mtu); 547 if (ret) 548 return ret; 549 if (kern_mtu == mtu) { 550 priv->mtu = mtu; 551 DRV_LOG(DEBUG, "port %u adapter MTU set to %u", 552 dev->data->port_id, mtu); 553 return 0; 554 } 555 rte_errno = EAGAIN; 556 return -rte_errno; 557 } 558 559 /** 560 * Configure the RX function to use. 561 * 562 * @param dev 563 * Pointer to private data structure. 564 * 565 * @return 566 * Pointer to selected Rx burst function. 567 */ 568 eth_rx_burst_t 569 mlx5_select_rx_function(struct rte_eth_dev *dev) 570 { 571 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst; 572 573 MLX5_ASSERT(dev != NULL); 574 if (mlx5_check_vec_rx_support(dev) > 0) { 575 if (mlx5_mprq_enabled(dev)) { 576 rx_pkt_burst = mlx5_rx_burst_mprq_vec; 577 DRV_LOG(DEBUG, "port %u selected vectorized" 578 " MPRQ Rx function", dev->data->port_id); 579 } else { 580 rx_pkt_burst = mlx5_rx_burst_vec; 581 DRV_LOG(DEBUG, "port %u selected vectorized" 582 " SPRQ Rx function", dev->data->port_id); 583 } 584 } else if (mlx5_mprq_enabled(dev)) { 585 rx_pkt_burst = mlx5_rx_burst_mprq; 586 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function", 587 dev->data->port_id); 588 } else { 589 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function", 590 dev->data->port_id); 591 } 592 return rx_pkt_burst; 593 } 594 595 /** 596 * Get the E-Switch parameters by port id. 597 * 598 * @param[in] port 599 * Device port id. 600 * @param[in] valid 601 * Device port id is valid, skip check. This flag is useful 602 * when trials are performed from probing and device is not 603 * flagged as valid yet (in attaching process). 604 * @param[out] es_domain_id 605 * E-Switch domain id. 606 * @param[out] es_port_id 607 * The port id of the port in the E-Switch. 608 * 609 * @return 610 * pointer to device private data structure containing data needed 611 * on success, NULL otherwise and rte_errno is set. 612 */ 613 struct mlx5_priv * 614 mlx5_port_to_eswitch_info(uint16_t port, bool valid) 615 { 616 struct rte_eth_dev *dev; 617 struct mlx5_priv *priv; 618 619 if (port >= RTE_MAX_ETHPORTS) { 620 rte_errno = EINVAL; 621 return NULL; 622 } 623 if (!valid && !rte_eth_dev_is_valid_port(port)) { 624 rte_errno = ENODEV; 625 return NULL; 626 } 627 dev = &rte_eth_devices[port]; 628 priv = dev->data->dev_private; 629 if (!(priv->representor || priv->master)) { 630 rte_errno = EINVAL; 631 return NULL; 632 } 633 return priv; 634 } 635 636 /** 637 * Get the E-Switch parameters by device instance. 638 * 639 * @param[in] port 640 * Device port id. 641 * @param[out] es_domain_id 642 * E-Switch domain id. 643 * @param[out] es_port_id 644 * The port id of the port in the E-Switch. 645 * 646 * @return 647 * pointer to device private data structure containing data needed 648 * on success, NULL otherwise and rte_errno is set. 649 */ 650 struct mlx5_priv * 651 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev) 652 { 653 struct mlx5_priv *priv; 654 655 priv = dev->data->dev_private; 656 if (!(priv->representor || priv->master)) { 657 rte_errno = EINVAL; 658 return NULL; 659 } 660 return priv; 661 } 662 663 /** 664 * DPDK callback to retrieve hairpin capabilities. 665 * 666 * @param dev 667 * Pointer to Ethernet device structure. 668 * @param[out] cap 669 * Storage for hairpin capability data. 670 * 671 * @return 672 * 0 on success, a negative errno value otherwise and rte_errno is set. 673 */ 674 int 675 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) 676 { 677 struct mlx5_priv *priv = dev->data->dev_private; 678 struct mlx5_dev_config *config = &priv->config; 679 680 if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) { 681 rte_errno = ENOTSUP; 682 return -rte_errno; 683 } 684 cap->max_nb_queues = UINT16_MAX; 685 cap->max_rx_2_tx = 1; 686 cap->max_tx_2_rx = 1; 687 cap->max_nb_desc = 8192; 688 return 0; 689 } 690